Semiconductor device

Abstract

A semiconductor device may include: a first active pattern; a second active pattern spaced apart from the first active pattern by a first distance; a third active pattern spaced apart from the second active pattern by a second distance; a first device isolation layer between the first active pattern and the second active pattern; a second device isolation layer between the second active pattern and the third active pattern; a first channel structure overlapping the first active pattern; a second channel structure overlapping the second active pattern; a third channel structure overlapping the third active pattern; and a separation dielectric layer between the first channel structure and the second channel structure. The separation dielectric layer may overlap the first device isolation layer. A level of a top surface of the first device isolation layer may be higher than a level of a top surface of the second device isolation layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0110241 filed on August 23, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a separation dielectric layer. Background Art

[0004] A semiconductor device may include an integrated circuit having a metal oxide semiconductor field effect transistor (MOSFET). As the size and design rules of semiconductor devices are gradually reduced, the size of the MOSFET may also be further reduced. The reduction of the MOSFET may degrade the operating characteristics of the semiconductor device. Therefore, various studies have been conducted to manufacture semiconductor devices with excellent performance while overcoming the limitations caused by the integration of semiconductor devices. Summary of the invention

[0005] Some embodiments of the inventive concept provide a semiconductor device having increased reliability and improved electrical characteristics.

[0006] According to some embodiments of the inventive concept, a semiconductor device may include: a first active pattern; a second active pattern spaced apart from the first active pattern by a first distance; a third active pattern spaced apart from the second active pattern by a second distance; a first device isolation layer between the first active pattern and the second active pattern; a second device isolation layer between the second active pattern and the third active pattern; a first channel structure overlapping the first active pattern;

[0007] A second channel structure overlapping the second active pattern; a third channel structure overlapping the third active pattern; and a separation dielectric layer between the first channel structure and the second channel structure. The second active pattern may be between the first active pattern and the third active pattern. The first distance may be less than the second distance. The separation dielectric layer may overlap the first device isolation layer. The level of the top surface of the first device isolation layer may be higher than the level of the top surface of the second device isolation layer.

[0008] According to some embodiments of the inventive concept, a semiconductor device may include: a first active pattern and a second active pattern adjacent to each other; a device isolation layer between the first active pattern and the second active pattern; a first channel structure overlapping the first active pattern; a second channel structure overlapping the second active pattern; a first gate electrode overlapping the first channel structure; a second gate electrode overlapping the second channel structure; and a separation dielectric layer between the first channel structure and the second channel structure and between the first gate electrode and the second gate electrode. The level of the bottom surface of the separation dielectric layer may be lower than the level of the top surface of the device isolation layer.

[0009] According to some embodiments of the present inventive concept, a semiconductor device may include: a first active pattern and a second active pattern adjacent to each other; a device isolation layer between the first active pattern and the second active pattern; a first channel structure overlapping the first active pattern; a second channel structure overlapping the second active pattern; a first gate electrode overlapping the first channel structure; a second gate electrode overlapping the second channel structure; a first upper source / drain pattern connected to the first channel structure; a second upper source / drain pattern connected to the second channel structure; a first lower dielectric pattern between the first channel structure and the first active pattern; a second lower dielectric pattern between the second channel structure and the second active pattern; and a separation dielectric layer between the first channel structure and the second channel structure, between the first gate electrode and the second gate electrode, between the first upper source / drain pattern and the second upper source / drain pattern, and between the first lower dielectric pattern and the second lower dielectric pattern. The separation dielectric layer may overlap the device isolation layer. The separation dielectric layer and the device isolation layer may include dielectric materials different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A plan view showing a semiconductor device according to some embodiments is shown.

[0011] Figure 1B Shown along Figure 1A A cross-sectional view taken along line AA'.

[0012] Figure 1C Shown along Figure 1A A cross-sectional view taken along line BB'.

[0013] Figure 1D Shown along Figure 1A A cross-sectional view taken along line CC'.

[0014] Figure 1E Shown along Figure 1A A cross-sectional view taken along line D-D'.

[0015] Figure 1FShown along Figure 1A A cross-sectional view taken along line EE'.

[0016] Figure 1G Shows the display Figure 1B An enlarged view of part F1.

[0017] FIG. 2A to FIG. 15C A cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0018] Fig.16A , Fig. 16B and Fig. 16C A cross-sectional view showing a semiconductor device according to some embodiments is shown.

[0019] Fig.16D Shows the display Fig.16A An enlarged view of part F2.

[0020] Figures 17 to 25B A cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0021] Fig.26A and Fig.26B A cross-sectional view showing a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0022] Figure 1A A plan view showing a semiconductor device according to some embodiments is shown. Figure 1B Shown along Figure 1A A cross-sectional view taken along line AA'. Figure 1C Shown along Figure 1A A cross-sectional view taken along line BB'. Figure 1D Shown along Figure 1A A cross-sectional view taken along line CC'. Figure 1E Shown along Figure 1A A cross-sectional view taken along line D-D'. Figure 1F

[0023] Shown along Figure 1A A cross-sectional view taken along line EE'. Figure 1G Shows the display Figure 1B An enlarged view of part F1.

[0024] Reference Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G, the semiconductor device may include a substrate 10. A logic transistor included in a logic circuit may be provided on the substrate 10. The substrate 10 may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may include, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium phosphide (GaP), or gallium arsenide (GaAs).

[0025] The substrate 10 may have a plate shape extending along a plane defined in the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other.

[0026] The substrate 10 may include active patterns AP1, AP2, AP3, and AP4. Each of the active patterns AP1, AP2, AP3, and AP4 may extend in the second direction D2. Each of the active patterns AP1, AP2, AP3, and AP4 may be an upper portion of the substrate 10, and the upper portion may protrude in the third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0027] The active patterns AP1, AP2, AP3, and AP4 may include a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, and a fourth active pattern AP4. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may be arranged in order along the first direction D1. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may be spaced apart from each other in the first direction D1. The first active pattern AP1 and the second active pattern AP2 may be adjacent to each other in the first direction D1. The third active pattern AP3 and the fourth active pattern AP4 may be adjacent to each other in the first direction D1. The second active pattern AP2 may be disposed between the first active pattern AP1 and the third active pattern AP3. A first distance DS1 between the first active pattern AP1 and the second active pattern AP2 in the first direction D1 may be smaller than a second distance DS2 between the second active pattern AP2 and the third active pattern AP3 in the first direction D1.

[0028] A first device isolation layer 11 and a second device isolation layer 12 may be disposed on the substrate 10. The first device isolation layers 11 and the second device isolation layers 12 may be alternately arranged along the first direction D1. One of the first device isolation layers 11 may be disposed between the first active pattern AP1 and the second active pattern AP2. Another of the first device isolation layers 11 may be disposed between the third active pattern AP3 and the fourth active pattern AP4. One of the second device isolation layers 12 may be disposed between the second active pattern AP2 and the third active pattern AP3.

[0029] The width of the first device isolation layer 11 disposed between the first active pattern AP1 and the second active pattern AP2 in the first direction D1 may be smaller than the width of the second device isolation layer 12 disposed between the second active pattern AP2 and the third active pattern AP3 in the first direction D1. The first distance DS1 may be the same as the width of the first device isolation layer 11 disposed between the first active pattern AP1 and the second active pattern AP2 in the first direction D1. The second distance DS2 may be the same as the width of the second device isolation layer 12 disposed between the second active pattern AP2 and the third active pattern AP3 in the first direction D1.

[0030] The first device isolation layer 11 and the second device isolation layer 12 may include a dielectric material. For example, the first device isolation layer 11 and the second device isolation layer 12 may include silicon oxide.

[0031] A first channel structure CH1 may be formed overlapping the first active pattern AP1 in the third direction D3, a second channel structure CH2 may be formed overlapping the second active pattern AP2 in the third direction D3, a third channel structure CH3 may be formed overlapping the third active pattern AP3 in the third direction D3, and a fourth channel structure CH4 may be formed overlapping the fourth active pattern AP4 in the third direction D3.

[0032] The channel structures among the channel structures CH1, CH2, CH3, and CH4 overlapping one of the active patterns AP1, AP2, AP3, and AP4 in the third direction D3 may be arranged in the second direction D2. For example, the first channel structure CH1 overlapping the first active pattern AP1 in the third direction D3 may be arranged in the second direction D2. The channel structures among the channel structures CH1, CH2, CH3, and CH4 overlapping one of the active patterns AP1, AP2, AP3, and AP4 in the third direction D3 may be spaced apart from each other in the second direction D2. For example, the first channel structure CH1 overlapping the first active pattern AP1 in the third direction D3 may be spaced apart from each other in the second direction D2.

[0033] The first channel structures CH1 may each include a first semiconductor pattern SP1 arranged in the third direction D3. The first semiconductor patterns SP1 may be spaced apart from each other in the third direction D3. The second channel structures CH2 may each include a second semiconductor pattern SP2 arranged in the third direction D3. The second semiconductor patterns SP2 may be spaced apart from each other in the third direction D3. The third channel structures CH3 may each include a third semiconductor pattern SP3 arranged in the third direction D3. The third semiconductor patterns SP3 may be spaced apart from each other in the third direction D3. The fourth channel structures CH4 may each include a fourth semiconductor pattern SP4 arranged in the third direction D3. The fourth semiconductor patterns SP4 may be spaced apart from each other in the third direction D3.

[0034] The number of semiconductor patterns SP1, SP2, SP3 or SP4 included in one channel structure CH1, CH2, CH3 or CH4 may not be limited to that shown in the figure. In some embodiments, the number of semiconductor patterns SP1, SP2, SP3 or SP4 included in one channel structure CH1, CH2, CH3 or CH4 may be equal to or less than 3 or equal to or greater than 5.

[0035] In some embodiments, the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 may include silicon (Si). For example, the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 may include crystalline silicon.

[0036] The first lower source / drain pattern LSD1 may be disposed on the first active pattern AP1. The lower portion of the first lower source / drain pattern LSD1 may be disposed in the first active pattern AP1. The second lower source / drain pattern LSD2 may be disposed on the second active pattern AP2. The lower portion of the second lower source / drain pattern LSD2 may be disposed in the second active pattern AP2. The third lower source / drain pattern LSD3 may be disposed on the third active pattern AP3. The lower portion of the third lower source / drain pattern LSD3 may be disposed in the third active pattern AP3. The fourth lower source / drain pattern LSD4 may be disposed on the fourth active pattern AP4. The lower portion of the fourth lower source / drain pattern LSD4 may be disposed in the fourth active pattern AP4.

[0037] The first lower source / drain pattern LSD1, the second lower source / drain pattern LSD2, the third lower source / drain pattern LSD3, and the fourth lower source / drain pattern LSD4 may be epitaxial patterns formed by a selective epitaxial growth process. For example, the first lower source / drain pattern LSD1, the second lower source / drain pattern LSD2, the third lower source / drain pattern LSD3, and the fourth lower source / drain pattern LSD4 may include silicon (Si) or silicon germanium (SiGe).

[0038] The first upper source / drain pattern USD1 may be disposed to overlap the first active pattern AP1 in the third direction D3. The first upper source / drain pattern USD1 may be disposed between the first channel structures CH1 adjacent to each other in the second direction D2. The first upper source / drain pattern USD1 may be connected to the first semiconductor pattern SP1 of the first channel structure CH1. The second upper source / drain pattern USD2 may be disposed to overlap the second active pattern AP2 in the third direction D3. The second upper source / drain pattern USD2 may be disposed between the second channel structures CH2 adjacent to each other in the second direction D2. The third upper source / drain pattern USD3 may be disposed to overlap the third active pattern AP3 in the third direction D3. The third upper source / drain pattern USD3 may be disposed between the third channel structures CH3 adjacent to each other in the second direction D2. The fourth upper source / drain pattern USD4 may be disposed to overlap the fourth active pattern AP4 in the third direction D3. The fourth upper source / drain pattern USD4 may be disposed between the fourth channel structures CH4 adjacent to each other in the second direction D2.

[0039] The first upper source / drain pattern USD1 may overlap the first lower source / drain pattern LSD1 in the third direction D3. The second upper source / drain pattern USD2 may overlap the second lower source / drain pattern LSD2 in the third direction D3. The third upper source / drain pattern USD3 may overlap the third lower source / drain pattern LSD3 in the third direction D3. The fourth upper source / drain pattern USD4 may overlap the fourth lower source / drain pattern LSD4 in the third direction D3.

[0040] The first upper source / drain pattern USD1, the second upper source / drain pattern USD2, the third upper source / drain pattern USD3, and the fourth upper source / drain pattern USD4 may be epitaxial patterns formed by a selective epitaxial growth process. The first upper source / drain pattern USD1, the second upper source / drain pattern USD2, the third upper source / drain pattern USD3, and the fourth upper source / drain pattern USD4 may include, for example, silicon (Si) or silicon germanium (SiGe).

[0041] In some embodiments, the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 and the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 may be doped with impurities to have a first conductivity type, and the third lower source / drain pattern LSD3 and the fourth lower source / drain pattern LSD4 and the third upper source / drain pattern USD3 and the fourth upper source / drain pattern USD4 may be doped with impurities to have a second conductivity type different from the first conductivity type. For example, the first conductivity type may be a p-type, and the second conductivity type may be an n-type.

[0042] The first gate electrode GE1 may be arranged to overlap the first active pattern AP1 in the third direction D3. The first gate electrode GE1 may overlap the first channel structure CH1 in the third direction D3. The second gate electrode GE2 may be arranged to overlap the second active pattern AP2 in the third direction D3. The second gate electrode GE2 may overlap the second channel structure CH2 in the third direction D3. The third gate electrode GE3 may be arranged to overlap the third active pattern AP3 in the third direction D3. The third gate electrode GE3 may overlap the third channel structure CH3 in the third direction D3. The fourth gate electrode GE4 may be arranged to overlap the fourth active pattern AP4 in the third direction D3. The fourth gate electrode GE4 may overlap the fourth channel structure CH4 in the third direction D3.

[0043] The first gate electrode GE1 may be disposed between the first upper source / drain patterns USD1 adjacent to each other in the second direction D2. The second gate electrode GE2 may be disposed between the second upper source / drain patterns USD2 adjacent to each other in the second direction D2. The third gate electrode GE3 may be disposed between the third upper source / drain patterns USD3 adjacent to each other in the second direction D2. The fourth gate electrode GE4 may be disposed between the fourth upper source / drain patterns USD4 adjacent to each other in the second direction D2. In some embodiments, the gate separation structure may be provided to separate the second gate electrode GE2 and the third gate electrode GE3 from each other.

[0044] The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 and the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 may constitute a three-dimensional field effect transistor (e.g., MBCFET or GAAFET). The conductive material included in the first gate electrode GE1 and the second gate electrode GE2 may be different from the conductive material included in the third gate electrode GE3 and the fourth gate electrode GE4.

[0045] The first lower dielectric pattern 61 may be disposed between the first active pattern AP1 and the first channel structure CH1. The second lower dielectric pattern 62 may be disposed between the second active pattern AP2 and the second channel structure CH2. The third lower dielectric pattern 63 may be disposed between the third active pattern AP3 and the third channel structure CH3. The fourth lower dielectric pattern 64 may be disposed between the fourth active pattern AP4 and the fourth channel structure CH4.

[0046] The first lower dielectric pattern 61 may surround an upper portion of the first lower source / drain pattern LSD1. The second lower dielectric pattern 62 may surround an upper portion of the second lower source / drain pattern LSD2. The third lower dielectric pattern 63 may surround an upper portion of the third lower source / drain pattern LSD3. The fourth lower dielectric pattern 64 may surround an upper portion of the fourth lower source / drain pattern LSD4.

[0047] The first lower dielectric pattern 61 may contact the top surface of the first active pattern AP1. The second lower dielectric pattern 62 may contact the top surface of the second active pattern AP2. The third lower dielectric pattern 63 may contact the top surface of the third active pattern AP3. The fourth lower dielectric pattern 64 may contact the top surface of the fourth active pattern AP4.

[0048] The first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63, and the fourth lower dielectric pattern 64 may include a dielectric material. For example, each of the first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63, and the fourth lower dielectric pattern 64 may include at least one selected from silicon carbonitride, silicon oxide, silicon nitride, and silicon carbonitride.

[0049] A separation dielectric layer 20 may be provided. The separation dielectric layer 20 may extend in the second direction D2. The separation dielectric layers 20 may be spaced apart from each other in the first direction D1. One of the separation dielectric layers 20 may be disposed between the first gate electrode GE1 and the second gate electrode GE2, between the first channel structure CH1 and the second channel structure CH2, between the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2, between the first lower dielectric pattern 61 and the second lower dielectric pattern 62, and between the first active pattern AP1 and the second active pattern AP2. Another of the separation dielectric layers 20 may be disposed between the third gate electrode GE3 and the fourth gate electrode GE4, between the third channel structure CH3 and the fourth channel structure CH4, between the third upper source / drain pattern USD3 and the fourth upper source / drain pattern USD4, between the third lower dielectric pattern 63 and the fourth lower dielectric pattern 64, and between the third active pattern AP3 and the fourth active pattern AP4.

[0050] The separation dielectric layer 20 may overlap the first device isolation layer 11 in the third direction D3. The separation dielectric layer 20 may contact the first device isolation layer 11. One of the separation dielectric layers 20 may contact the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2. Another of the separation dielectric layers 20 may contact the third upper source / drain pattern USD3 and the fourth upper source / drain pattern USD4. The separation dielectric layer 20 may include a dielectric material different from the dielectric material of the first isolation layer 11 and the second isolation layer 12. For example, the separation dielectric layer 20 may include silicon nitride, and the first device isolation layer 11 and the second device isolation layer 12 may include silicon oxide.

[0051] A gate dielectric layer GI may be provided. The gate dielectric layer GI may separate the gate electrodes GE1, GE2, GE3, and GE4 from the semiconductor patterns SP1, SP2, SP3, and SP4 of the channel structures CH1, CH2, CH3, and CH4. The gate dielectric layer GI may contact the first device isolation layer 11, the second device isolation layer 12, the lower dielectric patterns 61, 62, 63, and 64, and the separation dielectric layer 20. The gate dielectric layer GI may include a dielectric material. For example, the gate dielectric layer GI may include silicon oxide.

[0052] A gate spacer GS may be provided. The gate spacer GS may be disposed on opposite sides of each of the gate electrodes GE1, GE2, GE3, and GE4. The gate spacer GS may include a dielectric material. For example, the gate spacer GS may include silicon oxycarbon nitride.

[0053] A gate capping pattern GP may be provided. The gate capping pattern GP may be disposed on the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4. The gate capping pattern GP may include a dielectric material. For example, the gate capping pattern GP may include silicon nitride.

[0054] A lower capping dielectric layer 51 may be provided. The lower capping dielectric layer 51 may contact the lower source / drain patterns LSD1, LSD2, LSD3, and LSD4, the lower dielectric patterns 61, 62, 63, and 64, the separation dielectric layer 20, the first device isolation layer 11, and the second device isolation layer 12. At least a portion of the lower capping dielectric layer 51 may be disposed between the upper source / drain patterns USD1, USD2, USD3, and USD4 and the active patterns AP1, AP2, AP3, and AP4. The lower capping dielectric layer 51 may include a dielectric material.

[0055] An upper capping dielectric layer 52 may be provided. The upper capping dielectric layer 52 may contact the upper source / drain patterns USD1, USD2, USD3, and USD4, the separation dielectric layer 20, and the lower capping dielectric layer 51. The upper capping dielectric layer 52 may include a dielectric material.

[0056] The dielectric layer 13 may be disposed on the lower cover dielectric layer 51 and the upper cover dielectric layer 52. The dielectric layer 13 may include a dielectric material.

[0057] An active contact 41 may be provided. The active contact 41 may pass through the dielectric layer 13 to make contact with the upper source / drain patterns USD1, USD2, USD3, and USD4. The active contact 41 may include a conductive material.

[0058] A gate contact 45 may be provided. The gate contact 45 may pass through the gate capping pattern GP to contact the gate electrodes GE1, GE2, GE3, and GE4. The gate contact 45 may include a conductive material.

[0059] Reference Figure 1B and Figure 1C , the width W1 of the separation dielectric layer 20 in the first direction D1 may be smaller than the width of the first device isolation layer 11 in the first direction D1. The width W1 of the separation dielectric layer 20 in the first direction D1 may be, for example, about 1.8 times to about 3 times the distance between the first semiconductor pattern SP1 and the separation dielectric layer 20 in the first direction D1. The width W1 of the separation dielectric layer 20 in the first direction D1 may be, for example, in the range from about 15 nm to about 20 nm. The distance between the first semiconductor pattern SP1 and the separation dielectric layer 20 in the first direction D1 may be, for example, in the range from about 5 nm to about 11 nm. Each of the first upper source / drain pattern USD1, the second upper source / drain pattern USD2, the third upper source / drain pattern USD3, and the fourth upper source / drain pattern USD4 may be in contact with the side surface 20_S of the separation dielectric layer 20.

[0060] Reference Figure 1C , Figure 1E and Figure 1G, the first device isolation layer 11 may include a first portion 11_1 and a second portion 11_2. The first portion 11_1 of the first device isolation layer 11 may be located at a lower level than the level of the second portion 11_2 of the first device isolation layer 11. The second portion 11_2 of the first device isolation layer 11 may protrude from the first portion 11_1 of the first device isolation layer 11 in the third direction D3. The second portion 11_2 of the first device isolation layer 11 may be arranged along the second direction D2. The second portions 11_2 of the first device isolation layer 11 may be spaced apart from each other in the second direction D2. The width of the first portion 11_1 of the first device isolation layer 11 in the second direction D2 may be greater than the width of the second portion 11_2 of the first device isolation layer 11 in the second direction D2.

[0061] The first device isolation layer 11 may have a first top surface 11_T1 and a second top surface 11_T2. The first top surface 11_T1 of the first device isolation layer 11 may be located at a higher level than the level of the second top surface 11_T2 of the first device isolation layer 11. The distance between the first top surface 11_T1 of the first device isolation layer 11 and the bottom surface of the first device isolation layer 11 in the third direction D3 may be greater than the distance between the second top surface 11_T2 of the first device isolation layer 11 and the bottom surface of the first device isolation layer 11 in the third direction D3.

[0062] The first top surface 11_T1 of the first device isolation layer 11 may contact the gate dielectric layer GI. The second top surface 11_T2 of the first device isolation layer 11 may contact the lower cover dielectric layer 51. The first top surface 11_T1 of the first device isolation layer 11 may be a top surface of the second portion 11_2 of the first device isolation layer 11.

[0063] The first top surface 11_T1 and the second top surface 11_T2 of the first device isolation layer 11 may be located at a level higher than that of the top surface 12_T of the second device isolation layer 12. The distance between the first top surface 11_T1 of the first device isolation layer 11 and the bottom surface of the first device isolation layer 11 in the third direction D3 and the distance between the second top surface 11_T2 of the first device isolation layer 11 and the bottom surface of the first device isolation layer 11 in the third direction D3 may be greater than the distance between the top surface 12_T of the second device isolation layer 12 and the bottom surface of the second device isolation layer 12 in the third direction D3.

[0064] The first top surface 11_T1 of the first device isolation layer 11, the second top surface 11_T2 of the first device isolation layer 11, and the top surface 12_T of the second device isolation layer 12 may be located at a higher level than the level of the bottom surface 20_B of the separation dielectric layer 20. The distance between the first top surface 11_T1 of the first device isolation layer 11 and the bottom surface of the first device isolation layer 11 in the third direction D3, the distance between the second top surface 11_T2 of the first device isolation layer 11 and the bottom surface of the first device isolation layer 11 in the third direction D3, and the distance between the top surface 12_T of the second device isolation layer 12 and the bottom surface of the second device isolation layer 12 in the third direction D3 may be greater than the distance between the bottom surface 20_B of the separation dielectric layer 20 and the bottom surface of the first device isolation layer 11 and between the bottom surface 20_B of the dielectric layer 20 and the bottom surface of the second device isolation layer 12 in the third direction D3.

[0065] A first top surface 11_T1 of the first device isolation layer 11 may overlap the gate electrodes GE1, GE2, GE3, and GE4 in the third direction D3. A second top surface 11_T2 of the first device isolation layer 11 may overlap the upper source / drain patterns USD1, USD2, USD3, and USD4 in the third direction D3.

[0066] The bottom surface 20_B of the separation dielectric layer 20 may be located at a higher level than the levels of the bottom surfaces of the first device isolation layer 11 and the second device isolation layer 12 .

[0067] Reference Figure 1G , the first gate electrode GE1 may include a first portion GE1_1, a second portion GE1_2, a third portion GE1_3, and a fourth portion GE1_4. The first portion GE1_1 of the first gate electrode GE1 may be disposed between the first semiconductor patterns SP1 or between the first semiconductor pattern SP1 and the first lower dielectric pattern 61. The second portion GE1_2 of the first gate electrode GE1 may be disposed between the separation dielectric layer 20 and the first semiconductor pattern SP1. The second portion GE1_2 of the first gate electrode GE1 may overlap the first device isolation layer 11 in the third direction D3. The third portion GE1_3 of the first gate electrode GE1 may overlap the second device isolation layer 12 in the third direction D3.

[0068] The second portion GE1_2 and the third portion GE1_3 of the first gate electrode GE1 may be connected to opposite sides of each of the first portion GE1_1 of the first gate electrode GE1. The fourth portion GE1_4 of the first gate electrode GE1 may be located at a higher level than that of the first semiconductor pattern SP1. The fourth portion GE1_4 of the first gate electrode GE1 may be connected to the second portion GE1_2 and the third portion GE1_3 of the first gate electrode GE1.

[0069] Similar to the first gate electrode GE1 , each of the second gate electrode GE2 , the third gate electrode GE3 , and the fourth gate electrode GE4 may include a first portion, a second portion, a third portion, and a fourth portion.

[0070] The semiconductor device according to some embodiments may include a portion interposed between the separation dielectric layer 20 and the semiconductor pattern, and thus it may include a three-dimensional field effect transistor and have a relative advantage in channel control.

[0071] The semiconductor device according to some embodiments may include a portion interposed between the separation dielectric layer 20 and the semiconductor pattern, and thus the semiconductor pattern may have a relatively uniform width, and current distribution flowing through the semiconductor pattern may be relatively reduced.

[0072] Figure 2A , Figure 2B , Figure 2C , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Figure 7 , Fig. 8A , Figure 8B , Fig. 9 , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B and Fig. 15C A cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments is shown. Figure 2A , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 7 , Fig. 8A , Fig. 9 , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.15ACorresponds to Figure 1B . Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig.14A Corresponds to Figure 1C . Figure 2B , Figure 6B , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 14B and Fig. 15B Corresponds to Figure 1D . Figure 2C , Figure 6C , Figure 8B , Fig. 10D , Fig.11D , Fig.12D , Fig. 14C and Fig. 15C Corresponds to Figure 1E . Fig. 13C Corresponds to Figure 1F .

[0073] Reference Figure 2A , Figure 2B and Figure 2C , active patterns AP1, AP2, AP3 and AP4, a first semiconductor layer 81, a second semiconductor layer 82, a third semiconductor layer 83 and a mask pattern 84 may be formed. The first semiconductor layer 81 may be formed on the active patterns AP1, AP2, AP3 and AP4. The second semiconductor layer 82 and the third semiconductor layer 83 may be alternately formed on the first semiconductor layer 81 along the third direction D3. The mask pattern 84 may be formed on the third semiconductor layer 83.

[0074] The first and second semiconductor layers 81 and 82 may include a material having an etching selectivity with respect to the third semiconductor layer 83. For example, the first and second semiconductor layers 81 and 82 may include silicon germanium (SiGe), and the third semiconductor layer 83 may include silicon (Si).

[0075] The germanium (Ge) concentration of the first semiconductor layer 81 may be different from that of the second semiconductor layer 82. For example, the germanium concentration of the first semiconductor layer 81 may be greater than that of the second semiconductor layer 82. The mask pattern 84 may include a dielectric material. For example, the mask pattern 84 may include silicon nitride.

[0076] The formation of active patterns AP1, AP2, AP3, and AP4, a first semiconductor layer 81, a second semiconductor layer 82, a third semiconductor layer 83, and a mask pattern 84 may include: forming an initial semiconductor layer on a substrate 10; forming an initial mask pattern layer on the initial semiconductor layer; patterning the initial mask pattern layer to form a mask pattern 84; and patterning the initial semiconductor layer and the substrate 10 using the mask pattern 84. The substrate 10 may be patterned to form active patterns AP1, AP2, AP3, and AP4. The initial semiconductor layer may be patterned to form semiconductor layers 81, 82, and 83.

[0077] Reference Figure 3 , an initial separation layer 85 may be formed. The initial separation layer 85 may cover the active patterns AP1, AP2, AP3, and AP4, the first semiconductor layer 81, the second semiconductor layer 82, the third semiconductor layer 83, and the mask pattern 84. The initial separation layer 85 may include a dielectric material. For example, the initial separation layer 85 may include silicon oxide.

[0078] Reference Figure 4 , the upper portion of the preliminary separation layer 85 may be removed. For example, the upper portion of the preliminary separation layer 85 may be removed by a chemical mechanical polishing process. The upper portion of the preliminary separation layer 85 may be removed to expose the mask pattern 84.

[0079] Reference Figure 5 , a photoresist pattern 86 may be formed. The formation of the photoresist pattern 86 may include: forming a photoresist layer on the initial separation layer 85 and the mask pattern 84; and patterning the photoresist layer to form the photoresist pattern 86. The photoresist pattern 86 may include a photoresist material. The photoresist pattern 86 may expose a portion of the initial separation layer 85.

[0080] Reference Fig. 6A , Figure 6B and Figure 6C , the first device isolation layer 11 may be formed. The portion of the preliminary separation layer 85 exposed by the photoresist pattern 86 may be etched to form the first device isolation layer 11.

[0081] Reference Figure 7 , the photoresist pattern 86 may be removed. For example, the photoresist pattern 86 may be removed by using at least one selected from an ashing process and a stripping process.

[0082] Reference Fig. 8A and Figure 8B, a sacrificial layer 87 may be formed. The sacrificial layer 87 may extend in the second direction D2. One of the sacrificial layers 87 may be formed between the second semiconductor layer 82 and the third semiconductor layer 83 overlapping the first active pattern AP1 along the third direction D3 and the second semiconductor layer 82 and the third semiconductor layer 83 overlapping the second active pattern AP2 along the third direction D3. Another of the sacrificial layers 87 may be formed between the second semiconductor layer 82 and the third semiconductor layer 83 overlapping the third active pattern AP3 along the third direction D3 and between the second semiconductor layer 82 and the third semiconductor layer 83 overlapping the fourth active pattern AP4 along the third direction D3. The sacrificial layer 87 may overlap the first device isolation layer 11 in the third direction D3. The sacrificial layer 87 may be formed in the first device isolation layer 11. The sacrificial layer 87 may be formed by an epitaxial growth process in which the second semiconductor layer 82 and the third semiconductor layer 83 are used as seeds. In some embodiments, the sacrificial layer 87 may be formed by a deposition process and an etching process.

[0083] The sacrificial layer 87 may include silicon germanium (SiGe). The sacrificial layer 87 may have a germanium (Ge) concentration of, for example, about 25 wt % to about 35 wt %. In some embodiments, the germanium concentration of the sacrificial layer 87 may be the same as that of the second semiconductor layer 82 .

[0084] Reference Fig. 9 , the second device isolation layer 12 may be formed. The initial separation layer 85 may be etched to form the second device isolation layer 12. Since the sacrificial layer 87 is disposed on the first device isolation layer 11, the first device isolation layer 11 may not be etched in the process for forming the second device isolation layer 12. Therefore, the top surface 11_T of the first device isolation layer 11 may be located at a higher level than the top surface 12_T of the second device isolation layer 12. The mask pattern 84 may be removed.

[0085] Reference Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D , a first lower dielectric pattern 61, a second lower dielectric pattern 62, a third lower dielectric pattern 63, and a fourth lower dielectric pattern 64 may be formed. The formation of the first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63, and the fourth lower dielectric pattern 64 may include: selectively removing the first semiconductor layer 81; and forming the first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63, and the fourth lower dielectric pattern 64 in an empty space formed by selectively removing the first semiconductor layer 81.

[0086] A first gate sacrificial layer 71, a second gate sacrificial layer 72, a gate mask pattern 73, and an initial gate spacer layer 74 may be formed. The formation of the first gate sacrificial layer 71, the second gate sacrificial layer 72, the gate mask pattern 73, and the initial gate spacer layer 74 may include: forming a first initial gate sacrificial layer on the second device isolation layer 12, the first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63, and the fourth lower dielectric pattern 64, the second semiconductor layer 82 and the third semiconductor layer 83, and the sacrificial layer 87; and forming a second initial gate sacrificial layer on the first initial gate sacrificial layer; forming an initial gate mask pattern layer on the second initial gate sacrificial layer; patterning the initial gate mask pattern layer to form a gate mask pattern 73; using the gate mask pattern 73 to pattern the first initial gate sacrificial layer and the second initial gate sacrificial layer to form a first gate sacrificial layer 71 and a second gate sacrificial layer 72; and forming an initial gate spacer layer 74 on the gate mask pattern 73, the first gate sacrificial layer 71, and the second gate sacrificial layer 72.

[0087] The first gate sacrificial layer 71, the second gate sacrificial layer 72, and the gate mask pattern 73 may extend in the first direction D1. The first gate sacrificial layer 71 may be arranged in the second direction D2. The second gate sacrificial layer 72 may be arranged in the second direction D2. The gate mask pattern 73 may be arranged in the second direction D2.

[0088] The first gate sacrificial layer 71 may include a dielectric material. For example, the first gate sacrificial layer 71 may include silicon oxide. The second gate sacrificial layer 72 may include, for example, polysilicon. The gate mask pattern 73 may include a dielectric material. For example, the gate mask pattern 73 may include silicon nitride. The initial gate spacer layer 74 may include a dielectric material. For example, the initial gate spacer layer 74 may include silicon oxycarbonitride.

[0089] Reference Fig.11A , Fig. 11B , Fig. 11C and Fig.11D , the initial gate spacer layer 74 may be etched. Etching the initial gate spacer layer 74 may form a gate spacer GS. Etching the initial gate spacer layer 74 may expose the gate mask pattern 73. As a result of etching the initial gate spacer layer 74, a portion of the second semiconductor layer 82 and the third semiconductor layer 83 and the sacrificial layer 87 may be exposed through the space between the gate spacers GS.

[0090] The second and third semiconductor layers 82 and 83 and the sacrificial layer 87 may be etched. There may be a removed portion that overlaps the space between the second and third semiconductor layers 82 and 83 and the gate spacer GS of the sacrificial layer 87 along the third direction D3. One second semiconductor layer 82 may be divided into a plurality of semiconductor sacrificial patterns 88. One third semiconductor layer 83 may be divided into a plurality of semiconductor patterns SP1, SP2, SP3, and SP4. One sacrificial layer 87 may be divided into a plurality of sacrificial patterns 89.

[0091] The device isolation layer 11 may be etched together with etching the second and third semiconductor layers 82 and 83 and the sacrificial layer 87. As the sacrificial layer 87 is etched, a portion of the first device isolation layer 11 may be exposed between the sacrificial patterns 89, and a portion of the first device isolation layer 11 may be removed. Etching the first device isolation layer 11 may define a first top surface 11_T1 and a second top surface 11_T2 of the first device isolation layer 11, and may also define a first portion 11_1 and a second portion 11_2 of the first device isolation layer 11.

[0092] Reference Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D , a dielectric liner 75 may be formed. A dielectric liner 75 may be formed on the first device isolation layer 11 and the second device isolation layer 12, the first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63 and the fourth lower dielectric pattern 64, the semiconductor patterns SP1, SP2, SP3 and SP4, the semiconductor sacrificial pattern 88, the sacrificial pattern 89 and the gate spacer GS. The dielectric liner 75 may include a dielectric material. For example, the dielectric liner 75 may include silicon nitride.

[0093] A gap-filling layer 76 may be formed. The gap-filling layer 76 may be formed on the dielectric liner 75. The gap-filling layer 76 may include a dielectric material. For example, the gap-filling layer 76 may include silicon oxide.

[0094] Reference Fig.13A , Fig. 13B and Fig. 13C , a separation dielectric layer 20 may be formed. The separation dielectric layer 20 may pass through the gate mask pattern 73 , the second gate sacrificial layer 72 , the first gate sacrificial layer 71 , the sacrificial pattern 89 , and the dielectric liner 75 .

[0095] The formation of the separation dielectric layer 20 may include: forming a groove passing through the gate mask pattern 73, the second gate sacrificial layer 72, the first gate sacrificial layer 71, the sacrificial pattern 89 and the dielectric liner 75; and forming the separation dielectric layer 20 filling the groove. The formation of the separation dielectric layer 20 may divide one sacrificial pattern 89 into two sacrificial patterns 89. The two sacrificial patterns 89 may contact the separation dielectric layer 20.

[0096] Reference Fig.14A , Fig. 14B and Fig. 14C , the gap filling layer 76 and the dielectric liner 75 may be removed. A first lower source / drain pattern LSD1, a second lower source / drain pattern LSD2, a third lower source / drain pattern LSD3, and a fourth lower source / drain pattern LSD4 may be formed. The formation of the lower source / drain patterns LSD1, LSD2, LSD3, and LSD4 may include: forming holes by etching the lower dielectric patterns 61, 62, 63, and 64 and the active patterns AP1, AP2, AP3, and AP4; and epitaxially growing the lower source / drain patterns LSD1, LSD2, LSD3, and LSD4 from seeds or the active patterns AP1, AP2, AP3, and AP4 exposed through the holes.

[0097] A lower capping dielectric layer 51 may be formed. The formation of the lower capping dielectric layer 51 may include: forming an initial lower capping dielectric layer on the first device isolation layer 11 and the second device isolation layer 12, the first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63 and the fourth lower dielectric pattern 64, the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, the semiconductor sacrificial pattern 88 and the sacrificial pattern 89; and etching the initial lower capping dielectric layer to expose the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, the semiconductor sacrificial pattern 88 and the sacrificial pattern 89. The initial lower capping dielectric layer may be etched into the lower capping dielectric layer 51.

[0098] A first upper source / drain pattern USD1, a second upper source / drain pattern USD2, a third upper source / drain pattern USD3, and a fourth upper source / drain pattern USD4 may be formed. The formation of the first upper source / drain pattern USD1, the second upper source / drain pattern USD2, the third upper source / drain pattern USD3, and the fourth upper source / drain pattern USD4 may include performing an epitaxial growth process in which the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4, the semiconductor sacrificial pattern 88, and the sacrificial pattern 89 are used as seeds.

[0099] An upper capping dielectric layer 52 may be formed on the first, second, third, and fourth upper source / drain patterns USD1, USD2, USD3, and USD4. A dielectric layer 13 may be formed on the lower and upper capping dielectric layers 51 and 52.

[0100] Reference Fig.15A , Fig. 15B and Fig. 15C , the gate mask pattern 73, the second gate sacrificial layer 72, the first gate sacrificial layer 71, the semiconductor sacrificial pattern 88, and the sacrificial pattern 89 may be removed. In some embodiments, the semiconductor sacrificial pattern 88 and the sacrificial pattern 89 may be removed by a process that selectively removes silicon germanium.

[0101] A gate dielectric layer GI, gate electrodes GE1 , GE2 , GE3 , and GE4 , and a gate capping pattern GP may be formed in an empty space formed by removing the gate mask pattern 73 , the second gate sacrificial layer 72 , the first gate sacrificial layer 71 , the semiconductor sacrificial pattern 88 , and the sacrificial pattern 89 .

[0102] Reference Figure 1B , Figure 1C , Figure 1D and Figure 1E , a gate contact 45 and an active contact 41 may be formed.

[0103] In a method of manufacturing a semiconductor device according to some embodiments, as the sacrificial pattern 89 is formed and the separation dielectric layer 20 is subsequently formed, the semiconductor pattern may have a relatively uniform width.

[0104] In the method of manufacturing a semiconductor device according to some embodiments, as the gate spacer GS is formed and the separation dielectric layer 20 is subsequently formed, the gate spacer GS may not remain on the sidewall of the separation dielectric layer 20. Therefore, in the process of removing the semiconductor sacrificial pattern 88 and the sacrificial pattern 89, a phenomenon in which both the semiconductor sacrificial pattern 88 and the sacrificial pattern 89 are not partially removed due to the gate spacer GS remaining on the sidewall of the separation dielectric layer 20 may be limited and / or prevented.

[0105] In the method of manufacturing a semiconductor device according to some embodiments, with the formation of a semiconductor pattern and the subsequent formation of a separation dielectric layer 20, a reduction in the height of the separation dielectric layer 20 in a process for forming the semiconductor pattern can be limited and / or prevented, and a phenomenon in which the height of the separation dielectric layer 20 is reduced to connect upper source / drain patterns to each other can be limited and / or prevented.

[0106] Fig.16A , Fig. 16B and Fig. 16CA cross-sectional view showing a semiconductor device according to some embodiments is shown. Fig.16D Shows the display Fig.16A An enlarged view of part F2. Fig.16A Corresponds to Figure 1B . Fig. 16B Corresponds to Figure 1C . Fig. 16C Corresponds to Figure 1E In addition to the following, FIG. 16A to FIG. 16D The semiconductor device can be similar to Figures 1A to 1G semiconductor device.

[0107] Reference Fig.16A , Fig. 16B , Fig. 16C and Fig.16D , an intermediate dielectric pattern 55 may be provided. The intermediate dielectric pattern 55 may be disposed on the first device isolation layer 11. The intermediate dielectric pattern 55 may overlap the first device isolation layer 11 in the third direction D3.

[0108] The intermediate dielectric pattern 55 may include a dielectric material different from the dielectric material separating the dielectric layer 20, the first device isolation layer 11, and the second device isolation layer 12. For example, the intermediate dielectric pattern 55 may include silicon oxycarbonitride or silicon carbon nitride.

[0109] The intermediate dielectric patterns 55 may extend in the second direction D2. The intermediate dielectric patterns 55 may be arranged along the first direction D1. The intermediate dielectric patterns 55 may be spaced apart from each other in the first direction D1. The separation dielectric layer 20 may be disposed between the intermediate dielectric patterns 55 adjacent to each other along the first direction D1. The intermediate dielectric patterns 55 may be disposed between the separation dielectric layer 20 and the channel structure CH1, CH2, CH3, or CH4.

[0110] The intermediate dielectric pattern 55 may include a first portion 55_1 and a second portion 55_2. The first portion 55_1 of the intermediate dielectric pattern 55 may be located at a lower level than the level of the second portion 55_2 of the intermediate dielectric pattern 55. The second portion 55_2 of the intermediate dielectric pattern 55 may protrude from the first portion 55_1 of the intermediate dielectric pattern 55 in the third direction D3. The second portions 55_2 of the intermediate dielectric pattern 55 may be arranged along the second direction D2. The second portions 55_2 of the intermediate dielectric pattern 55 may be spaced apart from each other in the second direction D2. The width of the first portion 55_1 of the intermediate dielectric pattern 55 in the second direction D2 may be greater than the width of the second portion 55_2 of the intermediate dielectric pattern 55 in the second direction D2.

[0111] The intermediate dielectric pattern 55 may have a first top surface 55_T1 and a second top surface 55_T2. The first top surface 55_T1 of the intermediate dielectric pattern 55 may be located at a higher level than the level of the second top surface 55_T2 of the intermediate dielectric pattern 55. The distance between the first top surface 55_T1 of the intermediate dielectric pattern 55 and the bottom surface 55_B of the intermediate dielectric pattern 55 in the third direction D3 may be greater than the distance between the second top surface 55_T2 of the intermediate dielectric pattern 55 and the bottom surface 55_B of the intermediate dielectric pattern 55 in the third direction D3. The bottom surface 55_B of the intermediate dielectric pattern 55 may contact the top surface 11_T of the first device isolation layer 11. The bottom surface 55_B of the intermediate dielectric pattern 55 may be located at a higher level than the level of the bottom surface 20_B of the separation dielectric layer 20.

[0112] The first top surface 55_T1 of the intermediate dielectric pattern 55 may be in contact with the gate dielectric layer GI and the gate spacer GS. The second top surface 55_T2 of the intermediate dielectric pattern 55 may be in contact with the upper source / drain pattern USD1, USD2, USD3, or USD4. The first top surface 55_T1 of the intermediate dielectric pattern 55 may be a top surface of the second portion 55_2 of the intermediate dielectric pattern 55. The first top surface 55_T1 and the second top surface 55_T2 of the intermediate dielectric pattern 55 may be connected to the sidewall of the separation dielectric layer 20.

[0113] In some embodiments, the first top surface 55_T1 of the intermediate dielectric pattern 55 may be located at the same level as a top surface of an uppermost one of the semiconductor patterns SP1 , SP2 , SP3 , and SP4 included in the channel structures CH1 , CH2 , CH3 , and CH4 .

[0114] The second top surface 55_T2 of the intermediate dielectric pattern 55 may be at a level lower than that of the top surface of the upper source / drain pattern USD1, USD2, USD3 or USD4 and higher than that of the bottom surface of the upper source / drain pattern USD1, USD2, USD3 or USD4.

[0115] A first top surface 55_T1 of the intermediate dielectric pattern 55 may overlap the gate electrode GE1, GE2, GE3 or GE4 in the third direction D3. A second top surface 55_T2 of the intermediate dielectric pattern 55 may overlap the upper source / drain pattern USD1, USD2, USD3 or USD4 in the third direction D3.

[0116] The intermediate dielectric pattern 55 may be in contact with the separation dielectric layer 20. The intermediate dielectric pattern 55 may have a first sidewall 55_S1 in contact with the semiconductor pattern SP1, SP2, SP3, or SP4, and may also have a second sidewall 55_S2 and a third sidewall 55_S3 in contact with the upper source / drain pattern USD1, USD2, USD3, or USD4. The first sidewall 55_S1 and the second sidewall 55_S2 of the intermediate dielectric pattern 55 may be parallel to the second direction D2. The third sidewall 55_S3 of the intermediate dielectric pattern 55 may be parallel to the first direction D1.

[0117] The height of the first sidewall 55_S1 of the intermediate dielectric pattern 55 in the third direction D3 may be greater than the height of the second and third sidewalls 55_S2 and 55_S3 of the intermediate dielectric pattern 55 in the third direction D3. The third sidewall 55_S3 of the intermediate dielectric pattern 55 may be a sidewall of the second portion 55_2 of the intermediate dielectric pattern 55.

[0118] When in Fig.16D When viewed in the cross section shown in FIG. 1 , the width of the separation dielectric layer 20 in the first direction D1 may be, for example, about 1.8 times to about 3 times the width of the intermediate dielectric pattern 55 in the first direction D1. Fig.16D When viewed in the illustrated cross section, the distance of the intermediate dielectric pattern 55 in the first direction D1 may be in a range of, for example, about 5 nm to about 11 nm.

[0119] Each of the semiconductor patterns SP1, SP2, SP3, and SP4 may have a sidewall in contact with the first sidewall 55_S1 of the intermediate dielectric pattern 55. For example, the first semiconductor pattern SP1 may have a sidewall SP1_S in contact with the first sidewall 55_S1 of the intermediate dielectric pattern 55.

[0120] The gate dielectric layer GI may be in contact with a first sidewall 55_S1 of the intermediate dielectric pattern 55. The lower capping dielectric layer 51 and the upper capping dielectric layer 52 may be in contact with a second sidewall 55_S2 of the intermediate dielectric pattern 55.

[0121] According to some embodiments, as the intermediate dielectric pattern 55 is disposed between the separation dielectric layer 20 and the gate electrode of the semiconductor device, the semiconductor pattern may have a relatively uniform width, and current distribution flowing through the semiconductor pattern may be relatively reduced.

[0122] Fig.17 , Fig.18A , Fig.18B , Fig.19 , Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A and Fig.25B A cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments is shown. Fig.17 , Fig.18A , Fig.19 , Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.25A Corresponds to Fig.16A . Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B and Fig.24A Corresponds to Fig. 16B . Fig.18B , Fig. 21C , Fig. 22C , Fig. 24B and Fig.25B Corresponds to Fig. 16C .

[0123] Reference Fig.17 ,and Figures 2A to 7 Similar to the discussion, a substrate 10 including active patterns AP1 , AP2 , AP3 , and AP4 may be provided, and a first device isolation layer 11 , first, second, and third semiconductor layers 81 , 82 , and 83 , a mask pattern 84 , and a preliminary separation layer 85 may be formed on the substrate 10 .

[0124] A preliminary pattern layer 56 may be formed on the first device isolation layer 11, the mask pattern 84, and the preliminary separation layer 85. For example, the preliminary pattern layer 56 may be formed by a deposition process. The preliminary pattern layer 56 may include, for example, silicon oxycarbonitride or silicon carbonitride.

[0125] Reference Fig.18A and Fig.18B , the initial pattern layer 56 may be etched. The initial pattern layer 56 may be etched into a plurality of intermediate dielectric patterns 55.

[0126] Reference Fig.19 , the second device isolation layer 12 may be formed. The initial separation layer 85 may be etched to form the second device isolation layer 12. Since the intermediate dielectric pattern 55 is disposed on the first device isolation layer 11, the device isolation layer may not etch the first device isolation layer 11 in a process for forming the second device isolation layer 12. The mask pattern 84 may be removed.

[0127] Reference Fig. 20Aand Fig. 20B , a first lower dielectric pattern 61, a second lower dielectric pattern 62, a third lower dielectric pattern 63, and a fourth lower dielectric pattern 64 may be formed. A first gate sacrificial layer 71, a second gate sacrificial layer 72, a gate mask pattern 73, and an initial gate spacer layer 74 may be formed. The first gate sacrificial layer 71 may contact the top surface of the intermediate dielectric pattern 55. The initial gate spacer layer 74 may contact the top surface of the intermediate dielectric pattern 55.

[0128] Reference Fig.21A , Fig.21B and Fig. 21C , the initial gate spacer layer 74 may be etched. The etching of the initial gate spacer layer 74 may form a gate spacer GS. Etching the initial gate spacer layer 74 may include etching the second semiconductor layer 82 and the third semiconductor layer 83, and a portion of the intermediate dielectric pattern 55 may be exposed between the gate spacers GS.

[0129] The second and third semiconductor layers 82 and 83 and the intermediate dielectric pattern 55 may be etched. A portion of the second and third semiconductor layers 82 and 83 and the intermediate dielectric pattern 55 exposed between the gate spacers GS may be removed. One second semiconductor layer 82 may be divided into a plurality of semiconductor sacrificial patterns 88. One third semiconductor layer 83 may be divided into a plurality of semiconductor patterns SP1, SP2, SP3, and SP4.

[0130] The intermediate dielectric pattern 55 may be etched to define a first top surface 55_T1 and a second top surface 55_T2 of the intermediate dielectric pattern 55 , and also to define a first portion 55_1 and a second portion 55_2 of the intermediate dielectric pattern 55 .

[0131] Reference Fig.22A , Fig. 22B and Fig. 22C , a dielectric liner 75 may be formed. The dielectric liner 75 may be formed on the second device isolation layer 12, the first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63 and the fourth lower dielectric pattern 64, the intermediate dielectric pattern 55 and the gate spacer GS.

[0132] A gap-filling layer 76 may be formed. The gap-filling layer 76 may be formed on the dielectric liner 75.

[0133] Reference Fig.23A and Fig. 23B , a separation dielectric layer 20 may be formed. The separation dielectric layer 20 may pass through the gate mask pattern 73 , the second gate sacrificial layer 72 , the first gate sacrificial layer 71 , the intermediate dielectric pattern 55 , and the dielectric liner 75 .

[0134] The formation of the separation dielectric layer 20 may include: forming a groove passing through the gate mask pattern 73, the second gate sacrificial layer 72, the first gate sacrificial layer 71, the intermediate dielectric pattern 55 and the dielectric liner 75; and forming the separation dielectric layer 20 filling the groove. The formation of the separation dielectric layer 20 may divide one intermediate dielectric pattern 55 into two intermediate dielectric patterns 55. The two intermediate dielectric patterns 55 may contact the separation dielectric layer 20.

[0135] Reference Fig.24A and Fig. 24B , the gap-filling layer 76 and the dielectric liner 75 may be removed. A first lower source / drain pattern LSD1, a second lower source / drain pattern LSD2, a third lower source / drain pattern LSD3, and a fourth lower source / drain pattern LSD4 may be formed.

[0136] A lower capping dielectric layer 51 may be formed. The formation of the lower capping dielectric layer 51 may include: forming an initial lower capping dielectric layer on the second device isolation layer 12, the first lower dielectric pattern 61, the second lower dielectric pattern 62, the third lower dielectric pattern 63, and the fourth lower dielectric pattern 64, the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4, the semiconductor sacrificial pattern 88, and the intermediate sacrificial pattern 55; and etching the initial lower capping dielectric layer to expose the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4, the semiconductor sacrificial pattern 88, and the intermediate sacrificial pattern 55.

[0137] A first upper source / drain pattern USD1, a second upper source / drain pattern USD2, a third upper source / drain pattern USD3, and a fourth upper source / drain pattern USD4 may be formed. An upper capping dielectric layer 52 may be formed on the first upper source / drain pattern USD1, the second upper source / drain pattern USD2, the third upper source / drain pattern USD3, and the fourth upper source / drain pattern USD4. A dielectric layer 13 may be formed on the lower capping dielectric layer 51 and the upper capping dielectric layer 52.

[0138] Reference Fig.25A and Fig.25B , the gate mask pattern 73 , the second gate sacrificial layer 72 , the first gate sacrificial layer 71 , and the semiconductor sacrificial pattern 88 may be removed.

[0139] The gate dielectric layer GI, the gate electrodes GE1 , GE2 , GE3 , and GE4 , and the gate capping pattern GP may be formed in an empty space formed by removing the gate mask pattern 73 , the second gate sacrificial layer 72 , the first gate sacrificial layer 71 , and the semiconductor sacrificial pattern 88 .

[0140] Reference Fig.16A , Fig. 16B and Fig. 16C , a gate contact 45 and an active contact 41 may be formed. The gate contact 45 may be formed through the capping pattern GP to contact the gate electrodes GE1, GE2, GE3, and GE4. The active contact 41 may be formed through the dielectric layer 13 to contact the first upper source / drain pattern USD1, the second upper source / drain pattern USD2, the third upper source / drain pattern USD3, and the fourth upper source / drain pattern USD4.

[0141] In a method of manufacturing a semiconductor device according to some embodiments, with the formation of the intermediate dielectric pattern 55 and the subsequent formation of the separation dielectric layer 20 , the semiconductor pattern may have a relatively uniform width.

[0142] Fig.26A and Fig.26B A cross-sectional view showing a semiconductor device according to some embodiments is shown. Fig.26A Corresponds to Fig.16A . Fig.26B Corresponds to Fig. 16B In addition to the following, Fig.26A and Fig.26B The semiconductor device can be similar to FIG. 16A to FIG. 16D semiconductor device.

[0143] Reference Fig.26A and Fig.26B , a lower portion of the separation dielectric layer 20 may be disposed in the intermediate dielectric pattern 55. The bottom surface 20_B of the separation dielectric layer 20 may be disposed in the intermediate dielectric pattern 55. One of the intermediate dielectric patterns 55 may contact the first and second semiconductor patterns SP1 and SP2 and the first and second upper source / drain patterns USD1 and USD2, and the other of the intermediate dielectric patterns 55 may contact the third and fourth semiconductor patterns SP3 and SP4 and the third and fourth upper source / drain patterns USD3 and USD4.

[0144] The bottom surface 20_B of the separation dielectric layer 20 may be located at a lower level than the levels of the first top surface 55_T1 and the second top surface 55_T2 of the intermediate dielectric pattern 55. The bottom surface 20_B of the separation dielectric layer 20 may be located at a higher level than the level of the bottom surface 55_B of the intermediate dielectric pattern 55.

[0145] In a semiconductor device according to some embodiments of the inventive concept, since a semiconductor pattern may have a relatively uniform width, the semiconductor device may have improved electrical characteristics.

[0146] In a method of manufacturing a semiconductor device according to some embodiments of the inventive concept, since a gate spacer layer may be formed and then a separation dielectric layer may be formed, the semiconductor device may have improved electrical characteristics.

[0147] Although some embodiments of the present invention are discussed with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are only illustrative and not restrictive in all aspects.

Claims

1. A semiconductor device comprising: a first active pattern; a second active pattern spaced apart from the first active pattern by a first distance; a third active pattern spaced apart from the second active pattern by a second distance; a first device isolation layer between the first active pattern and the second active pattern; a second device isolation layer between the second active pattern and the third active pattern; a first channel structure overlapping the first active pattern; a second channel structure overlapping the second active pattern; a third channel structure overlapping the third active pattern; as well as a separation dielectric layer between the first channel structure and the second channel structure, Wherein, the second active pattern is between the first active pattern and the third active pattern, wherein the first distance is smaller than the second distance, wherein the separation dielectric layer overlaps with the first device isolation layer, and The top surface of the first device isolation layer has a higher level than the top surface of the second device isolation layer.

2. The semiconductor device according to claim 1, wherein A level of a bottom surface of the separation dielectric layer is lower than a level of a top surface of the first device isolation layer.

3. The semiconductor device according to claim 1, wherein The level of the bottom surface of the separation dielectric layer is higher than the level of the bottom surface of the first device isolation layer.

4. The semiconductor device according to claim 1, wherein The separation dielectric layer and the first device isolation layer include dielectric materials different from each other.

5. The semiconductor device according to claim 1, further comprising: a first gate electrode overlapping the first channel structure; as well as A first upper source / drain pattern connected to the first channel structure, wherein The top surface of the first device isolation layer includes a first top surface and a second top surface, The first top surface of the first device isolation layer overlaps with the first gate electrode, The second top surface of the first device isolation layer overlaps with the first upper source / drain pattern, The first top surface of the first device isolation layer has a higher level than the second top surface of the first device isolation layer.

6. The semiconductor device according to claim 5, further comprising: a gate dielectric layer between the first top surface of the first device isolation layer and the first gate electrode; as well as a lower covering dielectric layer between the second top surface of the first device isolation layer and the first upper source / drain pattern, wherein the first top surface of the first device isolation layer contacts the gate dielectric layer, and Wherein, the second top surface of the first device isolation layer contacts the lower covering dielectric layer.

7. The semiconductor device according to claim 1, wherein The width of the first device isolation layer is greater than the width of the separation dielectric layer.

8. The semiconductor device according to claim 1, further comprising: a gate electrode overlapping the first channel structure, Wherein, the first channel structure includes a plurality of semiconductor patterns overlapping each other, wherein the first portion of the gate electrode is between the plurality of semiconductor patterns, and The second portion of the gate electrode is between the plurality of semiconductor patterns and the separation dielectric layer.

9. The semiconductor device according to claim 1, further comprising: an intermediate dielectric pattern between the first channel structure and the separation dielectric layer, The bottom surface of the intermediate dielectric pattern has a higher level than the bottom surface of the separation dielectric layer.

10. A semiconductor device comprising: a first active pattern and a second active pattern, the first active pattern and the second active pattern being adjacent to each other; a device isolation layer between the first active pattern and the second active pattern; a first channel structure overlapping the first active pattern; a second channel structure overlapping the second active pattern; a first gate electrode overlapping the first channel structure; a second gate electrode overlapping the second channel structure; as well as a separation dielectric layer between the first channel structure and the second channel structure and between the first gate electrode and the second gate electrode, Wherein, the level of the bottom surface of the separation dielectric layer is lower than the level of the top surface of the device isolation layer.

11. The semiconductor device according to claim 10, wherein The level of the bottom surface of the separation dielectric layer is higher than the level of the bottom surface of the device isolation layer.

12. The semiconductor device according to claim 10, wherein: The first channel structure includes a plurality of semiconductor patterns overlapping each other, A first portion of the first gate electrode is between the plurality of semiconductor patterns, and A second portion of the first gate electrode is between the plurality of semiconductor patterns and the separation dielectric layer.

13. The semiconductor device according to claim 12, wherein: The second portion of the first gate electrode overlaps the device isolation layer.

14. The semiconductor device according to claim 10, wherein: The device isolation layer includes a first portion and a plurality of second portions protruding from the first portion, and A width of the first portion of the device isolation layer is greater than a width of each of the plurality of second portions of the device isolation layer.

15. The semiconductor device according to claim 14, wherein: The plurality of second portions of the device isolation layer are spaced apart from one another.

16. The semiconductor device according to claim 10, further comprising: an intermediate dielectric pattern between the first channel structure and the separation dielectric layer, wherein the intermediate dielectric pattern includes a first portion and a second portion protruding from the first portion, A width of the first portion of the intermediate dielectric pattern is greater than a width of the second portion of the intermediate dielectric pattern.

17. The semiconductor device according to claim 16, further comprising: an upper source / drain pattern in contact with a top surface of the second portion of the intermediate dielectric pattern and a sidewall of the second portion of the intermediate dielectric pattern, wherein The upper source / drain pattern contacts a sidewall of the separation dielectric layer.

18. The semiconductor device according to claim 17, wherein: A top surface of the second portion of the intermediate dielectric pattern is connected to a sidewall of the separation dielectric layer.

19. A semiconductor device comprising: a first active pattern and a second active pattern, the first active pattern and the second active pattern being adjacent to each other; a device isolation layer between the first active pattern and the second active pattern; a first channel structure overlapping the first active pattern; a second channel structure overlapping the second active pattern; a first gate electrode overlapping the first channel structure; a second gate electrode overlapping the second channel structure; a first upper source / drain pattern connected to the first channel structure; a second upper source / drain pattern connected to the second channel structure; a first lower dielectric pattern between the first channel structure and the first active pattern; a second lower dielectric pattern between the second channel structure and the second active pattern; as well as a separation dielectric layer between the first channel structure and the second channel structure, between the first gate electrode and the second gate electrode, between the first upper source / drain pattern and the second upper source / drain pattern, and between the first lower dielectric pattern and the second lower dielectric pattern, wherein the separation dielectric layer overlaps the device isolation layer, and The separation dielectric layer and the device isolation layer include dielectric materials different from each other.

20. The semiconductor device according to claim 19, wherein The separation dielectric layer comprises silicon nitride, and The device isolation layer includes silicon oxide.

Images