A vertical chip and a manufacturing method thereof

Abstract

The application provides a vertical chip and a manufacturing method thereof. The method comprises the following steps: providing an epitaxial wafer substrate, the epitaxial wafer substrate comprising a substrate, a metal bonding layer and an epitaxial layer which are sequentially stacked on the substrate; performing a patterning process on the epitaxial layer to form a plurality of independent LED epitaxial layers on the metal bonding layer; depositing a first passivation layer, so that the first passivation layer at least covers the sidewalls of the LED epitaxial layers and exposes the metal bonding layer on the channel between adjacent LED epitaxial layers; etching the exposed metal bonding layer on the channel, so that the etched metal is adhered to the first passivation layer to form a light isolation layer; and depositing a second passivation layer, so that the second passivation layer covers the light isolation layer. The exposed metal bonding layer on the channel is etched, so that the etched metal is adhered to the first passivation layer and surrounds the sidewalls of the LED epitaxial layers to form light isolation. The manufacturing process of the light isolation and the light isolation material are saved, and the chip manufacturing cost is greatly reduced.

Description

Technical Field

[0001] This application relates to the field of chip fabrication technology, and more particularly to a vertical chip and a method for fabricating the same. Background Technology

[0002] Currently, the main application scenarios for Micro-LED are concentrated in AR glasses. AR glasses require the fabrication of higher resolution displays in a small area. As the required display area becomes smaller and smaller, the spacing between chips also decreases. The light interference on the pixels becomes increasingly important. Therefore, it is necessary to fill the gaps between pixels with light-isolating materials to solve the problem of light interference.

[0003] However, most existing optical isolation materials use metal and black glue (such as gold and black glue), and the cost of metal and black glue is extremely high, which will increase the manufacturing cost of the chip.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a vertical chip and a method for manufacturing the same, which forms an optical isolation layer by etching metal on a substrate and then re-adheding the etched metal onto a first passivation layer. This layer surrounds the sidewall of the LED epitaxial layer, saving the optical isolation process and material, and greatly reducing the chip manufacturing cost.

[0006] The technical solution of this application is as follows:

[0007] A method for fabricating a vertical chip, wherein the method includes the following steps:

[0008] An epitaxial wafer substrate is provided, the epitaxial wafer substrate comprising a substrate, and a metal bonding layer and an epitaxial layer sequentially stacked on the substrate;

[0009] The epitaxial layer is patterned to form multiple independent LED epitaxial layers on the metal bonding layer;

[0010] A first passivation layer is deposited such that the first passivation layer at least covers the sidewalls of the LED epitaxial layer and exposes the metal bonding layer in the passage between adjacent LED epitaxial layers.

[0011] The exposed metal bonding layer on the passageway is etched so that the etched metal adheres back to the first passivation layer to form an optical isolation layer.

[0012] A second passivation layer is deposited, thereby covering the optical isolation layer.

[0013] With the above solution, multiple independent LED epitaxial layers are connected to the substrate through a metal bonding layer. By etching the exposed metal bonding layer in the etching channel, the etched metal adheres to the first passivation layer and surrounds the sidewall of the LED epitaxial layer to form optical isolation. This saves on the optical isolation manufacturing process and optical isolation materials, and greatly reduces the chip manufacturing cost.

[0014] In one embodiment, the step of etching the exposed metal bonding layer on the passageway, such that the etched metal adheres back to the first passivation layer to form a photoisolation layer, includes:

[0015] The exposed metal bonding layer on the passage is etched by ion beam etching, so that the metal of the metal bonding layer is sputtered and re-adhered to the first passivation layer.

[0016] The re-adhesion metal of the first passivation layer is modified to form the optical isolation layer on the first passivation layer.

[0017] The above scheme involves etching the exposed metal bonding layer on the ion beam etching channel, causing the etched metal to be re-adhered to the first passivation layer of the LED epitaxial layer, and then modifying the re-adhered metal to achieve optical isolation on the first passivation layer of the LED epitaxial layer.

[0018] In one embodiment, the step of etching the exposed metal bonding layer on the channel by ion beam etching, such that the metal of the metal bonding layer is sputtered and re-adhered to the first passivation layer, includes:

[0019] The epitaxial substrate is mounted such that it is placed on the ion beam etching stage;

[0020] The tilt angle of the etching stage is adjusted for the first time so that the ion beam etched by the ion beam has a first incident angle with the epitaxial substrate.

[0021] The metal bonding layer exposed on the passageway is etched using the ion beam at the first incident angle, such that the etched metal is sputtered and re-adhered to the first passivation layer.

[0022] By using the above method, the epitaxial substrate is mounted on the etching stage, and the tilt angle of the etching stage can be adjusted so that the ion beam and the epitaxial substrate have a certain tilt angle, so that the ion beam can not only etch the metal bonding layer on the channel, but also allow the etched metal to be sputtered back onto the first passivation layer.

[0023] In one embodiment, the step of modifying the re-adhesion metal of the first passivation layer to form the optical isolation layer on the first passivation layer includes:

[0024] The tilt angle of the etching stage is adjusted a second time so that the ion beam etched by the ion beam has a second incident angle with the epitaxial substrate;

[0025] The ion beam is used to modify the re-adhesive metal of the first passivation layer at the second incident angle, so as to form a smooth and flat optical isolation layer in the first passivation layer.

[0026] By adjusting the tilt angle of the etching stage, the ion beam can be used to modify the re-adhesive metal on the first passivation layer, thereby forming a smooth and flat optical isolation layer around the LED epitaxial layer.

[0027] In one embodiment, in the step of etching the exposed metal bonding layer on the passageway using the ion beam at the first incident angle, such that the etched metal is sputtered and re-adhered to the first passivation layer, the metal bonding layer comprises one of the following metals:

[0028] Cr, Pt, Ti, Au, Sn, Ni or Al;

[0029] The thickness of the metal bonding layer is 0.5-0.9 μm.

[0030] The above scheme ensures that the sputtered metal can form optical isolation and achieve a certain height of optical isolation. When the thickness of the metal bonding layer is 0.5-0.9 μm, the height of the optical isolation layer can be ensured to be between the multi-quantum well layer and the second semiconductor layer, so as to achieve a better optical isolation effect.

[0031] In one embodiment, in the step of etching the metal bonding layer exposed on the passageway using the ion beam at the first incident angle, such that the etched metal is sputtered and re-adheded onto the first passivation layer, the epitaxial layer includes at least a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer stacked sequentially.

[0032] The height of the optical isolation layer is at least not lower than that of the multiple quantum well layer, and the height of the optical isolation layer is not higher than that of the second semiconductor layer.

[0033] Through the above scheme, the metal bonding layer can be made of Cr, Pt, Ti, Au, Sn, Ni or Al, and the thickness of the metal bonding layer can be 0.5-0.9 μm. By using ion beam etching on the metal bonding layer, the metal bonding layer can form optical isolation on the first passivation layer. The height of the optical isolation should not be lower than the multi-quantum well layer and should not be higher than the height of the second semiconductor layer.

[0034] In one embodiment, the height of the optical isolation layer is 0.7-1.3 μm.

[0035] With the above scheme, the height of the optical isolation layer is 0.7-1.3 μm. 0.7 μm can be understood as the preferred height of the multiple quantum well layer, and 1.3 μm can be understood as the preferred height of the second semiconductor layer.

[0036] In one embodiment, in the step of modifying the re-adhesion metal of the first passivation layer with the ion beam at the second incident angle to form a smooth and flat optical isolation layer in the first passivation layer, the first incident angle ranges from 90 to 110° and the etching time of the ion beam is 25 to 35 minutes; the second incident angle ranges from 150 to 170° and the modification time of the ion beam is 4 to 6 minutes.

[0037] The above scheme adjusts the tilt angle of the etching stage to 90-110° between the ion beam and the epitaxial substrate, enabling the ion beam to etch the metal bonding layer on the epitaxial substrate and allowing the etched metal to adhere back onto the first passivation layer. Adjusting the tilt angle of the etching stage to 150-170° between the ion beam and the epitaxial substrate allows the ion beam to modify the adhered metal.

[0038] In one embodiment, in the step of modifying the re-adhesive metal of the first passivation layer with the ion beam at the second incident angle to form a smooth and flat optical isolation layer in the first passivation layer, the type of the ion beam includes one of the following:

[0039] Gallium ion beam, helium ion beam, neon ion beam, or argon ion beam;

[0040] When the ion beam is an argon ion beam, the etching energy of the ion beam is 450-550 mJ; the accelerating voltage of the ion beam is 280-320 V; and the ion beam current is 130-170 mA.

[0041] The above scheme allows for the etching of metals using any of the following ion beams: gallium ion beam, helium ion beam, neon ion beam, or argon ion beam. When using an argon ion beam, the above parameters are used to give it a certain energy, which is then directed at the surface of the metal bonding layer to strike its surface atoms, causing sputtering of the bonded metal atoms and achieving the purpose of re-adhesion, thereby forming an optical isolation layer on the first passivation layer.

[0042] In one embodiment, after the step of depositing the second passivation layer to cover the optical isolation layer, the method further includes:

[0043] The second passivation layer is patterned so that the LED epitaxial layer exposes the electrode position;

[0044] Electrodes are deposited at the electrode locations.

[0045] The above method can form a coating around the optical isolation layer and expose the electrode positions. By evaporating the electrodes, the epitaxial layers of each LED can be connected in parallel to form a parallel array, which can improve the luminous efficiency and be used to make a higher resolution display screen.

[0046] This application also provides a vertical chip, comprising:

[0047] A substrate, wherein the substrate includes multiple independent light-emitting units;

[0048] The light-emitting unit includes a metal bonding layer, an LED epitaxial layer, a first passivation layer, a light-isolating layer, and a second passivation layer, which are sequentially stacked on the substrate.

[0049] The metal bonding layer is located between the LED epitaxial layer and the substrate;

[0050] The first passivation layer at least covers the sidewalls of the LED epitaxial layer;

[0051] The optical isolation layer is connected to the metal bonding layer, surrounds the sidewall of the LED epitaxial layer, and adheres to the first passivation layer;

[0052] The second passivation layer covers the optical isolation layer.

[0053] With the above solution, multiple independent LED epitaxial layers are connected to the substrate through a metal bonding layer. The metal bonding layer exposed on the etching channel can be used to make the etched metal adhere to the first passivation layer and surround the sidewall of the LED epitaxial layer to form optical isolation. This saves the optical isolation manufacturing process and optical isolation materials, and greatly reduces the chip manufacturing cost.

[0054] This application discloses a vertical chip and its fabrication method. The method includes: providing an epitaxial substrate, the epitaxial substrate including a substrate, and a metal bonding layer and an epitaxial layer sequentially stacked on the substrate; patterning the epitaxial layer to form multiple independent LED epitaxial layers on the metal bonding layer; depositing a first passivation layer such that the first passivation layer covers at least the sidewalls of the LED epitaxial layers and exposes the metal bonding layer in the passages between adjacent LED epitaxial layers; etching the exposed metal bonding layer in the passages such that the etched metal adheres to the first passivation layer to form an optical isolation layer; and depositing a second passivation layer such that the second passivation layer covers the optical isolation layer. This application etches the exposed metal bonding layer in the passages such that the etched metal adheres to the first passivation layer and surrounds the sidewalls of the LED epitaxial layers to form optical isolation, saving the optical isolation fabrication process and material, and significantly reducing chip manufacturing costs. Attached Figure Description

[0055] Figure 1 This is a schematic diagram illustrating the fabrication process of a vertical chip according to an embodiment of this application;

[0056] Figure 2 This is a schematic diagram of the metal etching process for a vertical chip according to an embodiment of this application;

[0057] Figure 3 This is a flowchart illustrating a specific embodiment of the vertical chip in this application.

[0058] Figure 4 This is a schematic diagram of the epitaxial substrate in a vertical chip according to an embodiment of this application;

[0059] Figure 5 This is a schematic diagram of the LED epitaxial structure in the vertical chip according to an embodiment of this application;

[0060] Figure 6 This is a schematic diagram showing the connection between the LED epitaxial layer and the first passivation layer in the vertical chip of this application embodiment;

[0061] Figure 7 This is a schematic diagram of the assembly structure of the optical isolation layer and the first passivation layer in the vertical chip of this application embodiment;

[0062] Figure 8 This is a schematic diagram of the assembly structure of the optical isolation layer and the LED epitaxial layer in the vertical chip of this application embodiment;

[0063] Figure 9 This is a schematic diagram showing the connection between the LED epitaxial layer and the second passivation layer in the vertical chip of this application embodiment;

[0064] Figure 10 This is a schematic diagram of the structure of the vertical chip according to an embodiment of this application;

[0065] Figure 11 This is a schematic diagram showing the connection between the Si substrate and the epitaxial wafer in a vertical chip according to an embodiment of this application;

[0066] Figure 12 This is a schematic diagram of the metal bonding state of the epitaxial substrate in the vertical chip of this application embodiment.

[0067] The labels in the diagram are as follows:

[0068] 10a, Epitaxial substrate; 10b, Epitaxial wafer; 10, Substrate; 20, Metal bonding layer; 30, Epitaxial layer; 40, LED epitaxy; 50, First passivation layer; 60, Optical isolation layer; 70, Second passivation layer; 80, Electrode; 81, Electrode position; 21, First metal layer; 22, Second metal layer; 31, First semiconductor layer; 32, Multiple quantum well layer; 33, Second semiconductor layer; 34, Third semiconductor layer; 41, Channel. Detailed Implementation

[0069] This application provides a vertical chip and a method for fabricating the same. To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description is provided with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0070] like Figure 1 As shown in the figure, this embodiment provides a method for fabricating a vertical chip, which includes the following steps:

[0071] Step S100, as follows Figure 4 As shown, an epitaxial substrate 10a is provided. The epitaxial substrate 10a includes a substrate 10, and a metal bonding layer 20 and an epitaxial layer 30 sequentially stacked on the substrate 10.

[0072] Step S200, as follows Figure 5 As shown, the epitaxial layer 30 is patterned to form multiple independent LED epitaxial layers 40 on the metal bonding layer 20.

[0073] Step S300, as follows Figure 6 As shown, a first passivation layer 50 is deposited such that the first passivation layer 50 at least covers the sidewalls of the LED epitaxial layer 40 and exposes the metal bonding layer 20 on the passage 41 between adjacent LED epitaxial layers 40.

[0074] Step S400, as follows Figure 7 As shown, the exposed metal bonding layer 20 on the passage 41 is etched so that the etched metal adheres back to the first passivation layer 50 to form an optical isolation layer 60.

[0075] Step S500, as follows Figure 8 and Figure 9 As shown, a second passivation layer 70 is deposited, so that the second passivation layer 70 covers the light isolation layer 60.

[0076] In this embodiment, the epitaxial substrate 10a includes a substrate 10, a metal bonding layer 20, and an epitaxial layer 30. The epitaxial layer 30 is connected to the substrate 10 via the metal bonding layer 20. By patterning the epitaxial layer 30, multiple independent LED epitaxial layers 40 are formed on the metal bonding layer 20. Then, a first passivation layer 50 is deposited on the sidewall of the LED epitaxial layer 40, exposing the metal bonding layer 20 on the channel 41. The exposed metal bonding layer 20 on the channel 41 is then etched, so that the etched metal adheres back to the first passivation layer 50 to form a light-isolating layer 60. This allows the metal bonding layer 20 on the channel 41 to be made into a light-isolating layer to solve the light interference problem of the light-emitting unit. Since the material of the light-isolating layer 60 is taken from the metal bonding layer 20 etched on the channel 41, this embodiment does not require the use of metal and black glue to make light isolation on the sidewall of the LED epitaxial layer 40, which can save light isolation material and save the process of making light isolation separately, and can greatly reduce the chip manufacturing cost.

[0077] Through the above scheme, multiple independent LED epitaxial layers 40 are connected to the substrate 10 through the metal bonding layer 20. By etching the exposed metal bonding layer 20 on the etching channel 41, the etched metal adheres to the first passivation layer 50 and surrounds the sidewall of the LED epitaxial layer 40 to form optical isolation. This saves the optical isolation manufacturing process and optical isolation materials, and greatly reduces the chip manufacturing cost.

[0078] Furthermore, such as Figure 1 As shown, the following steps may also be included after step S500:

[0079] Step S600, as follows Figure 9 As shown, the second passivation layer 70 is patterned so that the LED epitaxial layer 40 exposes the electrode position 81.

[0080] Step S700, as follows Figure 10 As shown, electrode 80 is deposited at electrode position 81.

[0081] In this embodiment, after the second passivation layer 70 is deposited on the optical isolation layer 60, the second passivation layer 70 can be patterned so that the LED epitaxial layer 40 exposes the electrode position 81. Then, the electrode 80 can be deposited at the electrode position 81 so that each LED epitaxial layer 40 is connected in parallel, that is, each LED epitaxial layer 40 shares N electrodes 80 to form a parallel array.

[0082] The above scheme allows for patterning of the second passivation layer 70 and exposure of electrode positions 81 on the LED epitaxial layer 40. By evaporating the electrodes 80, the individual LED epitaxial layers 40 can be connected in parallel to form a parallel array, which can improve luminous efficiency and enable the fabrication of higher resolution displays.

[0083] Specifically, such as Figure 2 As shown, step S400 may include the following steps:

[0084] Step S410: The exposed metal bonding layer 20 on the channel 41 is etched by ion beam etching, so that the metal of the metal bonding layer 20 is sputtered and re-adhered to the first passivation layer 50.

[0085] Step S420: Modify the re-adhesion metal of the first passivation layer 50 to form an optical isolation layer 60 in the first passivation layer 50.

[0086] In this embodiment, the exposed metal bonding layer 20 on the channel 41 can be etched by ion beam first, so that the etched metal is re-adhered to the first passivation layer 50 of the LED epitaxial layer 40. Then, the re-adhered metal can be modified by ion beam to form a smooth and flat light isolation layer 60 on the first passivation layer 50.

[0087] Through the above scheme, the exposed metal bonding layer 20 on the ion beam etching channel 41 is etched so that the etched metal is re-adhered to the first passivation layer 50 of the LED epitaxial layer 40, and the re-adhered metal is modified to achieve optical isolation on the first passivation layer 50 of the LED epitaxial layer 40.

[0088] Specifically, such as Figure 3 As shown, step S410 includes the following steps:

[0089] Step S411: Install the epitaxial substrate 10a so that the epitaxial substrate 10a is placed on the ion beam etching stage.

[0090] Step S412: Adjust the tilt angle of the etching stage for the first time so that the ion beam of the ion beam etching has a first incident angle with the epitaxial substrate 10a.

[0091] Step S413: Use an ion beam to etch the exposed metal bonding layer 20 on the channel 41 at a first incident angle, so that the etched metal is sputtered and re-adhered to the first passivation layer 50.

[0092] By using the above method, the epitaxial substrate 10a is mounted on the etching stage. The tilt angle of the etching stage can be adjusted so that the ion beam and the epitaxial substrate 10a have a certain tilt angle, so that the ion beam can not only etch the metal bonding layer 20 on the channel 41, but also allow the etched metal to be sputtered back onto the first passivation layer 50.

[0093] Specifically, such as Figure 3 As shown, step S410 includes the following steps:

[0094] Step S421: Adjust the tilt angle of the etching stage for the second time so that the ion beam of the ion beam etching has a second incident angle with the epitaxial substrate 10a.

[0095] Step S422: Modify the re-adhesive metal of the first passivation layer 50 using an ion beam at a second incident angle, so as to form a smooth and flat optical isolation layer 60 in the first passivation layer 50.

[0096] By adjusting the tilt angle of the etching stage, the ion beam can be used to modify the re-adhesive metal on the first passivation layer 50, so as to form a smooth and flat light isolation layer 60 around the LED epitaxial layer 40.

[0097] Optionally, the substrate 10 can be a driving substrate (e.g., a CMOS substrate) or other temporary substrates, such as a silicon substrate or sapphire.

[0098] Optionally, the metal bonding layer 20 may include one of the following metals:

[0099] Cr, Pt, Ti, Au, Sn, Ni or Al.

[0100] For example, the metal bonding layer 20 can be Au, that is, the metal bonding layer 20 is made of gold, and is used to connect the substrate 10 and the epitaxial layer 30. The gold exposed on the channel 41 can be etched by ion beam etching, so that the sputtered gold is re-adhered to the first passivation layer 50 to form optical isolation.

[0101] For example, the metal bonding layer 20 can be Ti, meaning it is made of titanium, to connect the substrate 10 and the epitaxial layer 30. The exposed titanium on the channel 41 can be etched using ion beam etching, causing the sputtered titanium to adhere back to the first passivation layer 50 to form optical isolation. It should be understood that the metal of the metal bonding layer 20 is not limited to Cr, Pt, Ti, Au, Sn, Ni, or Al as described above; other metals are also possible and are not limited here.

[0102] Optionally, the thickness of the metal bonding layer 20 is 0.5-0.9 μm.

[0103] In this embodiment, in order to ensure that the sputtered metal can form optical isolation and achieve a certain height of optical isolation, a reasonable thickness of the metal bonding layer 20 needs to be set. For example, a thickness of 0.5-0.9 μm for the metal bonding layer 20 can ensure that the height of the optical isolation layer 60 is between the multi-quantum well layer 32 and the second semiconductor layer 33, thereby achieving a better optical isolation effect.

[0104] Optionally, the epitaxial layer 30 includes at least a first semiconductor layer 31, a multiple quantum well layer 32, and a second semiconductor layer 33 stacked sequentially.

[0105] For example, the epitaxial substrate 10a includes a substrate 10, a metal bonding layer 20, and an epitaxial layer 30. The epitaxial layer 30 includes at least a first semiconductor layer 31, a multiple quantum well layer 32, and a second semiconductor layer 33 stacked sequentially. The first semiconductor layer 31 may be a P-type GaN layer, and the second semiconductor layer 33 may be an N-type GaN layer. That is, the epitaxial layer 30 includes at least a P-type GaN layer, a multiple quantum well layer 32, and an N-type GaN layer stacked sequentially to form a light-emitting unit. For example, the epitaxial layer 30 may also include a first semiconductor layer 31, a multiple quantum well layer 32, a second semiconductor layer 33, and a third semiconductor layer 34 stacked sequentially. For example, the third semiconductor layer 34 may be a U-type GaN layer.

[0106] Optionally, the height of the optical isolation layer 60 is at least not lower than that of the multi-quantum well layer 32, and the height of the optical isolation layer 60 is not higher than that of the second semiconductor layer 33.

[0107] For example, the height of the optical isolation layer 60 is not lower than that of the multiple quantum well layer 32, and the height of the optical isolation layer 60 is not higher than that of the second semiconductor layer 33, in order to ensure the optical isolation effect of the optical isolation layer 60, thereby effectively solving the problem of light interference of the light-emitting unit.

[0108] Through the above scheme, the metal bonding layer 20 can be made of Cr, Pt, Ti, Au, Sn, Ni or Al, and the thickness of the metal bonding layer 20 can be 0.5-0.9 μm. By using ion beam etching on the metal bonding layer 20 in the channel 41, the metal bonding layer 20 can form optical isolation on the first passivation layer 50. The height of the optical isolation is at least not lower than the multi-quantum well layer 32 and not higher than the height of the second semiconductor layer 33, so as to ensure the optical isolation effect of the optical isolation layer 60, thereby effectively solving the problem of light interference of the light-emitting unit.

[0109] Optionally, the height of the optical isolation layer 60 is 0.7-1.3 μm.

[0110] For example, the epitaxial substrate 10a includes a substrate 10, a metal bonding layer 20, a P-type GaN layer, a multiple quantum well layer 32, and an N-type GaN layer.

[0111] With the above scheme, the height of the optical isolation layer 60 is 0.7-1.3 μm. 0.7 μm can be understood as the preferred height of the multi-quantum well layer 32, and 1.3 μm can be understood as the preferred height of the second semiconductor layer 33, so that the optical isolation layer 60 can have a good optical isolation effect and can effectively solve the problem of light interference of the light-emitting unit.

[0112] Preferably, the height of the optical isolation layer 60 can be flush with the height of the second semiconductor layer 33, so that the optical isolation layer 60 has a good optical isolation effect and can effectively solve the problem of light interference from the light-emitting unit. For example, the height of the optical isolation layer 60 is flush with the height of the second semiconductor layer 33 of the epitaxial layer 30, and the height of the optical isolation layer 60 can be set to 1.3 μm.

[0113] Optionally, in step S413, the first incident angle ranges from 90 to 110° and the etching time of the ion beam is 25 to 35 minutes.

[0114] Optionally, in step S422, the second incident angle ranges from 150 to 170°, and the modification time of the ion beam is 4 to 6 minutes.

[0115] By adjusting the tilt angle of the etching stage to make the tilt angle between the ion beam and the epitaxial substrate 10a 90-110°, the ion beam can etch the metal bonding layer 20 on the epitaxial substrate 10a, and the etched metal can be re-adhered to the first passivation layer 50. By adjusting the tilt angle of the etching stage to make the tilt angle between the ion beam and the epitaxial substrate 10a 150-170°, the ion beam can modify the re-adhered metal.

[0116] The types of ion beams include one of the following:

[0117] Gallium ion beam, helium ion beam, neon ion beam, or argon ion beam;

[0118] When the ion beam is an argon ion beam, the etching energy of the ion beam is 450-550 mJ; the accelerating voltage of the ion beam is 280-320 V; and the ion beam current is 130-170 mA.

[0119] The above scheme allows for the etching of metals using any of the following ion beams: gallium ion beam, helium ion beam, neon ion beam, or argon ion beam. When using an argon ion beam, the above parameters are used to give it a certain energy, and the ion beam is then directed at the surface of the metal bonding layer 20 to strike its surface atoms, causing the bonded metal atoms to sputter and achieve the purpose of re-adhesion, thereby forming an optical isolation layer 60 on the first passivation layer 50.

[0120] In one embodiment, the method for fabricating a vertical chip in a specific embodiment of this application includes the following steps:

[0121] S11, such as Figure 11As shown, an epitaxial wafer 10b and a Si substrate are provided, and metal is deposited on the surfaces of the epitaxial wafer 10b and the Si substrate. The epitaxial wafer 10b may include a sapphire substrate and a U-type GaN layer, an N-type GaN layer, a multiple quantum well layer 32 and a P-type GaN layer sequentially stacked on the sapphire substrate. That is, a first metal layer 21 can be deposited on the surface of the Si substrate, and a second metal layer 22 can be deposited on the P-type GaN layer of the epitaxial wafer 10b.

[0122] S12, such as Figure 12 As shown, metal bonding is performed between the epitaxial wafer 10b and the Si substrate, such that the first metal layer 21 on the surface of the Si substrate and the second metal layer 22 on the surface of the epitaxial wafer 10b form a metal bonding layer 20.

[0123] S13, such as Figure 4 As shown, the sapphire substrate on the epitaxial wafer 10b is removed. For example, the sapphire substrate on the epitaxial wafer 10b can be removed by laser lift-off, exposing the U-shaped GaN layer on the epitaxial wafer 10b.

[0124] For example, a solid-state laser lifter can be used to remove the sapphire substrate. The laser wavelength can be 257.5 nm, which removes the non-conductive sapphire substrate and exposes the U-shaped GaN layer.

[0125] S14, such as Figure 4 As shown, the U-type GaN layer on the epitaxial wafer 10b is removed, exposing the N-type GaN layer. The epitaxial wafer 10b and the Si substrate are then bonded together and peeled off to form the epitaxial substrate 10a.

[0126] Since the U-type GaN layer serves as a buffer layer during epitaxial growth and has a relatively high resistance, it needs to be removed to expose the N-type GaN layer, ensuring a total light-emitting layer thickness of 1.2-1.6 μm (i.e., the total thickness of the P-type GaN layer, multiple quantum well layer 32, and N-type GaN layer is 1.2-1.6 μm). Therefore, stripping the sapphire substrate and removing the U-type GaN layer reduces chip voltage and improves chip stability, thus exposing the N-type GaN layer.

[0127] S15, such as Figure 5 As shown, the epitaxial layer 30 is patterned to form multiple independent LED epitaxial layers 40 on the metal bonding layer 20. For example, a BCL can be used. 3 or Cl 2 The epitaxial layer 30 is etched to form multiple independent LED epitaxial layers 40 on the metal bonding layer 20. These LED epitaxial layers 40 form independent light-emitting units, enabling uniform light emission from various locations. The LED epitaxial layers 40 can be angled to facilitate subsequent SiO2 deposition. 2The layer can be inclined at the sidewall of the LED epitaxial layer 40. For example, the inclination angle of the sidewall of the LED epitaxial layer 40 can be 50-75°.

[0128] S16, as Figure 6 As shown, a first passivation layer 50 is deposited on the sidewall of the LED epitaxial layer 40.

[0129] Since a high-power ion beam is required for the subsequent etching of the metal bonding layer 20 on the metal etching channel 41, using a photoresist mask would cause photoresist smearing, which is difficult to remove. Therefore, a hard mask is preferable for the first passivation layer 50. For example, the metal etching method for the metal bonding layer 20 can be IBE etching, ICP etching, or RIE etching. For example, SiO2 with the same thickness as the second semiconductor layer 33 can be deposited. 2 Layer; then can be added to SiO 2 A photoresist layer is applied to form the MESA step and the pattern of the channel 41, exposing the SiO2 layer of the channel 41 of the LED epitaxial layer 40. Then, the SiO2 layer on the channel 41 is etched down to the metal bonding layer 20, exposing the metal bonding layer 20 of the channel 41. After removing the photoresist on the SiO2 layer, the sidewalls of the LED epitaxial layer 40 are covered by the SiO2 layer, and the SiO2 layer on the channel 41 is etched away, exposing the metal bonding layer 20 of the channel 41.

[0130] S17, such as Figure 7 As shown, the metal bonding layer 20 on the channel 41 is etched by ion beam, so that the etched metal adheres back to the first passivation layer 50 to form the optical isolation layer 60.

[0131] For example, the LED epitaxial layer 40 can be first fixed on an etching stage; then the tilt angle of the etching stage can be adjusted so that the tilt angle between the metal bonding layer 20 on the channel 41 and the ion beam is 90-110°. Then, an argon ion beam can be used to etch the metal bonding layer 20 on the channel 41. The etching energy of the argon ion beam can be 450-550 mJ; the accelerating voltage of the argon ion beam can be 280-320 V; and the argon ion beam current can be 130-170 mA. This allows the metal bonding layer 20 on the channel 41 to be sputtered and re-adheded onto the SiO₂ on the LED epitaxial layer 40. 2 On the layer, ensure that the height of the re-adhesive metal is between the multi-quantum well layer 32 and the second semiconductor layer 33, for example, such that the height of the re-adhesive metal is 0.7-1.3 μm; then the tilt angle of the etching stage can be adjusted so that the tilt angle between the epitaxial substrate 10a and the ion beam is 150-170°, and then the re-adhesive metal is modified with an argon ion beam to form a smooth and flat optical isolation layer 60 on the SiO2 layer.

[0132] S18, such as Figure 8 As shown, the first passivation layer 50 is removed.

[0133] For example, SiO₂ on the 40-sided sidewall of the LED epitaxial layer can be chemically etched by immersion in BOE solution. 2 Layers, for example, can be made using aqueous solutions of HF and NH4+. 4 The SiO2 layer on the sidewalls of the LED epitaxial layer can be etched using HF aqueous solution and NH4F in a 1:6 ratio. In this embodiment, the SiO2 layer can be removed from the LED epitaxial layer by chemical wet etching with BOE solution. 2 layer.

[0134] S19, such as Figure 9 As shown, a second passivation layer 70 is deposited, so that the second passivation layer 70 covers the light isolation layer 60.

[0135] For example, the LED epitaxial layer 40 and the photoisolator layer 60 can be insulated by ALD deposition to form a second passivation layer 70 on the LED epitaxial layer 40 and the photoisolator layer 60.

[0136] S20, such as Figure 9 As shown, the second passivation layer 70 is patterned so that the LED epitaxial layer 40 exposes the electrode position 81.

[0137] For example, the second passivation layer 70 can be photolithographically ...

[0138] S21, such as Figure 10 As shown, electrode 80 is deposited at electrode position 81, and LED epitaxial layer 40 is connected in parallel through electrode 80 to form common N electrode 80.

[0139] For example, electrodes 80 can be deposited on the N-type GaN layer of the LED epitaxial layer 40, and the individual LED epitaxial layers 40 can be connected in parallel through the electrodes 80 to form a common N electrode 80, which is used to form a parallel array of LED epitaxial layers 40.

[0140] This application also provides a vertical chip, such as Figure 10 As shown, it is manufactured by the vertical chip manufacturing method described above, which includes: a substrate 10, on which a plurality of independent light-emitting units are included; the light-emitting units include a metal bonding layer 20, an LED epitaxial layer 40, a first passivation layer 50, a light-isolating layer 60, and a second passivation layer 70 sequentially stacked on the substrate 10; the metal bonding layer 20 is located between the LED epitaxial layer 40 and the substrate 10; the first passivation layer 50 at least covers the sidewalls of the LED epitaxial layer 40; the light-isolating layer 60 is connected to the metal bonding layer 20, surrounds the sidewalls of the LED epitaxial layer 40 and is adhered to the first passivation layer 50; the second passivation layer 70 covers the light-isolating layer 60.

[0141] In this embodiment, the light-emitting unit's light-isolating layer 60 is formed by etching the metal bonding layer 20 on the channel 41, and making the etched metal adhere to the first passivation layer 50 and surround the sidewall of the LED epitaxial layer 40 to form light isolation, which effectively solves the problem of light interference, saves the light isolation manufacturing process and light isolation materials, and greatly reduces the chip manufacturing cost.

[0142] Through the above scheme, multiple independent LED epitaxial layers 40 are connected to the substrate 10 through the metal bonding layer 20. The metal bonding layer 20 exposed on the etching channel 41 can be etched so that the etched metal adheres to the first passivation layer 50 and surrounds the sidewall of the LED epitaxial layer 40 to form optical isolation. Optical isolation can effectively solve the problem of light interference. This embodiment saves the optical isolation manufacturing process and optical isolation materials, and greatly reduces the chip manufacturing cost.

[0143] In summary, this application proposes a vertical chip and its fabrication method. The method includes: providing an epitaxial substrate, the epitaxial substrate comprising a substrate, and a metal bonding layer and an epitaxial layer sequentially stacked on the substrate; patterning the epitaxial layer to form multiple independent LED epitaxial layers on the metal bonding layer; depositing a first passivation layer such that the first passivation layer at least covers the sidewalls of the LED epitaxial layers and exposes the metal bonding layer in the passages between adjacent LED epitaxial layers; etching the exposed metal bonding layer in the passages such that the etched metal adheres to the first passivation layer to form an optical isolation layer; and depositing a second passivation layer such that the second passivation layer covers the optical isolation layer. This application, by etching the exposed metal bonding layer in the passages, allows the etched metal to adhere to the first passivation layer and surround the sidewalls of the LED epitaxial layers to form optical isolation, saving on the optical isolation fabrication process and optical isolation material, thus significantly reducing chip manufacturing costs.

[0144] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for fabricating a vertical chip, the method comprising: The method comprises the following steps: providing an epitaxial wafer substrate, the epitaxial wafer substrate comprising a substrate, and a metal bonding layer and an epitaxial layer sequentially stacked on the substrate; patterning the epitaxial layer to form a plurality of independent LED epitaxial layers on the metal bonding layer; depositing a first passivation layer, the first passivation layer covering at least the sidewalls of the LED epitaxial layers and exposing the metal bonding layer on the channel between adjacent LED epitaxial layers; etching the exposed metal bonding layer on the channel to form a light isolation layer by sputtering the etched metal on the first passivation layer; depositing a second passivation layer to cover the light isolation layer.

2. The method of claim 1, wherein the step of forming the through silicon via comprises: forming a first through silicon via in the first die; and forming a second through silicon via in the second die. The step of etching the exposed metal bonding layer on the channel to form a light isolation layer by sputtering the etched metal on the first passivation layer comprises: etching the exposed metal bonding layer on the channel by ion beam etching to sputter and sputter the metal of the metal bonding layer on the first passivation layer; modifying the sputtered metal of the first passivation layer to form the light isolation layer on the first passivation layer.

3. The method of claim 2, wherein the step of forming the through silicon via comprises: forming a first through silicon via in the first die; and forming a second through silicon via in the second die. The step of etching the exposed metal bonding layer on the channel by ion beam etching to sputter and sputter the metal of the metal bonding layer on the first passivation layer comprises: mounting the epitaxial wafer substrate on the etching stage of the ion beam etching; adjusting the inclination angle of the etching stage for the first time to make the ion beam of the ion beam etching have a first incident angle with the epitaxial wafer substrate; etching the exposed metal bonding layer on the channel by the ion beam at the first incident angle to sputter and sputter the etched metal on the first passivation layer.

4. The method of claim 3, wherein the step of forming the through silicon via comprises: forming a first through silicon via in the first die; and forming a second through silicon via in the second die. The step of modifying the sputtered metal of the first passivation layer to form the light isolation layer on the first passivation layer comprises: adjusting the inclination angle of the etching stage for the second time to make the ion beam of the ion beam etching have a second incident angle with the epitaxial wafer substrate; modifying the sputtered metal of the first passivation layer by the ion beam at the second incident angle to form a smooth and flat light isolation layer on the first passivation layer.

5. The method of claim 3, wherein the step of forming the through silicon via comprises: forming a first through silicon via in the first die; and forming a second through silicon via in the second die. In the step of etching the exposed metal bonding layer on the channel by the ion beam at the first incident angle to sputter and sputter the etched metal on the first passivation layer, the metal bonding layer comprises one of the following metals: Cr, Pt, Ti, Au, Sn, Ni or Al; and the thickness of the metal bonding layer is 0.5-0.9um.

6. The method of claim 5, wherein the step of forming the vertical chips is performed by a method comprising: In the step of etching the exposed metal bonding layer on the channel by the ion beam at the first incident angle to sputter and sputter the etched metal on the first passivation layer, the epitaxial layer at least comprises a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer sequentially stacked; the height of the light isolation layer is at least not lower than that of the multiple quantum well layer, and the height of the light isolation layer is not higher than that of the second semiconductor layer.

7. The method of claim 4, wherein the step of forming the vertical chips is performed by a method comprising: The ion beam is used to modify the back-dipped metal of the first passivation layer at the second incident angle, so that in the step of forming a smooth and flat light isolation layer from the first passivation layer, the first incident angle ranges from 90 to 110 degrees and the etching metal time of the ion beam ranges from 25 to 35 minutes; the second incident angle ranges from 150 to 170 degrees, and the modification time of the ion beam ranges from 4 to 6 minutes. ​ 8. The method of claim 4, wherein the step of forming the vertical chip is performed by a method comprising: The type of ion beam used to modify the back-dipped metal of the first passivation layer at the second incident angle includes one of the following: ​ Gallium ion beam, helium ion beam, neon ion beam, or argon ion beam; When the ion beam is an argon ion beam, the etching energy of the ion beam is 450-550 mj; the acceleration voltage of the ion beam is 280-320 V; and the ion beam current is 130-170 mA.

9. The method of claim 1, wherein the vertical chip is formed by a process comprising: The step of depositing a second passivation layer to cover the light isolation layer further includes: Patterning the second passivation layer to expose the electrode position of the LED epitaxial layer; Evaporating an electrode at the electrode position.

10. A vertical chip, characterized by Comprise: A substrate comprising a plurality of independent light emitting units; The light emitting unit comprises a metal bonding layer, an LED epitaxial layer, a first passivation layer, a light isolation layer, and a second passivation layer, which are sequentially stacked on the substrate; The metal bonding layer is located between the LED epitaxial layer and the substrate; The first passivation layer covers at least the sidewall of the LED epitaxial layer; The light isolation layer is connected with the metal bonding layer, surrounds the sidewall of the LED epitaxial layer, and adheres to the first passivation layer; The second passivation layer covers the light isolation layer; The light isolation layer is formed by etching the metal bonding layer on the passageway between adjacent LED epitaxial layers, so that the etched metal is back-dipped on the first passivation layer.

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