Display device

Abstract

A display device is provided. The display device includes: a substrate; a pixel electrode disposed on the substrate; a light emitting element disposed on the pixel electrode and including a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; a connection electrode provided between the pixel electrode and the light emitting element; an adhesive layer disposed between the connection electrode and the pixel electrode; and a common electrode disposed on the light emitting element. The first semiconductor layer includes a body portion adjacent to the active layer and a support portion protruding from the body portion toward the pixel electrode, and the adhesive layer overlaps the support portion of the first semiconductor layer in a horizontal direction of the substrate.

Description

[0001] This application claims priority to and all benefits of Korean Patent Application No. 10-2023-0112044 filed in the Korean Intellectual Property Office on August 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more aspects of an embodiment of the present disclosure relate to a display device. Background Art

[0003] As multimedia technology develops, the importance of display devices has steadily increased. In response to this, various types (or kinds) of display devices such as organic light emitting displays (OLEDs), liquid crystal displays (LCDs), etc. have been utilized.

[0004] The display device is a device for displaying an image, and may include a display panel such as an organic light-emitting display panel and / or a liquid crystal display panel. The light-emitting display panel may include a light-emitting element (e.g., a light-emitting diode (LED)), and examples of the light-emitting diode may include an organic light-emitting diode (OLED) using an organic material as a light-emitting material and an inorganic light-emitting diode using an inorganic material as a light-emitting material. Summary of the invention

[0005] One or more aspects of an embodiment of the present disclosure are directed to a display device having an improved bonding yield between a light emitting element and a pixel electrode.

[0006] One or more aspects of embodiments of the present disclosure also relate to a display device having improved color purity and brightness.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a pixel electrode on the substrate; a light-emitting element on the pixel electrode and including a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a connecting electrode between the pixel electrode and the light-emitting element; an adhesive layer between the connecting electrode and the pixel electrode; and a common electrode on the light-emitting element, wherein the first semiconductor layer includes a main body portion adjacent to the active layer, and a supporting portion protruding from the main body portion toward the pixel electrode, and the adhesive layer overlaps with the supporting portion of the first semiconductor layer in a horizontal direction of the substrate.

[0009] The support portion of the first semiconductor layer may be located adjacent to an edge (eg, a periphery) of the body portion.

[0010] The thickness of the support portion of the first semiconductor layer may be equal to or greater than the thickness of the connection electrode.

[0011] The support portion of the first semiconductor layer may be in contact with the pixel electrode.

[0012] The body portion and the support portion of the first semiconductor layer may be integrated with each other.

[0013] The connection electrode may be surrounded by the support portion (eg, the support portion may be around the connection electrode).

[0014] The support portion of the first semiconductor layer may include a first pillar and a second pillar facing the first pillar, and the adhesive layer and the connection electrode may be between the first pillar and the second pillar of the support portion.

[0015] The first pillar and the second pillar may be spaced apart from each other in plan view.

[0016] The width of the adhesive layer may be greater than the distance between the first pillar and the second pillar.

[0017] A space between the body portion of the first semiconductor layer and the adhesive layer may be empty.

[0018] A space between the body portion of the first semiconductor layer and the adhesive layer may be empty or may include a via layer.

[0019] The cross-section of the support portion of the first semiconductor layer may be square, pentagonal, or hexagonal.

[0020] The bonding layer may comprise solder.

[0021] The pixel electrode may include glass.

[0022] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first pixel electrode on the substrate and including a groove; an adhesive layer on the groove of the first pixel electrode; a connecting electrode on the adhesive layer; a first light-emitting element on the connecting electrode and including a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a common electrode on the first light-emitting element; and a first wavelength conversion layer on the common electrode, the first wavelength conversion layer overlapping the first light-emitting element, wherein the connecting electrode, the first light-emitting element and the first wavelength conversion layer overlap with the groove of the first pixel electrode.

[0023] The width of the adhesive layer may be equal to or greater than the width of the groove of the first pixel electrode.

[0024] The display device may further include: a bank layer on the first pixel electrode, the bank layer not overlapping the groove of the first pixel electrode; and a light blocking layer on the common electrode and overlapping the bank layer.

[0025] The display device may also include: a second pixel electrode on the substrate and separated from the first pixel electrode; a second light-emitting element on the connecting electrode, the second light-emitting element including a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; and a light-transmitting layer on the common electrode and overlapping with the second light-emitting element.

[0026] The first semiconductor layer of the first light emitting element may include a body portion adjacent to the active layer and a support portion protruding from the body portion toward the first pixel electrode, and the support portion may be in contact with the first pixel electrode.

[0027] The supporting portion of the first semiconductor layer may include a first pillar and a second pillar facing the first pillar, and a width of the groove of the first pixel electrode may be equal to or smaller than a distance between the first pillar and the second pillar.

[0028] The display device according to one or more embodiments includes a support portion protruding from the bottom surface of the light emitting element, so that the light emitting element can be stably and properly connected to the pixel electrode without falling. Therefore, the bonding yield of the light emitting element can be improved, and the color purity and brightness can be improved.

[0029] In the display device according to one or more embodiments, since the pixel electrode includes the groove, the contact area between the light emitting element and the adhesive layer is increased, thereby improving the bonding yield of the light emitting element.

[0030] However, the effects according to the embodiments of the present disclosure are not limited to the effects exemplified above, and various other effects are included therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in more detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a perspective view showing a display device according to one or more embodiments;

[0033] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments;

[0034] Figure 4 is shown in more detail Figure 1 A layout diagram of the display area;

[0035] Figure 5 It is shown along Figure 4 A cross-sectional view of one or more embodiments of the display device taken along line II';

[0036] Figure 6 is a perspective view of a light emitting element according to one or more embodiments;

[0037] Figure 7 It is along Figure 6 An enlarged cross-sectional view of the display device taken along line II-II';

[0038] Figure 8 is a perspective view of a light emitting element according to one or more other embodiments;

[0039] Fig. 9 It is along Figure 8 An enlarged cross-sectional view of the display device taken along line III-III';

[0040] Fig.10 It is along Figure 8 An enlarged cross-sectional view of the display device taken along line IV-IV';

[0041] Fig.11 and Fig.12 is an enlarged cross-sectional view of a display device according to one or more embodiments;

[0042] Fig.13 is a cross-sectional view showing a bonding defect in a light emitting element excluding a supporting portion;

[0043] Fig.14 is a cross-sectional view schematically showing a display device according to one or more embodiments;

[0044] Fig.15 yes Fig.14 An enlarged view of region B;

[0045] Fig.16 and Fig.17 is an enlarged view of region B according to one or more embodiments;

[0046] Figures 18 to 30 is a diagram illustrating a method of manufacturing a display device according to one or more embodiments;

[0047] Fig.31 is an exemplary diagram showing a virtual reality device including a display device according to one or more embodiments;

[0048] Fig.32 is an exemplary diagram showing a smart device including a display device according to one or more embodiments;

[0049] Fig.33 is an exemplary diagram showing a portion of a car including a display device according to one or more embodiments; and

[0050] Fig.34is an exemplary diagram illustrating a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0051] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which example embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0052] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate (eg, without any intervening layers therebetween), or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0053] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0054] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0055] It will also be understood that when the terms “include,” “comprises,” and / or variations thereof are used in this specification, it indicates the presence of stated features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0056] As used herein, the term "use" and variations thereof may be considered synonymous with the term "utilize" and variations thereof, respectively.

[0057] As used herein, expressions such as "at least one of", "one of", and "selected from", when preceding / preceding a list of elements, modify the entire list of elements without modifying the individual elements of the list. For example, "at least one of selected from a, b, and c" and "at least one of a, b, and c" may indicate only a, only b, only c, both a and b (e.g., simultaneously), both a and c (e.g., simultaneously), both b and c (e.g., simultaneously), all of a, b, and c, or variations thereof.

[0058] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0059] Furthermore, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.”

[0060] For ease of description, spatially relative terms such as "under," "below," "down," "above," "up," "bottom," "top," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as "under" or "beneath" other elements or features will then be oriented to be "above" or "on" the other elements or features. Therefore, the term "under" can include both above and below orientations. The device can be oriented otherwise (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0061] As used herein, the terms "substantially," "approximately," and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. "Approximately" or "approximately" as used herein include the stated value and mean: within the acceptable range of deviations of the specific value as determined by one of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0062] Any numerical range recorded here is intended to include all sub-ranges of the same numerical precision contained in the range of the record. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 recorded and the maximum value 10.0 recorded (and including the minimum value 1.0 recorded and the maximum value 10.0 recorded), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit recorded here is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to clearly record any sub-range contained in the range clearly described here.

[0063] The electronic device and / or any other related device or component according to the embodiment of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware and hardware. For example, the various components of the device can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of the device can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described here. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as a random access memory (RAM) as an example). The computer program instructions can also be stored in other non-temporary computer-readable media (such as a CD-ROM, a flash drive, etc. as an example). In addition, it should be appreciated by those skilled in the art that, without departing from the scope of the embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed to one or more other computing devices.

[0064] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0065] Figure 1 is a perspective view illustrating a display device according to one or more embodiments.

[0066] Reference Figure 1 The display device 10 is a device for displaying moving images and / or still images. The display device 10 may be used as a display screen of one or more suitable devices such as a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IOT) device, and a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and / or an ultra mobile PC (UMPC).

[0067] The display device 10 may be a light-emitting display device such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro-light-emitting display using a micro light-emitting diode (LED) or a nano light-emitting diode (LED). In the following description, a micro-light-emitting display device is exemplified as the display device 10, but the present disclosure is not limited thereto. To simplify the description, an ultra-small light-emitting diode is hereinafter referred to as a micro-light-emitting diode.

[0068] The display device 10 includes a display panel 100 , a display driving circuit 200 , and a circuit board 300 .

[0069] In a plan view, the display panel 100 may be formed in a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a set or predetermined curvature, or may be a right angle (e.g., a sharp right angle corner). The planar shape of the display panel 100 is not limited to a rectangular shape, and may be formed in another suitable shape such as a polygonal shape, a circular shape, and / or an elliptical shape. The display panel 100 may be formed to be flat (or substantially flat), but is not limited thereto. For example, the display panel 100 may include a curved portion formed at a left end (or left edge) and a right end (or right edge) (e.g., may be curved at the left end (or left edge) and the right end (or right edge), and the curved portion may have a constant curvature or a curvature that varies appropriately). In some embodiments, the display panel 100 may be flexibly formed so that it may be bent, bent, folded, and / or rolled.

[0070] The substrate 110 (see Figure 5 ) may include a main area MA and a sub-area SBA.

[0071] The main area MA may include a display area DA that displays (e.g., is configured to display) an image and a non-display area NDA that is a peripheral area of ​​the display area DA. The display area DA may include a plurality of pixels that display (e.g., is configured to display) an image. For example, a pixel may include a first sub-pixel SPX1 that emits (e.g., is configured to emit) a first light (see Figure 4 ), a second sub-pixel SPX2 (see Figure 4 ), and a third sub-pixel SPX3 (see Figure 4 ).

[0072] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Figure 1 , the sub-region SBA is shown to be unfolded, but in some embodiments, the sub-region SBA may be curved, and in this case, the sub-region SBA may be arranged on the bottom surface of the display panel 100. In the case where the sub-region SBA is curved, the sub-region SBA may overlap the main region MA in the third direction DR3 which is the thickness direction of the display panel 100. The display driving circuit 200 may be arranged in the sub-region SBA.

[0073] The display driving circuit 200 may generate signals and voltages for driving the display panel 100. The display driving circuit 200 may be formed as an integrated circuit (IC) and may be attached to the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, and / or an ultrasonic bonding method, but the present disclosure is not limited thereto. For example, the display driving circuit 200 may be attached to the circuit board 300 by a chip on film (COF) method.

[0074] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. Therefore, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 200. The display panel 100 and the display driving circuit 200 may receive digital video data, timing signals and / or driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board, a printed circuit board and / or a flexible film such as a chip on film.

[0075] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments. Figure 2 exemplarily shows that the sub-area SBA is not bent but unfolded. Figure 3 exemplarily shows that the sub-area SBA is curved.

[0076] Reference Figure 2 and Figure 3 , the display panel 100 may include a main area MA and a sub-area SBA.

[0077] The main area MA may include a display area DA that displays (e.g., is configured to display) an image and a non-display area NDA that is a peripheral area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be disposed at the center of the main area MA (e.g., in the central portion of the main area MA).

[0078] The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be disposed to surround the display area DA. The non-display area NDA may be an edge area of ​​the display panel 100.

[0079] The first scan driver SDC1 and the second scan driver SDC2 may be disposed in the non-display area NDA. The first scan driver SDC1 may be disposed at one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 may be disposed at the other side (e.g., the right side) of the display panel 100, but the present disclosure is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected (e.g., electrically coupled) to the display driving circuit 200 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal input from the display driving circuit 200, generate a scan signal in response to the scan control signal, and output the generated scan signal to the scan line.

[0080] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be substantially equal to or less than the length of the main region MA in the first direction DR1. The sub-region SBA may be foldably disposed under the display panel 100. In some embodiments, the sub-region SBA may overlap the main region MA in the third direction DR3 when bent or folded.

[0081] The sub-area SBA may include a connection area CA, a pad (or referred to as a “pad” or “pad”) area PA, and a bending area BA.

[0082] The connection area CA is an area protruding from one side of the main area MA in the second direction DR2. One side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0083] The pad area PA is an area in which the pad PD and the display driving circuit 200 are disposed. The display driving circuit 200 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA may be in contact with the bending area BA.

[0084] The bending area BA is an area that is bent (e.g., configured to be bent). When the bending area BA is bent, the pad area PA may be disposed below the connection area CA and the main area MA. The bending area BA may be disposed between the connection area CA and the pad area PA. One side of the bending area BA may be in contact with the connection area CA, and the other side of the bending area BA may be in contact with the pad area PA.

[0085] Figure 4is shown in more detail Figure 1 Layout diagram of the display area DA.

[0086] Reference Figure 4 , the display area DA may include a plurality of pixels PX. Each of the plurality of pixels PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0087] A plurality of pixels PX may be arranged in a matrix form. In each of the pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be arranged alternately with each other in the first direction DR1. The first sub-pixel SPX1 may be arranged in the second direction DR2, the second sub-pixel SPX2 may be arranged in the second direction DR2, and the third sub-pixel SPX3 may be arranged in the second direction DR2.

[0088] The first subpixel SPX1 , the second subpixel SPX2 , and the third subpixel SPX3 may include pixel electrodes PE1 , PE2 , and PE3 , respectively, and a plurality of light emitting elements LE.

[0089] In a plan view, the pixel electrodes PE1 , PE2 , and PE3 may have a rectangular shape having short sides extending in the first direction DR1 and long sides extending in the second direction DR2 , but embodiments of the present disclosure are not limited thereto.

[0090] The plurality of light emitting elements LE may emit light in a blue wavelength band, which may be in the range of about 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0091] A plurality of light emitting elements LE may be arranged to overlap the pixel electrodes PE1, PE2, and PE3. The plurality of light emitting elements LE may be spaced apart from each other in the first direction DR1 and the second direction DR2. The light emitting elements LE may be arranged to be aligned in the first direction DR1 and may be arranged to be aligned in the second direction DR2.

[0092] Figure 5 It is shown along Figure 4 FIG. 1 is a cross-sectional view of the embodiment of the display device 10 taken along line II′. Figure 6 is a perspective view of a light emitting element LE according to one or more embodiments. Figure 7 yes Figure 5 An enlarged cross-sectional view of region A, and also along Figure 6 An enlarged cross-sectional view of the display device 10 taken along line II-II′. Figure 8 is a perspective view of a light emitting element LE according to one or more other embodiments. Fig. 9 It is along Figure 8An enlarged cross-sectional view of the display device 10 taken along line III-III'. Fig.10 It is along Figure 8 An enlarged cross-sectional view of the display device 10 taken along line IV-IV′. Fig.11 and Fig.12 is an enlarged cross-sectional view of a display device 10 according to one or more other embodiments. Fig.13 is a cross-sectional view showing a bonding defect in a light emitting element LE not including a supporting portion. Figures 6 to 13 Detailed Description of the Invention In the present invention, the same or similar reference numerals indicate the same or similar components.

[0093] Reference Figure 5 , the display device 10 may include a substrate 110 and a light emitting element portion LEP disposed on the substrate 110. The substrate 110 may be an insulating substrate. The substrate 110 may include a transparent material. For example, the substrate 110 may include a transparent insulating material such as glass, quartz, etc. The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto. The substrate 110 may include a plastic such as polyimide, etc., and may have flexible properties so that it can be twisted, bent, folded and / or curled. A plurality of emission areas EA1, EA2 and EA3 and a non-emission area NEA may be defined in the substrate 110.

[0094] The switching elements T1, T2, and T3 may be placed on the substrate 110. In one or more embodiments, the first switching element T1 may be placed in the first emission area EA1 of the substrate 110, the second switching element T2 may be placed in the second emission area EA2 of the substrate 110, and the third switching element T3 may be placed in the third emission area EA3 of the substrate 110. However, the present disclosure is not limited thereto, and in some embodiments, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be positioned in the non-emission area NEA.

[0095] In one or more embodiments, each of the first switching element T1, the second switching element T2, and the third switching element T3 may be a thin film transistor including amorphous silicon, polycrystalline silicon, and / or an oxide semiconductor. In some embodiments, a plurality of signal lines (e.g., gate lines, data lines, and / or power lines, etc.) that transmit signals to the switching elements may be further placed on the substrate 110.

[0096] Each of the switching elements T1 , T2 , and T3 may include a semiconductor layer 65 , a gate electrode 75 , a source electrode 85 a , and a drain electrode 85 b .

[0097] For example, the buffer layer 60 may be disposed on the substrate 110. The buffer layer 60 may be disposed to cover the entire surface of the substrate 110. The buffer layer 60 may include silicon nitride, silicon oxide, and / or silicon oxynitride, and may be formed as a single layer or a double layer of silicon nitride, silicon oxide, and / or silicon oxynitride (e.g., a double layer including any of the above materials).

[0098] The semiconductor layer 65 may be disposed on the buffer layer 60. The semiconductor layer 65 may form a channel of each of the switching elements T1, T2, and T3, respectively. The semiconductor layer 65 may include amorphous silicon, polycrystalline silicon, and / or an oxide semiconductor. The oxide semiconductor may include, for example, a binary compound (Ab) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (Ab x C y ) and / or quaternary compounds (Ab x C y D z In one or more embodiments, the semiconductor layer 65 may include indium tin zinc oxide (IGZO).

[0099] The gate insulating layer 70 may be disposed on the semiconductor layer 65. The gate insulating layer 70 may include a silicon compound, a metal oxide, etc. For example, the gate insulating layer 70 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. In one or more embodiments, the gate insulating layer 70 may include silicon oxide.

[0100] The gate electrode 75 may be disposed on the gate insulating layer 70. The gate electrode 75 may be disposed to overlap the semiconductor layer 65. The gate electrode 75 may include a conductive material. The gate electrode 75 may include a conductive material such as ITO, IZO, ITZO, and / or In 2 O 3 The gate electrode 75 may be formed of a metal oxide and / or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and / or nickel (Ni). For example, the gate electrode 75 may be formed as a Cu / Ti double layer in which an upper layer made of copper is stacked on a lower layer made of titanium, but the present disclosure is not limited thereto.

[0101] The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be disposed on the gate electrode 75. The first interlayer insulating layer 80 may be disposed directly on the gate electrode 75, and the second interlayer insulating layer 82 may be disposed directly on the first interlayer insulating layer 80. Each of the first interlayer insulating layer 80 and the second interlayer insulating layer 82 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, etc. However, the present disclosure is not limited thereto, and the second interlayer insulating layer 82 may include an organic insulating material capable of flattening (or substantially flattening) a step portion disposed below the second interlayer insulating layer 82. Although two interlayer insulating layers of the first interlayer insulating layer 80 and the second interlayer insulating layer 82 have been shown and described in the given embodiment, the present disclosure is not limited thereto, and only one interlayer insulating layer may be provided.

[0102] The source electrode 85a and the drain electrode 85b may be disposed on the second interlayer insulating layer 82. The source electrode 85a and the drain electrode 85b may contact the semiconductor layer 65 through corresponding contact holes passing through the first interlayer insulating layer 80, the second interlayer insulating layer 82, and the gate insulating layer 70. The source electrode 85a and the drain electrode 85b may include, for example, ITO, IZO, ITZO, and / or In 2 O 3 The source electrode 85a and the drain electrode 85b may be formed as a Cu / Ti double layer in which an upper layer made of copper is stacked on a lower layer made of titanium, but the present disclosure is not limited thereto.

[0103] The first planarization layer 120 may be disposed on the first switching element T1, the second switching element T2, and the third switching element T3. The first planarization layer 120 may include an organic material. For example, the first planarization layer 120 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, etc. In one or more embodiments, the first planarization layer 120 may include a positive photosensitive material and / or a negative photosensitive material.

[0104] The pixel connection electrode 125 may be disposed on the first planarization layer 120. The pixel connection electrode 125 may be disposed corresponding to each of the first switching element T1, the second switching element T2, and the third switching element T3, and may be electrically connected to each of the first switching element T1, the second switching element T2, and the third switching element T3. The pixel connection electrode 125 may connect the pixel electrodes PE1, PE2, and PE3 described in more detail below to the above-mentioned switching elements T1, T2, and T3, respectively. The pixel connection electrode 125 may contact the switching elements T1, T2, and T3 through corresponding contact holes passing through the first planarization layer 120.

[0105] The second planarization layer 130 may be disposed on the first planarization layer 120 and the pixel connection electrode 125. The second planarization layer 130 may planarize (or substantially planarize) a stepped portion disposed below the second planarization layer 130, and may include the same material as that of the first planarization layer 120 described above.

[0106] The light emitting element portion LEP may be disposed on the second planarization layer 130. The light emitting element portion LEP may include a plurality of pixel electrodes PE1, PE2, and PE3, a plurality of light emitting elements LE, and a common electrode CE. In addition, the light emitting element portion LEP may further include a bank layer BNL separating emission areas EA1, EA2, and EA3, and a first via layer VIA1 and a second via layer VIA2.

[0107] The plurality of pixel electrodes PE1, PE2, and PE3 may include a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be used as first electrodes of the corresponding light emitting elements LE, and may be anode electrodes or cathode electrodes. The first pixel electrode PE1 may be located in the first emission area EA1, the second pixel electrode PE2 may be located in the second emission area EA2, and the third pixel electrode PE3 may be located in the third emission area EA3. In some embodiments, the first pixel electrode PE1 may overlap the first emission area EA1, the second pixel electrode PE2 may overlap the second emission area EA2, and the third pixel electrode PE3 may overlap the third emission area EA3.

[0108] The pixel electrodes PE1, PE2 and PE3 may be directly connected to the pixel connection electrode 125 through the corresponding contact holes passing through the second planarization layer 130, and may be electrically connected to the switching elements T1, T2 and T3 through the pixel connection electrode 125, respectively. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may include glass and / or metal. The metal may include, for example, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. In addition, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a multilayer structure in which two or more metal layers are stacked. For example, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a double-layer structure in which a copper layer is stacked on a titanium layer, but the present disclosure is not limited thereto.

[0109] In one or more embodiments, the pixel electrodes PE1, PE2, and PE3 may be glass. When the pixel electrodes PE1, PE2, and PE3 are made of glass, they may be easily or appropriately bonded to the light emitting element LE including a support.

[0110] The bank layer BNL may be arranged to cover the edges of the pixel electrodes PE1, PE2, and PE3. The bank layer BNL may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The bank layer BNL may include a light blocking material to prevent or reduce the light of the light emitting element LE of any one sub-pixel from traveling to an adjacent sub-pixel. For example, the bank layer BNL may contain an organic black pigment such as carbon black and / or an inorganic black pigment.

[0111] The light emitting element LE may be disposed on the pixel electrodes PE1, PE2, and PE3, which are exposed without being covered by the bank layer BNL. One or more light emitting elements LE may be disposed on each of the pixel electrodes PE1, PE2, and PE3.

[0112] like Figure 5 As shown in , the light emitting element LE may be respectively arranged in each of the first emission area EA1, the second emission area EA2 and the third emission area EA3. The light emitting element LE may be a vertical light emitting diode element extending in the third direction DR3. For example, the length of the light emitting element LE in the third direction DR3 may be longer than the length of the light emitting element LE in the horizontal direction. The length in the horizontal direction refers to the length in the first direction DR1 or the length in the second direction DR2. For example, the length of the light emitting element LE in the third direction DR3 may be approximately 1 μm to 5 μm. However, the present disclosure is not limited thereto, and the length of the light emitting element LE in the third direction DR3 may also be equal to or less than the length of the light emitting element LE in the horizontal direction.

[0113] The light emitting element LE may be a micro light emitting diode element. Figure 6 and Figure 7 , the connection electrode 150 and the adhesive layer 160 may be disposed between the light emitting element LE and the corresponding pixel electrodes PE1, PE2, and PE3. The light emitting element LE may include a first semiconductor layer SEM1, an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2 sequentially stacked in the thickness direction (i.e., the third direction DR3) of the substrate 110. The light emitting element LE may include an insulating layer surrounding at least a portion of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 (e.g., around at least a portion of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2).

[0114] The light emitting element LE may have a cylindrical shape, a disk shape, and / or a rod shape whose height is longer than its width. However, the present disclosure is not limited thereto, and the light emitting element LE may have one or more suitable shapes such as a line shape, a tube shape, a polygonal prism shape (such as a regular cube, a cuboid, and / or a hexagonal prism), and / or a shape extending in one direction and having a partially inclined outer surface.

[0115] The first semiconductor layer SEM1 may be disposed on the pixel electrodes PE1, PE2, and PE3 and the connection electrode 150. The first semiconductor layer SEM1 may include a body portion SEM1a disposed adjacent to the active layer MQW and / or the electron blocking layer EBL and a support portion SEM1b protruding from the body portion SEM1a toward the pixel electrodes PE1, PE2, and PE3. The body portion SEM1a may cover the entire contact surface of the electron blocking layer EBL and / or the active layer MQW that contacts the body portion SEM1a.

[0116] The support portion SEM1b may be disposed on an edge of the body portion SEM1a or may be disposed adjacent to an edge of the body portion SEM1a. The support portion SEM1b may contact the pixel electrodes PE1, PE2, and PE3 to support the light emitting element LE so that the light emitting element LE may stand upright in a properly stable state without falling on the pixel electrodes PE1, PE2, and PE3.

[0117] The main body SEM1a and the support part SEM1b of the first semiconductor layer SEM1 may be one main body (eg, may be formed as a whole together) and may include the same material. After forming the first semiconductor layer SEM1, a portion of the first semiconductor layer SEM1 may be etched to form the support part SEM1b. The first semiconductor layer SEM1 may be a p-type semiconductor and may include a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, the first semiconductor layer SEM1 may be any one or more of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer SEM1 may be doped with a p-type dopant, and the p-type dopant may be Mg, Zn, Ca, Ba, etc. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The total thickness of the first semiconductor layer SEM1 may be in the range of 30nm to 200nm, but is not limited thereto.

[0118] The connection electrode 150 may be disposed on the corresponding pixel electrodes PE1, PE2, and PE3, and may be disposed between the light emitting element LE and the corresponding pixel electrodes PE1, PE2, and PE3. For example, the connection electrode 150 may be disposed on the bottom surface of the main body portion SEM1a of the first semiconductor layer SEM1 of the light emitting element LE. The support portion SEM1b of the first semiconductor layer SEM1 may have a thickness equal to or greater than that of the connection electrode 150. In one or more embodiments, the connection electrode 150 may contact the pixel electrodes PE1, PE2, and PE3. In some embodiments, the connection electrode 150 may not contact the pixel electrodes PE1, PE2, and PE3, but may contact the adhesive layer 160.

[0119] In the display panel 100 according to one or more embodiments, when the light emitting element LE is electrically connected to the pixel electrode, the connection electrode 150 can reduce the resistance between the light emitting element LE and the pixel electrode. The connection electrode 150 may include a conductive metal. For example, the connection electrode 150 may include at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag). For example, the connection electrode 150 may include a 9:1 alloy, an 8:2 alloy, and / or a 7:3 alloy of gold and tin and / or may include an alloy of copper, silver, and tin (SAC305).

[0120] In some embodiments, an ohmic contact layer may be further provided on the connection electrode 150. The ohmic contact layer may be provided between the connection electrode 150 and the first semiconductor layer SEM1. The ohmic contact layer may be an ohmic connection electrode. However, the present disclosure is not limited thereto, and the ohmic contact layer may be a Schottky connection electrode. The ohmic contact layer may include ITO. However, it is not limited thereto, and may include at least one selected from gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag), an alloy, and / or a multilayer structure thereof.

[0121] Adhesive layer 160 may be disposed between connection electrode 150 and corresponding pixel electrodes PE1, PE2 and PE3 to physically and electrically connect connection electrode 150 and corresponding pixel electrodes PE1, PE2 and PE3 to each other. Adhesive layer 160 may include a conductive material. In one or more embodiments, adhesive layer 160 may include an anisotropic conductive film and / or solder. Solder may be at least one or an alloy of two or more of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al) and silver (Ag). Here, an example is given of a case where adhesive layer 160 is solder. However, this is only an example, and the present disclosure is not limited thereto. For example, adhesive layer 160 may include an alloy (SAC305) of copper, silver and tin.

[0122] The connection electrode 150 may be melt-bonded to the pixel electrodes PE1, PE2, and PE3 by a welding process of the adhesive layer 160. Because the adhesive layer 160 is melted by laser and / or heat and pressure, it may have an expanded form. In addition, after melting, it may be difficult to clearly or properly distinguish the boundary line between the adhesive layer 160 and the connection electrode 150. However, because the adhesive layer 160 and the first semiconductor layer SEM1 of the light emitting element LE include different materials, they can be distinguished from each other even after melting.

[0123] The adhesive layer 160 and the connecting electrode 150 may overlap with the supporting portion SEM1b of the first semiconductor layer SEM1 in the horizontal direction (e.g., the first direction DR1) of the substrate. The supporting portion SEM1b of the first semiconductor layer SEM1 may be disposed adjacent to the edge (e.g., the periphery) of the main body portion SEM1a. The adhesive layer 160 and the connecting electrode 150 may be disposed adjacent to the center of the main body portion SEM1a compared to the supporting portion SEM1b (e.g., relative to the supporting portion SEM1b). The adhesive layer 160 may be sealed by the supporting portion SEM1b of the first semiconductor layer SEM1, or a portion of the adhesive layer 160 may be detached from the supporting portion SEM1b and further unfolded from the supporting portion SEM1b. A portion of the adhesive layer 160 may not overlap with the main body portion SEM1a of the first semiconductor layer SEM1 in the thickness direction (the third direction DR3) of the substrate.

[0124] Reference Figure 6 and Figure 7 The support portion SEM1b may be disposed on an edge (eg, periphery) of the body portion SEM1a and may be shaped to surround the body portion SEM1a along the edge. The body portion SEM1a may include a curved bottom surface facing the pixel electrodes PE1, PE2, PE3 in a cross-sectional view (see FIG. 2 ). Figure 7 ). However, it is not limited thereto, and may also have a flat (or substantially flat) bottom surface. The thickness of the support portion SEM1b surrounding the body portion SEM1a may be constant (or substantially constant).

[0125] The connection electrode 150 may be surrounded by the support portion SEM1b. The adhesive layer 160 may also be surrounded by the support portion SEM1b. However, when a portion of the solder is squeezed out from the support portion SEM1b during the bonding of the light emitting element LE with the pixel electrodes PE1, PE2, and PE3, a portion of the adhesive layer 160 (e.g., the squeezed portion) may not be surrounded by the support portion SEM1b.

[0126] exist Figure 6 and Figure 7In the embodiment, the lower space of the body portion SEM1a of the first semiconductor layer SEM1 may be surrounded by the support portion SEM1b and the pixel electrodes PE1, PE2 and PE3, and the connection electrode 150 and the adhesive layer 160 may be positioned only therein. The space between the body portion SEM1a of the first semiconductor layer SEM1 and the adhesive layer 160 may be empty.

[0127] Reference Figures 8 to 10 , the support portion SEM1b may include a first column and a second column facing each other. The first column and the second column may be spaced apart from each other in a plan view. The thickness of the first column may be the same as the thickness of the second column.

[0128] Reference Fig. 9 , the adhesive layer 160 and the connection electrode 150 may be disposed between the first pillar and the second pillar. Fig.10 , the separation space between the first column and the second column ( Figure 8 Since there is no support portion between the body portion SEM1a_1 and the corresponding pixel electrodes PE1, PE2, and PE3, the adhesive layer 160 can be widely extended. For example, the width of the adhesive layer 160 in the separation space between the first pillar and the second pillar can be greater than the distance between the first pillar and the second pillar.

[0129] like Figure 8 As shown in , when the support portion SEM1b is configured to have a plurality of pillars, the lower space of the main body portion SEM1a of the first semiconductor layer SEM1 includes an opening portion that is not laterally blocked or surrounded by the support portion SEM1b. The space between the adhesive layer 160 and the main body portion SEM1a of the first semiconductor layer SEM1 may be empty, or a via layer, which will be described in more detail below, may be provided therein.

[0130] Fig.11 is a cross-sectional view of a light emitting element LE according to one or more embodiments. Fig.11 The light emitting element LE and Fig. 9 The light emitting element LE of the first semiconductor layer SEM1 is different in that the cross section of the support portion SEM1b_2 is pentagonal. Here, a portion of the adhesive layer 160 may be further extended from the support portion SEM1b_2. The support portion SEM1b of the first semiconductor layer SEM1 may have any suitable shape as long as it can properly support the light emitting element LE on the corresponding pixel electrodes PE1, PE2, and PE3. In an exemplary embodiment, the cross-sectional shape of the support portion SEM1b may be a polygonal shape such as a square shape, a pentagonal shape, and / or a hexagonal shape.

[0131] Fig.12 is a cross-sectional view of a light emitting element LE according to one or more embodiments. Fig. 9 compared to, Fig.12 The support portion SEM1b_3 of the first semiconductor layer SEM1_3 may be positioned inside the edge of the body portion SEM1a_3 (e.g., inside the periphery of the body portion SEM1a_3) without being aligned with the edge of the body portion SEM1a_3. The position of the support portion SEM1b may be adjusted by adjusting the etching process for forming the support portion SEM1b of the first semiconductor layer SEM1.

[0132] like Fig.13 As shown in , in the case where the light emitting element LE does not include a support portion at its lower portion, if the material of the adhesive layer 160 is not properly aligned with the center of the light emitting element LE, the light emitting element LE may not be properly attached to the pixel electrodes PE1, PE2, and PE3, and the light emitting element LE may fall. Or, for example, the light emitting element LE may be tilted and bonded to the pixel electrodes PE1, PE2, and PE3 in such a tilted arrangement, thereby reducing the light emitting efficiency. When solder is used as the material of the adhesive layer 160, it may be difficult to finely or properly control the size and position of the solder. Therefore, the light emitting element LE may often topple or tilt.

[0133] like Figures 5 to 12 As shown in , in an embodiment where the light emitting element LE includes the support portion SEM1b, even if the alignment of the material of the adhesive layer 160 is biased to one side or the material of the adhesive layer 160 is partially melted, the support portion SEM1b can make the light emitting element LE stand stably or appropriately on the pixel electrodes PE1, PE2 and PE3. The support portion SEM1b can prevent or reduce the expansion of the material of the adhesive layer 160, and thus the material can be concentrated on connecting the connection electrode 150 to the pixel electrodes PE1, PE2 and PE3. In addition, in addition to the main body portion SEM1a, the adhesive layer 160 can also contact the support portion SEM1b, thereby increasing the contact area and improving the adhesion. Therefore, the bonding yield of the light emitting element LE can be improved, and the color purity and brightness of the display panel can be improved.

[0134] Reference Figure 5 and Figure 6 , an electron blocking layer EBL may be disposed on the first semiconductor layer SEM1. The electron blocking layer EBL may be a layer for suppressing or reducing excessive electrons from flowing into the active layer MQW. For example, the electron blocking layer EBL may be AlGaN and / or p-AlGaN doped with p-type Mg. In some embodiments, the electron blocking layer EBL may not be disposed (e.g., may be omitted).

[0135] The active layer MQW may be disposed on the electron blocking layer EBL. The active layer MQW may emit light by recombination of electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light (e.g., light in a blue band) having a central wavelength band of 450 nm to 495 nm.

[0136] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. For example, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN and / or AlGaN, but the present disclosure is not limited thereto. The thickness of the well layer may be about 1 nm to 4 nm, and the thickness of the barrier layer may be 3 nm to 10 nm.

[0137] In some embodiments, the active layer MQW may have a structure in which a semiconductor material having a relatively large energy band gap and a semiconductor material having a relatively small energy band gap are alternately stacked, and may include other suitable III- to V-group semiconductor materials according to the wavelength band of the emitted light. The light emitted by the active layer MQW is not limited to the first light, and in some embodiments, a second light (e.g., light in the green wavelength band) and / or a third light (e.g., light in the red wavelength band) may be emitted. In some embodiments, when the semiconductor material included in the active layer MQW includes indium, the color of the emitted light may vary according to the content (e.g., amount) of indium. For example, when the content of indium is about 15%, light in the blue wavelength band may be emitted, when the content of indium is about 25%, light in the green wavelength band may be emitted, and when the content of indium is about 35% or more, light in the red wavelength band may be emitted.

[0138] The superlattice layer SLT may be disposed on the active layer MQW. The superlattice layer SLT may be a layer for alleviating or reducing stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer SLT may be formed of InGaN and / or GaN. In some embodiments, the superlattice layer SLT may not be disposed (e.g., may be omitted).

[0139] The second semiconductor layer SEM2 may be disposed on the superlattice layer SLT. The second semiconductor layer SEM2 may be an n-type semiconductor. The second semiconductor layer SEM2 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, the semiconductor material may be any one or more of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN and InN. The second semiconductor layer SEM2 may be doped with an n-type dopant, and the n-type dopant may be Si, Ge, Sn, Se, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be in the range of 2μm to 4μm, but the present disclosure is not limited thereto.

[0140] The first via layer VIA1 may be disposed on the pixel electrodes PE1, PE2, and PE3 and the bank layer BNL. The height of the first via layer VIA1 may be less than the height of the light emitting element LE. The first via layer VIA1 may be disposed to correspond to each of the emission areas EA1, EA2, and EA3. For example, the first via layer VIA1 may be disposed in an island pattern shape in each of the emission areas EA1, EA2, and EA3. For example, the first via layer VIA1 disposed in the emission areas EA1, EA2, and / or EA3 may be disposed to be spaced apart from the first via layer VIA1 disposed in the adjacent emission areas EA1, EA2, and / or EA3. A portion of the first via layer VIA1 may be in contact with the bank layer BNL.

[0141] The first via layer VIA1 may include an organic material to planarize (or substantially planarize) a stepped portion disposed below the first via layer VIA1. For example, the first via layer VIA1 may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) resin, etc.

[0142] The second via layer VIA2 may be disposed on the bank layer BNL and the first via layer VIA1. The second via layer VIA2 may cover the first via layer VIA1 and flatten (or substantially flatten) the step portion disposed below the first via layer VIA1 so that a common electrode CE may be formed, which will be described in more detail below. The second via layer VIA2 may include the same organic material as the first via layer VIA1. The second via layer VIA2 may be formed to have a set or predetermined height so that at least a portion of the light emitting element LE (e.g., the second semiconductor layer SEM2) may protrude above the second via layer VIA2. For example, the height of the second via layer VIA2 may be less than the height of the light emitting element LE.

[0143] The second via layer VIA2 may cover and protect the first via layer VIA1 disposed in each of the emission areas EA1, EA2, and EA3. The second via layer VIA2 may be disposed to correspond to each of the emission areas EA1, EA2, and EA3, respectively. For example, the second via layer VIA2 may be disposed in each of the emission areas EA1, EA2, and EA3 in an island pattern shape. For example, the second via layer VIA2 disposed in the emission areas EA1, EA2, and / or EA3 may be disposed to be spaced apart from the second via layer VIA2 disposed in the adjacent emission areas EA1, EA2, and / or EA3.

[0144] The common electrode CE may be disposed on the second via layer VIA2, the bank layer BNL, and the plurality of light emitting elements LE. For example, the common electrode CE may be disposed on one surface of the substrate 110 on which the light emitting elements LE are formed, and may be entirely disposed in the display area DA of the substrate 110. The common electrode CE may be disposed to overlap each of the emission areas EA1, EA2, and EA3 and the non-emission area NEA, and may be formed with an appropriately thin thickness so that light may be appropriately emitted.

[0145] The common electrode CE may be directly disposed on the top surface and the side surface of the plurality of light emitting elements LE. The common electrode CE may be in direct contact with the second semiconductor layer SEM2 exposed on the top surface of the light emitting element LE. Figure 5 As shown in , the common electrode CE may be a common layer that covers the plurality of light emitting elements LE and is provided by connecting the plurality of light emitting elements LE in common. Since the second semiconductor layer SEM2 having conductivity has a patterned structure in each of the light emitting elements LE, the common electrode CE may be in direct contact with the second semiconductor layer SEM2 of each of the light emitting elements LE, so that a common voltage may be applied to each of the light emitting elements LE.

[0146] Since the common electrode CE is entirely disposed on the substrate 110 and a common voltage is applied, the common electrode CE may include a material having a relatively low resistance. For example, the common electrode CE may include a metal material having a relatively low resistance such as aluminum (Al), silver (Ag), copper (Cu), etc. and / or a metal oxide such as ITO, IZO, ITZO, etc. The thickness of the common electrode CE may be about 1000 Å. to But it is not limited to this.

[0147] The above-mentioned light emitting element LE can receive a pixel voltage or an anode voltage from each of the pixel electrodes PE1, PE2 and PE3, and can receive a common voltage through the common electrode CE. The light emitting element LE can emit light with a set or predetermined brightness according to the voltage difference between the pixel voltage and the common voltage. In one or more embodiments, by providing a plurality of light emitting elements LE (e.g., inorganic light emitting diodes) on the pixel electrodes PE1, PE2 and PE3, the disadvantages of organic light emitting diodes that are susceptible to external moisture and / or oxygen can be eliminated or reduced, and the life span and reliability can be improved.

[0148] The light emitting element part LEP may further include a first cover layer CAP1 covering the common electrode CE. The first cover layer CAP1 may be directly disposed on the common electrode CE. The first cover layer CAP1 is used to cover the elements disposed under the first cover layer CAP1 (e.g., the light emitting element LE and the common electrode CE) to protect them from moisture and / or foreign matter.

[0149] The first capping layer CAP1 may include an inorganic material. For example, the first capping layer CAP1 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. The first capping layer CAP1 may be formed as a multilayer in which inorganic layers are alternately stacked, each of which includes at least one of the above-described exemplary materials that may be included in the first capping layer CAP1.

[0150] The wavelength controller WCP may be disposed on the light emitting element part LEP. The wavelength controller WCP may include a wavelength conversion layer QDL, a reflective layer RFL, a light blocking part BM including first and second light blocking layers BM1 and BM2, and a second cover layer CAP2.

[0151] The light blocking part BM may be disposed on the first cover layer CAP1 and may separate the plurality of emission areas EA1, EA2, and EA3. The light blocking part BM may be disposed to extend in the first direction DR1 and the second direction DR2 and may be formed in a grid pattern throughout the display area DA. In some embodiments, the light blocking part BM may not overlap the plurality of emission areas EA1, EA2, and EA3 and may overlap the non-emission area NEA.

[0152] The light blocking part BM may be used to provide a space for forming a wavelength conversion layer QDL. To this end, the light blocking part BM may include a first light blocking layer BM1 and a second light blocking layer BM2 disposed on the first light blocking layer BM1. In order to provide a space for forming the wavelength conversion layer QDL, the light blocking part BM may have a double-layer structure including a first light blocking layer BM1 and a second light blocking layer BM2 to have a relatively large thickness or a suitable thickness. For example, the thickness of the first light blocking layer BM1 and the thickness of the second light blocking layer BM2 may be in the range of 1 μm to 10 μm. The first light blocking layer BM1 and the second light blocking layer BM2 may include an organic insulating material having a relatively large thickness or a suitable thickness. The organic insulating material may include, for example, epoxy resin, acrylic resin, cardo resin and / or imide resin.

[0153] In one or more embodiments, the first light blocking layer BM1 and the second light blocking layer BM2 may block or reduce the transmission of light in the non-emission area NEA. The first light blocking layer BM1 and the second light blocking layer BM2 may also include a light blocking material, and may include a dye and / or a pigment having a light blocking property. For example, the first light blocking layer BM1 and the second light blocking layer BM2 may be a black matrix. External light incident from the outside of the display device 10 may cause distortion of the color reproducibility of the wavelength controller WCP. According to the given embodiment, by providing a light blocking portion BM including a light blocking material in the wavelength controller WCP, at least a portion of the external light is absorbed by the light blocking portion BM. Therefore, the color distortion caused by the reflection of the external light can be reduced. In addition, the light blocking portion BM including a light blocking material can prevent or reduce light penetration and color mixing between adjacent emission areas, which causes further improvement in color reproducibility. In the given embodiment, although the light blocking portion BM including the first light blocking layer BM1 and the second light blocking layer BM2 has been shown and described, the present disclosure is not limited thereto, and the light blocking portion BM may also be formed by a single layer.

[0154] The reflective layer RFL may be disposed on the light blocking part BM. The reflective layer RFL may not overlap the emission areas EA1, EA2, and EA3, and may be disposed to overlap the non-emission area NEA. The reflective layer RFL may be disposed to extend in the first direction DR1 and the second direction DR2, and may be formed in a grid pattern throughout the display area DA. The reflective layer RFL may completely overlap the light blocking part BM.

[0155] The reflective layer RFL may reflect light emitted from the light emitting element LE upward (eg, in the third direction DR3 ). The reflective layer RFL may include a metal material having a relatively high light reflectivity, such as aluminum (Al).

[0156] In one or more embodiments, a wavelength conversion layer QDL may be disposed on each of the emission areas EA1, EA2, and EA3. The wavelength conversion layer QDL may emit light by converting and / or shifting the peak wavelength of the incident light to another set or specific peak wavelength. The wavelength conversion layer QDL may convert the first light emitted from the light emitting element LE as blue light into the second light as red light and / or the third light as green light and / or may transmit the first light as blue light without conversion.

[0157] The wavelength conversion layer QDL may be disposed in each of the emission areas EA1, EA2, and EA3 separated by the light blocking portion BM, and may be disposed to be spaced apart from each other. For example, the wavelength conversion layer QDL may include island patterns spaced apart from each other. The wavelength conversion layer QDL may be disposed to overlap each of the first emission area EA1, the second emission area EA2, and the third emission area EA3. In example embodiments, each of the wavelength conversion layers QDL may completely overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively.

[0158] The wavelength conversion layer QDL may include a first wavelength conversion layer WCL1 overlapping the first emission region EA1 , a second wavelength conversion layer WCL2 overlapping the second emission region EA2 , and a light transmission layer WCL3 overlapping the third emission region EA3 .

[0159] The first wavelength conversion layer WCL1 may be disposed to overlap with the first emission area EA1. The first wavelength conversion layer WCL1 may emit light by converting and / or shifting the peak wavelength of the incident light to another set or specific peak wavelength. In one or more embodiments, the first wavelength conversion layer WCL1 may convert the first light emitted as blue light from the light emitting element LE of the first emission area EA1 into the second light as red light having a single peak wavelength in the range of about 610 nm to about 650 nm, and emit red light.

[0160] The first wavelength conversion layer WCL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. In some embodiments, the first wavelength conversion layer WCL1 may further include a scatterer. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include epoxy resin, acrylic resin, cardo resin and / or imide resin.

[0161] The first wavelength conversion particle WCP1 can convert the first light incident from the light emitting element LE into the second light. For example, the first wavelength conversion particle WCP1 can convert the light in the blue band into the light in the red band. The first wavelength conversion particle WCP1 can be a quantum dot (QD), a quantum rod, a fluorescent material and / or a phosphorescent material. For example, a quantum dot can be a particle material that emits (or is configured to emit) a set or specific color light when an electron transitions from a conduction band to a valence band.

[0162] Quantum dots can be semiconductor nanocrystal materials. Quantum dots can have a set or specific band gap depending on their composition and size. Therefore, quantum dots can absorb light and then emit light with an inherent (e.g., set) wavelength. Examples of semiconductor nanocrystals of quantum dots can include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group nanocrystals, combinations thereof, etc.

[0163] The II-VI compound may be at least one selected from the group consisting of a binary compound, a ternary compound, and a quaternary compound, wherein the binary compound is selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof, and the ternary compound is selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, H gSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof, and the quaternary compound is selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0164] The III-V compound can be at least one selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, wherein the binary compound is selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof, the ternary compound is selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb and mixtures thereof, and the quaternary compound is selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0165] The IV-VI compound may be at least one selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, wherein the binary compound is selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof, the ternary compound is selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof, and the quaternary compound is selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be at least one selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe and mixtures thereof.

[0166] In this case, the binary compound, ternary compound and / or quaternary compound may be present in the particle at a uniform (or substantially uniform) concentration, or may be present in the same particle divided into a state where the concentration distribution is partially different. In addition, the particle may have a core-shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0167] In one or more embodiments, the quantum dot may have a core-shell structure including a core comprising the above-mentioned nanocrystals and a shell surrounding the core (e.g., around the core). The shell of the quantum dot may be used as a protective layer to maintain semiconductor properties by preventing or reducing the chemical denaturation of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or multiple layers. Examples of the shell of the quantum dot may include metal oxides, non-metal oxides, semiconductor compounds, and mixtures thereof.

[0168] For example, the metal oxide and / or non-metal oxide may be SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 and / or binary compounds of NiO and / or such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 and / or CoMn 2 O 4 The present disclosure may include, but is not limited to, a ternary compound.

[0169] In some embodiments, the semiconductor compound may be, for example, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but is not limited thereto.

[0170] The scatterer may scatter the light of the light emitting element LE in random directions. The scatterer may have a refractive index different from that of the first matrix resin BRS1, and may form an optical interface with the first matrix resin BRS1. For example, the scatterer may include (for example, may be) light scattering particles. The scatterer is not specifically limited as long as it is a suitable material capable of scattering at least a portion of the transmitted light, but may be, for example, metal oxide particles and / or organic particles. Examples of metal oxides may include titanium oxide (TiO 2 )、ZrO 2), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 )、ZnO、SnO 2 ) etc. Examples of the material of the organic particles may include acrylic resin, polyurethane resin, etc. Regardless of the incident direction of the incident light, the scatterer may scatter the light in random directions without substantially converting the wavelength of the light.

[0171] The second wavelength conversion layer WCL2 may be disposed to overlap with the second emission area EA2. The second wavelength conversion layer WCL2 may emit light by converting and / or shifting the peak wavelength of the incident light to another set or specific peak wavelength. In one or more embodiments, the second wavelength conversion layer WCL2 may convert the first light emitted as blue light from the light emitting element LE of the second emission area EA2 into a third light as green light having a peak wavelength in the range of about 510 nm to 550 nm, and emit green light.

[0172] The second wavelength conversion layer WCL2 may include a second matrix resin BRS2 and second wavelength conversion particles WCP2 dispersed in the second matrix resin BRS2. The second wavelength conversion layer WCL2 may further include a scatterer.

[0173] The second base resin BRS2 may be made of a material having a relatively high light transmittance, and may be made of the same material as that of the first base resin BRS1, or may include at least one of the materials exemplified as constituent materials thereof.

[0174] The second wavelength conversion particles WCP2 can convert and / or shift the peak wavelength of the incident light to another set or specific peak wavelength. In one or more embodiments, the second wavelength conversion particles WCP2 can convert the first light provided from the light emitting element LE as blue light into a third light as green light having a peak wavelength in the range of about 510nm to 550nm, and can emit green light. Examples of the second wavelength conversion particles WCP2 may include quantum dots, quantum rods, phosphors, etc. A more detailed description of the second wavelength conversion particles WCP2 is substantially the same or similar to the description of the first wavelength conversion particles WCP1, and therefore a more detailed description thereof will not be provided (e.g., will be omitted).

[0175] The light transmission layer WCL3 may be disposed to overlap with the third emission area EA3. The light transmission layer WCL3 may transmit incident light. The light transmission layer WCL3 may transmit the first light emitted as blue light from the light emitting element LE disposed in the third emission area EA3 without conversion. The light transmission layer WCL3 may include a third matrix resin BRS3. The light transmission layer WCL3 may further include scatterers dispersed in the third matrix resin BRS3. Because the third matrix resin BRS3 is substantially the same as or similar to the above-mentioned first matrix resin BRS1, its description will not be provided (e.g., will be omitted).

[0176] The wavelength controller WCP may further include a second cover layer CAP2 disposed on the light blocking part BM, the reflective layer RFL, and the wavelength conversion layer QDL. The second cover layer CAP2 is used to cover the wavelength conversion layer QDL disposed below the second cover layer CAP2 and protect the wavelength conversion layer QDL from moisture and / or foreign matter. The second cover layer CAP2 may include an inorganic material and may include a material substantially the same as or similar to that of the first cover layer CAP1 described above.

[0177] In one or more embodiments, a color filter layer CFL may be disposed on the wavelength controller WCP. The first light, the second light, and the third light emitted from the wavelength controller WCP may pass through the color filter layer CFL to achieve full-color display. The color filter layer CFL may include a first coating layer OC1, a first color filter CF1, a second color filter CF2, a third color filter CF3, and a second coating layer OC2.

[0178] The first coating layer OC1 may be disposed on the wavelength controller WCP. The first coating layer OC1 may be disposed directly on the second cover layer CAP2 of the wavelength controller WCP. The first coating layer OC1 may be disposed entirely in the display area DA and may have a flat (or substantially flat) surface. The first coating layer OC1 may flatten (or substantially flatten) a stepped portion formed below the first coating layer OC1 by the wavelength controller WCP to facilitate formation of the color filter layer CFL.

[0179] The first coating layer OC1 may include a light-transmitting organic material, such as epoxy resin, acrylic resin, cardo resin, imide resin, etc.

[0180] First, second, and third color filters CF1, CF2, and CF3 may be disposed on the first overcoat layer OC1. The first color filter CF1 may be disposed in the first emission area EA1, the second color filter CF2 may be disposed in the second emission area EA2, and the third color filter CF3 may be disposed in the third emission area EA3.

[0181] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant (such as a dye and / or a pigment) that absorbs wavelengths other than the corresponding color wavelength. The first color filter CF1 may selectively transmit the second light (e.g., red light), and block, absorb, or reduce the first light (e.g., blue light) and the third light (e.g., green light). The second color filter CF2 may selectively transmit the third light (e.g., green light), and block, absorb, or reduce the first light (e.g., blue light) and the second light (e.g., red light). The third color filter CF3 may selectively transmit the first light (e.g., blue light), and block, absorb, or reduce the second light (e.g., red light) and the third light (e.g., green light). For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0182] In one or more embodiments, the light incident on the first color filter CF1 may be the second light converted by the first wavelength conversion layer WCL1, the light incident on the second color filter CF2 may be the third light converted by the second wavelength conversion layer WCL2, and the light incident on the third color filter CF3 may be the first light that has passed through the light transmission layer WCL3. Therefore, the second light that has passed through the first color filter CF1, the third light that has passed through the second color filter CF2, and the first light that has passed through the third color filter CF3 may be emitted upward from the substrate to achieve full-color display.

[0183] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb a portion of light from outside the display device 10 to reduce reflected light of the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent or reduce color distortion caused by reflection of external light.

[0184] The second coating layer OC2 may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The second coating layer OC2 may be disposed directly on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The second coating layer OC2 may be disposed entirely in the display area DA and may have a flat (or substantially flat) surface. The second coating layer OC2 may flatten (or substantially flatten) a step portion formed below the second coating layer OC2 by the first color filter CF1, the second color filter CF2, and the third color filter CF3. The second coating layer OC2 may include a light-transmitting organic material and may be substantially the same or similar to the above-mentioned first coating layer OC1.

[0185] Fig.14 is a cross-sectional view schematically illustrating a display device according to one or more embodiments. Fig.15 yes Fig.14 A magnified view of area B, Fig.16 and Fig.17 is an enlarged view of region B according to one or more embodiments. Figures 14 to 17 Detailed Description of the Invention In the present invention, the same or similar reference numerals indicate the same or similar components.

[0186] Reference Figures 14 to 16 , one or more of these embodiments may be different from the above Figures 5 to 12 The difference of the embodiment is that the pixel electrodes PE1', PE2' and PE3' include grooves, and the light emitting element LE' does not include a supporting portion. Fig.17 The pixel electrodes PE1', PE2' and PE3' are connected to the above Figures 5 to 12 The embodiment of FIG. 1 is different in that the pixel electrodes PE1', PE2', and PE3' include grooves. In the following description, a redundant description of the above-mentioned embodiment may not be provided (eg, will be omitted), and the differences will be focused on.

[0187] The pixel electrodes PE1', PE2' and PE3' may include grooves PE1'a, PE2'a and PE3'a, respectively. An adhesive layer 160 may be provided on the grooves PE1'a, PE2'a and PE3'a of the pixel electrodes PE1', PE2' and PE3' to connect the pixel electrodes PE1', PE2' and PE3' to the connection electrode 150. The grooves PE1'a, PE2'a and PE3'a may overlap with the connection electrode 150, the light emitting element LE' and the wavelength conversion layer QDL in the thickness direction (third direction DR3) of the substrate.

[0188] When the pixel electrodes PE1', PE2' and PE3' include grooves PE1'a, PE2'a and PE3'a, the contact area between the adhesive layer 160 and the pixel electrodes PE1', PE2' and PE3' increases. In addition, the grooves PE1'a, PE2'a and PE3'a can prevent or reduce the tilt of the light emitting element LE', and can make (or help) the light emitting element LE' stand upright in the vertical (or substantially vertical) direction of the substrate. Therefore, the bonding yield of the light emitting element LE' can be improved, and the color purity and brightness of the display panel can be improved.

[0189] The cross-sectional shape of the grooves PE1 ′ a , PE2 ′ a , and PE3 ′ a may be a polygonal shape such as a square shape, a semicircular shape, a semielliptical shape, and / or an arc shape.

[0190] The pixel electrodes PE1', PE2' and PE3' may include a single or multiple number of grooves PE1'a, PE2'a and PE3'a overlapping one light emitting element LE'. Fig.15The pixel electrode PE1' includes a groove PE1'a overlapping the light emitting element LE'. Fig.16 The pixel electrode PE1'_1 includes a plurality of grooves PE1'a_1 overlapping the light emitting element LE'.

[0191] The pixel electrodes PE1', PE2' and PE3' including grooves PE1'a, PE2'a and PE3'a may include metal materials. The metal may include, for example, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. In some embodiments, the pixel electrodes PE1', PE2' and PE3' may have a multilayer structure in which two or more metal layers are stacked.

[0192] In one or more embodiments, the pixel electrodes PE1', PE2', and PE3' may include a titanium layer and a copper layer disposed on the titanium layer. The grooves PE1'a, PE2'a, PE3'a may be formed in the copper layer.

[0193] The adhesive layer 160 may be disposed on the grooves PE1'a, PE2'a, and PE3'a of the pixel electrodes PE1', PE2', and PE3'. The width of the adhesive layer 160 may be the same as the width of each groove PE1'a, PE2'a, and PE3'a, or may be greater than the width of each groove PE1'a, PE2'a, and PE3'a. The width of each groove PE1'a, PE2'a, and PE3'a may be less than the width of the light emitting element LE'.

[0194] In one or more embodiments, Fig.17 As shown in FIG, the first semiconductor layer SEM1_5 of the light emitting element LE' disposed on the pixel electrode PE1'_2 including the groove PE1'a_2 may include a main body portion SEM1a_5 adjacent to the active layer MQW and a support portion SEM1b_5 protruding from the main body portion SEM1a_5 toward the pixel electrode PE1'_2. The support portion SEM1b_5 may be in contact with the pixel electrode PE1'_2. The support portion SEM1b_5 may not overlap with the groove PE1'a_2 of the pixel electrode PE1'_2.

[0195] The supporting portion SEM1b_5 may include a first pillar and a second pillar facing the first pillar. A width of the groove PE1'a_2 of the pixel electrode PE1'_2 may be equal to or smaller than a distance between the first pillar and the second pillar.

[0196] Hereinafter, a manufacturing process of the display device 10 according to one or more embodiments will be described with reference to other drawings.

[0197] Figures 18 to 30 is a diagram illustrating a method of manufacturing a display device according to one or more embodiments.

[0198] Figures 18 to 30 1 and 2 are cross-sectional views showing the structure corresponding to the order of forming each layer of the display device 10 . Figures 18 to 30 The manufacturing process of the light emitting element part LEP and the wavelength controller WCP is mainly shown, and both can be roughly the same as Figure 5 In addition, the accompanying drawings relate to Figures 5 to 12 By partially changing the manufacturing process, it is possible to manufacture Figures 14 to 17 Furthermore, hereinafter, the first emission area EA1 of the display device 10 will be mainly described.

[0199] Reference Fig.18 and Fig.19 , a plurality of light emitting element layers LEL are formed on the base substrate WAF.

[0200] For example, a base substrate WAF is prepared. The base substrate WAF may be a sapphire substrate (Al 2 O 3 ) and / or a silicon wafer containing silicon. However, the present disclosure is not limited thereto, and in one or more embodiments, the case where the base substrate WAF is a sapphire substrate is described as an example.

[0201] A plurality of semiconductor material layers SEML1, MQWL, and SEML2 are formed on the base substrate WAF. Figures 18 to 30 In the embodiment, the electron blocking layer and the superlattice layer are not included (e.g., omitted). A plurality of semiconductor material layers grown by an epitaxial method can be formed by growing a seed crystal. Here, at least one of electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual thermal evaporation, sputtering, and metal organic chemical vapor deposition (MOCVD) (e.g., by using metal organic chemical vapor deposition (MOCVD)) can be used to form the semiconductor material layer. However, the present disclosure is not limited thereto.

[0202] The precursor material for forming the plurality of semiconductor material layers may be selected to form the target material within an appropriately selectable range without any limitation. For example, the precursor material may be a metal precursor including an alkyl group such as a methyl group and / or an ethyl group. Examples of the precursor material may include, but are not limited to, trimethylgallium Ga (CH 3 ) 3 、Trimethylaluminum Al(CH 3 ) 3 and triethyl phosphate (C 2 H 5 ) 3PO 4 .

[0203] For example, the second semiconductor material layer SEML2 may be formed on the base substrate WAF. Although the drawings show that one second semiconductor material layer SEML2 is deposited, the present disclosure is not limited thereto, and a plurality of layers may be formed.

[0204] The active material layer MQWL and the first semiconductor material layer SEML1 are sequentially formed on the second semiconductor material layer SEML2 using any one of the above methods.

[0205] Next, if Fig.19 As shown in FIG. 1 , a plurality of semiconductor material layers SEML2, MQWL and SEML1 are etched, and the first semiconductor material layer SEML1 is partially etched to form a support portion. Fig.15 and Fig.16 The light emitting element LE′ shown in FIG. 1 does not include a supporting portion, and the process of partially etching the first semiconductor material layer SEML1 can be omitted.

[0206] The semiconductor material layer may be etched by any suitable method. For example, the process of etching the semiconductor material layer may be performed by a dry etching method, a wet etching method, a reactive ion etching (RIE) method, a deep reactive ion etching (DRIE) method, an inductively coupled plasma reactive ion etching (ICP-RIE) method, etc. Since anisotropic etching can be performed, the dry etching method is suitable for vertical etching. In the case of using the above etching techniques, Cl 2 and / or 2 As an etchant. However, the present disclosure is not limited thereto.

[0207] Through these processes, a plurality of light emitting elements LE can be obtained. Therefore, a plurality of light emitting elements LE are formed by including the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1.

[0208] Next, refer to Fig. 20 , a connection electrode 150 is formed on the first semiconductor layer SEM1 of the light emitting element LE.

[0209] The connection electrode 150 may be formed between the support parts on the first semiconductor layer SEM1 by stacking an electrode material layer on the base substrate WAF and then etching the electrode material layer through an etching process.

[0210] Next, refer to Fig.21 Attach the first support film SPL1 to Fig. 20In this case, the first adhesion promoting layer ADL1 may be disposed between the first supporting film SPL1 and the light emitting elements LE.

[0211] The first adhesion promoting layer ADL1 may be aligned on the plurality of light emitting elements LE and attached to the connection electrode 150 and / or the support portion of the plurality of light emitting elements LE. Since the plurality of light emitting elements LE are provided in a relatively large number, they may be attached to the first adhesion promoting layer ADL1 without separation.

[0212] The first supporting film SPL1 may be made of a material that is transparent and has suitable mechanical stability to allow light to pass through. For example, the first supporting film SPL1 may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The first adhesion layer ADL1 may include an adhesion material for adhering the light-emitting element LE. For example, the adhesion material may include polyurethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesion material may be a material whose viscosity changes when ultraviolet (UV) and / or heat is applied, so that the adhesion layer can be easily or appropriately separated from the light-emitting element LE.

[0213] Then, refer to Fig.21 and Fig. 22 By irradiating the base substrate WAF with laser light (first laser light), the light emitting element LE is separated from the base substrate WAF. The base substrate WAF is separated from each of the second semiconductor material layers SEML2 of the plurality of light emitting elements LE.

[0214] The process of separating the base substrate WAF may be a laser lift-off (LLO) process. In the laser lift-off process using laser, KrF excimer laser (248 nm wavelength) may be used as a source. The excimer laser is used at about 550 mJ / cm 2 Up to 950mJ / cm 2 The energy density can be irradiated within a range of 50 × 50 μm. 2 Up to 1×1cm 2 By irradiating the laser to the base substrate WAF, the base substrate WAF may be separated from the light emitting element LE.

[0215] Next, refer to Fig. 22 , a region of the first adhesion promoting layer ADL1 that does not overlap with the light emitting element LE (eg, a region of the first adhesion promoting layer ADL1 that does not overlap with the corresponding connection electrode 150) is etched.

[0216] Next, refer to Fig.23, align the first supporting film SPL1 on the intermediate substrate SPL2. The intermediate substrate SPL2 may be constructed with a second supporting layer and a second adhesion promoting layer disposed on the second supporting layer. The second supporting layer may be made of a material that is suitably mechanically stable and transparent to allow light to pass through it. As a material for the second supporting layer, any one of the materials used in the examples of the first supporting film SPL1 may be applied. The second adhesion promoting layer may include an adhesion promoting material for adhering the light emitting element LE. As a material for the second adhesion promoting layer, any one of the materials used in the examples of the first adhesion promoting layer ADL1 may be applied.

[0217] Thereafter, the desired light emitting element LE may be selectively transferred to the intermediate substrate SPL2 using the mask MASK and the laser In this case, the first adhesion promoting layer ADL1 is removed from the connection electrode 150 .

[0218] Reference Fig.24 , the light emitting element LE not covered by the mask MASK is transferred to the intermediate substrate SPL2 by laser.

[0219] Next, refer to Fig.25 , an adhesive layer material 161 is deposited on the transferred light emitting element LE and the connecting electrode 150. In one or more embodiments, the adhesive layer material 161 may be a solder. The solder may be at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag) or an alloy of two or more. The adhesive layer material 161 is disposed between the supporting portions of the light emitting element LE or in the supporting portion of the light emitting element LE. When the adhesive layer material 161 includes a high content of tin (Sn), deposition control may be relatively difficult, and thus the size and / or arrangement / alignment of the adhesive layer material 161 may vary.

[0220] pass Figures 18 to 25 The light emitting element LE can be manufactured and transferred to the intermediate substrate SPL2.

[0221] Next, refer to Fig.26 , prepare a substrate (including a second planarization layer 130) on which a bank layer BNL and pixel electrodes PE1, PE2 and PE3 are provided, and attach an intermediate substrate SPL2 to the substrate 110 so that the connection electrode 150 of the light emitting element LE contacts the pixel electrodes PE1, PE2 and PE3.

[0222] The adhesive layer material 161 is melted by applying heat and pressure and / or irradiating laser to bond the pixel electrodes PE1, PE2, and PE3 to the plurality of light emitting elements LE. Fig. 27 As shown in , the intermediate substrate SPL2 is separated.

[0223] Figures 27 to 30The manufacturing process of the light emitting element portion LEP and the wavelength controller WCP is mainly shown, and the adhesive layer 160 disposed under the light emitting element LE is omitted (eg, not shown).

[0224] Reference Fig.28 , via layers VIA1 and VIA2 may be formed to flatten (or substantially flatten) the stepped portion caused by the plurality of light emitting elements LE, and a common electrode CE may be formed on the via layers VIA1 and VIA2 and the plurality of light emitting elements LE. The via layers may include a first via layer VIA1 and a second via layer VIA2.

[0225] Next, if Fig.29 As shown in FIG. 1 , a first capping layer CAP1 is formed on the common electrode CE, and then a light blocking part BM, a reflective layer RFL, and a first wavelength conversion layer WCL1 are formed on the first capping layer CAP1. Fig.30 As shown in FIG, a second capping layer CAP2 and a first coating layer OC1 are formed on the light blocking part BM, the reflective layer RFL and the first wavelength conversion layer WCL1, and a plurality of color filters CF1, CF2 and CF3 are formed on the first coating layer OC1. Thereafter, a second coating layer OC2 is formed on the color filters CF1, CF2 and CF3.

[0226] Reference Figures 18 to 30 , the manufacturing process of the display device including the supporting portion in the light emitting element LE has been described. Fig.19 The etching process of the first semiconductor material layer SEML1 of the support part shown in FIG. 1 and the first pixel electrode PE1 may be partially etched to form a groove. By modifying the process, a display device including a pixel electrode having a groove may be manufactured.

[0227] Fig.31 is an exemplary diagram illustrating a virtual reality device including a display device according to one or more embodiments. Fig.31 A virtual reality device 1 to which a display device 10 according to one or more embodiments is applied is shown.

[0228] Reference Fig.31 The virtual reality device 1 according to one or more embodiments may be a glasses type device (e.g., glasses). The virtual reality device 1 according to one or more embodiments may include a display device 10, a left lens 10a, a right lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device memory 50.

[0229] although Fig.31The virtual reality device 1 including the temples 30a and 30b is shown, but the virtual reality device 1 according to one or more embodiments may be applied to a head mounted display including a headband that can be worn on the head instead of the temples 30a and 30b. That is, the virtual reality device 1 according to one or more embodiments is not limited to Fig.31 The virtual reality device shown in the figure can be applied to various suitable electronic devices in various suitable forms.

[0230] The display device storage 50 may include a display device 10 and a reflective member 40. The image displayed on the display device 10 may be reflected by the reflective member 40 and provided to the right eye of the user through the right lens 10b. Therefore, the user can view the virtual reality image displayed on the display device 10 through the right eye.

[0231] Fig.31 The display device memory 50 is shown to be disposed at the right end of the support frame 20, but the embodiments of the present disclosure are not limited thereto. For example, the display device memory 50 may be disposed at the left end of the support frame 20, and in this case, the image displayed on the display device 10 may be reflected by the reflective member 40 and provided to the left eye of the user through the left lens 10a. Therefore, the user is able to view the virtual reality image displayed on the display device 10 through the left eye. In some embodiments, the display device memory 50 may be disposed at both the left and right ends of the support frame 20. In this case, the user may view the virtual reality image displayed on the display device 10 through both the left and right eyes.

[0232] Fig.32 is an exemplary diagram illustrating a smart device (eg, smart watch 2 ) including a display device according to one or more embodiments.

[0233] Reference Fig.32 The display device 10 according to one or more embodiments may be applied to a smart watch 2 which is one of the smart devices.

[0234] Fig.33 is an exemplary diagram illustrating a portion of a vehicle (eg, a car) including a display device according to one or more embodiments. Fig.33 A portion of a vehicle (eg, a car) to which the display device 10 according to one or more embodiments is applied is shown.

[0235] Reference Fig.33, the display devices 10_a, 10_b, and 10_c according to one or more embodiments may be applied to a dashboard of a vehicle (e.g., an automobile), a central dashboard of a vehicle (e.g., an automobile), and / or a central information display (CID) of a dashboard of a vehicle (e.g., an automobile). In one or more embodiments, the display devices 10_d and 10_e according to one or more embodiments may be applied to an interior mirror display (e.g., an interior mirror display included on a dashboard of a vehicle (e.g., an automobile)) that replaces a side mirror of a vehicle (e.g., an automobile).

[0236] Fig.34 is an exemplary diagram illustrating a transparent display device including a display device according to one or more embodiments.

[0237] Reference Fig.34 , the display device 10 according to one or more embodiments may be applied to a transparent display device. The transparent display device may display an image IM and may also transmit light. Therefore, a user positioned at the front side of the transparent display device may not only view the image IM displayed on the display device 10, but may also view an object RS and / or a background at the rear side of the transparent display device. When the display device 10 is applied to a transparent display device, the substrate 110 of the display device 10 may include a light-transmitting portion capable of transmitting light and / or may be made of a material capable of transmitting light.

[0238] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments presented without departing substantially from the principles of the present disclosure as set forth in the claims and their equivalents. Therefore, the embodiments disclosed in the present disclosure are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: substrate; A pixel electrode, on the substrate; A light emitting element, on the pixel electrode, the light emitting element comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; A connecting electrode, between the pixel electrode and the light emitting element; an adhesive layer, between the connecting electrode and the pixel electrode; as well as A common electrode, on the light emitting element, The first semiconductor layer includes a main body portion adjacent to the active layer and a support portion protruding from the main body portion toward the pixel electrode, and The adhesive layer overlaps the support portion of the first semiconductor layer in a horizontal direction of the substrate.

2. The display device according to claim 1, wherein: The support portion of the first semiconductor layer is located adjacent to an edge of the main body portion.

3. The display device according to claim 1, wherein: The thickness of the support portion of the first semiconductor layer is equal to or greater than the thickness of the connection electrode.

4. The display device according to claim 1, wherein: The supporting portion of the first semiconductor layer is in contact with the pixel electrode.

5. The display device according to claim 1, wherein: The body portion and the support portion of the first semiconductor layer are integral with each other.

6. The display device according to claim 1, wherein: The connection electrode is surrounded by the support portion.

7. The display device according to claim 1, wherein: The supporting portion of the first semiconductor layer includes a first pillar and a second pillar facing the first pillar, and The adhesive layer and the connection electrode are between the first pillar and the second pillar of the support part.

8. The display device according to claim 7, wherein: The first pillar and the second pillar are spaced apart from each other in a plan view.

9. The display device according to claim 8, wherein: The width of the adhesive layer is greater than the distance between the first pillar and the second pillar.

10. The display device according to claim 6, wherein: A space between the main body portion of the first semiconductor layer and the adhesive layer is empty.

11. The display device according to claim 7, wherein: A space between the main body portion of the first semiconductor layer and the adhesive layer is empty or includes a via layer.

12. The display device according to claim 1, wherein: The support portion of the first semiconductor layer has a cross-section that is square, pentagonal, or hexagonal.

13. The display device according to claim 1, wherein: The adhesive layer includes solder.

14. The display device according to claim 1, wherein: The pixel electrode includes glass.

15. A display device, comprising: substrate; a first pixel electrode on the substrate and comprising a groove; an adhesive layer, on the groove of the first pixel electrode; connecting electrodes on the adhesive layer; A first light emitting element is on the connection electrode and includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; A common electrode, on the first light-emitting element; as well as a first wavelength conversion layer, on the common electrode, the first wavelength conversion layer overlapping the first light-emitting element, The connecting electrode, the first light emitting element and the first wavelength conversion layer overlap with the groove of the first pixel electrode.

16. The display device according to claim 15, wherein: The width of the adhesive layer is equal to or greater than the width of the groove of the first pixel electrode.

17. The display device according to claim 15, further comprising: a bank layer, on the first pixel electrode, the bank layer not overlapping the groove of the first pixel electrode; as well as A light blocking layer is provided on the common electrode, and the light blocking layer overlaps the bank layer.

18. The display device according to claim 15, further comprising: a second pixel electrode, on the substrate and spaced apart from the first pixel electrode; a second light emitting element, on the connection electrode, and comprising a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; as well as A light transmission layer is provided on the common electrode, and the light transmission layer is overlapped with the second light emitting element.

19. The display device according to claim 15, wherein: The first semiconductor layer of the first light emitting element includes a main body portion adjacent to the active layer and a support portion protruding from the main body portion toward the first pixel electrode, and The supporting portion contacts the first pixel electrode.

20. The display device according to claim 19, wherein: The supporting portion of the first semiconductor layer includes a first pillar and a second pillar facing the first pillar, and A width of the groove of the first pixel electrode is equal to or smaller than a distance between the first column and the second column.

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