Design and manufacturing of submicron texture silicon substrate heterojunction

Abstract

The invention belongs to the technical field of perovskite laminated solar cells, and relates to design and manufacturing of a submicron texture silicon substrate heterojunction. In order to solve the problems that in the prior art, surface textures are not matched with perovskite thin film preparation, and the silicon surface passivation effect is poor, surface modification is carried out through metal-assisted chemical corrosion, and a nano structure is formed; etching the surface structure by using plasma; an ordered structure is formed on a substrate through molecular action by applying a self-assembly technology; the matching between the surface texture of the silicon substrate and the preparation of the perovskite thin film is optimized, and the passivation effect is improved. The method has the advantages of high photoelectric conversion efficiency and high stability, the performance of the heterojunction solar cell is remarkably improved, and important technical support is provided for industrial application of next-generation efficient solar cells.

Description

Technical field:

[0001] The present invention belongs to the technical field of perovskite tandem solar cells, and more specifically relates to the design and manufacture of a submicron-level textured silicon substrate heterojunction. Background technology:

[0002] With the rapid development of solar energy technology, perovskite / silicon heterojunction tandem solar cells have attracted widespread attention due to their high-efficiency photoelectric conversion capabilities. Among various types of solar cells, heterojunction structures have become an important way to improve photoelectric conversion efficiency due to their advantages in carrier separation and transmission. By optimizing the surface structure of silicon wafers, the light reflectivity can be significantly reduced, the light absorption efficiency can be improved, and the overall performance of optoelectronic devices can be improved. However, the design and manufacture of heterojunctions on such textured silicon substrates face many technical challenges. In the manufacturing process of heterojunction devices, the texture surface design of the silicon substrate directly affects the carrier transmission efficiency and device stability of the interface. Although traditional silicon surface texturing methods, such as random pyramid texture design, perform well in reducing reflection losses and enhancing light capture capabilities, the highly undulating characteristics of the surface pose great challenges to subsequent processes. For example, in the preparation process of heterojunction interfaces, how to achieve uniform and stable interface passivation becomes a key issue. The complexity of surface texture often leads to problems such as increased interface charge recombination rate and poor uniformity of thin film deposition, which not only limits the diffusion efficiency of carriers, but also reduces the stability and overall performance of the device. In addition, although double-sided textured silicon wafers have good optical properties, there are many compatibility issues in interface design. For example, the polishing process of the silicon wafer surface is expensive, the reflection loss cannot be completely eliminated, and the interface recombination problem is still prominent. These shortcomings put higher requirements on silicon substrates and also limit the widespread application of such substrates in high-efficiency optoelectronic devices.

[0003] The present invention proposes a heterojunction design and manufacturing method for a submicron textured silicon substrate. Through innovative surface texture optimization technology and efficient interface passivation scheme, this method can significantly improve the transmission efficiency and stability of the heterojunction interface. At the same time, by optimizing the surface treatment process of the silicon substrate, the interface charge recombination rate and device reflection loss are effectively reduced, thereby providing technical support for the development of a new generation of high-performance optoelectronic devices. Summary of the invention:

[0004] In view of the problems existing in the prior art, such as poor compatibility between the silicon substrate texture structure of the stacked cell and the perovskite film, and unsatisfactory interface characteristics, the present invention aims to provide a design and manufacturing method for a submicron textured silicon substrate heterojunction, so as to significantly improve the photoelectric conversion efficiency, stability and reliability of solar cells. To achieve the above objectives, the present invention adopts the following technical solutions:

[0005] The optical and electrical properties of the silicon substrate surface are improved by texture construction technology, and the light capture ability is enhanced; the interface optimization technology is used to improve the interface bonding strength and reduce the carrier recombination rate, thereby constructing a high-performance submicron textured silicon substrate heterojunction; the specific manufacturing method includes the following steps:

[0006] (1) Texture construction technology, which uses a comprehensive method of substrate pretreatment etching, nanosphere template coating and fixing, and plasma template etching to construct textures on the silicon surface. The specific steps are as follows:

[0007] S1, substrate pretreatment etching method, using potassium hydroxide solution to etch and pretreat the silicon substrate (concentration range is between 1wt%-5wt%); immersing the silicon substrate in the etching solution, controlling the etching temperature (20℃-50℃) and time (5min-20min) to form a preliminary rough structure on the surface of the silicon substrate, providing a basis for the subsequent nanosphere template method to prepare the texture structure;

[0008] S2, nanosphere template coating and fixing method; prepare a monodisperse nanosphere solution, the nanosphere material is polystyrene (PS), and the particle size is between 200nm-600nm; the nanosphere solution is evenly coated on the silicon substrate after surface etching by spin coating, the spin coating speed is controlled at 1000rpm-3000rpm, and the dipping time is 1min-5min; after coating, the nanosphere film is formed on the surface of the silicon substrate by heating (temperature between 80℃-150℃);

[0009] S3, plasma template etching, plasma etching is performed with fixed nanospheres as templates; the silicon substrate with nanosphere film is placed in a plasma etching device, the etching gas is a mixed gas of oxygen and chlorine, the gas flow rate (10sccm-50sccm), the etching power (150W-200W) and the etching time (10min-30min); after the etching is completed, the nanosphere template is removed to obtain a submicron textured silicon substrate;

[0010] Through the above process parameters, the texture height is controlled between 300nm and 700nm, and the spacing is controlled between 500nm and 1μm to achieve the best light capture effect and the lowest surface reflectivity;

[0011] (2) Interface optimization technology: Comprehensively utilize the energy level matching deposition method and defect state dual control optimization method to optimize the interface between perovskite and textured silicon substrate. The specific steps are as follows:

[0012] S1, energy level matching deposition method, carries out interface energy level alignment design and interface engineering treatment at the interface between perovskite and textured silicon substrate; determines the energy level matching relationship between perovskite and silicon substrate by first principle calculation, and selects interface modification materials (such as organic molecules, metal oxides, etc.) according to the calculation results; deposits the selected interface modification materials on the surface of textured silicon substrate by solution spin coating, and the deposition thickness is controlled between 1nm-5nm to form an energy level matching layer, so that the energy levels of perovskite and silicon substrate are aligned, and the effective transmission of carriers is promoted;

[0013] S2, defect state dual control optimization method: an aluminum oxide passivation layer is deposited on the energy level matching layer using atomic layer deposition (ALD) technology, and the thickness of the passivation layer is controlled between 1.5nm and 2nm to reduce the interface defect state density;

[0014] (3) Preparation and packaging of perovskite film: a two-step solution deposition process using spin coating is used to prepare the perovskite film, and the solar cell is packaged. The specific steps are as follows:

[0015] S1, prepare perovskite precursor solution, PbI 2 and CsI are dissolved in a mixed solvent of N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO), the solution concentration is controlled at 1.2 mol / L, and the mixture is stirred in a 65°C water bath until completely dissolved; at the same time, an ionic liquid (tetrabutylammonium trifluoromethanesulfonate) is added to the perovskite precursor solution, the concentration of which is controlled between 0.5wt% and 1wt%, and a perovskite film is grown on the passivation layer to further repair interface defects and achieve high interface bonding strength and low carrier recombination rate;

[0016] S2, adding a precursor solution to a textured silicon substrate that has undergone interface optimization treatment, and spin coating at a speed of 2000 rpm for 30 seconds to form a uniform precursor layer; after spin coating, the substrate is placed on a 70°C hot plate for pre-annealing for 10 minutes to promote initial nucleation of crystals, and then transferred to a 150°C environment for annealing for 20 minutes to form a stable perovskite crystal structure; during the annealing process, a halogen additive methylamine iodide is added to optimize the grain size, improve the density of the film layer, and reduce the interface defect density, thereby enhancing the photoelectric performance of the film;

[0017] S3, depositing a transparent conductive electrode (indium tin oxide) with a thickness of 150nm to 200nm on the top of the perovskite film by magnetron sputtering technology, and using screen printing to make a metal electrode on the back of the silicon substrate to form a complete circuit; coating a hydrophobic protective coating with a thickness of 100nm to 200nm on the surface of the perovskite film by atomic layer deposition to improve moisture resistance;

[0018] S4, adopts a double-layer packaging structure, including EVA (ethylene-vinyl acetate) packaging film and PET (polyethylene terephthalate) protective film, places the perovskite / silicon solar cell between EVA and PET, and laminates it for 20 minutes at 150°C and 10MPa pressure using a vacuum laminator to ensure the tight bonding between the packaging film and the battery; the edge of the battery is sealed with UV- and moisture-resistant epoxy resin to further prevent moisture intrusion and extend battery life;

[0019] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention. Other features of the present application will become easy to understand through the following description. Description of the drawings:

[0020] Figure 1 is a schematic cross-sectional view of a perovskite solar cell according to an embodiment of the present invention;

[0021] Figure 2 This is a flow chart of preparing a silicon substrate with a submicron texture structure according to an embodiment of the present invention;

[0022] Figure 3 This is a flow chart of the preparation of a perovskite film according to an embodiment of the present invention;

[0023] Figure 4 This is a solar cell packaging flow chart of an embodiment of the present invention;

[0024] The numbers in the figure are: 1. Silicon substrate; 2. Nanosphere film; 3. Submicron textured silicon substrate; 4. Aluminum oxide passivation layer; 5. Precursor layer; 6. Perovskite film; 7. Transparent conductive electrode; 8. Metal electrode; 9. Hydrophobic protective coating; 10. Encapsulation film; 11. Protective film. Specific implementation method:

[0025] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0026] Example 1

[0027] like Figure 1and Figure 2 As shown, the texture construction technology of the submicron-level textured silicon substrate heterojunction specifically includes the following steps:

[0028] (1) Substrate pretreatment etching method

[0029] Further, potassium hydroxide solid was measured and added to deionized water, and a magnetic stirrer was used to continuously stir the potassium hydroxide to fully dissolve the potassium hydroxide, thereby preparing a potassium hydroxide etching solution with a concentration of 3 wt %; the etching temperature was controlled at 30° C. and the etching time was 10 min, so as to form a preliminary rough structure on the surface of the silicon substrate 1, providing a good foundation for the subsequent preparation of the texture structure by the nanosphere template method;

[0030] Further, the silicon substrate 1 was cleaned by ultrasonic cleaning with acetone, ethanol and deionized water in sequence, with an ultrasonic frequency of 30 kHz for 10 minutes, and then dried with nitrogen and immersed in the prepared etching solution;

[0031] Specifically, the reaction container is placed in a constant temperature water bath, the etching temperature is maintained at 30° C., and the etching time is 10 min. During the reaction process, the potassium hydroxide etching solution chemically reacts with the surface of the silicon substrate 1, and gradually forms a preliminary rough structure on the surface of the silicon substrate 1.

[0032] Furthermore, after the etching is completed, the silicon substrate 1 is rinsed with deionized water to completely remove the residual etching solution, and then dried in a nitrogen atmosphere to prevent oxidation of the surface of the silicon substrate 1;

[0033] (2) Nanosphere template coating and fixation method

[0034] Furthermore, a monodisperse nanosphere solution was prepared, and polystyrene (PS) with a particle size of 400 nm was selected as the nanosphere material;

[0035] Furthermore, the nanosphere solution was evenly coated on the silicon substrate after surface etching by spin coating, with a spin coating speed of 2000 rpm and a spin coating time of 3 min, so that the nanospheres had sufficient adhesion and were evenly distributed on the surface of the silicon substrate;

[0036] Furthermore, after the coating is completed, the silicon substrate with the nanosphere film 2 is placed in an oven and heated (temperature 120° C.) to fix the nanosphere film 2 on the surface of the silicon substrate, which is beneficial to the subsequent plasma etching operation;

[0037] (3) Plasma template etching

[0038] Further, the silicon substrate with the nanosphere film 1 is placed in a plasma etching device; a mixed gas of oxygen and chlorine is selected as the etching gas;

[0039] Specifically, the gas flow rate is 30 sccm, the etching power is 180 W, and the etching time is 20 min. After the etching is completed, ultrasonic cleaning (ultrasonic frequency is 30 kHz, time is 10 minutes) is used to remove the nanosphere film 1 to obtain a submicron textured silicon substrate 3.

[0040] Example 2

[0041] The interface optimization technology of the submicron textured silicon substrate heterojunction specifically includes the following steps:

[0042] (1) Energy level matching deposition method

[0043] Furthermore, the energy level matching relationship between the perovskite and the silicon substrate was determined through first-principles calculations, and organic molecules were selected as interface modification materials based on the calculation results;

[0044] Specifically, a series of perovskite materials (CsPb(I 1-x Br x ) 3 , where x takes values ​​of 0.1, 0.2, 0.3, 0.4, and 0.5 respectively) to carry out simulation calculations; analyze the band structure of each ratio material to determine the position of its conduction band bottom, valence band top, and band gap size; study the value of the optical band gap to understand its absorption capacity for light of different wavelengths; and evaluate the electrical properties, including carrier mobility and conductivity;

[0045] Further, according to the simulation calculation, the formula of x=0.3 is used as the final ratio;

[0046] (2) Defect state dual control optimization method

[0047] Furthermore, an aluminum oxide passivation layer 4 is deposited on the submicron textured silicon substrate 3 using atomic layer deposition (ALD) technology;

[0048] Specifically, the reaction temperature is set to 150° C., the precursor pulse time is 0.1 second, and the purge time is 10 seconds, to ensure that the aluminum oxide passivation layer 4 is evenly and densely covered on the surface of the silicon substrate, effectively reducing the defect state density on the surface of the silicon substrate and enhancing its bonding with the subsequent perovskite film;

[0049] Example 3

[0050] like Figure 3 and Figure 4 As shown, a perovskite film is prepared on a silicon substrate by a solution method, which specifically includes the following steps:

[0051] (1) Perovskite film deposition

[0052] Furthermore, the perovskite film was prepared by a two-step solution deposition process using spin coating;

[0053] Further, a perovskite precursor solution is prepared, and PbI is dissolved 2 and CsI in a mixed solvent of N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO) at a concentration of 1.2 mol / L; the solution was placed in a 65°C water bath and stirred continuously until it was completely dissolved;

[0054] Furthermore, an ionic liquid (tetrabutylammonium trifluoromethanesulfonate) was added to the perovskite precursor solution, and its concentration was controlled to be 0.8wt% to repair the interface defects, further improve the interface bonding strength and reduce the carrier recombination rate, so that the film and the interface are more tightly bonded and the carrier transmission is smoother;

[0055] Furthermore, the precursor solution was dropped onto the textured silicon substrate after the interface optimization treatment, and spin-coated at a rotation speed of 2000 rpm for 30 seconds to form a uniform precursor layer;

[0056] Furthermore, after the spin coating was completed, the substrate was placed on a 70°C hot plate for pre-annealing for 10 minutes to promote the initial nucleation of the crystal; then, the sample was transferred to a 150°C environment for annealing for 20 minutes to form a stable perovskite crystal structure;

[0057] Furthermore, during the crystal annealing process, a methylamine iodide halogen additive is added to optimize the grain size and reduce the defect density, thereby improving the compactness and optoelectronic properties of the perovskite film 6;

[0058] (2) Solar cell packaging

[0059] Furthermore, a transparent conductive electrode 7 (indium tin oxide) is deposited on the top of the perovskite film by magnetron sputtering, and the film thickness is 150nm-200nm; a metal electrode 8 is made on the back of the silicon substrate by screen printing to form a complete circuit;

[0060] Furthermore, a hydrophobic protective coating 9 is coated on the surface of the perovskite film by atomic layer deposition to enhance its moisture resistance; the thickness of the protective coating is controlled within the range of 100nm to 200nm, and the coating is completed by atomic layer deposition (ALD) technology to ensure uniformity;

[0061] Further, a double-layer packaging structure is selected, including an EVA (ethylene-vinyl acetate) packaging film 10 and a PET (polyethylene terephthalate) protective film 11;

[0062] Specifically, the perovskite / silicon solar cell is placed between the packaging film 10 and the protective film 11, and a vacuum laminator is used for packaging. The component is placed in a vacuum environment to remove bubbles that may exist in the packaging film 10. The lamination temperature is 150° C., the pressure is 10 MPa, and the time is 20 minutes to ensure that the packaging film 10 is tightly combined with the battery.

[0063] Furthermore, the battery edge is sealed with an epoxy resin that is resistant to ultraviolet rays and moisture, thereby preventing the intrusion of environmental moisture and improving the service life of the battery.

Claims

1. A design and manufacturing method for a submicron textured silicon substrate heterojunction, characterized in that: Including texture construction technology and interface optimization technology, the specific steps are as follows: (1) Texture construction technology: The silicon substrate is pretreated by a surface etching method, a potassium hydroxide solution is prepared as an etching solution, the silicon substrate is immersed in the etching solution, and the etching temperature and time are controlled to form a preliminary rough structure on the surface of the silicon substrate; A monodisperse polystyrene nanosphere solution is prepared, and the nanosphere solution is evenly coated on a silicon substrate that has been subjected to surface etching by spin coating, and the spin coating speed and dipping time are controlled. After the coating is completed, the nanospheres are fixed on the surface of the silicon substrate by heating; Plasma etching is performed using nanospheres as templates, and the gas flow, etching power and etching time are controlled. After the etching is completed, the nanosphere template is removed to obtain a submicron texture structure; (2) Interface optimization technology: The energy level matching relationship between the perovskite and the silicon substrate is determined by first-principles calculations, and the interface modification material is selected according to the calculation results. The interface modification material is deposited on the surface of the textured silicon substrate by solution spin coating, and the deposition thickness is controlled to form an energy level matching layer. An aluminum oxide passivation layer is deposited on the energy level matching layer using atomic layer deposition technology, and tetrabutylammonium trifluoromethanesulfonate is added to the perovskite precursor solution to grow a perovskite film on the passivation layer.

2. A method for designing and manufacturing a submicron textured silicon substrate heterojunction as claimed in claim 1, characterized in that: In the substrate pretreatment etching method, the concentration of potassium hydroxide solution is 3wt%, the etching temperature is 30°C, the etching time is 10min, and the silicon wafer is cleaned by ultrasonic cleaning with acetone, ethanol and deionized water in sequence, the ultrasonic frequency is 30kHz, the time is 10 minutes, and the silicon wafer is dried by nitrogen and then immersed in the etching solution. After the etching is completed, the silicon substrate is rinsed with deionized water and dried in a nitrogen atmosphere.

3. A method for designing and manufacturing a submicron textured silicon substrate heterojunction as claimed in claim 1, characterized in that: In the nanosphere template coating and fixing method, the nanosphere particle size is 400 nm, the spin coating speed is 2000 rpm, the dipping time is 3 min, and the heating temperature is 120°C.

4. A method for designing and manufacturing a submicron textured silicon substrate heterojunction as claimed in claim 1, characterized in that: In the plasma template etching molding, the etching gas flow rate is 30 sccm, the etching power is 180 W, and the etching time is 20 min. After the etching is completed, the nanosphere template is removed by ultrasonic cleaning, the ultrasonic frequency is 30 kHz, and the time is 10 minutes.

5. A method for designing and manufacturing a submicron textured silicon substrate heterojunction as described in claim 1, wherein in the energy level matching deposition method, a series of perovskite materials with different ratios are simulated and calculated to determine the energy level matching relationship and select the interface modification material, and the deposition thickness of the interface modification material is 1nm-5nm.

6. A method for designing and manufacturing a submicron textured silicon substrate heterojunction as claimed in claim 1, characterized in that: In the defect state dual-control optimization method, the thickness of the aluminum oxide passivation layer is 1.5nm-2nm, the reaction temperature is 150°C, the precursor pulse time is 0.1 second, the purge time is 10 seconds, and the concentration of tetrabutylammonium trifluoromethanesulfonate in the perovskite precursor solution is 0.8wt%.

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