Quasi-asynchronous sampling frequency grid

Abstract

A global navigation satellite system (GNSS) receiver for processing GNSS satellite signals uses a quasi-asynchronous sampling frequency grid to process the received signals. The GNSS receiver includes a plurality of RF paths configured to receive global navigation satellite system (GNSS) signals from the antenna and to transmit the GNSS signals within a range of frequencies to digitize the GNSS signals. The phase-locked loop is configured to generate a clock signal, and the plurality of clock frequency dividers are configured to receive and divide the clock signal. Each of the plurality of navigation systems receives a clock signal from one of the plurality of clock dividers.

Description

Technical Field

[0001] The present disclosure relates generally to receivers, and more particularly to receivers for processing satellite navigation signals using a quasi-asynchronous sampling frequency grid. Background Art

[0002] A Global Navigation Satellite System (GNSS) receiver can obtain a navigation solution (i.e., positioning information) if it is able to receive reliable signals from multiple GNSS satellites that the receiver is in contact with. Reliable signal reception is typically only achieved under certain operating conditions, namely, in an open sky environment where there are no obstructions to the propagation of radio signals from the selected navigation satellites to the receiver's antenna. Any natural or artificial obstruction (e.g., tall trees with dense foliage, vertical walls of buildings, bridges, urban canyons, and structural elements of mobile vehicles with installed GNSS antennas, etc.) blocking the antenna will have a severe impact on the quality of signal reception. As a result, the accuracy of these navigation solutions may be greatly compromised, including the complete loss of the ability to accurately provide GNSS positioning in any way. The GNSS receiver must also have sufficient processing power to perform the required operations to determine the positioning information in a timely manner.

[0003] GNSS receivers typically process GNSS satellite signals within one clock cycle. Processing the signals within one clock cycle requires significant processing power and memory storage. The amount of processing power and memory storage required results in the use of expensive components, thereby driving up the cost of GNSS receivers. What is needed is a receiver that can quickly process GNSS satellite signals using inexpensive components. Summary of the invention

[0004] A navigation receiver includes: a plurality of RF paths, the plurality of RF paths being configured to receive global navigation satellite system (GNSS) signals. A phase-locked loop is configured to generate a clock signal, and a plurality of clock dividers are configured to receive the clock signal and divide the clock signal. Each of the plurality of navigation systems receives a clock signal from one of the plurality of clock dividers. Each of the plurality of navigation systems includes a plurality of analog-to-digital converters, each of the analog-to-digital converters being configured to receive GNSS signals. Each of the plurality of navigation systems further comprises: a plurality of signal processors configured to process digitized signals, a plurality of extractors configured to extract digitized signals, a plurality of signal processors configured to process extracted signals, a plurality of requantizers configured to convert processed extracted signals into low-bit data, a plurality of navigation system to CPU system interface blocks (NS2CS) configured to generate packets, a plurality of signal processors configured to distribute data streams, a plurality of requantizers configured to generate tick signals, and a time control unit. The navigation receiver further comprises a CPU system comprising a memory, a multi-channel navigation direct memory access device (DMA), a plurality of hardware accelerators, and a plurality of channels. The navigation receiver further comprises a CPU configured to control the plurality of navigation systems and the CPU system, and the CPU is further configured to process data received from the plurality of channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In the drawings, like reference numerals describe similar components in different figures. Like reference numerals with different letter suffixes represent different instances of similar components and / or signals.

[0006] FIG1 shows a prior art Global Navigation Satellite System (GNSS) receiver;

[0007] Figure 2A shows a source clock for a GNSS receiver according to one embodiment;

[0008] Figure 2B A GNSS receiver according to one embodiment is shown;

[0009] Figure 2C A GNSS receiver according to one embodiment is shown;

[0010] Figure 3 shows a navigation system communicating with a CPU system via a NS2CS interface block according to one embodiment;

[0011] Figure 4A shows a signal diagram of an NS2CS interface block operating in single packet mode according to one embodiment;

[0012] Figure 4B shows a signal diagram of an NS2CS interface block operating in multiple packet mode according to an embodiment;

[0013] Figure 5 shows signals received by a multi-channel navigation direct memory access device (DMA) according to an embodiment;

[0014] Figure 6 shows a clock generating a clock signal according to one embodiment;

[0015] Figure 7 A navigation channel in communication with a multi-channel navigation direct memory access device (DMA) is shown according to one embodiment.

[0016] Fig. 8A shows the steps of packet processing according to one embodiment;

[0017] Figure 8B According to one embodiment, Figure 2B , Figure 2C , Figure 3 , Figure 5 ,and Figure 7 Figure 1 shows a multi-channel navigation DMA operating in a CPU fully controlled operating mode.

[0018] Figure 8C According to one embodiment, Figure 2B , Figure 2C , Figure 3 , Figure 5 ,and Figure 7 Figure 1 shows a multi-channel navigation DMA operating in the first attempt automatic operation mode;

[0019] Fig. 9 illustrates frequency reduction and energy savings according to one embodiment; and

[0020] Fig.10 A high-level block diagram of a computer for performing the operations of the components described herein is shown, according to an embodiment. DETAILED DESCRIPTION

[0021] FIG1 shows a schematic diagram of components of a prior art navigation receiver 1 (e.g., a GNSS receiver) that includes a navigation system 100 that includes “A” analog-to-digital converters (ADCs), as shown by ADCs 101(1) ... 101(A). ADCs 101(1) ... 101(A) will be collectively referred to as ADC 101. Navigation system 100 also includes a plurality of signal processors that form a plurality of signal paths. A signal path including “S” signal processors is shown by signal processors 102(1, 1) ... 102(S, 1). There are “P” signal paths, as shown by signal processors 102(1, P) ... 102(S, P). Thus, a first path is shown by signal processors 102(1, 1) ... 102(S, 1), and a last path is shown by signal processors 102(1, P) ... 102(S, P). A plurality of signal processors including signal processors 102(1,1)...102(1,P) and signal processors 102(S,1)...102(S,P) will be collectively referred to as signal processors 102. The navigation receiver 1 also includes "Q" requantizers, as shown by requantizers 103(1)...103(Q). Requantizers 103(1)...103(Q) will be collectively referred to as requantizers 103. The navigation receiver 1 shown in FIG. 1 also includes a navigation channel 104, a time controller 105 that transmits a tick signal S106, and a CPU system 110 that includes a CPU 107, a bus 108, and a memory 109, and the CPU system receives a data ready flag signal S111.

[0022] GNSS signals received by one or more antennas (not shown) are transmitted to one or more RF paths of a plurality of RF paths, which are connected to the input of ADC 101. In one embodiment, the RF path is configured to transmit GNSS signals within a specific frequency range for digitization. In one embodiment, each ADC 101 in ADC 101 receives a signal from a corresponding one of the plurality of RF paths. In one embodiment, a plurality or all of ADCs 101 may receive a signal from a single RF path. From the output of ADC 101, the digitized signal is input to a signal processor 102 that processes the signal.

[0023] One or more components may be used as the signal processor 102 , for example, the signal processor 102 may be a filter, a noise suppressor, an equalizer, and / or a decimator, etc.

[0024] The signals output from the signal processors 102(S, 1) ... 102(S, P) are input to the requantizers 103(1) ... 103(Q), which requantize the received data into low-bit data. The low-bit data output from the requantizers 103(1) ... 103(Q) are input to the navigation channel 104, which processes the low-bit data.

[0025] The navigation channel 104 transmits a data ready flag signal S111 to the CPU 107. The data ready flag signal S111 indicates that the data in the navigation channel 104 is ready.

[0026] The time controller 105 generates a tick signal S106, which in one embodiment is a time scale. The period of the tick signal S106 is equal to the number of clock cycles of CLKnav, which is set by the CPU 107 before operation (hereinafter referred to as Figure 6 104, and 105. The clocks CLKnav and CLKcpu are typically asynchronous, and the CLKcpu rate is generally substantially higher than the CLKnav rate.

[0027] The CPU 107, the memory 109, and all the components of the navigation system 100 are respectively connected to the bus 108, thereby allowing communication between the CPU 107, the memory 109, and all the components of the navigation system 100. In one embodiment, when the tick signal S106 occurs, the CPU 107 receives data via the bus 108 and controls the navigation system 100 based on the received data. The memory 109 is used for data storage.

[0028] Figure 2A Components of a source clock for a GNSS receiver are shown according to one embodiment and include a phase locked loop (PLL) 211 and "D" clock dividers 212 ( 1 ) ... 212 (D). Figure 2A"D" navigation systems 200(1)...200(D) are shown, each of which communicates with a CPU system 210. A PLL 211 is connected to each of "D" clock dividers 212(1)...212(D). The navigation systems 200(1)...200(D) are collectively referred to as navigation systems 200. The clock dividers 212(1)...212(D) are collectively referred to as clock dividers 212.

[0029] In one embodiment, the GNSS receiver operates using a clock signal (referred to as CLKnav) generated for use in the navigation system 200. The clock signal output from the PLL 211 is input to the clock divider 212. In each of the clock dividers 212, a different integer coefficient may be applied to divide the input clock. The clock signal output from each of the clock dividers 212 is input to a corresponding one of the navigation systems 200. The clock signals output from the clock divider 212 are quasi-asynchronous, i.e., they are obtained from a clock signal (not shown) generated by the PLL 211, but they are divided by different integer coefficients.

[0030] Signals from one or more RF paths (not shown) that receive GNSS signals from one or more antennas are input to the navigation system 200 for processing. The navigation system 200 exchanges data with the CPU system 210.

[0031] Figure 2B Components of a GNSS receiver 2 according to one embodiment are shown. Figure 2B Details of the navigation system 200(1)...200(D) and the CPU system 210 are shown, such as the navigation system 200 and the CPU system 210. The navigation system 200 includes a signal processing channel 214 that communicates with the bus 108 of the CPU system 210 via the MUX interconnect 201 and "N" navigation system to CPU system interface blocks (NS2CS) interface blocks 202(1)...202(N). The NS2CS interface blocks 202(1)...202(N) are collectively referred to as NS2CS interface blocks 202.

[0032] The signal processing channel 214 includes "P+1" signal processors 102, which receive the tick signal S106 from the time controller 105. One or more components can be used as the signal processor 102, for example, the signal processor 102 can be a filter, a noise suppressor, an equalizer, and / or an extractor. In the signal processor 102 (P+1), preprocessing occurs before the extraction in 110. The signal output from the signal processor (P+1) is input to the "P" extractors 110 (1)...110 (P). The output of each of the extractors 110 (1)...110 (P) is input to a corresponding one of the "P" signal processors 102 (1)...102 (P). The output of each of the signal processors 102 (1)...102 (P) is input to a corresponding one of the "Q" requantizers 103 (1)...103 (Q). The "P" decimators, the "P" signal processors, and the "Q" requantizers are collectively referred to as the signal processor 102, the decimator 110, and the requantizer 103, respectively.

[0033] The CPU system 210 includes a bus 108 that communicates with the CPU system 210 and components of the navigation system 200(1)...202(D). The bus 108 communicates with the "D" navigation systems 200(1)...202(D), the CPU 107, the memory 109, the "H" hardware accelerators 204(1)...204(H), the multi-channel navigation DMA 205, the "N" NS2CS 202(1)...202(N), and the navigation channel 104. The hardware accelerators 204(1)...204(H) are collectively referred to as hardware accelerators 204.

[0034] In one embodiment, the navigation system 200 operates as follows. A clock signal (CLKnav S213) is output from the clock divider 212. The GNSS satellite signal is received by the antenna and transmitted to the input of the ADC 101 through the RF path. From the output of the ADC 101, the digitized signal enters the input of the signal processor 102 (P+1), where the digitized signal is processed. The signal processor 102 (P+1) outputs a signal that is input to the extractor 110, where the signal is extracted. From the output of the extractor 110, the signal is input to the signal processor 102, where the signal is processed. The signal output from the signal processor 102 is input to the requantizer 103, where the signal is requantized into low-bit data.

[0035] In one embodiment, the signal processing channel 214 (eg Figure 2B ) can be replaced by multiple signal processing channels that process data in a parallel manner. In one embodiment, the navigation system 200 can be replaced by multiple navigation systems. In such an embodiment, each navigation system in the multiple navigation systems has its own tick signal S106, and the tick signals S106 between the navigation systems 200 are synchronized (i.e., they are enabled at the same time, they have the same time duration, and they are generated at the same time each time).

[0036] The signals output from the decimator 110, the requantizer 103, the ADC 101, and the signal processor 102 are input to the MUX interconnect 201. From the MUX interconnect 201, the signals output from one or more of the decimator 110, the requantizer 103, the ADC 101, and the signal processor 102 may be input to any NS2CS interface block in the NS2CS interface block 202 and further processed.

[0037] In one embodiment, the time controller 105 generates a tick signal S106. The tick signal S106 is used to control the components, and the tick signal S106 is input to the extractor 110, the signal processor 102, the requantizer 103, the CPU 107, and the NS2CS interface block 202. In one embodiment, the CPU 107 uses the tick signal S106 to synchronize the control between the extractor 110, the signal processor 102, the requantizer 103, and the NS2CS interface block 202.

[0038] In one embodiment, the navigation clock signal (in Figure 2B The S213 CLKnav) output from the clock divider 212 and the CPU clock signal are asynchronous, wherein the CLKcpu frequency is much higher than the CLKnav frequency.

[0039] The CLKnav and CLKcpu clocks are typically asynchronous, and the CLKcpu frequency is substantially higher than the CLKnav frequency.

[0040] In one embodiment, the frequency of CPU 107 is synchronized and much higher than CLKcpu. In other embodiments, the operating frequency of hardware accelerators 204, 205, and 104 is synchronized and significantly higher than CLKcpu.

[0041] In one embodiment, the CPU 107 may write data to the memory 109 for storage via the bus 108. In one embodiment, the CPU 107 may write data to the hardware accelerator 204 for processing via the bus 108. The following units may be used as a data source for packets: ADC 101, signal processor 102, requantizer 103, decimator 110, hardware accelerator 204, NS2CS interface block 202, and CPU 107.

[0042] After processing at the output of the requantizer 103, the number of samples in a time segment may be different due to different decimation factors. The outputs of the requantizer 103 with the same number of samples in a time segment may be collected into a stream and may be input to a NS2CS interface block 202 via a MUX interconnect 201 for further processing. After decimation at 110, subsequent data processing (in 102, 103, 202) is performed on a clock that is synchronous with and slower than the clock CLKnav.

[0043] In one embodiment, the output of each requantizer in the requantizer 103 is directly connected to the input of any NS2CS interface block in the NS2CS interface block 202. The NS2CS interface block 202 can write data from the navigation system 200 to the following via the bus 108: the memory 109, the hardware accelerator 204, and the CPU 107.

[0044] In one embodiment, the hardware accelerator 204 may write the result of the data processing to the following via the bus 108 : the memory 109 , a different one of the hardware accelerators 204 ( 1 ) . . . 204 (H), and the CPU 107 .

[0045] The hardware accelerator 204 may be a coarse-grained reconfigurable architecture (CGRA), a field programmable gate array (FPGA), the coarse-grained reconfigurable architecture (CGRA) may be built into an application-specific integrated circuit (ASIC), the field programmable gate array (FPGA) may be embedded in an ASIC, a spectrum analyzer, or other devices. When processing data, the hardware accelerator 204 generates an interrupt request (IRQ), which is transmitted to the CPU 107, and a signal S707 (see Figure 5 ) is transmitted to the multi-channel navigation DMA 205.

[0046] The multi-channel navigation DMA 205 reads data from the memory 109 via the bus 108. The multi-channel navigation DMA 205 transfers the data from the memory 109 to the navigation channel 104, where the data is processed. After the operation is completed, the multi-channel navigation DMA 205 outputs an IRQ signal S206 to the CPU 107. The multi-channel navigation DMA 205 can retrieve data from multiple memory areas simultaneously.

[0047] The CPU 107 uses the tick signal S106 and the IRQ (eg, IRQ S206 ) from the multi-channel navigation DMA 205 , the NS2CS interface block 202 , and the hardware accelerator 204 to control the data flow among: the multi-channel navigation DMA 205 , the NS2CS interface block 202 , and the hardware accelerator 204 .

[0048] Figure 2C Components of a GNSS receiver 3 according to one embodiment are shown. Figure 2C The components of the GNSS receiver 3 shown in FIG. Figure 2B Components of the GNSS receiver 2 shown in FIG. 1 are similar, although some components are not shown and new components have been added for clarity. Bus 213 is shown communicating with NS2CS interface block 202, bus 108, and memory 109. In one embodiment, the GNSS signal through the antenna and RF path is input to ADC 101. From the output of ADC 101, the digitized signal is input to signal processor 102 (P+1), where the digitized signal is processed. From the output of signal processor 102 (P+1), the signal is input to extractor 110, where the signal is processed. From the output of extractor 110, the signal is input to signal processor 102, where the signal is processed.

[0049] From the output of signal processor 102, the signal is input to NS2CS interface block 202 where it is further processed. From the output of NS2CS interface block 202, the data is written directly to memory 109 via bus 213, or to hardware accelerator 204 via bus 108, or to CPU 107 via bus 108.

[0050] In one embodiment, the NS2CS interface block 202 performs data preprocessing. The NS2CS interface block 202 converts the data into a format suitable for use by the multi-channel navigation DMA 205, the CPU 107, the memory 109, and the hardware accelerator 204 ( Figure 2B and Figure 2CThe output data stream from the NS2CS interface block 202 is packets.

[0051] Figure 3 The navigation system 200 is shown communicating with a CPU system 210 via a NS2CS interface block 202 according to one embodiment.

[0052] In one embodiment, the NS2CS interface block 202 includes a NS2CS controller 300 that receives a tick signal S106 from the time controller 105. The NS2CS controller 300 communicates with a NS2CS extractor 301. The NS2CS extractor 301 and the MUX interconnect 201 transmit the signal to a multiplexer 302 that communicates with the NS2CS controller 300. The MUX interconnect 201 transmits a continuous data stream S308 to the multiplexer 302 and the NS2CS extractor 301. The signal output from the multiplexer 302 is transmitted to a preparation data and requantizer 303 that communicates with the NS2CS controller 300. The preparation data and requantizer 303 transmits the signal to an asynchronous asymmetric first-in, first-out (FIFO) buffer 304 (also referred to as FIFO 304) that communicates with the NS2CS controller 300. The asynchronous asymmetric FIFO buffer 304 transmits a signal to a packet manager 309 that communicates with the NS2CS controller 300. The packet manager 309 communicates with the bus 108. The bus 108 communicates with the CPU 107 and a multi-channel navigation direct memory access device (DMA) 205. The multi-channel navigation DMA 205 also receives a RUN signal S307 from the NS2CS controller 300.

[0053] The continuous data stream signal S308 from the MUX interconnection device 201 is input to the NS2CS decimator 301 and, if necessary, decimated using different decimation coefficients. The signal output from the NS2CS decimator 301 is input to the data preparation and requantizer 303 via the multiplexer 302.

[0054] The data preparation and requantizer 303 prepares data and, if necessary, requantizes the data into lower bit data.

[0055] If decimation is not used, the continuous data stream signal S308 from the MUX interconnect 201 is input to the multiplexer 302 and then transmitted to the data preparation and requantizer 303 .

[0056] The data output from the data preparation and requantizer 303 is input to the asynchronous asymmetric FIFO buffer 304. Then, the output of the asynchronous asymmetric FIFO buffer 304 is input to the packet manager 309, where the data is converted into packets having a given number of samples.

[0057] In one embodiment, prior to initiating operation, the NS2CS controller 300 configures the NS2CS decimator 301 (if needed), multiplexer 302, prepare data and requantizer 303, asynchronous asymmetric FIFO buffer 304, and packet manager 309. In one embodiment, decimation is used to reduce the number of samples in a packet without losing signal quality in further processing.

[0058] In one embodiment, a packet is the number of samples assigned / set by the CPU 107. A sample is the data within one clock cycle CLKnav. The NS2CS interface block 202 starts generating packets based on the tick signal S106. In one embodiment, the NS2CS interface block 202 generates packets and places them in the memory 109 (e.g., Figure 2B and Figure 2C shown in ).

[0059] In one embodiment, the data in the packet may be processed in the following: using the navigation channel 104 of the multi-channel navigation DMA 205 (in Figure 2B and Figure 2C ), CPU 107 and / or hardware accelerator 204.

[0060] In one embodiment, the packets may be generated by: CPU 107 , NS2CS interface block 202 , and / or hardware accelerator 204 .

[0061] In one embodiment, the asynchronous asymmetric FIFO buffer 304 resynchronizes data from the clock CLKnav to the clock CLKcpu.

[0062] In one embodiment, during operation, the NS2CS interface block 202 stacks data at a given address and generates an interrupt request signal S305 for the CPU 107. Data will be written cyclically if necessary. In another embodiment, the NS2CS extractor 301 is removed to reduce the NS2CS interface block 202 space required on the ASIC.

[0063] NS2CS interface block 202 operates in two modes: single packet mode and multiple packet mode.

[0064] Figure 4A106, a packet is formed. When a packet is formed, an IRQ signal S305 is generated and input to the CPU 107. In this mode, the CPU 107 uses the tick signal S106 and the IRQ signal from the NS2CS interface block 202 and the hardware accelerators 204, 205 to control the data flow. In one embodiment, the multi-channel navigation DMA 205 forms a multi-bit data signal S501 and an enable signal S502 for the navigation channel 104 (see Figure 7 ).

[0065] Figure 4B 1 shows a signal diagram of the NS2CS interface block 202 operating in multiple packet mode. The time controller 105 generates a tick signal S106, and data processing is started according to the tick signal S106. During one cycle of the tick signal S106, U packets are formed. When the first packet has been formed and written to the memory 109, a signal S305 is generated. A RUN signal S307 is generated after each packet is completed. In one embodiment, Packet 1...Package U has the same size. In another embodiment, Packet 1...Package U has different sizes. The multi-channel navigation DMA 205 reads the packet from the memory 109 and forms multi-bit data signals S501 and S502 for the navigation channel 104 based on the signal S307. When necessary, additional operations on the packet are performed, specifically, the NS2CS interface block generates the S305 and S307 signals at any time after the packet is written to the memory 109.

[0066] Figure 5 1 . The signals received by the multi-channel navigation DMA 205 are shown. The signals received by the multi-channel navigation DMA 205 include "N" signals from the output terminals of the NS2CS interface blocks 202(1) ... 202(N), as shown by signals S307(1) ... S307(N). The signals received by the multi-channel navigation DMA 205 also include "H" RUN signals (as shown by RUN signals S707(1) ... S707(H)) from the output terminals of "H" hardware accelerators (as shown by hardware accelerators 204(1) ... 204(H)), respectively. The signals received by the multi-channel navigation DMA as described are used to first try the automatic mode.

[0067] In one embodiment, the signal S707 from the hardware accelerator 204 is received at the multi-channel navigation DMA 205. Before writing the packet to the memory 109 (see Figure 2B and Figure 2C) is completed. The multi-channel navigation DMA 205 uses the signal S707 in a similar manner to the signal S307, and the signal S707 is also used for the first attempt at the automatic mode.

[0068] The multi-channel navigation DMA 205 uses signals S307 and S707 to read packets from the memory 109 and simultaneously generates signals S501 and S502 (see FIG. 1 ) from different data sources NS2CS interface block 202 and / or hardware accelerator 204. Figure 4A , Figure 4B and Figure 8 ).

[0069] In the navigation system 200 (eg Figure 2B and Figure 2C ), the signal is extracted by one of the extractors 110.

[0070] Figure 6 One of the possible variations of the clock that generates the clock signal (referred to as the clock used for decimation) is shown. The tick signal S106 has a specific tick period. The tick signal S106 includes multiple ClkNav. The clock divider 2 signal shows the Clknav pulse divided by 2. Similarly, the clock divider 3 signal shows the Clknav clock divided by 3, and the clock divider 4 signal shows the Clknav clock divided by 4. In one embodiment, the signal is input to the signal processor 102 (decimator in this variation) to control the decimation. In one embodiment, the tick signal S106 is used for all components (for all clock divisions) simultaneously (for all decimation factors).

[0071] When decimation is used, the number of samples at the input of the NS2CS interface block 202 is reduced, thereby reducing the packet size. In one embodiment, the NS2CS interface block converts the received digitized signal into packets of a preset or specified size.

[0072] FIG. 8 shows a diagram according to one embodiment. Figure 58, in one embodiment, the navigation channel 104 includes at least one channel 500. Channel 500 receives "D" signals from the multi-channel navigation DMA 205, as shown by signals S501 (1) ... S501 (D) and S502 (1) ... S502 (D), and channel 500 includes a code rate NCO (CRNCO) 503, a code generator 506, a strobe generator 508, an integration period counter 510, an intermediate frequency NCO (IFNCO) 512, a correlator 515, and a commutator 516. The transmitted and / or received signals include a code rate signal S504, a code phase signal S505, a code signal S507, a strobe signal S509, an integration period (IP) signal S511, a cosine signal S513, a sine signal S514, and an output signal S517 from the commutator.

[0073] In one embodiment, the navigation channel 104 includes a plurality of channels. FIG. 8 shows a channel 500, which is one of the plurality of channels. In one embodiment, a packet may contain data from one or more data sources. Data from different sources may be merged into one packet with the same number of samples over a period of time. Figure 2B The lower data received at the output of the ) is multiplexed into a single multi-bit word and input to the assigned NS2CS interface block 202 to generate a common packet, which is transmitted to the memory 109, where it is stored. The multi-channel navigation DMA 205 reads the packet from the memory 109 and converts the packets from the requantizer 103 (1) ... 103 (Q) ( Figure 2B) is converted into "D" signals as shown by signals S501(1)...S501(D) and enable signals S502(1)...S502(D). Data from each requantizer in requantizers 103(1)...103(Q) are transmitted as signals S501(1)...S501(D), respectively. Signals S501(1)...S501(D) and S502(1)...S502(D) are fed from 205 to the input of commutator 516. Signals S501(1)...S502(1) are used simultaneously. Signals S501(D) and S502(D) are used simultaneously. CPU 107 connects channel 500 to the required signals S501(i) and S502(i) with the help of commutator 516. Here, "i" is any number from 1 to D. When the signal S502(i) is in an active state, the processing of the data S501(i) in the channel 500 is started. When the signal S502(i) is in an inactive state, the processing of the data S501(i) in the channel 500 is stopped.

[0074] In one embodiment, the multi-channel navigation DMA 205 sends a packet to the navigation channel 104 during the generation of the next packet. In one embodiment, the multi-channel navigation DMA 205 operates multiple packets in parallel and transmits multiple packets to the navigation channel 104 during the generation of the next packet. The CPU 107 controls the multi-channel navigation DMA 205 via the bus 108. Before operation, the CPU 107 adjusts the multi-channel navigation DMA 205 to operate in one of a plurality of modes.

[0075] The multi-channel navigation DMA 205 can operate in the following modes: CPU fully controlled mode and first attempt automatic mode.

[0076] According to one embodiment, in the CPU fully controlled mode, the CPU 107 controls the multi-channel navigation DMA 205 and the channel 500. In one embodiment, the CPU fully controlled mode is used only when the NS2CS interface block 202 operates in the single packet mode. The time controller 105 generates a tick signal S106, which sets the amount of data to be processed. The NS2CS interface block 202 operates in the single packet mode. When a packet is formed, a signal S305 is generated. According to the signal S305, the CPU 107 writes a control command in the navigation channel 104, and then, according to the command from the CPU 107, the multi-channel navigation DMA 205 sends the packet (or multiple packets). When the packet (or multiple packets) is sent, the multi-channel navigation DMA 205 generates a signal S206. Based on the signal S206, the CPU 107 reads data from the navigation channel 104. The advantage of this mode is that the chaining of data processing is more flexible, because the CPU 107 can determine by itself to which block the data is sent.

[0077] In the first attempt automatic mode according to one embodiment, the CPU 107 controls 205 and channel 500, and the multi-channel navigation DMA 205 itself uses signal S307 ( Figure 7 , Figure 5 ) and S707 ( Figure 5 ) sends the packet to channel 500. In one embodiment, the first attempt automatic mode is used only when the NS2CS interface block 202 operates in multiple packet mode. The time controller 105 generates a tick signal S106, which sets the amount of data to be processed. After the first packet is sent, a signal S305 is generated. According to the signal S305, the CPU 107 sends a control command to the navigation channel 104, and further, according to the command of the CPU, the multi-channel navigation DMA 205 sends the packet. At the end of each packet, according to the RUN signal S307, the multi-channel navigation DMA 205 is run and the packet is sent to the navigation channel 104. After the last packet, based on the current tick signal S106, the multi-channel navigation DMA 205 generates a signal S206. According to the signal S206, the CPU 107 reads data from the navigation channel 104. The advantage of this mode is that smaller packets require smaller memory. In addition, since this mode requires less control from the CPU, the power consumption is lower.

[0078] When a packet is completed, the multi-channel navigation DMA 205 reads the packet from the memory 109 and generates a multi-bit data signal S501 and an enable signal S502. When the data signal S501 (1) is sent via the commutator 516 and S502 (1) is active, S501 (1) is sent to the current channel 500 and processed. When the data S501 (D) is sent via the commutator 516 and S502 (D) is active, S501 (D) is sent to the current channel 500 and processed. The multi-channel navigation DMA 205 reads a packet (packets) from the memory 109 and converts the data into the signal S501 and the enable signal S502.

[0079] The multi-channel navigation DMA 205 in the CPU full controlled mode generates an IRQ signal S206 at the end of a packet after data is sent to the channel 500 , and the IRQ signal S206 corresponds to the cycle of the tick signal S106 .

[0080] The multi-channel navigation DMA 205 in the first attempt automatic mode generates an IRQ signal S206 for some packets at a time when data transmission to the channel 500 ends, and the IRQ signal S206 corresponds to the cycle of the tick signal S106.

[0081] Signals S501(1) ... S501(D) and S502(1) ... S502(D) are transmitted from multi-channel navigation DMA 205 to the input of inverter 516. CPU 107, in conjunction with inverter 516, connects channel 500 to signals S501(i) and S502(i), where i is any number from 1 to D.

[0082] When the multi-channel navigation DMA 205 is reading packets from the memory 109, if the signal S502 indicates that there is not enough or sufficient time to prepare the next data or S501 has been completed, the channel 500 will stop processing data during this period of time.

[0083] The navigation channel 104 comprises a set of channels 500. The CPU 107 controls and retrieves data from the channels 500 via the bus 108. In the channels 500, each sample from a packet is processed in a clock CLKcpu.

[0084] In one embodiment, the period of the tick signal S106 is smaller than the period of the integrated period signal S511 .

[0085] The configuration of channel 500 is a set of settings defined for a selected GNSS signal processing mode. For example, in 516 the parameters are the selected signals S501 ( i ) and S502 ( i ) and the configuration of the code generator 506 .

[0086] In one embodiment, when the multi-channel navigation DMA 205 does not send the data signal S501, the CPU 107 configures, controls, and retrieves data from the channel 500. Before operation, the CPU 107 sets the current configuration of the components and parameters of the channel 500 as follows: the code frequency and initial code phase in the code rate NCO 503, the code generator 506, the gate generator 508, the duration of the integration period signal S511 in the integration period counter 510, the intermediate frequency and initial code phase in the intermediate frequency NCO 512, and the commutator 516. In one embodiment, based on the integration period signal, the multi-channel navigation DMA fixes the data ready status in multiple channels, and the CPU reads them after data processing.

[0087] In one embodiment, channel 500 processes input signal S501 ( i ) from the beginning to the end of a packet.

[0088] The CRNCO 503 generates a code frequency signal S504, which is input to the code generator 506 and the integration period counter 510. The code generator 506 generates a code signal S507 at the rate of the signal S504. The code signal S507 is input to the gate generator 508 and the correlator 515. The CRNCO 503 generates a code phase signal S505, which is input to the gate generator 508. The gate generator 508 generates a gate signal S509 using the signals S507 and S505, which is input to the correlator 515. The IFNCO 512 generates a signal cosine (Cos) S513 and a signal sine (Sin) S514 having an intermediate frequency. The signals S513 and S514 are input to the correlator 515. The signal S517 is input to the correlator 515 from the commutator 516. Based on the code rate signal S504, the integration period counter 510 generates an integration period signal S511. The integration period signal S511 is input to the correlator 515 and the multi-channel navigation DMA 205. In one embodiment, the signal S517 is the signal S501(i).

[0089] In the correlator 515, the signal S517 is multiplied by the Cos signal S513 and the code signal S507, and the multiplication result is accumulated on the integration period signal S511. According to the integration period signal S511, the accumulated value (component I shown below) is stored in the buffer register 1, and if necessary, the CPU 107 takes the value and clears the accumulated value.

[0090]

[0091] In the correlator 515, the signal S517 is multiplied by the Sin signal S514 and the code signal S507, and the result of the multiplication is accumulated on the integration period signal S511. According to the signal S511, the accumulated value (component Q shown below) is stored in the buffer register 2, and if necessary, the CPU 107 takes the value and clears the accumulated value.

[0092]

[0093] In the correlator 515, the signal S517 is multiplied by the Cos signal S513 and the selection signal S509, and the multiplication result is accumulated on the integration period signal S511. According to the signal S511, the accumulated value (component dI shown below) is stored in the buffer register 3, and if necessary, the CPU 107 takes the value and clears the accumulated value.

[0094]

[0095] In the correlator 515, the signal S517 is multiplied by the Sin signal S514 and the selection signal S509, and the multiplication result is accumulated on the integration period signal S511. According to the signal S511, the accumulated value (component dQ shown below) is stored in the buffer register 4, and if necessary, the CPU 107 takes the value and clears the accumulated value.

[0096]

[0097] Based on signal S206, if signal S511 in multi-channel navigation DMA 205 is available, CPU 107 reads ready data from channel 500, including values ​​(component I, component Q, component dI, component dQ) from buffer registers 1 to 4. Note that the code phase CRNCO 503, the intermediate frequency phase in IFNCO 512, and the status of the integration cycle counter 510 can also be read.

[0098] Before processing according to signal S501 (i), CPU 107 can control / modify parameters of channel 500, including changing the code frequency in CRNCO 503, setting the code phase shift in CRNCO 503, changing the intermediate frequency in IFNCO 512, and setting the intermediate frequency phase shift in IFNCO 512.

[0099] The operation of gate generator 508 is described in US 7,764,226 Bl, the disclosure of which is incorporated herein by reference in its entirety.

[0100] Fig. 8A The packet processing steps are shown and are described as follows.

[0101] Signals S305, S307, and S707 indicate to the multi-channel navigation DMA 205 that there is a new packet in the memory 109. The CPU 107 uses a combination of signals S106, S206, S305, S307, and S707 to control the GNSS signals processed in the channel 500. Packet processing using the multi-channel navigation DMA 205 includes the following steps. The following table describes the packet processing steps. The name column of the table indicates Fig. 9 The last digit of the label in A is associated with a particular step (ie, labels 9112, 9212, and 9312 are each associated with a configuration step, labels 9113, 9213, and 9313 are each associated with a control step, and so on).

[0102]

[0103] In one embodiment, all steps required for each current configuration must be completed during the formation of a new package.

[0104] In the CPU fully controlled mode, the configuration and control steps are controlled by the CPU 107. During the configuration and control steps, the CPU 107 controls the channel 500 before sending a packet to the channel 500. The reading step is controlled by the CPU 107. At the reading step, the CPU 107 reads ready data from the channel 500 after processing the packet in the channel 500. The multi-channel navigation DMA 205 generates an IRQ signal S206 after processing the packet (after the processing step).

[0105] In the first attempt automatic mode, the configuration and control steps are controlled by the CPU 107. During the configuration and control steps, the CPU 107 controls the channel 500 before the first packet formed on the tick signal S106 is sent to the channel 500. The reading step is controlled by the CPU 107. In the reading step, the CPU 107 reads the ready data from the channel 500 after the channel 500 has processed the last packet generated during the cycle of the tick signal S106. The multi-channel navigation DMA 205 generates the IRQ signal S206 after processing the last packet generated during the cycle of the tick signal S106 in the channel 500 (after the processing step).

[0106] In one embodiment, the following steps are performed in the order shown:

[0107] Configuration steps:

[0108] For multiple channels 500, the configuration steps can be used one after another (e.g., Fig. 8AStep 9**2 shown in FIG. 1 ). If new GNSS signal processing needs to be run, channel 500 is set to the new configuration. Channel 500 can also stop GNSS signal processing if necessary.

[0109] Control steps:

[0110] For multiple channels 500, the control step (e.g., Fig. 8A Steps 9**3) shown in are used one after another. If necessary, a control command is sent to channel 500.

[0111] Processing steps:

[0112] Processing steps (e.g. Fig. 8A Steps 9**4) shown in FIG. 5 are applied simultaneously (in parallel) to all lanes 500. A packet (represented by signal S501) is sent simultaneously to all lanes 500. Each lane 500 processes its own packet received as signal S501(i).

[0113] Reading steps:

[0114] For multiple channels 500, read steps are used sequentially if necessary (e.g., Fig. 8A If the signal S511 is available in the multi-channel navigation DMA 205 , the CPU 107 reads the ready data from the channel 500 .

[0115] In one embodiment, if necessary, CPU 107 may read data from channel 500 without using multi-channel navigation DMA 205, thereby temporarily stopping the operation of 205 after signal S206.

[0116] In one embodiment, channel 500 does not process the current configuration of the previous configuration, and CPU 107 will not set one or more new current configurations of channel 500, then multi-channel navigation DMA 205 will not send a packet to channel 500 (i.e., multi-channel navigation DMA 205 skips all steps) and generates signal S206.

[0117] In CPU fully controlled and first attempt automatic modes, step configuration and control using the CPU 107 will ensure synchronization of control for all channels 500.

[0118] exist Fig. 8A In FIG. 1 , steps with shaded backgrounds are inactive (i.e., not used). In one embodiment, the time for packet generation is equal to the period of the tick signal S106 (see Figure 4A ).

[0119] In one embodiment, channel 500(1) processes signal S501(i) in its current configuration (Config 1). In Config 1, data packets are processed in the same manner as the operation of channel 500 in a typical GNSS receiver (shown in FIG. 1 ) in pipeline mode.

[0120] In one embodiment, Config 1 configuration is performed as follows: at Tick 1 9100 - the current configuration is set, GNSS signals are processed, and data is read if necessary; and at Tick 2 9200 and Tick 3 9300 - GNSS signal processing continues, and data is read if necessary.

[0121] exist Fig. 8A , the steps are performed in the following order:

[0122] Once tick signal S106 number 1 (ie, Tick 1 9100 ) occurs, the following steps will be performed: Config 9112 sets the following: Config 1; Process 9114; and Read 9115.

[0123] Once tick signal S106 number 2 (ie, Tick 2 9200 ) occurs, the following steps will be performed: Control 9213 for each of: Config 1 ; Process 9214 ; and Read 9215 .

[0124] Once tick signal S106 number 3 (ie, Tick 3 9300 ) occurs, the following steps will be performed: Control 9313 for each of: Config 1 ; Process 9314 ; and CPU Read 9315 .

[0125] It should be noted that in one embodiment, in the single GNSS signal processing mode, channel 500 always operates in the current configuration corresponding to Config 1.

[0126] Figure 8B The multi-channel navigation DMA 205 ( Figure 2B , Figure 2C , Figure 3 , Figure 4A ,and Figure 7 ) diagram of operation in a mode where the CPU is fully controlled.

[0127] The packet corresponds to the periodic tick S106. In the CPU fully controlled mode, the CPU 107 uses the tick signals S106, S305, and S206 and uses the multi-channel navigation DMA 205 to fully control the GNSS signal processing to control the Config step, the control step, and the read step. Based on the tick signal S106, the NS2CS interface block 202 starts to form a packet. The CPU 107 receives the signal S305 and performs the Config step and the control step. In the processing step, the multi-channel navigation DMA 205 transmits the packet to the navigation channel 104 by commanding the CPU 107. The multi-channel navigation DMA 205 completes the transmission of the packet and generates a signal S206. The CPU 107 receives the signal S206 and performs the read step. Then all steps are repeated cyclically.

[0128] In one embodiment, Figure 8C A diagram showing the multi-channel navigation DMA 205 operating in first attempt automatic (where 4 packets are formed per tick period) mode.

[0129] Within the periodic tick signal S106, four packets are formed (e.g., in multiple packet mode). In the first attempt automatic mode, the processing of packets 2 and 3 does not require any control from the CPU 107. After processing packet 4, the CPU 107 receives the signal S206 and reads the ready data from the channel 500. The NS2CS 202 starts to form packets through the tick signal S106. The CPU 107 receives the signal S305 and performs the Config step and the Control step. In the Processing step, the Multi-Channel Navigation DMA 205 transmits packet 1 to the Navigation channel 104 by commanding the CPU 107. In the Processing step, the Multi-Channel Navigation DMA 205 transmits packet 2, packet 3, and packet 4 to the Navigation channel 104 through the signal S307. The Multi-Channel Navigation DMA 205 ends with transmitting packet 4 and generates the signal S206. The CPU 107 receives the signal S206 and performs the Reading step. All steps are then repeated cyclically.

[0130] In one embodiment, Fig. 9 The frequency reduction and energy saving according to an embodiment using a quasi-asynchronous sampling frequency grid is shown, where packets having a duration of 0.8 ms are sent. The NS2CS interface block 202 forms 4 packets. Fig. 9 Described together with the components shown in other figures.

[0131] PLL 211 generates a clock signal with a frequency of 225 MHz. The clock signal output from PLL 211 is input to divider clock 212 (1) and divider clock 212 (2). In divider clock 212 (1), the division factor is 1, and the clock from PLL passes without any change. The clock frequency at the output end of divider clock 212 (1) is 225 MHz. In divider clock 212 (2), the division factor is 2, and the clock from PLL is divided by 2. The clock frequency at the output end of divider clock 212 (2) is 112.5 MHz.

[0132] The clock signal output from the divider clock 212 (1) is input to the navigation system 200 (1). The ADC 101 of the navigation system 200 (1) digitizes the signal received from the RF path, which is output with a frequency of 225 MHz.

[0133] The clock signal output from the divider clock 212 (2) is input to the navigation system 200 (2). The ADC 101 of the navigation system 200 (2) digitizes the signal received from the RF path, which is output with a frequency of 112.5 MHz.

[0134] In the navigation system 200(1), the decimation factor in the decimator 110(1) is 4. Samples having a frequency of 225 MHz are input to the decimator 110(1), which outputs samples having a frequency of 56.25 MHz. The NS2CS interface block 202(1) (eg, Figure 2B , Figure 2C ,and Figure 3 ) generates packet 1, which is equal to 45,000 samples with a duration of 0.8 ms.

[0135] In the navigation system 200(1), the decimation factor in the decimator 110(2) is 6. Samples having a frequency of 225 MHz are input to the decimator 110(2), which outputs samples having a frequency of 37.5 MHz. The NS2CS interface block 202(2) generates a packet 2 equal to 30,000 samples having a duration of 0.8 ms.

[0136] In navigation system 200(1), the decimation factor in decimator 110(3) is 3. Samples having a frequency of 225 MHz are input to decimator 110(3), which outputs samples having a frequency of 75 MHz. NS2CS interface block 202(3) generates packet 3, which is equal to 60,000 samples with a duration of 0.8 ms.

[0137] In navigation system 200(2), the decimation factor in decimator 110(4) is 2. Samples having a frequency of 112.5 MHz are input to decimator 110(4), which outputs samples having a frequency of 56.25 MHz. NS2CS interface block 202(N) generates packet 4, which is equal to 45,000 samples of duration 0.8 ms.

[0138] Package 1 ... Package 4 are formed at the same time period. The number of samples in Package 1 is equal to the number of samples in Package 4. The number of samples in Package 1, Package 2, and Package 3 is different.

[0139] Packet 1 ... Packet 4 is processed simultaneously by multiple channels 500. In channel 500, each sample of the packet is processed for one pulse of clock signal CLKcpu. In order to process packet 1 and packet 4, 45,000 pulses of clock signal CLKcpu are required. In order to process packet 2, 30,000 pulses of clock signal CLKcpu are required. In order to process packet 3, 60,000 clock pulses of clock signal CLKcpu are required. In channel 500, when channel 500 processes data S501 (i) from 205, clock CLKcpu is enabled.

[0140] The use of decimator 110 and divider clock 212 in navigation system 200 reduces the frequency of GNSS signal processing, thereby reducing power consumption and packet size due to the reduced number of samples. Reducing the packet size by reducing the number of samples results in reduced processing time and power consumption for packets using channel 500, and also reduces the size of the memory used.

[0141] The navigation system 200 processes the GNSS signals in a pipeline mode using the clock signal CLKnav and generates packets using the NS2CS interface block 202, thereby providing greater flexibility in the GNSS signal processing. In one embodiment, each of the NS2CS interface blocks generates packets in succession without losing any data. The formation of packets is associated with the tick signal S106. These packets are further processed in the CPU system 210 based on the clock signal CLKcpu.

[0142] In one embodiment, the GNSS receiver architecture includes multiple clock dividers 212, multiple navigation systems 200, and multiple decimators 110, which are used to reduce power consumption. In the navigation system 200, the processed and decimated signals are converted into packets through multiple NS2CS interface blocks. The NS2CS interface blocks write the packets to the memory 109. The packets in the NS2CS interface blocks are formed at the same time, but have different numbers of samples due to decimation.

[0143] When the packet generation is completed within a time period, the multi-channel navigation DMA 205 reads the generated packet from the memory 109 and transmits the generated packet to the navigation channel 104 .

[0144] Packets in the navigation channel 104 may be processed in the following modes: CPU full control mode and first attempt automatic mode.

[0145] In one embodiment, in the CPU fully controlled mode: the CPU 107 controls all processing, and the packet is equal to the period of the tick signal S106.

[0146] In one embodiment, in the first attempt automatic mode: the CPU 107 controls the processing only once every certain number of packets (specifically, between the cycles of the tick signal S106). In this mode, the size of the packet is reduced in multiple steps and less storage space is required in the memory 109. The NS2CS interface block 202 automatically notifies the multi-channel navigation DMA 205 about the readiness of the new packet, and the multi-channel navigation DMA 205 allows the automatic transfer of the partial packet to the navigation channel 104. The multi-channel navigation DMA 205 reads the packet from the memory 109 and transfers it to the navigation channel 104.

[0147] The use of clock divider 212 and decimator 110 results in a reduction in the frequency of processing GNSS signals in navigation system 200, and a reduction in the size of packets from NS2CS interface block 202. By reducing the size of packets, processing time in navigation channel 104 is reduced, resulting in reduced power consumption of the GNSS receiver.

[0148] In one embodiment, multiple NS2CS interface blocks 202 write data to memory 109 via bus 213, bypassing bus 108. This reduces the load on bus 108 and writes packets to memory 109 with minimal delay.

[0149] In one embodiment, a computer is used to perform the operations described herein and, for example, Figure 2A , Figure 2B , Figure 2C , Figure 3, Figure 5 ,and Figure 7 The components and equations shown in FIG. These components may be, for example, ADC, signal processor, requantizer, etc. Fig.10 A high-level block diagram of such a computer is shown in . The computer 1102 includes a processor 1104, which controls the overall operation of the computer 1102 by executing computer program instructions that define such operations. The computer program instructions may be stored in a storage device 1112 or other computer-readable medium (e.g., a disk, a CD ROM, etc.), and the computer program instructions are loaded into the memory 1110 when the computer program instructions need to be executed. Therefore, the method steps described herein may be defined by computer program instructions stored in the memory 1110 and / or the storage device 1112, and the method steps described herein may be controlled by the processor 1104 executing the computer program instructions. For example, the computer program instructions may be implemented as a computer executable code written by a person skilled in the art to execute an algorithm defined by one of the various methods described herein. Therefore, by executing the computer program instructions, the processor 1004 executes the algorithm defined by the method steps described herein. The computer 1102 also includes one or more network interfaces 1106 to communicate with other devices via a network. The computer 1102 also includes input / output devices 1108 (e.g., a display, keyboard, mouse, speakers, buttons, etc.) that enable a user to interact with the computer 1102. Those skilled in the art will recognize that the actual computer implementation may also include other components, and Fig.10 is a high-level representation of some of the components of such a computer for illustrative purposes.

[0150] The foregoing detailed description should be understood to be illustrative and exemplary in all respects, rather than restrictive, and the scope of the inventive concept disclosed herein should be interpreted in accordance with the full scope permitted by patent law. It should be understood that the embodiments shown and described herein are merely illustrative of the principles of the inventive concept, and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept. Various other feature combinations may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept.

Claims

1. A navigation receiver, comprising: a plurality of RF paths, the plurality of RF paths being configured to receive GNSS signals; a phase-locked loop configured to generate a clock signal; a plurality of clock dividers, the plurality of clock dividers being configured to receive the clock signal and divide the clock signal; a plurality of navigation systems, each of the plurality of navigation systems receiving a clock signal from one of the plurality of clock dividers, each of the plurality of navigation systems operating with its own CLKnav, and each of the plurality of navigation systems comprising: a plurality of analog-to-digital converters (ADCs), each analog-to-digital converter configured to receive a GNSS signal from a corresponding RF path of the plurality of said RF paths and generate a digitized signal; a plurality of signal processors, the plurality of signal processors being configured to process the digitized signals; a plurality of decimators, the plurality of decimators being configured to decimate the digitized signal; A plurality of said signal processors are configured to process said extracted signals; a plurality of requantizers, the plurality of requantizers being configured to convert the processed decimated signals into low-bit data; a plurality of navigation system to CPU system (NS2CS) interface blocks, the plurality of said NS2CS interface blocks being configured to generate packets of a preset size based on said low bit data; A MUX interconnect device configured to distribute the data flow; and a time control unit configured to generate a tick signal, the tick signal being a time scale; a CPU system that operates based on the tick signal, each navigation system communicating with the CPU system, the CPU system running at CLKcpu and comprising: a memory configured to store data and packets; a multi-channel navigation direct memory access device (multi-channel navigation DMA), the multi-channel navigation DMA configured to convert the packet into data; a plurality of hardware accelerators, wherein the plurality of hardware accelerators are configured to process the packets; a plurality of channels, the plurality of channels being configured to process data received from the multi-channel navigation DMA; and A CPU is configured to control the plurality of navigation systems and the CPU system, and the CPU is configured to process data received from the plurality of channels, wherein: The CPU is configured to synchronize control among: a plurality of the decimators, a plurality of the signal processors, a plurality of the requantizers, a plurality of the NS2CS interface blocks, a plurality of the hardware accelerators, a plurality of the channels, and the multi-channel navigation DMA.

2. The navigation receiver according to claim 1, wherein: The outputs of the plurality of requantizers are input to the plurality of NS2CS interface blocks via the MUX interconnection device.

3. The navigation receiver according to claim 1, wherein: Each of the plurality of NS2CS interface blocks writes a packet to a memory and generates an interrupt to the CPU, and the CPU processes the interrupts from the plurality of NS2CS interface blocks.

4. The navigation receiver according to claim 1, wherein: Each NS2CS interface block of the plurality of NS2CS interface blocks writes the packet to a memory and generates a RUN signal.

5. The navigation receiver according to claim 1, wherein: Each of the plurality of NS2CS interface blocks starts forming packets based on the tick signal and resynchronizes data from the clock signal CLKnav to the clock signal CLKcpu.

6. The navigation receiver according to claim 1, wherein: Each of the plurality of NS2CS interface blocks generates a packet within a period of the tick signal.

7. The navigation receiver according to claim 1, wherein: Each of the plurality of NS2CS interface blocks generates a plurality of packets during a period of the tick signal.

8. The navigation receiver according to claim 1, wherein: Packets formed for the same time include different numbers of lower-order data samples.

9. The navigation receiver according to claim 1, wherein: The multi-channel navigation DMA reads packets simultaneously formed by the plurality of the NS2CS interface blocks from a memory, and the multi-channel navigation DMA converts the packets into data and transmits the data and an enable signal to the plurality of the channels.

10. The navigation receiver of claim 9, each of the plurality of data from the multi-channel navigation DMA has its own enable signal.

11. The navigation receiver according to claim 9, further comprising: A channel commutator receives data for a plurality of the channels transferred from the multi-channel navigation DMA, wherein corresponding data is processed in the channel if a selected enable signal is available.

12. The navigation receiver according to claim 1, wherein: The multi-channel navigation DMA reads packets from the memory in response to a signal from the CPU.

13. The navigation receiver according to claim 4, wherein: The multi-channel navigation DMA reads packets from the memory based on a RUN signal.

14. The navigation receiver according to claim 1, wherein: The multi-channel navigation DMA fixes data ready states in the plurality of channels based on an integration period signal, and the CPU reads the data ready states after processing data.

15. The navigation receiver according to claim 1, wherein: The CPU reads data from the plurality of channels and sends the current configuration of the channels and controls the channels between processing packets.

16. The navigation receiver according to claim 1, wherein: The CPU and the plurality of NS2CS interface blocks access the memory via a common bus or a dedicated bus.

17. The navigation receiver according to claim 9, wherein: Once the last packet in the current cycle of the tick signal has been formed, the multi-channel navigation DMA transmits an interrupt request signal to the CPU, and the CPU processes the interrupt request signal.

18. The navigation receiver according to claim 1, wherein: Data from the requantizer forming an output of the same number of samples in a time period is converted into packets by an NS2CS.

19. The navigation receiver of claim 1, wherein: The decimated signal is processed on a reduced clock that is synchronous with the clock signal CLKnav.

20. The navigation receiver of claim 1, wherein: The channel clock CLKcpu is enabled when the channel processes data from the multi-channel navigation DMA.

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