System and method for memory pooling

Abstract

Systems and methods for memory pooling are provided. The system includes: a plurality of memory devices; a host configured to communicate with the plurality of memory devices; and a switch connecting the host with the plurality of memory devices, the switch configured to receive a memory allocation request from the host and to allocate the plurality of memory devices in response to the received memory allocation request received from the host. At least one of the plurality of memory devices is allocated to the host based on the rank information of the host and the rank information of the plurality of memory devices.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0116265 filed on September 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Background Art

[0003] The inventive concept relates to memory pooling, and in particular, to memory pooling in a system using a compute express link (CXL) interface.

[0004] A device configured to process data can perform various operations by accessing a memory. For example, the device can process data read from the memory or write processed data on the memory. Due to the performance and functionality required by the system, various devices that communicate with each other via links that provide high bandwidth and low latency can be included in the system. The memory included in the system can be shared and accessed by two or more devices. Therefore, the performance of the system can depend on the communication efficiency between the devices and the time spent accessing the memory, as well as the operating speed of each device. Summary of the invention

[0005] The inventive concept provides a method of determining a rank of a host according to importance of data processed by the host and allocating a memory device corresponding to the determined rank of the host to the host.

[0006] Aspects of the various example embodiments are not limited thereto, and additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented example embodiments.

[0007] According to some aspects of the inventive concept, a system is provided, including: a plurality of memory devices, including a first memory device and a second memory device different from the first memory device; a host, configured to communicate with the plurality of memory devices; and a switch connecting the host with the plurality of memory devices, the switch being configured to receive a memory allocation request from the host, and in response to the received memory allocation request, allocate at least one of the plurality of memory devices to the host based on rank information of the host and rank information of the plurality of memory devices.

[0008] According to some aspects of the present invention, a method is provided, including: receiving device information from a plurality of memory devices, the plurality of memory devices including a first memory device and a second memory device different from the first memory device; determining ranks of the plurality of memory devices based on the device information; receiving a memory allocation request including category information of an application executed on the host from a host; determining the rank of the host based on the category information; and allocating at least one of the plurality of memory devices to the host based on the rank information of the host and the rank information of the plurality of memory devices.

[0009] According to some aspects of the inventive concept, a system is provided, including: a plurality of memory devices, including a first memory device and a second memory device different from the first memory device; a plurality of hosts, including a first host configured to communicate with the plurality of memory devices and a second host different from the first host; and a switch connecting the plurality of hosts with the plurality of memory devices, the switch being configured to receive a memory allocation request from at least two of the plurality of hosts, and in response to the received memory allocation request, allocate at least one of the plurality of memory devices to each of the plurality of hosts based on rank information of the plurality of hosts and rank information of the plurality of memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a computing system including a storage system according to some example embodiments;

[0012] Figure 2 is a block diagram illustrating elements in a computing system according to some example embodiments;

[0013] Figure 3 is a block diagram of a computing system according to some example embodiments;

[0014] FIG. 4A to FIG. 4D is a block diagram for describing allocation of memory devices to hosts according to some example embodiments;

[0015] Figure 5 is a diagram for describing device information according to some example embodiments;

[0016] Figure 6 is a flowchart for describing a method of allocating memory according to some example embodiments;

[0017] Figure 7 is a block diagram of a computing system according to some example embodiments;

[0018] Figure 8is a block diagram of a computing system according to some example embodiments;

[0019] Fig. 9 is a block diagram of a computing system according to some example embodiments; and

[0020] Fig.10 is a block diagram of a data center to which a computing system according to some example embodiments is applied. DETAILED DESCRIPTION

[0021] Hereinafter, one or more exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, and repeated descriptions thereof are omitted.

[0022] Figure 1 is a block diagram of a computing system 100 including a storage system, according to some example embodiments.

[0023] refer to Figure 1 , the computing system 100 may include a host 101 , a plurality of memory devices 102 a and 102 b , a compute express link (CXL) storage device 110 , and a CXL memory 120 .

[0024] In some example embodiments, the computing system 100 may be included in a user device such as a personal computer, a laptop computer, a server, a media player, a digital camera, etc., or in an automotive device such as a navigation, a blocking box, a vehicle electronic device, etc. Alternatively, the computing system 100 may include a mobile system such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device.

[0025] The host 101 may control the overall operation of the computing system 100. In some example embodiments, the host 101 may be one of various processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), etc. In some example embodiments, the host 101 may include a single-core processor or a multi-core processor.

[0026] As described herein, any electronic device and / or portion thereof according to any example embodiment may include one or more instances of processing circuitry, may be included in one or more instances of processing circuitry, and / or may be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor executing software; or any combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a memory) storing an instruction program, such as a DRAM device, and a processor (e.g., a CPU) configured to execute the instruction program to implement the functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or portion thereof according to any example embodiment and / or any portion thereof.

[0027] The plurality of memory devices 102a and 102b may be used as a main memory or a system memory in the computing system 100. In some example embodiments, the plurality of memory devices 102a and 102b may each include a dynamic random access memory (DRAM) device and may have a form factor of a dual in-line memory module (DIMM). However, the scope of the inventive concept is not limited thereto, and the plurality of memory devices 102a and 102b may include a non-volatile memory such as a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetoresistive random access memory (MRAM), etc.

[0028] The plurality of memory devices 102a and 102b may communicate directly with the host 101 via a double data rate (DDR) interface. In some example embodiments, the host 101 may include a memory controller configured to control the plurality of memory devices 102a and 102b. However, the scope of the inventive concept is not limited thereto, and the plurality of memory devices 102a and 102b may communicate with the host 102 via various interfaces.

[0029] The CXL memory device 110 may include a CXL memory controller 111 and a nonvolatile memory NVM. The CXL memory controller 111 may store data in the nonvolatile memory NVM or transmit data stored in the nonvolatile memory NVM to the host 101 according to a control from the host 101. In some example embodiments, the nonvolatile memory NVM may be a NAND flash memory, but the inventive concept is not limited thereto.

[0030] The CXL memory 120 may include a CXL memory controller 121 and a buffer memory BFM. The CXL memory controller 121 may store data in the buffer memory BFM or transmit data stored in the buffer memory BFM to the host 101 according to a control from the host 101. In some example embodiments, the buffer memory BFM may include a DRAM, but the inventive concept is not limited thereto.

[0031] In some example embodiments, the host 101, the CXL storage device 110, and the CXL memory 120 may be configured to share the same interface with each other. For example, the host 101, the CXL storage device 110, and the CXL memory 120 may communicate with each other via the CXL interface IF_CXL. In some example embodiments, the CXL interface IF_CXL may represent a low-latency and high-bandwidth link that enables various connections between accelerators, memory devices, or various electronic devices by supporting dynamic protocol multiplexing of coherence, memory access, and input / output protocols.

[0032] In some example embodiments, the CXL storage controller 111 may manage data stored in the nonvolatile memory NVM by using mapping data. The mapping data may include information on a relationship between a logical block address managed by the host 101 and a physical block address of the nonvolatile memory NVM.

[0033] In some example embodiments, the CXL memory device 110 may not include an additional buffer memory for storing or managing mapping data. In some example embodiments, a buffer memory for storing or managing mapping data may be required. In some example embodiments, at least some areas of the CXL memory 120 may be used as a buffer memory for the CXL memory device 110. In some example embodiments, a mapping table managed by a CXL memory controller 111 of the CXL memory device 110 may be stored in the CXL memory 120. For example, at least some areas of the CXL memory 120 may be allocated by the host 101 as a buffer memory for the CXL memory device 110 (e.g., an exclusive area for the CXL memory device 110).

[0034] In some example embodiments, the CXL memory device 110 may access the CXL memory 120 via the CXL interface IF_CXL. For example, the CXL memory device 110 may store a mapping table in an allocated area in the CXL memory 120 or read a mapping table from an allocated area in the CXL memory 120. According to control from the CXL memory device 110, the CXL memory 120 may store data (e.g., mapping data) in the buffer memory BFM or transfer data (e.g., mapping data) stored in the buffer memory BFM to the CXL memory device 110.

[0035] The CXL memory controller 111 of the CXL memory device 110 may communicate with the host 101 and the CXL memory (i.e., the buffer memory) via the CXL interface IF_CXL. In other words, the CXL memory controller 111 of the CXL memory device 110 may communicate with the host 101 and the CXL memory 120 via the same type of interface or a common interface, and may use a certain area of ​​the CXL memory 120 as a buffer memory.

[0036] Hereinafter, for ease of description, it is assumed that the host 101, the CXL storage device 110, and the CXL memory 120 communicate with each other via the CXL interface IF_CXL. However, the scope of the inventive concept is not limited thereto, that is, the host 101, the CXL storage device 110, and the CXL memory 120 may communicate with each other based on various computing interfaces (such as GEB-Z protocol, NVLink protocol, Cache Coherent Interconnect for Accelerators (CCIX) protocol, Open Coherent Accelerator Processor Interface (CAPI) protocol, etc.).

[0037] Figure 2 1 is a block diagram illustrating elements in a computing system 100 according to some example embodiments. In detail, Figure 2 It is shown in detail Figure 1 A block diagram of the components of the computing system 100 is shown in FIG. Figure 1 describe Figure 2 , and redundant descriptions can be omitted.

[0038] refer to Figure 2 The computing system 100 may include a CXL switch SW_CXL, a host 101 , a CXL storage device 110 , and a CXL memory 120 .

[0039] The CXL switch SW_CXL may be included in the CXL interface IF_CXL. The CXL switch SW_CXL may be configured to relay communications between the host 101, the CXL storage device 110, and the CXL memory 120. For example, when the host 101 and the CXL storage device 110 communicate with each other, the CXL switch SW_CXL may be configured to transfer information such as a request, data, a response, or a signal transmitted from the host 101 or the CXL storage device 110 to the CXL storage device 110 or the host 101. When the host 101 and the CXL memory 120 communicate with each other, the CXL switch SW_CXL may be configured to transfer information such as a request, data, a response, or a signal transmitted from the host 101 or the CXL memory 120 to the CXL memory 120 or the host 101. When the CXL storage device 110 and the CXL memory 120 communicate with each other, the CXL switch SW_CXL may be configured to transfer information such as a request, data, response, or signal transferred from the CXL storage device 110 or the CXL memory 120 to the CXL memory 120 or the CXL storage device 110. The host 101 may include a CXL host interface circuit 101a. The CXL host interface circuit 101a may communicate with the CXL storage device 110 or the CXL memory 120 via the CXL switch SW_CXL.

[0040] The CXL memory device 110 may include a CXL memory controller 111 and a nonvolatile memory NVM. The CXL memory controller 111 may include a CXL memory interface circuit 111a, a processor 111b, a RAM 111c, a flash translation layer (FTL) 111d, an error correction code (ECC) engine 111e, and a NAND interface circuit 111f.

[0041] The CXL storage interface circuit 111 a may be connected to the CXL switch SW_CXL. The CXL storage interface circuit 111 a may communicate with the host 101 or the CXL memory 120 via the CXL switch SW_CXL.

[0042] The processor 111 b may be configured to control the overall operation of the CXL memory controller 111. The RAM 111 c may be used as an operation memory or a buffer memory of the CXL memory controller 111.

[0043] The FTL 111d may perform various management operations using the nonvolatile memory NVM (e.g., efficiently). For example, the FTL 111d may perform address conversion between a logical block address managed by the host 101 and a physical block address used in the nonvolatile memory NVM based on mapping data (or a mapping table). The FTL 111d may perform a bad block management operation on the nonvolatile memory NVM. The FTL 111d may perform a wear leveling operation on the nonvolatile memory NVM. The FTL 111d may perform a garbage collection operation on the nonvolatile memory NVM.

[0044] In some example embodiments, the FTL 111d may be implemented based on software, hardware, firmware, or a combination thereof. When the FTL 111d is implemented in the form of software or firmware, program codes associated with the FTL 111d may be stored in the RAM 111c and may be driven by the processor 111b. When the FTL 111d is implemented as hardware, hardware elements formed to perform the above-described various management operations may be implemented in the CXL storage controller 111.

[0045] The ECC engine 111e may perform error detection and correction on data stored in the nonvolatile memory NVM. For example, the ECC engine 111e may generate parity bits with respect to user data UD to be stored in the nonvolatile memory NVM, and the generated parity bits may be stored in the nonvolatile memory NVM together with the user data UD. When the user data UD is read from the nonvolatile memory NVM, the ECC engine 111e may detect and correct errors in the user data UD by using the parity bits read from the nonvolatile memory NVM together with the user data UD.

[0046] The NAND interface circuit 111f may control the nonvolatile memory NVM so that data may be stored in or read from the nonvolatile memory NVM. In some example embodiments, the NAND interface circuit 111f may be implemented to comply with standard rules, such as a toggle interface or ONFI, etc. For example, the nonvolatile memory NVM may include a plurality of NAND flash memory devices, and when the NAND interface circuit 111f is implemented based on a toggle interface, the NAND interface circuit 111f may communicate with the plurality of flash memory devices via a plurality of channels. The plurality of NAND flash memory devices may be connected to the plurality of channels via a multi-channel / multi-way structure.

[0047] The nonvolatile memory NVM may store or output the user data UD according to the control from the CXL memory controller 111. The nonvolatile memory NVM may store or output the mapping data MD according to the control from the CXL memory controller 111. In some example embodiments, the mapping data MD stored in the nonvolatile memory NVM may include mapping information corresponding to the entire user data UD stored in the nonvolatile memory NVM. The mapping data MD stored in the nonvolatile memory NVM may be stored in the CXL memory 120 during the initialization operation of the CXL memory device 110.

[0048] The CXL memory 120 may include a CXL memory controller 121 and a buffer memory BFM. The CXL memory controller 121 may include a CXL memory interface circuit 121 a , a processor 121 b , a memory manager 121 c , and a buffer memory interface circuit 122 d .

[0049] The CXL memory interface circuit 121 a may be connected to the CXL switch SW_CXL. The CXL memory interface circuit 121 a may communicate with the host 101 or the CXL memory device 110 via the CXL switch SW_CXL.

[0050] The processor 121b may be configured to control the overall operation of the CXL memory controller 121. The memory manager 121c may be configured to manage the buffer memory BFM. For example, the memory manager 121c may be configured to convert a memory address (e.g., a logical address or a virtual address) accessed by the host 101 or the CXL memory device 110 into a physical address with respect to the buffer memory BFM. In some example embodiments, the memory address may be an address for managing a storage area of ​​the CXL memory 120, and may be a logical address or a virtual address specified and managed by the host 101.

[0051] The buffer memory interface 121d may control the buffer memory BFM so that data may be stored in or read from the buffer memory BFM. In some example embodiments, the buffer memory interface circuit 122d may be implemented to comply with standard rules, such as a DDR interface, a LPDDR interface, or the like.

[0052] The buffer memory BFM may store data or output the stored data according to control from the CXL memory controller 121. In some example embodiments, the buffer memory BFM may be implemented to store mapping data MD used in the CXL memory device 110. During an initialization operation of the computing system 100 or the CXL memory device 110, the mapping data MD may be transferred from the CXL memory device 110 to the CXL memory 120.

[0053] As described above, the CXL memory device 110 according to some exemplary embodiments of the inventive concept may store mapping data MD required for managing the nonvolatile memory NVM in the CXL memory 120 connected thereto via the CXL switch SW_CXL (or the CXL interface IF_CXL). Thereafter, when the CXL memory device 110 performs a read operation according to a request from the host 101, the CXL memory device 110 may read at least some mapping data MD from the CXL memory 120 via the CXL switch SW_CXL (or the CXL interface IF_CXL), and may perform a read operation based on the read mapping data MD. Alternatively, when the CXL memory device 110 performs a write operation according to a request from the host 101, the CXL memory device 110 may perform a write operation on the nonvolatile memory NVM and update the mapping data MD. Here, the updated mapping data MD may be mainly stored in the RAM 111 c of the CXL memory controller 111 , and the mapping data MD stored in the RAM 111 c may be transferred to the buffer memory BFM of the CXL memory 120 via the CXL switch SW_CXL (or the CXL interface IF_CXL) and updated.

[0054] In some example embodiments, at least some areas in the buffer memory BFM of the CXL memory 120 may be allocated as a dedicated area of ​​the CXL memory device 110 , and the remaining areas may be used as an area accessible to the host 101 .

[0055] In some example embodiments, the host 101 and the CXL storage device 110 may communicate with each other via CXL.io as an input / output protocol. CXL.io may have an inconsistent input / output protocol based on Peripheral Component Interconnect Express (PCIe). The host 101 and the CXL storage device 110 may exchange user data or various information with each other by using CXL.io.

[0056] In some example embodiments, the CXL memory device 110 and the CXL memory 120 may communicate with each other via CXL.mem as a memory access protocol. CXL.mem may be a memory access protocol supporting memory access. The CXL memory device 110 may access a certain area of ​​the CXL memory 120 (e.g., an area in which mapping data MD is stored or a dedicated area for the CXL memory device) by using CXL.mem.

[0057] In some example embodiments, the host 101 and the CXL memory 120 may communicate with each other by using CXL.mem as a memory access protocol. The host 101 may access the remaining area of ​​the CXL memory 120 (e.g., an area other than an area storing mapping data MD or an area other than a dedicated area for CXL storage) by using CXL.mem.

[0058] The above-mentioned access types (CXL.io, CXL.mem, etc.) are examples, and the scope of the present inventive concept is not limited to the above-mentioned examples.

[0059] In some example embodiments, the CXL storage device 110 and the CXL memory 120 may be installed in a physical port (e.g., a PCIe physical port) based on a CXL interface. In some example embodiments, the CXL storage device 110 and the CXL memory 120 may be implemented based on E1.S, E1.L, E3.S, E3.L, and PCIe AIC (CEM) form factors. Alternatively, the CXL storage device 110 and the CXL memory 120 may be implemented based on a U.2 form factor, an M.2 form factor, or other various types of PCIe-based form factors, or other various types of small form factors. The CXL storage device 110 and the CXL memory 120 may support a hot-swap function to be attachable to / detachable from a physical port. hereinafter referred to as Figure 8 Describe the hot-swap feature in detail.

[0060] Figure 3 is a block diagram of a computing system 200 according to some example embodiments.

[0061] In the specification, the computing system 200 may be referred to as a system. Figure 3 , the computing system 200 may correspond to Figure 2 A computing system 100 is provided. Figure 3 The computing system 200 may include a plurality of hosts 210_1 to 210_j (j is an integer of 2 or more), a CXL switch SW_CXL, and a plurality of memory devices 230_1 to 230_k (k is an integer of 2 or more). Here, the number of the plurality of hosts 210_1 to 210_j and the number of the plurality of memory devices 230_1 to 230_k may be different from each other. Figure 3 Each of the plurality of memory devices 230_1 to 230_k shown in FIG. 1 may correspond to a memory device that can be accessed through Figure 1 and Figure 2 The CXL storage device 110 , the CXL memory 120 or other peripheral devices communicating with the CXL interface IF_CXL shown in FIG.

[0062] A plurality of hosts 210_1 to 210_j may be configured to communicate with a plurality of memory devices 230_1 to 230_k via a CXL switch SW_CXL. Here, a host that needs memory allocation may transmit a memory allocation request to the CXL switch SW_CXL. The memory allocation request provided by the host to the CXL switch SW_CXL may include category information indicating the kind of application executed on the host. For example, when a banking application is executed on the first host 210_1, the memory allocation request sent from the first host 210_1 to the CXL switch SW_CXL may include category information indicating that the application being executed on the first host 210_1 is a banking application. In addition, for example, when a social network service (SNS) application is executed on the second host 210_2, the memory allocation request sent from the second host 210_2 to the CXL switch SW_CXL may include category information indicating that the application being executed on the second host 210_2 is an SNS application. As described above, the first host 210_1 and the second host 210_2 executing banking applications and SNS applications are examples, and the applications that can be executed on multiple hosts 210_1 to 210_j may include various applications such as security applications, media applications, game applications, browser applications, artificial intelligence (AI) applications, etc.

[0063] Figure 3 The CXL switch SW_CXL may correspond to Figure 1 In the specification, the CXL switch SW_CXL may be simply referred to as a switch. The CXL switch SW_CXL may be configured to provide connections between the plurality of hosts 210_1 to 210_j and the plurality of memory devices 230_1 to 230_k.

[0064] The CXL switch SW_CXL may include a fabric manager 221. The fabric manager 221 may allocate memory devices to the plurality of hosts 210_1 to 210_j based on the ranks of the plurality of hosts 210_1 to 210_j and the ranks of the plurality of memory devices 230_1 to 230_k. Here, the rank of the host indicates a processing priority of the host (e.g., an application executed by the host, a plurality of applications allocated to the host, etc.). In some example embodiments, the higher the rank of the host, the higher the priority that an application running on the host may have. For example, if the rank of the first host 210_1 is the first rank and the rank of the second host 210_2 is the second rank, the application executed by the first host 210_1 may be an application that may be processed with priority over the application executed by the second host 210_2. A memory device of a higher rank may be allocated to the first host 210_1. The fabric manager 221 may determine the rank of the host that has sent the memory allocation request based on the category information of the application executed by the host that has sent the memory allocation request. Here, the rank of the memory device indicates performance determined based on device information of the memory device. In some example embodiments, the higher the rank of a memory device, the faster the data input / output speed of the memory device. For example, when the rank of the first memory device 230_1 is the first rank and the rank of the second memory device 230_2 is the second rank, the first memory device 230_1 may have a faster data input / output speed than the second memory device 230_2. The structure manager 221 may determine the rank of the memory device based on the device information sent by the memory device to the structure manager 221. In some example embodiments, the device information of the memory device may include memory device type information, bandwidth information, latency information, refresh cycle information, operating voltage information, and operating temperature information. In some example embodiments, the structure manager 221 may assign a higher rank memory device to a host with a higher rank. In this specification, a high rank may mean a smaller rank number. For example, the first rank may be a rank greater than the second rank.

[0065] In response to memory allocation requests received from a plurality of hosts 210_1 to 210_j, the fabric manager 221 may determine the rank of the host that sent the memory allocation request, and may generate host rank information indicating the determined rank. The fabric manager 221 may determine the rank of the host that sent the memory allocation request based on category information about an application executed on the host that sent the memory allocation request. The rank of the host may be one of the first to Nth ranks (N is an integer of 2 or more).

[0066] In some example embodiments, the fabric manager 221 may determine the rank of the host that sent the memory allocation request in response to the memory allocation request from the host. Here, the rank of the host may be determined according to a rank determination reference value corresponding to the category information about the application executed on the host. The rank determination reference value may be predefined and stored in the fabric manager 221. For example, when an application (such as a banking application or a security application) requiring fast data processing is executed on the first host 210_1 that sends the memory allocation request to the fabric manager 221, the fabric manager 221 may determine the rank of the first host 210_1 to be a larger rank. For example, the fabric manager 221 may determine the rank of the first host 210_1 to be a first rank. In addition, for example, when an application (such as an SNS application) that does not require fast data processing compared to an application corresponding to the first rank is executed on the second host 210_2 that sends the memory allocation request to the fabric manager 221, the fabric manager 221 may determine that the rank of the second host 210_2 is less than the first rank. For example, the fabric manager 221 may determine the rank of the second host 210_2 to be a second rank. As described above, the fabric manager 221 may determine the level of the host according to the category information about the application executed on the host.

[0067] The fabric manager 221 may determine the ranks of the plurality of memory devices 230_1 to 230_k and may generate memory device rank information indicating the determined ranks. The fabric manager 221 may determine the rank of the corresponding memory device based on device information transmitted from the corresponding memory device to the fabric manager 221. The rank of the memory device may be one of the first rank to the Mth rank (M is an integer of 2 or more).

[0068] When a memory device is connected to the CXL switch SW_CXL, the fabric manager 221 may determine the rank of the memory device connected to the CXL switch SW_CXL based on the device information received from the memory device. For example, when the first memory device 230_1 is connected to the CXL switch SW_CXL, the first memory controller 231_1 of the first memory device 230_1 may provide the fabric manager 221 with first device information indicating the state of the first memory device 230_1. The fabric manager 221 may determine the rank of the first memory device 230_1 based on the first device information received from the first memory controller 231_1, and may generate first memory device rank information indicating the rank of the first memory device 230_1. For example, according to some example embodiments, based on the above method, the speed, accuracy and / or power efficiency of communication and operation of the device may be improved. Therefore, the improved device and method overcome the defects of conventional devices and methods of memory devices including memory devices related to the use of multiple memory devices, while reducing resource consumption, data accuracy and increasing data clarity. In addition, by providing the capabilities disclosed above, there is improvement in communication control and reliability between different memory devices.

[0069] In some example embodiments, the device information may be referred to as device status information, status information, or health information. Figure 5 Describes the device information in more detail.

[0070] The structure manager 221 may include a plurality of device status registers 221_1 to 221_k. In the specification, the device status register may be referred to as a register. Each device status register may include device information about a memory device corresponding to each device status register. For example, the first device status register 221_1 may store device information about the first memory device 230_1, and the kth device status register 221_k may store device information about the kth memory device 230_k.

[0071] In some example embodiments, fabric manager 221 may be implemented based on software, hardware, firmware, or a combination thereof.

[0072] A plurality of memory devices 230_1 to 230_k may include memory controllers 231_1 to 231_k and memory pools 232_1 to 232_k, respectively, and each memory pool may include a plurality of memory blocks. For example, a first memory device 230_1 may include a first memory controller 231_1 and a first memory pool 232_1. The first memory pool 232_1 may include a plurality of memory blocks. Each memory block may be a unit for logically dividing the first memory pool 232_1. In the specification, allocating a memory device to a host may mean allocating at least one of the memory blocks included in the memory pool of the memory device to the host.

[0073] FIG. 4A to FIG. 4D is a block diagram for describing allocation of a memory device to a host according to some example embodiments. In detail, Figure 4A is a diagram for describing a method of allocating a memory device to each of a plurality of hosts 210_1 to 210_j included in a computing system 200. Figure 4B is a diagram showing the rank of each of a plurality of hosts 210_1 to 210_j. Figure 4C is a diagram showing a hierarchy of each of a plurality of memory devices 230_1 to 230_k. Figure 4D is a diagram for describing the allocation between a plurality of hosts 210_1 to 210_j and a plurality of memory devices 230_1 to 230_k. Figure 3 describe FIG. 4A to FIG. 4D , and redundant descriptions can be omitted.

[0074] refer to Figure 4A , the fabric manager 221 may allocate memory devices to the plurality of hosts 210_1 to 210_j based on the ranks of the plurality of hosts 210_1 to 210_j and the ranks of the plurality of memory devices 230_1 to 230_k, such as Figure 4D shown.

[0075] Assumptions Figure 4A The levels of the plurality of hosts 210_1 to 210_j shown in FIG. Figure 4B That is, it is assumed that the level of the first host 210_1 is the first level, the level of the second host 210_2 is the second level, and the levels of the third host 210_3 to the j-th host 210_j are the third level. In addition, it is assumed that Figure 4A The hierarchy of the plurality of memory devices 230_1 to 230_k shown in FIG. Figure 4C That is, it is assumed that the rank of the first memory device 230_1 is the first rank, the rank of the second memory device 230_2 is the second rank, and the ranks of the third to k-th memory devices 230_3 to 230_k are the third rank.

[0076] In some example embodiments, because the first host 210_1 has the first rank, the fabric manager 221 may allocate the highest rank (ie, first rank) memory device to the first host 210_1. In other words, the fabric manager 221 may allocate the first memory device 230_1 to the first host 210_1.

[0077] In some example embodiments, when the memory required by the first host 210_1 is greater than the available memory of the first memory 230_1, the fabric manager 221 may allocate a first-level memory device of the same level as the first memory device 230_1 to the first host 210_1. Here, when there is no other memory device of the same level as the first memory device 230_1 in the computing system 200, or when there is no available memory that can be allocated to the first host 210_1, a memory device of the next level may be allocated to the first host 210_1. That is, as Figure 4A As shown, the fabric manager 221 may allocate a second memory device 230_2 having a second rank to the first host 210_1 .

[0078] In some example embodiments, because the second host 210_2 has the second rank, the fabric manager 221 may allocate to the second host 210_2 a memory device having a rank that is equal to or less than the rank of the memory device allocated to the first host 210_1. For example, the fabric manager 221 may allocate the second memory device 230_2 having the second rank to the second host 210_2.

[0079] In some example embodiments, because the third host 210_3 has a third rank, the fabric manager 221 may allocate a memory device having a rank equal to or less than the rank of the memory device allocated to the second host 210_2 to the third host 210_3. For example, the fabric manager 221 may allocate a third memory device 230_3 having a third rank to the third host 210_3. In some example embodiments, the first host 210_1 to the j-th host 210_j may read / write data from / to the allocated blocks of the memory device. For example, by allocating some or all of the memory devices to the host, the host may then control writing data and / or reading data, as well as performing other actions related to the allocated blocks.

[0080] Figure 5 is a diagram for describing device information according to some example embodiments. Figures 3 to 4D describe Figure 5 , and redundant descriptions can be omitted.

[0081] Figure 5 The table shows device information and device level information corresponding to each of the plurality of memory devices 230_1 to 230_k. The device information may include type information, bandwidth information, delay information, refresh cycle information, operating voltage information, operating temperature information, etc. of each memory device. For example, the first device information DI1 may include information indicating the type, bandwidth, delay, refresh cycle, operating voltage, and operating temperature of the first memory device 230_1.

[0082] In some example embodiments, the structure manager 221 may score each item in the device information and determine the rank of each memory device according to the score. For example, the structure manager 221 may store a predefined minimum reference value for determining each memory device as the first rank. Here, when the value of the score considering all bandwidth information, latency information, refresh cycle information, operating voltage information, and operating temperature information about the first memory device 230_1 is greater than the minimum reference value of the first rank, the structure manager 221 may determine the rank of the first memory device 230_1 as the first rank, and may generate first memory device rank information DGI1 indicating the rank of the first memory device 230_1. As described above, the structure manager 221 may store the minimum reference value for determining the second rank to the Mth rank (M is an integer of 2 or more) of each memory device.

[0083] In some example embodiments, the first memory controller 231_1 of the first memory device 230_1 may provide the first device information DI1 to the fabric manager 221. The fabric manager 221 may determine the rank of the first memory device 230_1 based on the first device information DI1. The fabric manager 221 may generate first memory device rank information DGI1 indicating the rank of the first memory device 230_1. The fabric manager 221 may store the first device information DI1 and the first memory device rank information DGI1 in the first device status register 221_1.

[0084] Figure 6 is a flowchart for describing a method of allocating memory according to some example embodiments. Figure 3 describe Figure 6 , and redundant descriptions can be omitted.

[0085] In operation S110 , the fabric manager 221 may receive device information from a plurality of memory devices 230_ 1 through 230 — k.

[0086] In some example embodiments, the fabric manager 221 may receive device information from a first memory device 230_1 and a second memory device 230_2 different from the first memory device.

[0087] In operation S120 , the fabric manager 221 may determine a rank of each of the plurality of memory devices 230_ 1 through 230 — k based on the device information received in operation S110 .

[0088] In some example embodiments, the fabric manager 221 may determine the rank of the first memory device 230_1 as one of first to Mth ranks (M is an integer of 2 or greater) based on the first device information DI1 received from the first memory device 230_1. The fabric manager 221 may generate first memory device rank information DGI1 indicating the rank of the first memory device 230_1.

[0089] In some example embodiments, the fabric manager 221 may store the first device information DI1 and the first memory device level information DGI1 in the first device status register 221_1 .

[0090] In some example embodiments, the fabric manager 221 may determine the rank of the memory device when the corresponding memory device is connected to the CXL switch SW_CXL. For example, when the first memory device 230_1 is connected to the CXL switch SW_CXL, the fabric manager 221 may determine the rank of the first memory device 230_1. Similarly, when the second memory device 230_2 is connected to the CXL switch SW_CXL, the fabric manager 221 may determine the rank of the second memory device 230_2.

[0091] In operation S130 , the fabric manager 221 may receive a memory allocation request from the host.

[0092] In some example embodiments, a host requiring memory allocation from among the plurality of hosts 210_1 to 210_j may send a memory allocation request to the fabric manager 221. For example, the first host 210_1 may send a memory allocation request to the fabric manager 221, the memory allocation request including category information about an application being executed on the first host 210_1.

[0093] In operation S140 , the fabric manager 221 may determine a rank of a host that transmits the memory allocation request received in operation S130 .

[0094] In some example embodiments, the fabric manager 221 may determine the rank of the host in response to a memory allocation request received from the host. For example, when the first host 210_1 sends a memory allocation request to the fabric manager 221, the fabric manager 221 may determine the rank of the first host 210_1.

[0095] In some example embodiments, the fabric manager 221 may determine the level of the host based on category information about an application executing on the host.

[0096] In operation S150 , the fabric manager 221 may allocate memory devices to hosts based on the ranks of the hosts and the ranks of the memory devices.

[0097] In some example embodiments, when the first host 210_1 has a first rank, the first memory device 230_1 may be assigned to the host 210_1, and when the first host 210_1 has a second rank, the second memory device 230_2 may be assigned to the first host 210_1. Here, the rank of the first memory device 230_1 may be greater than the rank of the second memory device 230_2. For example, the first memory device 230_1 may have a first rank, and the second memory device 230_2 may have a second rank.

[0098] Figure 7 is a block diagram of a computing system 400 according to some example embodiments. Hereinafter, for convenience of description, detailed descriptions of elements provided in the above embodiments are omitted.

[0099] refer to Figure 7 , the computing system 400 may include a host 401, a plurality of memory devices 302a and 302b, a CXL switch SW_CXL, a plurality of CXL storage devices 410_1 to 410_m, and a plurality of CXL memories 420_1 to 420_n.

[0100] The host 401 may be directly connected to the plurality of memory devices 402a and 402b. The host 401, the plurality of CXL storage apparatuses 410_1 to 410_m, and the plurality of CXL memories 420_1 to 420_n may be connected to the CXL switch SW_CXL, and may communicate with each other via the CXL switch SW_CXL.

[0101] In some example embodiments, the host 401 may manage the plurality of CXL storage devices 410_1 to 410_m as one storage device cluster, and manage the plurality of CXL memories 420_1 to 420_n as one storage device cluster. The host 401 may allocate a certain area of ​​the storage cluster to one storage device cluster as a dedicated area (i.e., an area for storing mapping data of the storage device cluster). Alternatively, the host 401 may allocate areas in the plurality of CXL memories 420_1 to 420_n to the plurality of CXL storage devices 410_1 to 410_m as dedicated areas, respectively.

[0102] Figure 8is a block diagram of a computing system 500 according to some example embodiments. Hereinafter, for convenience of description, detailed descriptions of elements provided in the above embodiments are omitted.

[0103] refer to Figure 8 , the computing system 500 may include a host 501 , a plurality of memory devices 502 a and 502 b , a CXL switch SW_CXL, a plurality of CXL storage devices 510_1 , 510_2 , and 510_3 , and a plurality of CXL memories 520_1 , 520_2 , and 520_3 .

[0104] The host 501 may be directly connected to a plurality of memory devices 502a and 502b. The host 501, a plurality of CXL storage devices 510_1 and 510_2, and a plurality of CXL memories 520_1 and 520_2 may be connected to a CXL switch SW_CXL and may communicate with each other via the CXL switch SW_CXL. Similar to the above description, some areas of the CXL memories 520_1 and 520_2 may be allocated as dedicated areas for the CXL storage devices 510_1 and 510_2.

[0105] In some example embodiments, during driving of the computing system 500, the CXL storage devices 510_1 and 510_2 or the CXL memories 520_1 and 520_2 may be partially released from the connection with the CXL switch SW_CXL or removed from the CXL switch SW_CXL (hot removal). Alternatively, during driving of the computing system 500, the CXL storage device 510_3 or the CXL memory 520_3 may be connected to or added to the CXL switch SW_CXL (hot addition). In some example embodiments, the host 501 may re-perform memory allocation by performing an initialization operation on a device connected to the CXL switch SW_CXL through a reset operation or a hot plug operation. That is, the CXL storage device and the CXL memory according to some example embodiments may support a hot plug function, and through various connections, the storage capacity and the memory capacity of the computing system may be expanded.

[0106] Fig. 9 is a block diagram of a computing system 1000 according to some example embodiments. Hereinafter, for convenience of description, detailed descriptions of elements provided in the above embodiments are omitted.

[0107] refer to Fig. 9The computing system 1000 may include a first central processing unit (CPU) 1110 , a second CPU 1120 , a graphics processing unit (GPU) 1130 , a neural processing unit (NPU) 1140 , a CXL switch SW_CXL, a CXL storage device 1210 , a CXL memory 1220 , a PCIe device 1310 , and an accelerator (CXL device) 1320 .

[0108] The first CPU 1110 , the second CPU 1120 , the GPU 1130 , the NPU 1140 , the CXL storage 1210 , the CXL memory 1220 , the PCIe device 1310 , and the accelerator (CXL device) 1320 may be commonly connected to the CXL switch SW_CXL and may communicate with each other via the CXL switch SW_CXL.

[0109] In some example embodiments, each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140 may be the above-referenced Figures 1 to 8 describes the host and can be directly connected to individual storage devices.

[0110] In some example embodiments, the CXL storage device 1210 and the CXL memory 1220 may correspond to the above referenced Figures 1 to 8 The CXL storage device and the CXL memory described above, and at least a partial area of ​​the CXL memory 1220 may be allocated as a dedicated area for the CXL storage device 1210 by one or more of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140. That is, the CXL storage device 1210 and the CXL memory 1220 may be used as a storage space STR of the computing system 1000.

[0111] In some example embodiments, the CXL switch SW_CXL may be connected to a PCIe device 1310 or an accelerator 1320 configured to support various functions, and the PCIe device 1310 or the accelerator 1320 may communicate with each of the first CPU 1110, the second CPU 1120, the GPU 1130, and the NPU 1140, or may access a storage space STR including a CXL storage device 1210 and a CX memory 1220 via the CXL switch SW_CXL.

[0112] In some example embodiments, the CXL switch SW_CXL may be connected to an external network or fabric, and may communicate with an external server via the external network or fabric.

[0113] Fig.10is a block diagram of a data center 2000 to which a computing system according to some example embodiments is applied. Hereinafter, for convenience of description, detailed descriptions of elements provided in the above-described embodiments are omitted.

[0114] refer to Fig.10 , the data center 2000 is a facility that collects various data and provides services, and may be referred to as a data storage center. The data center 2000 may be a system for operating a search engine and a database, and may be a computing system used in a company such as a bank or a government organization. The data center 2000 may include application servers 2110 to 21m0 and storage servers 2210 to 22n0. The number of application servers and the number of storage servers may be selected in various ways according to the embodiment, and the number of application servers may be different from the number of storage servers.

[0115] Hereinafter, the following mainly describes the structure of the first storage server 2210. Each of the application servers 2110 to 21m0 and each of the storage servers 2210 to 22n0 may have similar structures to each other, and the application servers 2110 to 21m0 and the storage servers 2210 to 22n0 may communicate with each other via the network NT.

[0116] The first storage server 2210 may include a processor 2211, a memory 2212, a switch 2213, a storage device 2215, a CXL memory 2214, and a network interface card (NIC) 2216. The processor 2211 may control the overall operation of the first storage server 2210, and may access the memory 2212 to execute instructions loaded on the memory 2212 or process data. Examples of the memory 2212 may include a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, and / or a non-volatile DIMM (NVMDIMM). The processor 2211 and the memory 2212 may be directly connected to each other, and the number of processors 2211 and the number of memories 2212 included in one storage server 2210 may be selected in different ways.

[0117] In some example embodiments, the processor 2211 and the memory 2212 may provide a processor-memory pair. In some example embodiments, the number of processors 2211 may be different from the number of memories 2212. The processor 2211 may include a single-core processor or a multi-core processor. The above description about the storage server 2210 may be similarly applied to each of the application servers 2110 to 21m0.

[0118] The switch 2213 may be configured to relay or route communications between various elements included in the first storage server 2210. In some example embodiments, the switch 2213 may include the Figures 1 to 9 The described CXL switch SW_CXL. That is, the switch 2213 can be implemented based on the CXL protocol.

[0119] CXL memory 2214 may be connected to switch 2213. In some example embodiments, CXL memory 2214 may be used as a memory expander for processor 2211. Alternatively, CXL memory 2214 may be allocated as exclusive memory or buffer memory for storage device 2215, as described above with reference to Figures 1 to 9 as described.

[0120] The storage device 2215 may include a CXL interface circuit CXL_IF, a controller CTRL, and a NAND flash memory NAND. The storage device 2215 may store data or output stored data according to a request from the processor 2211. In some example embodiments, the storage device 2215 may include the above-mentioned reference Figures 1 to 9 In some example embodiments, storage device 2215 may be allocated at least a portion of CXL memory 2214 as a CXL storage device similar to reference 2214. Figures 1 to 9 A dedicated area for the description is provided, and the dedicated area may be used as a buffer memory (ie, mapping data is stored in CXL memory 2214).

[0121] According to some example embodiments, the application servers 2210 to 21m0 may not include the storage device 2215. The storage server 2210 may include at least one storage device 2215. According to example embodiments, the number of storage devices 2215 included in the storage server 2210 may be selected in various ways.

[0122] The NIC 2216 may be connected to the CXL switch SW_CXL. The NIC 2216 may communicate with other storage servers 2220 to 22n0 or other application servers 2110 to 21m0 via the network NT.

[0123] In some example embodiments, the NIC 2216 may include a network interface card, a network adapter, etc. The NIC 2216 may be connected to the network NT via a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 2216 may include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and may be connected to the processor 2211 and / or the switch 2213 via the host bus interface. In some example embodiments, the NIC 2216 may be integrated with at least one of the processor 2211, the switch 2213, and the storage device 2215.

[0124] In some example embodiments, the network NT may be implemented by using Fibre Channel (FC), Ethernet, etc. Here, FC is a medium for transmitting data at a relatively high speed, and an optical switch providing high performance / high availability may be used. Depending on the access type of the network NT, the storage servers may each be provided as file storage, block storage, or object storage.

[0125] In some example embodiments, the network NT may include a storage-exclusive network, such as a storage area network (SAN). For example, the SAN may include an FC-SAN that may use an FC network and may be implemented according to the FC protocol (FCP). Otherwise, the SAN may include an IP-SAN that may use a transmission control protocol / Internet protocol (TCP / IP) network and may be implemented according to a small computer system interface (SCSI) or Internet SCSI (iSCSI) protocol over TCP / IP. In some example embodiments, the network NT may include a general network such as a TCP / IP network. For example, the network NT may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), non-volatile memory express (NVMe) over fabric (NVMe-oF), and the like.

[0126] In some example embodiments, at least one of the application servers 2110 to 21m0 may store data requested to be stored from a user or client in one of the storage servers 2210 to 22n0 via the network NT. At least one of the application servers 2110 to 21m0 may obtain data requested to be read from a user or client from one of the storage servers 2210 to 22n0 via the network NT. For example, at least one of the application servers 2110 to 21m0 may be implemented as a network server, a database management system (DBMS), and the like.

[0127] In some example embodiments, at least one of the application servers 2110 to 21m0 may access a memory, CXL memory, or storage device included in another application server via the network NT, or may access a memory, CXL memory, or storage device included in the storage servers 2210 to 22n0 via the network NT. In this way, at least one of the application servers 2110 to 21m0 may perform various operations on data stored in another application server and / or storage server. For example, at least one of the application servers 2110 to 21m0 may execute instructions for moving or copying data between different application servers and / or storage servers. Here, data may be moved from a storage device of a storage server to a memory or CXL memory of an application server directly or through a memory or CXL memory of a storage server. For security or privacy, data moved over the network may be encrypted.

[0128] In some example embodiments, a storage device included in at least one of the application servers 2110 to 21m0 and the storage servers 2210 to 22n0 may receive allocation of a CXL memory included in at least one of the application servers 2110 to 21m0 and the storage servers 2210 to 22n0 as a dedicated area, and the storage device may use the dedicated area as a buffer memory (i.e., storing mapping data). For example, a storage device 2215 included in the storage server 2210 may receive allocation of a CXL memory included in another storage server (e.g., 22m0), and may access the CXL memory included in the other storage server (e.g., 22m0) via the switch 2213 and the NIC 2216. In some example embodiments, mapping data about the storage device 2215 of the first storage server 2210 may be stored in the CXL memory of the other storage server 22m0. That is, the storage device and the CXL memory of the data center according to the inventive concept may be connected and implemented in various ways.

[0129] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A system for storage, comprising: a plurality of memory devices, including a first memory device and a second memory device different from the first memory device; a host configured to communicate with the plurality of memory devices; as well as A switch connecting the host and the plurality of memory devices, the switch being configured to: receiving a memory allocation request from the host, and In response to the received memory allocation request, at least one of the plurality of memory devices is allocated to the host based on rank information of the host and rank information of the plurality of memory devices.

2. The system according to claim 1, wherein: The switch is also configured to: receiving device information from the first memory device, determining a rank of the first memory device as one of a first rank to an Mth rank based on the device information received from the first memory device, M being an integer of 2 or greater, and Memory device rank information indicative of the rank of the first memory device is generated.

3. The system according to claim 2, wherein: The device information includes at least one of device type information, bandwidth information, latency information, cell capacity information, voltage information, and temperature information corresponding to the first memory device.

4. The system according to claim 2, wherein: The switch includes a device information register configured to store first device information indicating a state of the first memory device and the rank information of the first memory device.

5. The system according to claim 2, wherein: The first memory device also includes a first memory controller configured to transmit the device information to the switch.

6. The system according to claim 2, wherein: The switch is also configured to: determining a rank of the host based on receiving the memory allocation request from the host and generating host rank information indicating the rank of the host, and The memory device rank information indicating the rank of the first memory device is generated when the first memory device is connected to the switch.

7. The system of claim 1, wherein The memory allocation request includes category information of an application executed on the host, and The switch is further configured to determine a level of the host as one of a first level to an Nth level based on the category information of the application, where N is an integer of 2 or more.

8. The system according to claim 7, wherein: The switch is also configured to: allocating the first memory device to the host based on the rank of the host being a first rank, Based on the rank of the host being the second rank and the rank of the second memory device being lower than the rank of the first memory device, the second memory device is allocated to the host.

9. A method for storage, comprising: receiving device information from a plurality of memory devices, the plurality of memory devices comprising a first memory device and a second memory device different from the first memory device; determining a rank of the plurality of memory devices based on the device information; receiving a memory allocation request from a host, the memory allocation request including category information of an application executed on the host; determining a level of the host based on the category information; as well as At least one of the plurality of memory devices is allocated to the host based on the rank information of the host and the rank information of the plurality of memory devices.

10. The method according to claim 9, wherein: Determining the rank of the plurality of memory devices includes: determining a rank of the first memory device as one of a first rank to an Mth rank based on the device information received from the first memory device, M being an integer of 2 or greater; and Memory device rank information indicative of the rank of the first memory device is generated.

11. The method according to claim 9, wherein: The device information includes at least one of device type information, bandwidth information, latency information, cell capacity information, voltage information, and temperature information corresponding to the first memory device.

12. The method according to claim 10, wherein Determining the level of the host includes: determining the rank of the host based on the memory allocation request received from the host; as well as generating host rank information indicating the rank of the host, and Determining the rank of the plurality of memory devices comprises: The memory device rank information indicating the rank of the first memory device is generated based on the first memory device being connected to the switch.

13. The method according to claim 9, wherein: Determining the rank of the host includes determining the rank of the host as one of a first rank to an Nth rank based on the category information, N being an integer of 2 or greater.

14. The method according to claim 13, wherein: Allocating at least one of the plurality of memory devices to the host comprises: allocating the first memory device to the host based on the rank of the host being a first rank; and Based on the rank of the host being the second rank and the rank of the second memory device being lower than the rank of the first memory device, the second memory device is allocated to the host.

15. A system for storage, comprising: a plurality of memory devices, including a first memory device and a second memory device different from the first memory device; a plurality of hosts, including a first host configured to communicate with the plurality of memory devices and a second host different from the first host; as well as A switch connecting the plurality of hosts and the plurality of storage devices, the switch being configured to: receiving a memory allocation request from at least two of the plurality of hosts, and In response to the received memory allocation request, at least one of the plurality of memory devices is allocated to each of the plurality of hosts based on rank information of the plurality of hosts and rank information of the plurality of memory devices.

16. The system of claim 15, wherein: The switch is also configured to: receiving device information from the first memory device, determining a rank of the first memory device as one of a first rank to an Mth rank based on the device information received from the first memory device, M being an integer of 2 or greater, and Memory device rank information indicating the determined rank of the first memory device is generated.

17. The system of claim 16, wherein: The device information includes at least one of device type information, bandwidth information, latency information, cell capacity information, voltage information, and temperature information corresponding to the first memory device.

18. The system of claim 16, wherein: The switch includes a device information register configured to store first device information indicating a state of the first memory device and the rank information of the first memory device.

19. The system of claim 15, wherein The memory allocation request includes Category information of the application executed on the first host, and The switch is also configured to: The level of the first host is determined as one of a first level to an Nth level based on the category information of the application, N being an integer of 2 or more.

20. The system of claim 19, wherein The category information of the first host is different from the category information of the second host, The switch is further configured to assign the first memory device to the first host and assign the second memory device to the second host based on the rank of the first host being greater than the rank of the second host and the rank of the first memory device being greater than or equal to the rank of the second memory device, and based on the rank of the first host being less than the rank of the second host and the rank of the first memory device being less than or equal to the rank of the second memory device.

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