In-memory computing system with built-in subtraction mode for supporting matrix vector multiplication of signed feature data and signed computational weight data

Abstract

The invention relates to an in-memory computing system with a built-in subtraction mode for supporting matrix vector multiplication of signed feature data and signed computational weight data. In-memory computing circuitry includes a memory array in which memory cells are arranged in a matrix in rows and columns. The memory cell group stores a calculation weight for an in-memory calculation (IMC) operation performed by a first multiplication and accumulation (MAC) refinement to generate a first analog signal, and performed by a second MAC refinement to generate a second analog signal. The analog-to-digital converter circuit is operative to: incrementing a count value in the counter circuit in response to a first analog signal; the counting value in the counter circuit is converted into a negated counting value; and incrementing the count value in the counter circuit from the negated count value in response to the second analog signal.

Description

Technical Field

[0001] Embodiments relate to in-memory computing systems, and more particularly to systems supporting in-memory computing operations involving matrix-vector multiplication of signed feature data and signed computation weight data. Background Art

[0002] In-memory computing (IMC) systems store information in bit cells of a memory array and perform operations at the bit cell level. An example of an operation performed by an IMC system is a multiply and accumulate (MAC) operation using a matrix-vector multiplication (MVM), where an input digital array (X values, also called feature or coefficient data) is multiplied by an array of computational weights (g values) stored in memory, and the products are then added together to produce an output digital array (Y values).

[0003]

[0004]

[0005] By performing these operations at the bit cell level in memory, IMC systems do not need to move data back and forth between memory devices and computing devices. Therefore, the limitations associated with data transfer bandwidth between devices are eliminated, and calculations can be performed with lower power consumption.

[0006] It can be appreciated that the characteristic or coefficient data X of the computational operation in the memory n The data value can be signed, and the calculation weight data g of the calculation operation in the memory mn The data values ​​of X can also be signed. With respect to supporting matrix-vector multiplication using signed data, each in-memory computation operation can be performed to include positive elaboration with feature or coefficient data X. n And calculate the weight data g mn are all positive or all negative) and negative elaboration (negative elaboration, which is related to the feature or coefficient data X n And calculate the weight data g mn The result of the matrix-vector multiplication of the in-memory computation operation is then determined by the difference between the result of the positive refinement and the result of the negative refinement.

[0007] There is a need in the art to efficiently support the execution of signed MAC operations that use both positive and negative refinement for each in-memory compute operation. Summary of the invention

[0008] In an embodiment, an in-memory computation circuit comprises: a memory array including a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein a group of memory cells stores computation weights for an in-memory computation (IMC) operation performed by a first multiplication and accumulation (MAC) refinement generating a first analog signal and a second MAC refinement generating a second analog signal; and an analog-to-digital converter circuit configured to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit into a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.

[0009] The analog-to-digital converter circuit includes: an integration circuit configured to integrate a first analog signal to generate a first series of pulses, and a counter circuit increments a count value in response to each pulse in the first series of pulses; and wherein the integration circuit is also configured to integrate a second analog signal to generate a second series of pulses, and the counter circuit increments the count value starting from the inverted count value in response to each pulse in the second series of pulses.

[0010] The conversion of the count value to the inverted count value in the counter circuit is performed by using a 2's complement operation on the count value.

[0011] The analog-to-digital converter circuit can be implemented with: an integrating stage configured to convert a current provided by each of the first analog signal and the second analog signal into a plurality of charge packets indicated by pulses; and a counting stage including a ripple counter having a counter input configured to receive pulses.

[0012] The counting stage includes a plurality of flip-flops and a multiplexing circuit system. The multiplexing circuit system is configured to connect the clock inputs of the plurality of flip-flops in response to a first logic state of a control signal to form the ripple counter. The multiplexing circuit system is also configured to apply an inverted pulse signal to the clock inputs of the plurality of flip-flops in response to a second logic state of the control signal to cause a logic inversion of each bit of the count value stored by the plurality of flip-flops during a logic inversion portion of a 2's complement operation, for converting the count value in the counter circuit into an inverted count value. The control circuit generates the control signal and also applies a single pulse to the counter input of the counting stage during an addition portion of the 2's complement operation, for converting the count value in the counter circuit into an inverted count value.

[0013] In an embodiment, a method for performing an in-memory compute (IMC) operation includes: performing a first multiply and accumulate (MAC) refinement of the IMC operation to generate a first analog signal; incrementing a count value in a counter circuit in response to the first analog signal; converting the count value in the counter circuit to a negated count value; performing a second MAC refinement of the IMC operation to generate a second analog signal; and incrementing the count value in the counter circuit starting from the negated count value in response to the second analog signal.

[0014] The first analog signal is integrated to produce a first series of pulses, wherein incrementing includes incrementing a count value in a counter circuit in response to each pulse in the first series. The second analog signal is integrated to produce a second series of pulses, wherein incrementing includes incrementing a count value in the counter circuit starting from a negated count value in response to each pulse in the second series.

[0015] The conversion of the count value to the negated count value is performed by using a 2's complement operation on the count value. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0017] Figure 1 is a schematic diagram of an embodiment of a computing circuit in memory;

[0018] Figure 2 Shows Figure 1 A circuit diagram of a row controller circuit used by a computing circuit in a memory of FIG.

[0019] Figure 3 Shows Figure 1 A circuit diagram of an analog-to-digital converter circuit used by a computing circuit in a memory;

[0020] Figure 4 It is a graphic Figure 3 A timing diagram of the operation of the analog-to-digital converter circuit;

[0021] Figure 5 It is used as a graphic Figure 1 A timing diagram of a computation operation in a memory of a circuit;

[0022] Figure 6 is a schematic diagram of an embodiment of a computing circuit in memory;

[0023] Figure 7 Shows Figure 6 A circuit diagram of a row controller circuit used by a computing circuit in a memory of FIG.

[0024] Figure 8 Shows Figure 6A circuit diagram of an analog-to-digital converter circuit used by an in-memory computing circuit of; and

[0025] Fig. 9 It is used as a graphic Figure 6 Timing diagram of the in-memory computation operations of the circuit. DETAILED DESCRIPTION

[0026] Reference now Figure 1 , which shows a schematic diagram of an in-memory computing circuit 110. The circuit 110 utilizes a plurality of memory cells 114 ab The memory array 112 is formed, and the plurality of memory cells 114 ab The array 112 is arranged in a matrix having m columns and n rows, where a is an integer from 1 to m and b is an integer from 1 to n. The array 112 is arranged as a group 115 including memory cells 114. 11 To 115 MN , where each group has 115 AB The memory array 115 includes four memory cells arranged in a 2x2 matrix of two rows and two columns across the array 112, where A is an integer from 1 to M and B is an integer from 1 to N. With this arrangement, there are N rows of groups 115. AB and group 115 of column M AB (where N=n / 2 and M=m / 2). Although group 115 AB The memory cells 114 are shown as being located in adjacent columns of the m columns of the array 112, but it will be appreciated that this is for ease of illustration only and that in a preferred embodiment these cells will likely be separated from one another using a form of column multiplexing well known to those skilled in the art.

[0027] Each group 115 of memory cells 114 AB Stores signed computation weights (also referred to as kernel data) for in-memory computation operations. Each memory cell 114 can be programmed to store a data bit g ab , where each group consists of 115 AB The four bits of data g stored in the four memory cells ab Formed the group 115 AB Each data bit has either a logic "1" or a logic "0" value, which is represented by, for example, a programmable conductance in memory cell 114. For a given group 115 AB , the signed computation weight "+1" is obtained by programming a logic "1" in the memory cells 114 of the main diagonal of the 2x2 matrix (see, for example, group 115 11 g 11 =1 and g 22=1) and programming logic "0" in the memory cells 114 on the opposite diagonal of the 2x2 matrix (see, for example, group 115 11 g 12 = 0 and g 21 =0) to represent, such as the matrix As shown, this is known in the art as the identity matrix. AB , the signed computation weight "-1" is obtained by programming a logic "0" in the memory cells 114 of the main diagonal of the 2x2 matrix (see, for example, g 11 = 0 and g 22 =0) and programming a logic "1" in the memory cells 114 on the opposite diagonal of the 2x2 matrix (see, for example, group 115 11 g 12 =1 and g 21 =1) to represent, such as the matrix As shown, this is known in the art as a commutation (or inverse identity) matrix. AB , a signed weight "0" is calculated by programming a logical "0" in all memory cells of the 2x2 matrix (see, for example, group 115 11 g 11 =0, g 22 =0, g 12 = 0 and g 21 =0) to represent, such as the matrix As shown, this is known in the art as a zero matrix.

[0028] In an embodiment of the memory array 112, each memory cell 114 includes a phase change memory (PCM) cell formed by a selection circuit (MOSFET transistor, BJT transistor, diode device, etc.) 114t operating as a switching element and a variable resistance element 114r providing a programmable conductance. In the case where a MOSFET transistor is used for the selection circuit 114t, the control node (gate) of the MOSFET transistor is connected to the word line WL. The source-drain path of the MOSFET transistor is connected in series with the variable resistance element 114r between the bit line BL and a reference node (e.g., a source line or ground). More specifically, the drain of the MOSFET transistor is connected to a first terminal of the variable resistance element 114r, the source of the MOSFET transistor is connected to the reference node, and the second terminal of the variable resistance element 114r is connected to the bit line BL.

[0029] As is well known to those skilled in the art, the PCM-type memory cell 114 is configured to store data using a phase change material (such as a chalcogenide) that can stably transform between an amorphous phase and a crystalline phase according to the heat transferred thereto. The amorphous phase and the crystalline phase exhibit two or more different resistances (corresponding to the variable resistance element 114r), in other words, two or more different conductances, which are used to distinguish two or more different logic states that can be programmed into the memory cell. The amorphous phase exhibits a relatively high resistance (i.e., a low conductance), and thus when this state is selected by asserting a word line signal at the gate of the selection circuit 114t, the current absorbed by the memory cell programmed in this state from the bit line BL is relatively small. Conversely, the crystalline phase exhibits a relatively low resistance (i.e., a high conductance), and thus when this state is selected by asserting a word line signal at the gate of the selection circuit 114t, the current absorbed by the memory cell programmed in this state from the bit line BL is relatively large.

[0030] In a specific but non-limiting example embodiment for two different logic states: the amorphous phase may represent programming the memory cell to a logic "0" (or reset state) of the associated coefficient weight, and the crystalline phase may represent programming the memory cell to a logic "1" (or set state) of the associated coefficient weight. Although binary (i.e., two different logic states) data is described in detail herein, it will be appreciated that in some applications, the memory cell 114 may instead support storage of m-ary (i.e., three or more different logic states) data.

[0031] It will be appreciated that other memory cell types may be used instead for array 112. For example, magnetoresistive random access memory (MRAM) cells or resistive random access memory (RRAM) cells may be used. The memory cells may alternatively include static random access memory (SRAM) cells.

[0032] Each memory cell 114 includes a word line WL and a bit line BL. The memory cells 114 in a common row of the matrix are connected to each other through the common word line WL. AB A group 115 of memory cells 114 in a common row AB By positive word line WL + and negative word lines WL -(Its formation for group 115 AB More specifically, the positive word line WL + connected to the top two memory cells in the 2x2 matrix of this group (see, for example, for group 115 11 g 11 and g 21 WL <1> +), while the negative word line WL - connected to the bottom two memory cells in the 2x2 matrix of the group (see, for example, for group 115 11 g 12 and g 22 WL <1> -).

[0033] The memory cells 114 in a common column of the matrix are connected to each other by a common bit line BL. AB A group 115 of memory cells 114 in a common column AB By forward thinning the bit line BL + and negative thinning bit line BL -(Its formation for group 115 AB More specifically, the bit line BL is positively thinned. + connected to the left two memory cells in the 2x2 matrix of this group (see, for example, for group 115 11 g 11 and g 12 BL <1> +), while the negative thinning bit line BL - connected to the right two memory cells in the 2x2 matrix of the group (see, for example, for group 115 11 g 21 and g 22 BL <1> -).

[0034] Each word line WL is driven by a word line driver circuit 116 using a pulsed word line signal generated by a row controller circuit 118. The word line driver circuit 116 may be implemented as a CMOS driver or buffer circuit (eg, formed by a series connection of two CMOS logic inverters).

[0035] The row controller circuit 118 receives the signed characteristic or coefficient data X1 to X2 for in-memory computation operations. N The row controller circuit 118 also receives an address signal (Address) for a computational operation in the memory and, under the control of the control circuit, selectively loads the signed feature or coefficient data X1 to X2 in response thereto. N , with the memory cell 114 of the group 115 AB The rows are associated with the word lines of the analog memory, which are to be selected in parallel simultaneously during each of the positive and negative refinements of the computational operation in the analog memory. During the simultaneous access of each of the positive and negative refinements, only one word line (WL) in each word line pair is pulsed using the word line signal. + or WL -) to actuate. Based on characteristic or coefficient data X B The logic state of the sign bit of selects one of the word lines in the word line pair to be activated in each refinement. For example, if the sign bit is a logic 0, indicating a positive coefficient data value, then the positive word line WL + is asserted. Conversely, if the sign bit is a logic 1, indicating a negative coefficient data value, then the negative word line WL - is asserted. For each corresponding activated word line, the row controller circuit 118 further controls the width of the generated pulse word line signal (ie, the turn-on time T ON ). This functionality is a form of pulse width modulation (PWM) control of the applied word line signal, which depends on the received signed characteristic or coefficient data X B The numeric value of .

[0036] In an embodiment, the signed feature or coefficient data X B Provided in multi-bit signed binary form, a 4-bit example is shown in the following table:

[0037]

[0038]

[0039] For signed feature or coefficient data X B The use of a 4-bit format is merely an example and it should be understood that the signed feature or coefficient data X B An arbitrarily selected number of bits may be used depending on the computing application.

[0040] It will be noted that the signed binary feature or coefficient data X B The most significant bit of the word line provides a sign bit (logic 0 is positive, logic 1 is negative) and is used to control the positive (WL +) or negative (WL -) word line selection, while the remaining less significant bits provide values ​​that specify the pulse width duration of the word line signal applied to the selected word line in the word line pair for each of the positive and negative going thinnings.

[0041] Figure 1 The simultaneous selection of groups 115 of memory cells 114 in response to non-zero feature or coefficient data is illustrated by way of example only. AB , and also illustrates, by way of example only, a refinement of the in-memory computational operation (positive or negative), including simultaneously actuating certain positive word lines (e.g., WL 1 , WL 2 ) corresponding to positively signed features or coefficient data (e.g., X1 and X2) using pulsed word line signals having pulse widths set by the digital values ​​of the corresponding coefficient data. <1> + and WL <2> +), and simultaneously actuating the negatively signed feature or coefficient data (e.g., X) using a pulse wordline signal having a pulse width set by the digital value of the corresponding coefficient data N ) corresponding to some negative word lines (e.g., WL <n>-). Again, it will be noted that at most only one word line in each word line pair is activated. Of course, it will be appreciated that a refinement of the analog in-memory computation operation may instead use a group 115 that selects fewer than the memory cells 114 simultaneously. AB All rows (selected by the Address signal or by the coefficient data X B of zero).

[0042] The analog signal Y generated on the positive / negative bit line BL corresponding to the positive / negative thinning A The weighted data bits g stored in the memory cells 114 of the columns are calculated based on the signed weights. ab and the width of the pulsed word line signal applied to the word line WL of those memory cells 114. More specifically, it will be appreciated that each memory cell 114 contributes to the logic state of X during refinement. B ×g ab is proportional to the bit line BL discharge current. Figure 1 As shown in FIG. 1 , the word line signals are simultaneously applied to the word lines WL <1> +、WL <2> +, …, WL <n>In the example of -, the analog signal Y generated on the positive refinement bit line BL<1>+ during positive refinement 1+ is proportional to the sum of the discharge currents caused by X1×g 11 , 0×g 12 , X2×g 13 , 0×g 14 , …, 0×g 1n-1 and X N ×g 1n . Similarly, in the negative refinement, the analog signal Y generated on the negative refinement bit line BL<1>- 1- is proportional to the sum of the discharge currents caused by X1×g 21 , 0×g 22 , X2×g 23 , 0×g 24 , …, 0×g 2n-1 and X N ×g 2n . The overall result of the in-memory computing operation depends on the difference between the analog signals Y A sensed on the positive and negative refinement bit lines BL<1>+, BL<1>- respectively for positive and negative refinement.

[0043] Now, just as an example, let's assume that some specific signed computational weights are used for group 115 of memory cell 114 in this column of the group AB . Group 115 11 is programmed with a weight of -1, which is represented by the swap matrix . Group 115 12 is programmed with a weight of 0, which is represented by the zero matrix . Group 115 1N is programmed with a weight of +1, which is represented by the identity matrix . Thus, for this example, the analog signal Y generated on the positive refinement bit line BL<1>+ during the positive refinement of the in-memory computing operation 1+ is proportional to the sum of the discharge currents caused by X1×0, 0×1, X2×0, 0×0, …, 0×1 and X N ×0; this will result in a zero discharge current on the positive refinement bit line BL<1>+. During the negative refinement of the in-memory computing operation, the analog signal Y generated on the negative refinement bit line BL<1>- 1- is proportional to the sum of the discharge currents caused by X1×1, 0×0, X2×0, 0×0, …, 0×0 and X N ×1; this will result in the sum of the discharge currents on the negative refinement bit line BL<1>- due to X1×1, … and X N ×1.

[0044] The column processing circuit 120 includes a forward thinning bit line BL coupled to a corresponding bit line pair. + and negative thinning bit line BL The column selection circuit is controlled by the logic state of the refinement control signal ELAB generated by the control circuit and acts as a multiplexer to selectively connect the negative refinement bit line BL to the negative refinement bit line BL during the negative refinement (ELAB=0) of the computation operation in the memory. - coupled to the ADC circuitry and selectively energizes the forward refinement bit line BL during forward refinement (ELAB=1) of a computation operation within the memory + is coupled to the ADC circuitry. The ADC circuitry receives an indication that the bit line BL is being thinned in the negative direction during the negative thinning (ELAB=0) period. - The analog signal Y generated on A- The bit line current is converted by an integration circuit through an integration process to generate a first series of pulses, and then the number of pulses in the first series of pulses is counted using a counter circuit. The number of pulses in the counted first series of pulses, and therefore the current count value in the counter circuit at this time, is obtained from the analog signal Y A- The ADC circuitry then performs a 2's complement operation on the count value in the counter circuit to produce a negated count value. The ADC circuitry then receives an indication that the bit line BL is being thinned during the forward thinning (ELAB=1) period. + The analog signal Y A+ The bit line current is converted by an integration circuit through an integration process to generate a second series of pulses, and then the number of pulses in the second series of pulses is counted using a counter circuit (starting from the inverted count value). The number of pulses in the second series of pulses counted is obtained from the analog signal Y A+ The digital value converted by the bit line current. At this time, the count value in the counter circuit is the digital signal dY A , whose digital value is equal to the analog signal Y A+ The converted digital value is the same as the analog signal Y A- The difference between the converted digital values ​​(in other words, dY A =-(dY A- )+dY A+ =dY A+ -dY A- , where "d" represents the analog signal Y obtained by the integration and counting operation of the ADC circuit system A- / + ).

[0045] Let us consider a specific example to illustrate the operations performed by column processing circuit 120. During negative thinning (ELAB=0) of a computation operation within the memory, the bit line BL is thinned negatively. - Connected to ADC circuitry and negatively thins the bit line BL -The bit line current iBL is integrated to generate the first series of pulses. The value in the counter circuit is reset and then incremented by one in response to each of the 350 pulses in the first series of pulses, so that the binary value in the counter circuit is (0b 01 0101 1110=350). Next, the ADC circuit system performs a 2's complement operation on the count value in the counter circuit to produce a negated count value. The 2's complement operation includes: a) inverting the logic state of each bit of the value in the counter circuit to produce (0b 10 1010 0001=-351); and then b) adding one to produce the negated count value in the counter circuit as (0b 10 1010 0010=-350). Then, during the forward refinement (ELAB=1) of the computation operation within the memory, the bit line BL is forwardly refined. + connected to ADC circuitry and positively thins the bit line BL +Bit line current iBL is integrated to generate the second series of pulses. The negated value in the counter circuit is incremented by one in response to each of the 200 pulses in the second series of pulses, so the binary value in the counter circuit is (0b 11 0110 1010 = -150).

[0046] The column processing circuit 120 also includes a digital signal processing circuit system for storing the result digital signal dY of the calculation operation in the memory. A And the digital signal dY A Perform digital calculations and operations to generate decision outputs of in-memory computational operations.

[0047] Although Figure 1 It is illustrated that one analog-to-digital converter (ADC) is provided for each bit line pair, but it will be appreciated that the ADC resources in the column processing circuit 120 may instead be shared by multiple bit line pairs using time division multiplexing.

[0048] Although Figure 1 It is not explicitly shown, but it is understood that the circuit 110 also includes conventional row decoding, column decoding, and read / write circuits known to those skilled in the art for use in connection with writing data bits (e.g., calculation weight data) to and reading data bits from the memory cells 114 of the memory array 112. This operation is referred to as a conventional memory access mode and is distinguished from the analog in-memory computation operations discussed above.

[0049] Reference now Figure 2 , which shows a circuit diagram of a row controller 118. A group 115 of memory cells 114 AB Each row of the latch circuit 152 is provided B , to latch coefficient data X B The corresponding sign and value of the signed digital value of the memory cell 114, for example, in response to the decoded Address value. AB Each row provides logic circuit 150 B . Logic circuits 1501 to 150 N The Start signal is asserted at the beginning of each of the positive and negative refinements of the in-memory computation operation. B ), for example in response to a global enable signal generated by a control circuit. The generation of the enable signal may, for example, depend on the coefficient data X B The corresponding signed digital value of , which has a non-zero value for the analog in-memory computation operation. The global counter circuit 154 increments the count value (Count) starting from a zero reset at the beginning of each (positive / negative) refinement of the in-memory computation operation, wherein the refinement ends when Count reaches a maximum value. The group 115 of memory cells 114 AB Each row of the comparison circuit 156 B Coupled to latch circuit 152 B And the count value Count and the latched coefficient data X B When the count value Count reaches or exceeds the latched digital value, the comparison circuit 156 B The output of the set-reset latch circuit 158 B has a set (S) input coupled to receive a B Start B signal output; and a reset (R) input, which is coupled to receive the comparison circuit 156 B The output of the combinational logic circuit 160 B Logically Combined Set-Reset Latch Circuit 158 B The output (Q) and the output from the latch circuit 152 B The sign bit B The logic inversion of the word line is used to generate a pulse word line signal to be applied to the positive word line WL + Driver circuit 116. Combinatorial logic circuit 162 B Logically Combined Set-Reset Latch Circuit 158 B The output (Q) and the output from the latch circuit 152 B The sign bit B To generate a pulse word line signal to be applied to the negative word line WL -driver circuit 116. In an embodiment, the combinational logic circuit 160 B and 162 B It is a logic AND gate.

[0050] The operation of the circuit system within the row controller 118 is as follows: When the calculation operation in the memory starts, the control coefficient data X1 to X2 are selectively loaded using the decoding of the address signal Address. N The digital value is stored in latch circuits 1521 to 152 N The latch is performed and the global counter 154 is reset. If the digital value of the coefficient data is non-zero, then the logic circuit 150 B Indicates the group 115 of memory cells 114 to be selected AB The line, logic circuit 150 B Start signal B The output is asserted logic high at the beginning of each of the positive and negative refinements and the set-reset latch circuit 158 B The output Q is set to logic high. B is logical 0, indicating that the coefficient data X B The digital value of is positive, then the AND gate 160 B Both inputs of the AND gate are logic high, and the B The output turns to logic high to the positive word line WL + provides the leading edge of the word line signal pulse. On the contrary, if the sign bit Sign B is logical 1, indicating that the coefficient data X B The digital value is negative, then the AND gate 162 B Both inputs of the AND gate 162 are logic high, and B The output turns to logic high to the negative word line WL - provides the leading edge of the word line signal pulse. Then the global counter 154 starts to increment the Count value. When the incremented Count value reaches or exceeds the value set by the latch circuit 152 B Latched coefficient data X B When the digital value of the comparison circuit 156 B The output of is asserted as logic high and the set-reset latch circuit 158 B is reset to its output Q as logic low. This logic low output is applied to AND gate 160 B and 162 B Both, and whichever output of these AND gates is logic high (corresponding to the assertion of the word line signal pulse), will transition to logic low to provide the trailing edge of the word line signal pulse. Thus, the pulse width (i.e., turn-on time T) of the generated pulse word line signal is ON ) depends on the incrementing of the Count value during the refinement of the in-memory calculation operation to the coefficient data X B The amount of time required to refine the given refinement. When Count reaches its maximum value, the given refinement ends.

[0051] Reference now Figure 3 , which shows a circuit diagram of an example of an ADC circuit (referred to herein as a digital detector 22 circuit). Each ADC circuit digital detector 22 is coupled to a corresponding bit line pair BL through a column selection circuit controlled by a refinement signal ELAB. + and BL -. Flows through the selected bit line BL + and BL - Current iBL Mirrored by the current mirror circuit 35 of the digital detector 22 .

[0052] For bit line pair BL + and BL Each digital detector 22 comprises an integration stage 33 and a counter stage 34 .

[0053] The integration stage 33 includes a first integration circuit 41 , a second integration circuit 42 , and a switch circuit 43 coupled between the first integration circuit 41 and the second integration circuit 42 .

[0054] The first integration circuit 41 and the second integration circuit 42 are coupled to receive the mirrored bit line current iBL as bias current.

[0055] The first integration circuit 41 includes a first inverter 45, a capacitor CA coupled at the output of the first inverter 45, and a second inverter 48 having an input coupled to the output of the first inverter 45. The first inverter 45 has a bit line current iBL coupled and mirrored. A biased power supply node (eg, a source node of a PMOS transistor within inverter 45 ) and an input configured to receive a first control signal INA.

[0056] The capacitor CA has a first terminal coupled to the output of the first inverter 45 and a second terminal coupled to a reference potential node (eg, ground).

[0057] The output of the first inverter 45 is a first integrated voltage dropped across the capacitor CA.

[0058] The second inverter 48 has a first sampling threshold (hereinafter referred to as the first threshold voltage Vth1) and has an input coupled to receive the first integrated voltage across the capacitor CA. The output of the second inverter 48 provides a switch control signal to control the actuation of the first switch SwA according to the first threshold voltage Vth1 and the first integrated voltage.

[0059] The switch control signal for the first switch SwA is a logic signal having a high logic value when the first integrated voltage is less than the first threshold voltage Vth1 and having a low logic value when the first integrated voltage is higher than the first threshold voltage Vth1.

[0060] The second integrating circuit 42 includes a first inverter 50, a capacitor CB coupled at the output of the first inverter 50, and a second inverter 53 having an input coupled to the output of the first inverter 50. The first inverter 50 has a bit line current iBL coupled and mirrored. A biased power supply node (eg, a source node of a PMOS transistor within inverter 50 ) and an input configured to receive a second control signal INB.

[0061] The capacitor CB has a first terminal coupled to the output of the first inverter 50 and a second terminal coupled to a reference potential node (eg, ground).

[0062] The output of the first inverter 50 is a second integrated voltage dropped across the capacitor CB.

[0063] The second inverter 53 has a second sampling threshold (hereinafter referred to as the second threshold voltage Vth2) and has an input coupled to receive the second integrated voltage across the capacitor CB. The output of the second inverter 53 provides a switch control signal to control the actuation of the second switch SwB according to the second threshold voltage Vth2 and the second integrated voltage.

[0064] The switch control signal for the second switch SwB is a logic signal having a high logic value when the second integrated voltage is less than the second threshold voltage Vth2 and having a low logic value when the second integrated voltage is higher than the second threshold voltage Vth2.

[0065] In this embodiment, the first threshold Vth1 is preferably equal to the second threshold Vth2; however, depending on the specific application, the first threshold Vth1 may also be different from the second threshold Vth2.

[0066] The switch circuit 43 includes a latch formed by two inverters arranged in a ring (or cross-coupled) configuration. The switch circuit 43 also includes a first switch SwA controlled by a first switch signal and a second switch SwB controlled by a second switch signal.

[0067] The latch of the switch circuit 43 has a first node 60 and a second node 61, the first node 60 is coupled to the input of one of the two inverters and the output of the other of the two inverters, and the second node 61 is coupled to the output of the one of the two inverters and the input of the other of the two inverters.

[0068] The first node 60 provides a first control signal INA, and the second node 61 provides a second control signal INB.

[0069] The switching circuit path of the first switch SwA is coupled between the first node 60 and a node at the power supply voltage Vdd. The switching circuit path of the second switch SwB is coupled between the second node 61 and a node at the voltage Vdd.

[0070] The power supply voltages Vdd of the current mirror circuit 35 and the switch circuit 43 may be equal, or may be different.

[0071] The switch circuit 43 also receives an enable signal EN, which controls the activation of the switch circuit 43. For example, the enable signal EN can be used to keep the switch circuit 43 in an off state when not in use, thereby allowing optimization of power consumption. In addition, the enable signal EN can be used to set each of the nodes 60 and 61 of the switch circuit 43 to a defined logic state, such as at startup.

[0072] The charge counter stage 34 may have an input coupled to receive the first control signal INA or the second control signal INB. Figure 3 An embodiment is shown in which the first control signal INA is applied as an input. At its core, the charge counter stage 34 is a ripple counter circuit formed by a plurality of D flip-flops 67. The first D flip-flop 67.1 has a clock input coupled to receive the first control signal INA. The Q output of the first D flip-flop 67.1 provides an output digital signal Y A The first bit (i.e., the least significant bit) of the first D flip-flop 67.1 is fed back to the D input of the first D flip-flop 67.1. The second D flip-flop 67.2 has a clock input coupled to receive a signal from the QB output of the first D flip-flop 67.1. The Q output of the second D flip-flop 67.2 provides an output digital signal Y A The second bit (i.e., the next more significant bit). The QB output of the second D flip-flop 67.2 is feedback-connected to the D input of the second D flip-flop 67.2. This connection scheme continues for the remaining D flip-flops 67 of the ripple counter circuit. Thus, the last D flip-flop 67.F has a clock input that is coupled to receive a signal from the QB output of the penultimate D flip-flop 67.F-1. The Q output of the last D flip-flop 67.F provides the output digital signal Y A The last bit (i.e., the most significant bit). The QB output of the last D flip-flop 67.F is feedback-connected to the D input of the last D flip-flop 67.F.

[0073] The first control signal INA includes a series of pulses, the generation rate of which depends on the bit line current iBL from the selected bit line among the bit lines during refinement The ripple counter circuit of the charge counter stage 34 functions to count the number of pulses in the first control signal INA. The number of pulses in the series of pulses provided by the counted first control signal INA is obtained from the analog signal Y A The bit line current iBL The converted numeric value.

[0074] The ripple counter circuit includes additional circuitry to support performing a 2's complement operation on the count value in the counter circuit to produce a negated count value after negative refinement is completed. As is known to those skilled in the art, the 2's complement operation is implemented on a multi-bit binary data value by first inverting the logic state of each bit and then adding one (incrementing by one). When performing a 2's complement operation, the signal applied to the clock input of each D flip-flop 67 is selected by the multiplexer circuit 68 to be changed to an inverted pulse (IP) when the select signal Sel generated by the control circuit is asserted in the first logic state. This will implement the portion of the 2's complement operation that inverts the logic state of each bit of the multi-bit binary data value stored by the D flip-flops 67.1, ..., 67.F. The control circuit then sets the select signal Sel to the second logic state to return the charge counter stage 34 to the ripple counter configuration. In response, the multiplexer circuit 68.1 will connect the input of the ripple counter circuit to the clock input of the first D flip-flop 67.1, passing, and the remaining multiplexer circuits 68.2, ..., 68.F will connect the clock input of each D flip-flop 67.2, ..., 67.F to the QB output of the previous D flip-flop 67.1, ..., 67.F-1. The control circuit will then further apply a single pulse (Pulse) at the input of the ripple counter circuit. This will implement the plus-one (increment-by-one) part of the 2's complement operation.

[0075] Figure 4 shows Figure 3 The first control signal INA of the digital detector 22, the first integrated voltage (V A ) on the capacitor CA, and the time behavior example of the second integrated voltage (V B ) on the capacitor CB.

[0076] For the time period t0 < t < t1, the first integrated voltage V A is lower than the first threshold Vth1. Therefore, the output of the second inverter 48 of the first integration circuit 41 is logic high. Thus, the first switch signal will control the first switch SwA to open. The first control signal INA has a logic low value here.

[0077] Therefore, with respect to the first inverter 45 of the first integration circuit 41, for the time period t0 < t < t1, the PMOS transistor of the first inverter 45 is turned on, and the mirrored bit line current iBL Current flows from current mirror 35 through the first inverter 45 of the first integration circuit 41 to charge capacitor CA.

[0078] Meanwhile, for the time period t0 < t < t1, the second control signal INB has a logic high value. Thus, with respect to the first inverter 50 of the second integration circuit 42, for the time period t0 < t < t1, the output of the first inverter 50 is logic low. Consequently, the mirrored bit line current iBL The current does not flow from the current mirror 35 to the first inverter 50 of the second integrating circuit 42 .

[0079] In response to the mirrored bit line current iBL flowing through the PMOS transistor of the first inverter 45 , the first integrated voltage V across the capacitor Ca A increases during the time period t0 < t < t1.

[0080] The first integrated voltage V A increases linearly during the time period t0 < t < t1; however, the behavior of the first integrated voltage V A depends on the bit line current iBL during the time period t0 < t < t1 Specific behaviors.

[0081] When the first integral voltage V A becomes equal to the first threshold voltage Vth1, the output of the second inverter 48 becomes logic low. Then the switch SwA is actuated, and the first control signal INA takes a logic high value at time t2.

[0082] The time delay between time t1 and time t2 can correspond to, for example, the propagation delay of the second inverter 48 of the first integration circuit 41 and / or the switching time of the first switch SwA.

[0083] For the time period t1 < t < t2, the mirrored bit-line current iBL The capacitor CA continues to be charged through the inverter 45. Therefore, the first integrated voltage V A will continue to increase until it reaches a maximum value at time t2.

[0084] At time t2, when the first control signal INA takes a high value, the second control signal INB (not shown here) takes a low value (note: the inverter 56 of the switch circuit 43 receives the first control signal INA at input).

[0085] When the first control signal INA has a high value, the output of the first inverter 45 is coupled to the ground node through the NMOS transistor of the first inverter 45 of the first integrator circuit 41. At the same time, when the second control signal INB has a low value, the PMOS transistor of the first inverter 50 of the second integrator circuit 42 is turned on, and the mirrored bit line current iBL The current flows from the current mirror 35 through the first inverter 50 of the second integrating circuit 42 to charge the capacitor CB.

[0086] Therefore, for time t>t2, the mirrored bit line current iBL The current from the current mirror 35 flows only through the first inverter 50 of the second integrating circuit 42 , and does not flow through the first inverter 45 of the first integrating circuit 41 .

[0087] The mirrored bit line current iBL flowing through the PMOS transistor of the first inverter 50 The capacitor CB of the second integration circuit 42 is charged. Therefore, the second integration voltage V B Increasing in time starting from time t2.

[0088] For t>t2, the second integrated voltage V B increases linearly over time; however, the second integrated voltage V B The behavior depends on the bit line current iBL Specific behaviors.

[0089] When the first control signal INA has a high value, the capacitor CA of the first integration circuit 41 discharges to ground through the NMOS transistor of the first inverter 45. Therefore, the first integration voltage V A drops to zero.

[0090] When the second integration voltage V B becomes equal to the second threshold voltage Vth2 (at time t3), the output of the second inverter 53 becomes logic low.

[0091] Therefore, at time t4, the second control signal INB takes a high value, similar to the case discussed above for the first control signal INA corresponding to time t2.

[0092] In response to the second integration voltage V B reaching the second threshold Vth2, the second switch signal switches to a low value, and the second switch SwB closes. In response, the second control signal INB takes a high value.

[0093] The time delay between time t3 and time t4 can correspond to, for example, the propagation delay of the second inverter 53 of the second integration circuit 42 and / or the switching time of the second switch SwB.

[0094] For the time period t3 < t < t4, the mirrored bit-line current iBL Continue to charge the capacitor CB of the second integration circuit 42; thus, the second integration voltage V B increases until it reaches the maximum value (time t4).

[0095] For the time period t2 < t < t4, the switching circuit 43 holds the first control signal INA at a high value and holds the second control signal INB at a low value.

[0096] At time t4, in response to the second control signal INB taking a high value, the first control signal INA takes a low value again.

[0097] In response to the first control signal INA taking a low value, the mirrored bit line current iBL The process returns to charging the capacitor CA of the first integrating circuit 41. The previous process is then repeated.

[0098] refer to Figure 3 , the counter stage 34, in particular the ripple counter circuit formed by the connected flip-flops 67.1,..., 67.F, counts the number of pulses in the first control signal INA. More specifically, the counter stage functions to count the number of switching events of the first control signal INA, and more particularly, in this embodiment, to count the number of rising edges of the first control signal INA.

[0099] In practice, each ADC circuit digital detector 22 measures the positive refinement bit line BL selected by the column selection circuit by performing a plurality of successive sampling iterations. + or negative thinning bit line BL - The bit line current iBL (depending on the logic state of the refinement control signal ELAB). In each sampling iteration, for example, the bit line current iBL mirrored therein The sampling iteration of the first integration circuit 41 generates a first integrated voltage V A The bit line current iBL as a mirror The time integral of the first integral voltage V A is compared with the first threshold value Vth1, and in response to the first integrated voltage V A When the first threshold Vth1 is reached, the first integrated voltage V A , here in particular by switching the first control signal INA. The counter stage 34 increments the count value at each switching of the first control signal INA.

[0100] In other words, each digital detector 22 converts the bit line current iBL The first control signal INA is converted into a plurality of charge packets indicated by the pulses of the first control signal INA and the charge packets are counted to calculate each corresponding bit line current iBL. Sampling is performed, wherein each charge packet corresponds to the charge accumulated on the capacitors CA, CB causing the switching of the second inverter 48,53.

[0101] According to the illustrated embodiment, the switch circuit 43 responds to the first integrated signal V A When the first threshold value Vth1 is reached, the first integration circuit 41 is disabled and the second integration circuit 42 is enabled; and in response to the second integration signal V B The second threshold Vth2 is reached to enable the first integration circuit 41 and disable the second integration circuit 42. This allows the bit line current iBL The bit line current iBL is alternately sampled by the first integration circuit 41 and the second integration circuit 42, thereby allowing the bit line current iBL When capacitor CB is discharging, capacitor CA is charged, and when capacitor CA is discharging, capacitor CB is charged. In this way, no bit line charge is lost during sampling, and digital detector 22 can achieve accurate detection of bit line current iBL. High measurement accuracy.

[0102] Reference now Figure 5 , which shows a simplified timing diagram of the operation of circuit 110 associated with an overall in-memory computation operation, including two separate refinements (i.e., a negative refinement followed by a positive refinement). At time t1, the latch control signal is asserted to cause latch circuits 1521 to 152 N Latch coefficient data X1 to X N At time t2, in response to a first logic state (e.g., logic 0) of the refinement indicator signal (ELAB) generated by the control circuit, the column selection circuitry of the column processing circuitry 120 selects the negative refinement bit line BL by multiplexing associated with performing a negative refinement of the in-memory computation operation. -. We assume that this is the case discussed above and Figure 1 In the example shown in FIG. 1 , in response to non-zero values ​​of coefficient data, groups 115 of memory cells 114 are selected simultaneously. AB All rows of , and in response to Start at time t3 B The assertion of the signal simultaneously activates the word lines WL corresponding to the positive characteristic or coefficient data X1, X2 using the pulse word line signal <1> +、WL <2> + and also use the pulse word line signal to simultaneously activate the negative characteristic or coefficient data X N The corresponding word line WL <n>-. Similarly, at time t3, the previously reset Count value begins to increment. At time t4, the incremented Count value reaches or exceeds the digital value of coefficient data X1, and the positive word line WL <1> + word line signal pulse terminates. At time t5, the incremented Count value reaches or exceeds the digital value of coefficient data X2, and the positive word line WL <2> + The word line signal pulse on the + is terminated. At time t6, the incremented Count value reaches or exceeds the coefficient data X N The digital value of the negative word line WL <n>-The word line signal pulse on terminates. At time t7, the Start signal is de-asserted and the Count value is reset.

[0103] Starting from time t3, each ADC starts to refine the bit line BL from the negative direction. - The bit line current iBL Integration is performed to generate a first series of pulses, and the count value in the ripple counter is incremented in response to each pulse in the first series. The increment of the negatively refined count value continues until time t8, which is after all word lines have been deactuated. At time t9, the control circuit asserts the select signal Sel to disconnect the ripple counter configuration and causes the multiplexer 68 in each ADC circuit to pass the inverted pulse IP signal at time t10. In response to the inverted pulse IP signal being applied to the clock input of the D flip-flop 67 in each ADC circuit, the bit of the negatively refined count value is logically inverted (performing step a) of the 2's complement operation described above). Then, the select signal is de-asserted to restore the multiplexer 68 in each ADC circuit back to the ripple counter connection, and then the control circuit applies a single pulse Pulse to the input of the ripple counter at time t11. This will cause the logically inverted bit of the count value to increase by one (performing step b) of the 2's complement operation described above). This will produce the negated refinement value via a 2's complement operation to reside in the D flip-flop 67 in each ADC circuit.

[0104] At time t12, in response to the second logic state (e.g., logic 1) of the refinement indicator signal (ELAB) generated by the control circuit, the column selection circuitry of the column processing circuit 120 selects the forward refinement bit line BL by multiplexing associated with performing the forward refinement of the in-memory computation operation. +. We again assume that this is the case discussed above and Figure 1 , where groups 115 of memory cells 114 are selected simultaneously in response to non-zero coefficient data. AB All rows of , and in response to Start at time t12 B The assertion of the signal simultaneously activates the word lines WL corresponding to the positive characteristic or coefficient data X1, X2 using the pulse word line signal <1> +、WL <2> + and use the pulse word line signal to simultaneously actuate with the negative characteristic or coefficient data X N The corresponding word line WL <n>-. Similarly, at time t12, the previously reset Count value begins to increment. At time t13, the incremented Count value reaches or exceeds the digital value of the coefficient data X1, and the positive word line WL <1> + word line signal pulse terminates. At time t14, the incremented Count value reaches or exceeds the digital value of coefficient data X2, and the positive word line WL <2> + The word line signal pulse on the + is terminated. At time t15, the incremented Count value reaches or exceeds the coefficient data X N The digital value of the negative word line WL <n>The word line signal pulse on - terminates. At time t16, the Start signal is de-asserted and the Count value is reset. At time t17, the forward refinement ends.

[0105] Starting from time t12, each ADC starts to receive the bit line BL from the forward refinement. +Bit line current iBL Integration is performed to generate a second series of pulses, and the count value in the ripple counter is incremented in response to each pulse in the second series starting from the negated refinement value (generated by performing a 2's complement operation on the negative refinement count value as described above). The incrementing of the count value for positive refinement continues until time t16 when all word lines have been deactivated. At time t17, when positive refinement is completed, the resulting count value in the D flip-flop 68 of each ADC circuit can be output as a digital signal dY A .

[0106] Reference now Figure 6 , which shows a schematic diagram of an in-memory computing circuit 210. The circuit 210 utilizes a plurality of memory cells 214 ab The memory array 212 is formed, and the plurality of memory cells 214 ab The array 212 is arranged in a matrix having m columns and n rows, where a is an integer from 1 to m and b is an integer from 1 to n. The array 212 is arranged to include groups 215 of memory cells 114. 11 To 215 mN , where each group has 215 aB The memory cell comprises two memory cells arranged in a 1x2 matrix, where a is an integer from 1 to m, and B is an integer from 1 to N. With this arrangement, there are N rows of groups 215 aB and m columns of group 215 aB (where N = n / 2).

[0107] Each group 215 of memory cells 214 aB Stores signed computation weights (also called kernel data) for in-memory computation operations. Each memory cell 214 can be programmed to store data bits g ab , where each group consists of 215 aB The two memory cells store two bits of data g ab Formation of the Group 215 aB Each data bit has either a logic "1" or a logic "0" value, for example, represented by a programmable conductance in memory cell 214. For a given group 215 aB The signed computation weight "+1" is obtained by programming a logic "1" in the upper memory cell (eg, see group 215). 11 g 11 =1) and programming logic "0" in the lower memory cell (eg, see group 215 11 g 12 =0) indicates that the matrix As shown, it is also called a (positive) single entry matrix in the art. aB The signed computation weight "-1" is obtained by programming a logic "0" in the upper memory cell (eg, see group 215). 11 g 11 = 0) and programming logic "1" in the lower memory cell (eg, see group 215 11 g 12 =1) indicates that the matrix As shown, it is also called a (negative) single element matrix in the art. aB A signed computation weight of "0" is represented by programming a logical "0" in both memory cells (see, for example, group 215 11 g 11 =0, g 12 =0), such as the matrix As shown, it is also called a zero matrix in the art.

[0108] In an embodiment of the memory array 212, each memory cell 214 includes a phase change memory (PCM) cell formed by a selection circuit (MOSFET transistor, BJT transistor, diode device, etc.) 214t operating as a switching element and a variable resistance element 214r providing programmable conductance. In the case where a MOSFET transistor is used for the selection circuit 214t, the control node (gate) of the MOSFET transistor is connected to the word line WL. The source-drain path of the MOSFET transistor is connected in series with the variable resistance element 214r between the bit line BL and a reference node (e.g., a source line or ground). More specifically, the drain of the MOSFET transistor is connected to a first terminal of the variable resistance element 214r, the source of the MOSFET transistor is connected to the reference node, and the second terminal of the variable resistance element 214r is connected to the bit line BL.

[0109] As is well known to those skilled in the art, the PCM-type memory cell 214 is configured to store data using a phase change material (such as a chalcogenide) that can stably transform between an amorphous phase and a crystalline phase according to the heat transferred thereto. The amorphous phase and the crystalline phase exhibit two or more different resistances (corresponding to the variable resistance element 214r), in other words, two or more different conductances, which are used to distinguish two or more different logic states that can be programmed into the memory cell. The amorphous phase exhibits a relatively high resistance (i.e., a low conductance), and thus when this state is selected by asserting a word line signal at the gate of the selection circuit 214t, the current absorbed by the memory cell programmed in this state from the bit line BL is relatively small. Conversely, the crystalline phase exhibits a relatively low resistance (i.e., a high conductance), and thus when this state is selected by asserting a word line signal at the gate of the selection circuit 214t, the current absorbed by the memory cell programmed in this state from the bit line BL is relatively large.

[0110] In an embodiment, for a specific but non-limiting example of two different logic states: the amorphous phase may represent programming the memory cell to a logic "0" (or reset state) of the associated coefficient weight, and the crystalline phase may represent programming the memory cell to a logic "1" (or set state) of the associated coefficient weight. Although binary (i.e., two different logic states) data is described in detail herein, it will be appreciated that in some applications, the memory cell 214 may instead support storage of m-ary (i.e., three or more different logic states) data.

[0111] It will be appreciated that other memory cell types may be used instead for array 212. For example, magnetoresistive random access memory (MRAM) cells or resistive random access memory (RRAM) cells may be used. The memory cells may alternatively include static random access memory (SRAM) cells.

[0112] Each memory cell 214 includes a word line WL and a bit line BL. The memory cells 214 in a common row of the matrix are connected to each other through a common word line WL. aB A group 215 of memory cells 214 in a common row aB By positive word line WL + and negative word lines WL -(Its formation is for group 215 aB More specifically, the positive word line WL + connected to the upper memory cell in the 1x2 matrix of this group (see, for example, for group 215 11 g 11 WL <1> +), while the negative word line WL - connected to the lower memory cells in the 1x2 matrix of the group (see, for example, for group 215 11 g 12 WL <1> -).

[0113] The memory cells 214 in a common column of the matrix are connected to each other via a common bit line BL. aB A group 215 of memory cells 214 in a common column aB Through the bit line BL More specifically, the bit line BL Two memory cells connected to the 1x2 matrix of the group (see, for example, for group 215 11 g 11 and g 12 BL <1> ).

[0114] Each word line WL is driven by a word line driver circuit 216 using a pulsed word line signal generated by a row controller circuit 218. The word line driver circuit 216 may be implemented as a CMOS driver or buffer circuit (eg, formed by a series connection of two CMOS logic inverters).

[0115] The row controller circuit 218 receives the signed characteristic or coefficient data X1 to X2 for in-memory computation operations. N The row controller circuit 218 also receives an address signal (Address) for in-memory computation operations and selectively loads signed feature or coefficient data X1 to X2 in response thereto. N , with the memory cell 214 of the group 215 AB The rows of memory are associated with each other, which will be selected in parallel simultaneously during each refinement of the computational operation in the analog memory. During the simultaneous access of a given refinement, each word line pair (WL + or WL The one word line in the word line pair that is activated is selected based on the following factors: a) which positive or negative refinement is being performed (this is indicated by the logic state of the refinement control signal ELAB generated by the control circuit), and b) the characteristic or coefficient data X B For example, consider the following: Case (1) If positive refinement is being performed (signal ELAB is logic 1) and the sign bit is logic 0 (indicating a positive coefficient data value), then the positive word line WL + is asserted; case (2) if positive refinement is being performed (signal ELAB is logic 1) and the sign bit is logic 1 (indicating a negative coefficient data value), then the negative word line WL - is asserted; Case (3) If negative refinement is being performed (signal ELAB is logic 0) and the sign bit is logic 0 (indicating a positive coefficient data value), then the negative word line WL - is asserted; and case (4) if negative refinement is being performed (signal ELAB is logic 0) and the sign bit is logic 1 (indicating a negative coefficient data value), then the positive word line WL + is asserted. For each corresponding activated word line, the row controller circuit 218 further controls the width of the generated pulse word line signal (ie, the turn-on time T ON ). This functionality is a form of pulse width modulation (PWM) control of the applied word line signal, which depends on the received signed characteristic or coefficient data X B The numeric value of .

[0116] In an embodiment, the signed feature or coefficient data X B Provided in multi-bit signed binary form, a 4-bit example is shown in the following table:

[0117]

[0118]

[0119] For signed feature or coefficient data X B The use of a 4-bit format is merely an example and it should be understood that the signed feature or coefficient data X B An arbitrarily selected number of bits may be used depending on the computing application.

[0120] It will be noted that the signed binary feature or coefficient data X B The most significant bit of the word line provides a sign bit (logic 0 is positive, logic 1 is negative) for controlling the positive (WL +) or negative (WL -) word line selection, while the remaining less significant bits provide values ​​that specify the pulse width duration of the word line signal applied to the selected word line of the word line pair during each refinement.

[0121] Figure 6 The simultaneous selection of groups 215 of memory cells 214 in response to non-zero coefficient data is illustrated by way of example only. aB , and also illustrating solid wordline signal pulses by way of example only (the adjacent numbers in parentheses identify the specific case as described above), the positive refinement of the in-memory computation operation (ELAB=1) includes simultaneously actuating certain positive wordlines (e.g., WL 1 ) corresponding to positively signed features or coefficient data (e.g., X1 and X2) using pulsed wordline signals having pulse widths set by the digital values ​​of the corresponding coefficient data. <1> + and WL <2> +) (case (1)), and simultaneously actuating the negatively signed feature or coefficient data (e.g., X) using a pulse word line signal having a pulse width set by the digital value of the corresponding coefficient data N ) corresponding to some negative word lines (e.g., WL <n>-)(Case (2)).

[0122] Figure 6 The simultaneous selection of a group 215 of memory cells 214 in response to non-zero coefficient data is further illustrated by way of example only. aB , and also illustrates, by way of example only, negative refinement of the in-memory computation operation (ELAB=0) using dashed wordline signal pulses (the adjacent parenthesized numbers identify the specific case as described above), including simultaneously actuating certain negative wordlines (e.g., WL1, WL2) corresponding to positively signed features or coefficient data (e.g., X1 and X2) using pulsed wordline signals having pulse widths set by the digital values ​​of the corresponding coefficient data. <1> - and WL <2> -) (case (3)), and using a pulse word line signal having a pulse width set by the digital value of the corresponding coefficient data to simultaneously activate the negatively signed feature or coefficient data (e.g., X N ) corresponding to some positive word lines (e.g., WL <n>+)(Case (4)).

[0123] Of course, it will be appreciated that the positive / negative refinement of the analog in-memory computation operation may instead use a group 215 that selects fewer than the memory cells 214 simultaneously. aB All rows (selected by the Address signal or by the coefficient data X B of zero).

[0124] During positive or negative refinement, each bit line BL The analog signal Y generated on a The weighted data bit g stored in the memory cell 214 of the column is calculated based on the signed weight. ab and the width of the pulsed word line signal applied to the word line WL of those memory cells 214. More specifically, it can be understood that each memory cell 214 contributes to the logic state of X during refinement. B ×g ab is proportional to the bit line BL discharge current. Figure 6 In the example shown in FIG. 1 , during the forward elaboration (ELAB=1) of the in-memory computing operation (solid line), the word line signal is simultaneously applied to the word line WL <1> +、WL <2> +, ..., WL <n>- In the case of bit line BL <1> The analog signal Y1 generated by X1×g 11 , 0×g 12 , X2×g 13 , 0×g 14 ,…,0×g 1n-1 and X N ×g 1n In contrast, during the negative refinement (ELAB=0) of the computational operation in the memory, the (dashed) word line signal is simultaneously applied to the word line WL <1> -、WL <2> -, ..., WL <n>+, on the same bit line BL <1> The analog signal Y1 generated by 0×g 11 ,X1×g 12 , 0×g 13 , X2×g 14 , …, X N ×g 1n-1 and 0×g 1n The overall result of the computational operation in the memory is based on the difference between the analog signals generated during the positive and negative refinements.

[0125] Now, just for example, let us assume that some particular signed computation weights are used for the group 215 of memory cells 214 in that column of the group. aB . Group 215 11 is programmed with a weight of -1, which is represented by the matrix Indicates. Group 115 12 is programmed with a weight of 0, which is represented by the matrix Indicates. Group 115 1N is programmed with a weight of +1, which is represented by the matrix Therefore, for this example, during forward thinning (ELAB=1), the bit line BL <1> The analog signal Y1 generated by X1×0, 0×1, X2×0, 0×0, …, 0×1 and X N ×0 is proportional to the sum of the discharge currents caused by the bit line BL <1> During negative thinning (ELAB=0), the discharge current on the bit line BL is zero. <1> The analog signal Y1 generated by 0×0, X1×1, 0×0, X2×0, …, X N The sum of the discharge currents caused by ×1 and 0×0 is proportional; this will cause the bit line BL <1> Due to X1×1, …, and X N ×1 is the sum of the discharge currents caused by.

[0126] Column processing circuit 220 includes ADC circuitry coupled to receive a signal indicating that a bit line BL is being processed during negative thinning (ELAB=0), which is performed first in this case. The analog signal Y generated on A- The ADC circuit system converts the bit line current through an integration process using an integration circuit to generate a first series of pulses, and then uses a counter circuit to count the number of pulses in the first series of pulses. The number of pulses in the counted first series of pulses, and therefore the current count value in the counter circuit at this time, is obtained from the analog signal Y A- The ADC circuitry then performs a 2's complement operation on the count value in the counter circuit to produce a negated count value. The ADC circuitry then receives an indication that a current on the bit line BL during forward thinning (ELAB=1) is present. The analog signal Y generated on A+ The ADC circuit system converts the bit line current by an integration process using an integration circuit to generate a second series of pulses, and then uses a counter circuit (starting from the inverted count value) to count the number of pulses in the second series of pulses. The number of pulses in the second series of pulses counted is obtained from the analog signal Y A+ The digital value converted by the bit line current. At this time, the count value in the counter circuit is the digital signal dY A , whose digital value is equal to the analog signal Y A+ The converted digital value is the same as the analog signal Y A- The difference between the converted digital values ​​(in other words, dY A =-(dY A- )+dY A+ =dY A+ -dY A -, where "d" represents the analog signal Y obtained by the integration and counting operation of the ADC circuit system A- / + ).

[0127] Let us consider a specific example to illustrate the operations performed by column processing circuit 220. During negative refinement (ELAB=0) of an in-memory computation operation, bit line BL The bit line current iBL is integrated to generate a first series of pulses. The value in the counter circuit is incremented by one in response to each of the 350 pulses in the first series of pulses, so the binary value in the counter circuit is (0b 01 0101 1110=350). Next, the ADC circuit performs a 2's complement operation on the count value in the counter circuit to produce a negated count value. The 2's complement operation includes: a) inverting the logic state of each bit of the value in the counter circuit to produce (0b 10 1010 0001=-351); and b) adding one to produce the negated count value in the counter circuit as (0b 10 1010 0010=-350). During the forward refinement (ELAB=1) of the computation operation within the memory, the bit line BL The bit line current iBL is integrated to generate the second series of pulses. The negated value in the counter circuit is incremented by one in response to each of the 200 pulses in the second series of pulses, so the binary value in the counter circuit is (0b 11 0110 1010 = -150).

[0128] The column processing circuit 220 also includes a digital signal processing circuit system for storing the result digital signal dY of the calculation operation in the memory. A And the digital signal dY A Performs digital operations and calculations to generate decision outputs of in-memory computational operations.

[0129] Although Figure 6 It is illustrated that one analog-to-digital converter (ADC) is provided for each bit line, but it will be appreciated that the ADC resources in the column processing circuit 220 may instead be shared by multiple bit lines using time division multiplexing.

[0130] Although Figure 6 It is not explicitly shown, but it is understood that the circuit 210 also includes conventional row decoding, column decoding and read / write circuits known to those skilled in the art for use in connection with writing data bits (e.g., calculation weight data) to and reading data bits from the memory cells 214 of the memory array 212. This operation is referred to as a conventional memory access mode and is distinguished from the analog in-memory computation operation discussed above.

[0131] Note that, Figure 6 An advantage of the embodiment is that the signed computation weights for the in-memory computation operations are encoded in the group 215 forming a 1x2 matrix configuration. aB The two memory cells 214 are Figure 1 Embodiments utilize groups 115 formed into a 2x2 matrix configuration. AB of four memory cells 114. Thus, there is a 2x reduction in memory for array 212 as compared to array 112 (or, there is a 2x increase in weight storage capacity for array 212 as compared to array 112).

[0132] Reference now Figure 7 , which shows a circuit diagram of the row controller 218. A group 215 of memory cells 214 aB Each row of the latch circuit 252 is provided B To latch coefficient data X B The corresponding sign and value of the signed digital value of the memory cell 214. aB Each row provides logic circuit 250 B . Logic circuits 2501 to 250 N The Start signal is asserted at the beginning of each refinement in the positive and negative refinements of the in-memory computation operation. B ), for example in response to a global enable signal generated by a control circuit. The generation of the enable signal may, for example, depend on the coefficient data X B The corresponding signed digital value of , which has a non-zero value for the analog in-memory computation operation. The global counter circuit 254 increments the count value (Count) starting from a zero reset at the beginning of each (positive and / or negative) refinement of the in-memory computation operation, wherein the refinement ends when Count reaches a maximum value. The group 215 of the memory cells 214 aB Each row of the comparison circuit 256 B Coupled to latch circuit 252 B And the count value Count and the latched coefficient data X B When the count value Count reaches or exceeds the latched digital value, the comparison circuit 256 B The output of the Set-Reset Latch Circuit 258 B having a logic circuit 250 coupled to receive B Output Start B The signal is set (S) input and is coupled to receive the comparison circuit 256 B The output of the reset (R) input of the combinational logic circuit 260 B Logically combine the latch circuit 252 from B The sign bit B and refinement indicator signal (ELAB). The switching logic state of refinement indicator signal ELAB indicates whether positive refinement (logic 1) or negative refinement (logic 0) is being performed. In an embodiment, combinational logic circuit 260 B It is a logical exclusive OR (XOR) gate. Combinational logic circuit 262 B The logically combined set-reset latch circuit 258 B The output (Q) of the combinational logic circuit 260 B The output of the pulsed word line signal is applied to the positive word line WL + Driver circuit 216. Combinatorial logic circuit 264 B Logically Combined Set-Reset Latch Circuit 258 B The output (Q) of the combinational logic circuit 260 B The output of the logic is inverted to generate a pulse word line signal for application to the negative word line WL -driver circuit 216. In one embodiment, the combinational logic circuit 262 B and 264 B It is a logic AND gate.

[0133] The operation of the circuit system within the row controller 218 is as follows: At the beginning of the in-memory calculation operation, the coefficient data X1 to X2 are selectively loaded using the decoding of the address signal Address. N The digital value is stored in latch circuits 2521 to 252 N The latch is latched, and the global counter 254 is reset. If the coefficient data is non-zero, then the group 215 of the memory cell 214 is selected. aB The row and logic circuit 250 B Start signal B The output is asserted logic high at the beginning of each refinement in the positive and negative refinements and the latch circuit 258 is set-reset. B is set to a logic high at its output Q. The logic state of the switch refinement indicator control signal ELAB indicates whether positive refinement is being performed (logic 1) or negative refinement is being performed (logic 0). Now consider each of the four cases described above. Case (1): If the sign bit Sign B is logic 0 (indicating coefficient data X B If the digital value of is positive), and the refinement indicator control signal ELAB is logic 1 (indicating that a positive refinement of the in-memory computation operation is being performed), then XOR gate 260 B The input of the XOR gate 260 is opposite in logic. B Here, the output of AND gate 262 is logic high. B Both inputs of the AND gate 262 are logic high, and B The output turns to logic high to the positive word line WL + provides the leading edge of the word line signal pulse. Case (2): If the sign bit Sign B is logic 1 (indicating coefficient data X B If the digital value of is negative), and the refinement indicator control signal ELAB is logic 1 (indicating that a positive refinement of the in-memory computation operation is being performed), then XOR gate 260 B Both inputs of the XOR gate are logic high, and the XOR gate 260 B Here, the AND gate 264 B Both inputs of the AND gate 264 are logic high, and B The output turns to logic high to the negative word line WL - provides the leading edge of the word line signal pulse. Case (3): If the sign bit Sign B is logic 0 (indicating coefficient data X B If the digital value of is positive), and the refinement indicator control signal ELAB is logic 0 (indicating that a negative refinement of the in-memory computation operation is being performed), then XOR gate 260 B Both inputs of the XOR gate are logic low, and the XOR gate 260 B Here, the AND gate 264 B Both inputs of the AND gate 264 are logic high, and B The output turns to logic high to the negative word line WL - provides the leading edge of the word line signal pulse. Case (4): If the sign bit Sign B is logic 1 (indicating coefficient data X B If the digital value of is negative), and the refinement indicator control signal ELAB is logic 0 (indicating that a negative refinement of the in-memory computation operation is being performed), then XOR gate 260 B The input of the XOR gate 260 is the opposite logic, and B Here, both inputs of AND gate 262B are logic high, and AND gate 262 B The output turns to logic high to the positive word line WL + provides the leading edge of the word line signal pulse. Then, the global counter 254 starts to increment the Count value. When the incremented Count value reaches or exceeds the value set by the latch circuit 252 B Latched coefficient data X B The digital value of the comparison circuit 256 B The output of is asserted logic high and the set-reset latch circuit 258 B is reset to its output Q as logic low. This logic low output is applied to AND gate 262 B and 264 B Both, and whichever output of these AND gates is logic high (corresponding to the assertion of the word line signal pulse) will transition to logic low to provide the trailing edge of the word line signal pulse. Therefore, the pulse width (i.e., the on time T) of the generated pulse word line signal ON ) depends on the incremented Count value reaching the coefficient data X B The amount of time required to calculate the numeric value of . A given refinement ends when Count reaches its maximum value. If the given refinement is the first refinement of an in-memory computation operation, the process is repeated for the second refinement of an in-memory computation operation.

[0134] Reference now Figure 8 , which shows a circuit diagram of an example of an ADC circuit (referred to herein as a digital detector 22 circuit). Figure 3 and Figure 8 Like reference numerals in the drawings represent the same or similar components. Figure 8 The digital detector 22 in Figure 3 The digital detector 22 in FIG. 1 differs only in its interface with the bit lines. Figure 3 In the embodiment, each ADC circuit digital detector 22 is coupled to a corresponding bit line pair BL through a column selection circuit controlled by a refinement signal ELAB. + and BL -。 Figure 6 The circuit 210 does not use separate bit lines for positive refinement and negative refinement. Instead, each bit line time multiplexes the positive refinement and negative refinement on a given bit line. Therefore, Figure 8 The digital detector 22 in the embodiment omits the column selection circuit and instead connects the bit line BL Directly coupled to the current mirror circuit 35. Flowing through the bit line BL The current iBL is mirrored by the current mirror circuit 35 and applied as bias currents of the first inverters 45 and 50 of the first and second integrating stages 41 and 42, respectively. In addition, Figure 8 The circuit configuration and operation of the digital detector 22 in Figure 3 The circuit configuration and operation of the digital detector 22 in are the same as those in FIG.

[0135] Reference now Fig. 9 , which shows a simplified timing diagram of the operation of circuit 210 (including two separate refinements and the use of circuit 218) associated with an overall in-memory computation operation. At time t1, the latch control signal is asserted to cause latch circuits 2521 to 252 N Latch coefficient data X1 to X N The signed digital value of , and the overall in-memory computing operation begins. At time t2, the refinement indicator signal ELAB switches to logic 0 in association with the negative refinement that initiates the in-memory computing operation. We assume that the above-discussed and Figure 6 , where during negative refinement of an in-memory computation operation, in response to non-zero coefficient data, a group 215 of memory cells 214 is selected simultaneously. aB All rows of , and in response to Start at time t2 B The assertion of the signal simultaneously activates the word lines WL corresponding to the positive characteristic or coefficient data X1, X2 using the pulse word line signal <1> -、WL <2> - (Case (3)) and using a pulse word line signal to simultaneously activate the negative characteristic or coefficient data X N The corresponding word line WL <n>+ (Case (4)). Similarly, at time t3, the previously reset Count value begins to increment. At time t4, the incremented Count value reaches or exceeds the digital value of coefficient data X1, and the negative word line WL <1> -The word line signal pulse on WL is terminated. At time t5, the incremented Count value reaches or exceeds the digital value of coefficient data X2, and the negative word line WL <2> -The word line signal pulse on the terminal is terminated. At time t6, the incremented Count value reaches or exceeds the coefficient data X N The digital value of the positive word line WL <n>The word line signal pulse on + terminates. At time t8, the Start signal is de-asserted and the Count value is reset.

[0136] Starting from time t3, each ADC starts to receive data from the bit line BL. The bit line current iBL Integration is performed to generate a first series of pulses, and the count value in the ripple counter is incremented in response to each pulse in the first series. The increment of the negatively refined count value continues until time t8, which is after all word lines have been deactivated. At time t9, the control circuit asserts the select signal Sel to disconnect the ripple counter configuration and causes the multiplexer 68 in each ADC circuit to pass the inverted pulse IP signal at time t10. In response to the inverted pulse IP signal being applied to the clock input of the D flip-flop 67 in each ADC circuit, the bit of the negatively refined count value is logically inverted (performing step a) of the 2's complement operation described above). Then, the select signal is de-asserted to restore the multiplexer 68 in each ADC circuit back to the ripple counter connection, and then the control circuit applies a single pulse Pulse to the input of the ripple counter at time t11. This will cause the logically inverted bit of the count value to increase by one (performing step b) of the 2's complement operation described above). This will produce the negated refinement value via a 2's complement operation to reside in the D flip-flop 67 in each ADC circuit.

[0137] At time t12, the refinement indicator signal ELAB switches to logic 1 in association with initiating a forward refinement of the in-memory computation operation. We again assume that the above-discussed and Figure 6 , where during forward refinement of an in-memory computation operation, groups 215 of memory cells 214 are simultaneously selected in response to non-zero coefficient data. aB All rows of , and in response to Start at time t12 B The assertion of the signal simultaneously activates the word lines WL corresponding to the positive characteristic or coefficient data X1, X2 using the pulse word line signal <1> +、WL <2> + (case (1)), and using a pulse word line signal to simultaneously activate the negative characteristic or coefficient data X N The corresponding word line WL <n>(Case (2)) Similarly, at time t12, the previously reset Count value begins to increment. At time t13, the incremented Count value reaches or exceeds the digital value of coefficient data X1, and the positive word line WL <1> + word line signal pulse terminates. At time t14, the incremented Count value reaches or exceeds the digital value of coefficient data X2, and the positive word line WL <2> + The word line signal pulse on the + is terminated. At time t15, the incremented Count value reaches or exceeds the coefficient data X N The digital value of the negative word line WL <n>The word line signal pulse on - terminates. At time t16, the Start signal is de-asserted and the Count value is reset.

[0138] From time t12, each ADC starts to receive data from the bit line BL. The bit line current iBL Integration is performed to generate a second series of pulses, and in response to each pulse in the second series, the count value in the ripple counter is incremented starting from the negated refinement value (generated by performing a 2's complement operation on the negative refinement count value as described above). The incrementing of the count value for positive refinement continues until time t16 when all word lines have been deactivated. At time t17, when positive refinement is completed, the resulting count value in the D flip-flop 68 of each ADC circuit can be output as a digital signal dY A .

[0139] The foregoing description has provided by way of exemplary and non-limiting examples a complete and informative description of exemplary embodiments of the present invention. However, various modifications and adaptations may become apparent to those skilled in the relevant art in view of the foregoing description when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of the present invention will still fall within the scope of the present invention as defined by the appended claims. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A memory computing circuit, comprising: a memory array comprising a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein a group of memory cells stores computation weights for an in-memory computation IMC operation performed by a first multiply-and-accumulate MAC refinement producing a first analog signal and a second MAC refinement producing a second analog signal; as well as The analog-to-digital converter circuit is configured as: incrementing a count value in a counter circuit in response to a first analog signal; converting the count value in the counter circuit into an inverted count value; and A count value in the counter circuit is incremented starting from the negated count value in response to the second analog signal.

2. The in-memory computing circuit of claim 1, wherein the analog-to-digital converter circuit comprises: an integration circuit configured to integrate the first analog signal to generate a first series of pulses, the counter circuit incrementing a count value in response to each pulse in the first series; as well as The integration circuit is further configured to integrate the second analog signal to generate a second series of pulses, and the counter circuit increments the count value starting from the inverted count value in response to each pulse in the second series.

3. The in-memory computation circuit of claim 1 , wherein the first MAC refinement is a negative refinement and the second MAC refinement is a positive refinement; and wherein the conversion of the count value in the counter circuit to the negated count value is performed by using a 2's complement operation on the count value.

4. The in-memory computing circuit according to claim 1: wherein the memory cells in each first column of the columns of the memory array are connected by a negatively thinned bit line; wherein during a first MAC refinement of a computation operation within the memory, a first analog signal is generated on each negative going refinement bit line; wherein the memory cells in every second column of the columns of the memory array are connected by a forward thinning bit line; and Wherein during a second MAC refinement of the in-memory compute operation, a second analog signal is generated on each forward refinement bitline.

5. The in-memory computation circuit of claim 4 , wherein the analog-to-digital converter circuit comprises a column selection circuit configured to select a first analog signal generated on a negative going refinement bit line during a first MAC refinement and to select a second analog signal generated on a positive going refinement bit line during a second MAC refinement.

6. The in-memory computation circuit of claim 4 , wherein each memory cell group storing computation weights comprises four memory cells arranged in a 2×2 matrix, wherein a first memory cell and a second memory cell in the 2×2 matrix of the group are connected to a negative refinement bit line, and a third memory cell and a fourth memory cell in the 2×2 matrix of the group are connected to a positive refinement bit line.

7. The in-memory computing circuit of claim 6, wherein the weight -1 is calculated by the matrix Calculate the weight 0 by the matrix Represented by, and the weight +1 is calculated by the matrix express.

8. The in-memory computing circuit according to claim 6: wherein the first memory cell and the third memory cell in the 2x2 matrix of the set are connected to a positive word line that is actuated during in-memory computing operations in response to positive characteristic data; and Wherein a second memory cell and a fourth memory cell in the 2x2 matrix of the group are connected to a negative word line that is actuated during in-memory computing operations in response to negative characteristic data.

9. The in-memory computing circuit according to claim 5: wherein the memory cells in each column of the memory array are connected by a bit line; wherein during a first MAC refinement of the in-memory compute operation, a first analog signal is generated on each bit line; as well as Wherein during a second MAC refinement of the in-memory compute operation, a second analog signal is generated on each of the bit lines.

10. The in-memory computation circuit of claim 9, wherein each memory cell group storing computation weights comprises two memory cells arranged in a 1x2 matrix, wherein a first memory cell and a second memory cell in the 1x2 matrix of the group are connected to a bit line.

11. The in-memory computing circuit of claim 10, wherein the weight -1 is calculated by the matrix Indicates that the weight 0 is calculated by the matrix Represented by, and the weight +1 is calculated by the matrix express.

12. The in-memory computing circuit of claim 10: wherein a first memory cell in the 1x2 matrix of the group is connected to a positive word line that is actuated during a computational operation within the memory in response to positive characteristic data; and Wherein a second memory cell in the 1x2 matrix of the group is connected to a negative word line that is actuated during a computational operation within the memory in response to negative characteristic data.

13. The in-memory computing circuit of claim 1, wherein the analog-to-digital converter circuit comprises: an integrating stage configured to convert a current provided by each of the first analog signal and the second analog signal into a plurality of charge packets indicated by the pulses; as well as A counting stage includes a ripple counter having a counter input configured to receive a pulse.

14. The in-memory computation circuit of claim 13, wherein the counting stage comprises: Multiple triggers; a multiplexing circuit system configured to connect clock inputs of the plurality of flip-flops to form the ripple counter in response to a first logic state of a control signal, and configured to apply an inverted pulse signal to the clock inputs of the plurality of flip-flops in response to a second logic state of the control signal to cause a logical inversion of each bit of the count value stored by the plurality of flip-flops during a logical inversion portion of a 2's complement operation for converting a count value in the counter circuit to the inverted count value; as well as A control circuit is configured to generate the control signal and also apply a single pulse to the counter input of the counting stage during an add portion of a 2's complement operation for converting a count value in the counter circuit to the negated count value.

15. A method for performing an in-memory computing (IMC) operation, comprising: performing a first multiply-and-accumulate MAC refinement of an IMC operation to generate a first analog signal; incrementing a count value in a counter circuit in response to a first analog signal; Convert the count value in the counter circuit into an inverted count value; performing a second MAC refinement of the IMC operation to generate a second analog signal; and A count value in the counter circuit is incremented starting from the negated count value in response to the second analog signal.

16. The method of claim 15, further comprising: integrating the first analog signal to generate a first series of pulses; wherein incrementing comprises incrementing a count value in a counter circuit in response to each pulse in the first stream; as well as integrating the second analog signal to generate a second series of pulses; Wherein incrementing comprises incrementing a count value in a counter circuit starting from the negated count value in response to each pulse of the second series.

17. The method of claim 15, wherein the first MAC refinement is a negative refinement and the second MAC refinement is a positive refinement, and converting the count value in the counter circuit to the negated count value comprises performing a 2's complement operation on the count value.

18. The method of claim 15, wherein the IMC operation is performed by an in-memory computation circuit, the in-memory computation circuit comprising a memory array, the memory array comprising a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein a group of memory cells stores computation weights for the IMC operation; wherein the memory cells in each first column of the columns of the memory array are connected by a negatively thinned bit line; wherein the memory cells in every second column of the columns of the memory array are connected by a forward thinning bit line; The method comprises: generating a first analog signal on each negative going refinement bit line during a first MAC refinement of a compute operation within the memory; as well as During a second MAC refinement of the in-memory compute operation, a second analog signal is generated on each forward refinement bitline.

19. The method of claim 18, further comprising selecting a first analog signal generated on a negative going refinement bit line during a first MAC refinement and selecting a second analog signal generated on a positive going refinement bit line during a second MAC refinement.

20. The method of claim 18, wherein each group of memory cells storing calculation weights comprises four memory cells arranged in a 2x2 matrix, and wherein: a first memory cell and a second memory cell in the 2x2 matrix of the group connected to a negatively thinned bit line, and a third memory cell and a fourth memory cell in the 2x2 matrix of the group connected to a positively thinned bit line; as well as A first memory cell and a third memory cell in the 2x2 matrix of the group are connected to a positive word line that is actuated during a computational operation within the memory in response to positive characteristic data; as well as The second and fourth memory cells in the 2x2 matrix of the group are connected to a negative word line that is actuated during in-memory computation operations in response to negative characteristic data.

21. The method of claim 20, wherein the weight -1 is calculated by the matrix Indicates that the weight 0 is calculated by the matrix Represented by, and the weight +1 is calculated by the matrix express.

22. The method of claim 15, wherein the IMC operation is performed by an in-memory computation circuit, the in-memory computation circuit comprising a memory array, the memory array comprising a plurality of memory cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein a group of memory cells stores computation weights for the IMC operation; wherein the memory cells in each column of the memory array are connected by a bit line; The method comprises: generating a first analog signal on each bit line during a first MAC refinement of an in-memory compute operation; as well as During a second MAC refinement of the in-memory compute operation, a second analog signal is generated on each bit line.

23. The method of claim 22, wherein each group of memory cells storing calculation weights comprises two memory cells arranged in a 1x2 matrix, and wherein: A first memory cell and a second memory cell in a 1x2 matrix of the group are connected to a bit line; A first memory cell in the 1x2 matrix of the group is connected to a positive word line that is actuated during a computational operation within the memory in response to positive characteristic data; as well as A second memory cell in the 1x2 matrix of the group is connected to a negative word line that is actuated during in-memory computation operations in response to negative characteristic data.

24. The method of claim 23, wherein the weight -1 is calculated by the matrix Indicates that the weight 0 is calculated by the matrix Represented by, and the weight +1 is calculated by the matrix express.

25. The method of claim 1, wherein integrating comprises converting a current provided by each of the first analog signal and the second analog signal into a plurality of charge packets indicated by pulses, and wherein incrementing comprises counting the pulses in a ripple counter.

26. The method of claim 25, wherein converting the count value comprises: switching a clock input of a flip-flop connected from the ripple counter to form the ripple counter; applying an inverted pulse signal to a clock input of the flip-flop so that each bit of the count value stored by the flip-flop is logically inverted during a logic inversion portion of a 2's complement operation for converting the count value in the counter circuit into the inverted count value; as well as A single pulse is applied to the input of the ripple counter during the add portion of the 2's complement operation for converting the count value in the counter circuit to the negated count value.

Images