Coroutine implementation method and device for GPU (Graphics Processing Unit) programming

Abstract

The invention provides a coroutine implementation method and device for GPU programming, and relates to the technical field of computer graphics and programming languages, and the method comprises the steps: obtaining a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code comprises at least one hanging node, and the hanging node is used for defining a hanging behavior and a recovery behavior of a coroutine; segmenting a calculation task corresponding to a coroutine according to a suspended node of the coroutine program code to obtain a plurality of sub-routines and a plurality of coroutine frames; wherein the coroutine frame is used for transmitting information among the plurality of subroutines; and based on the plurality of coroutine frames, respectively distributing the plurality of segmented sub-routines to a plurality of threads of the GPU for parallel execution. According to the method provided by the invention, the sub-routines are automatically processed and divided, the coroutine frame for storing the intermediate data is determined, and a large number of coroutines can be efficiently executed in parallel.

Description

Technical Field

[0001] The present invention relates to the technical field of computer graphics and programming languages, and in particular to a coroutine implementation method and device for GPU programming. Background Art

[0002] Modern GPUs have evolved into powerful general-purpose parallel computing devices capable of handling increasingly complex rendering tasks. However, although it is feasible to implement high-workload complex tasks such as path tracing in a single large kernel (mega-kernel), this straightforward implementation leads to low hardware utilization due to thread divergence in control flow and memory access. Therefore, graphics developers usually have to refactor rendering tasks into multiple smaller GPU kernels and manually plan their execution to improve performance. A classic example is wavefront path tracing, which decomposes the path tracing process of a large kernel into multiple sub-kernels. However, manually splitting and scheduling large kernels is quite complex and error-prone, which makes us seek a unified and automated solution to expand the expressive power of the original programming model so that developers can focus on algorithm design and avoid investing energy in complex scheduling logic design.

[0003] How to efficiently execute a large number of coroutines in parallel is a technical problem that needs to be solved at present. Summary of the invention

[0004] The present invention provides a coroutine implementation method and device for GPU programming, so as to solve the defects existing in the prior art.

[0005] The present invention provides a coroutine implementation method for GPU programming, comprising the following steps: Acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine; The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transfer information between the plurality of subroutines; Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.

[0006] According to a coroutine implementation method for GPU programming provided by the present invention, the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple subroutines, including: Converting the coroutine program code into an intermediate representation; Based on the intermediate representation and the suspended nodes of the coroutine program code, a plurality of preset calculation rules are executed to obtain a plurality of subroutines divided based on the calculation tasks corresponding to the coroutine.

[0007] According to a coroutine implementation method for GPU programming provided by the present invention, converting the coroutine program code into an intermediate representation includes: The abstract syntax tree corresponding to the coroutine program code is converted into a control flow graph, and the control flow graph is simplified to obtain a simplified control flow graph; wherein the simplified control flow graph is used to describe the overall control flow process of the coroutine, and the simplified control flow graph includes: basic nodes, control flow nodes and termination nodes.

[0008] According to a coroutine implementation method for GPU programming provided by the present invention, the suspended node based on the intermediate representation and the coroutine program code executes multiple preset calculation rules to obtain multiple subroutines divided based on the calculation tasks corresponding to the coroutine, including: Traversing the simplified control flow graph, determining a plurality of potential subroutines, and forming a reachable node set based on reachable nodes of each potential subroutine in the plurality of potential subroutines; Based on the reachable node set and the suspended nodes of the coroutine program code, a plurality of subroutines divided based on the computing tasks corresponding to the coroutine are obtained.

[0009] According to a coroutine implementation method for GPU programming provided by the present invention, the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple coroutine frames, including: The computing tasks corresponding to the coroutine are divided according to the suspended nodes of the coroutine formula code, and data flow analysis is performed on the divided coroutines to obtain the active state of each of the multiple division points; Based on the active state of each of the multiple segmentation points, a corresponding plurality of coroutine frames are obtained.

[0010] According to a coroutine implementation method for GPU programming provided by the present invention, the data flow analysis includes: internal usage definition parsing and cross-domain active state analysis; The data flow analysis is performed on the split coroutine to obtain the active state of each of the multiple split points, including: Perform internal usage definition analysis and cross-domain active status analysis on the split coroutines to obtain the active status of each of the multiple split points. The internal usage definition parsing is used to extract the internal calls and external references of each subroutine in the multiple subroutines; and the cross-domain active state analysis is used to determine the storage relationship and loading relationship between subroutines.

[0011] The present invention also provides a coroutine implementation device for GPU programming, comprising the following modules: An acquisition module, used to acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine; A segmentation module, used for segmenting the computing task corresponding to the coroutine according to the suspended nodes of the coroutine formula code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used for transmitting information between the plurality of subroutines; The scheduling module is used to allocate the divided multiple subroutines to multiple threads of the GPU for parallel execution based on the multiple coroutine frames.

[0012] According to a coroutine implementation device for GPU programming provided by the present invention, the segmentation module is specifically used for: Converting the coroutine program code into an intermediate representation; Based on the intermediate representation and the suspended nodes of the coroutine program code, a plurality of preset calculation rules are executed to obtain a plurality of subroutines divided based on the calculation tasks corresponding to the coroutine.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the coroutine implementation method for GPU programming as described in any one of the above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-described coroutine implementation methods for GPU programming.

[0015] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned coroutine implementation methods for GPU programming.

[0016] The present invention provides a coroutine implementation method and device for GPU programming, which obtains a coroutine formula code written by a user based on a GPU programming language; wherein the coroutine formula code includes at least one suspension node, and the suspension node is used to define the suspension behavior and recovery behavior of the coroutine; the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transfer information between the multiple subroutines; based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution. It can be seen from this that the present invention automatically processes the division of subroutines and determines the coroutine frame storing intermediate data according to the coroutine formula code written by the user, runs the coroutine according to the parsing result, and can efficiently execute a large number of coroutines in parallel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a flow chart of the coroutine implementation method for GPU programming provided by the present invention.

[0019] Figure 2 It is an overall flow chart of the coroutine implementation method for GPU programming provided by the present invention.

[0020] Figure 3 It is a schematic diagram of an example of using the GPU programming language provided by the present invention.

[0021] Figure 4 It is a transformation schematic diagram of the parser provided by the present invention.

[0022] Figure 5 It is a schematic diagram of a subroutine conversion diagram of the parser provided by the present invention.

[0023] Figure 6 It is a structural schematic diagram of a coroutine implementation device for GPU programming provided by the present invention.

[0024] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] Combine the following Figure 1-Figure 7 A coroutine implementation method and device for GPU programming of the present invention are described.

[0027] Figure 1 is a flow chart of the coroutine implementation method for GPU programming provided by the present invention, such as Figure 1 As shown, the method includes the following: Step 100: Obtain a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine.

[0028] It should be noted that GPU (Graphic Processing Unit) is a processor specially designed for efficient parallel processing of large amounts of data. The embodiment of the present invention implements the coroutine of GPU programming through three modules, specifically including: a coroutine programming model for GPU programming and its corresponding domain-specific language DSL (i.e., the above-mentioned GPU programming language); a parser corresponding to the coroutine programming model; and a scheduler for coroutine tasks. The above are all specific logic execution modules, not hardware structures.

[0029] Specifically, the embodiment of the present invention provides an asymmetric, stackless coroutine programming model. The coroutine language features and runtime support provided by this embodiment are based on Luisa to reuse its structure while avoiding platform-specific details. Figure 2 is an overall flow chart of the coroutine implementation method for GPU programming provided by the present invention, such as Figure 2 As shown in the figure, the implementation adds two new function categories, Coroutine and Generator, based on the original domain-specific language. Coroutine provides a basic function category declaration. The $suspend keyword can be used to mark the suspension position inside it, so that the parser can divide subroutines or identify specific subroutines. Other coroutines can also be called through the $await keyword to form a recursive coroutine call. Users can use the $promise keyword to explicitly store intermediate process values ​​in the coroutine frame and use them in the calling function; they can also use .target_token and .coro_id to obtain the running status corresponding to the coroutine frame, the corresponding thread index and other information. Figure 3 This is a schematic diagram of an example of using the GPU programming language provided by the present invention. For specific examples of use, see Figure 3 .

[0030] The DSL also includes the advanced function pattern Generator, which is a function object that produces a sequence only when called. Generators can suspend return values ​​using the $yield keyword.

[0031] Step 200: divide the computing task corresponding to the coroutine according to the suspension node of the coroutine program code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transfer information between the multiple subroutines.

[0032] It should be noted that step 200 is specifically implemented by a parser of the coroutine programming model. Figure 4 is a transformation schematic diagram of the parser provided by the present invention, Figure 5 is a schematic diagram of a subroutine conversion diagram of the parser provided by the present invention, such as Figure 4 and Figure 5 As shown, the main purpose of the parser is to convert the coroutine code into subroutines expressed in the backend shader language and organized as follows Figure 5 The subroutine transition graph shown in FIG. Specifically, the program entry point and each suspension point are associated with a split subroutine, which are represented as nodes in the graph. These subroutines are extracted as executable functions on the device side. The subroutine resumes the suspended program state from the corresponding coroutine frame at the beginning, and then executes the program instructions after the suspension point. When executing to the next suspension point, the subroutine saves the current program state to the coroutine frame and returns the execution control to the caller, thereby realizing the suspension operation. The transfer relationship between subroutines is modeled by directed edges in the graph. Each edge connects a pair of source subroutine and target subroutine with a "suspend-resume" relationship. In addition, each edge is embedded with coroutine frame information, recording the fields in the coroutine frame that need to be stored when the source subroutine is suspended and the fields that need to be loaded when the target subroutine is resumed. The scheduler can use the subroutine transition graph to plan and optimize the execution process of the coroutine, thereby improving parallel efficiency and resource utilization.

[0033] Specifically, step 200 divides the computing task corresponding to the coroutine according to the suspended node of the coroutine formula code to obtain multiple subroutines, including: Step 210: Convert the coroutine program code into an intermediate representation.

[0034] Step 210 specifically includes: The abstract syntax tree corresponding to the coroutine program code is converted into a control flow graph, and the control flow graph is simplified to obtain a simplified control flow graph; wherein the simplified control flow graph is used to describe the overall control flow process of the coroutine, and the simplified control flow graph includes: basic nodes, control flow nodes and termination nodes.

[0035] Step 220: Based on the intermediate representation and the suspended nodes of the coroutine program code, execute multiple preset computing rules to obtain multiple subroutines divided based on the computing tasks corresponding to the coroutine.

[0036] Step 220 specifically includes: Step 221: traverse the simplified control flow graph, determine multiple potential subroutines, and form a reachable node set based on the reachable nodes of each potential subroutine in the multiple potential subroutines.

[0037] Step 222: Based on the reachable node set and the suspended nodes of the coroutine program code, obtain a plurality of subroutines divided based on the computing tasks corresponding to the coroutine.

[0038] Furthermore, step 200 divides the computing task corresponding to the coroutine according to the suspended node of the coroutine formula code to obtain multiple coroutine frames, including: Step 230: Split the computing task corresponding to the coroutine according to the suspended node of the coroutine program code, and perform data flow analysis on the split coroutine to obtain the active state of each of the multiple split points.

[0039] It should be noted that the data flow analysis includes: internal usage definition analysis and cross-domain active status analysis.

[0040] Step 230 specifically includes: Perform internal usage definition analysis and cross-domain active status analysis on the split coroutines to obtain the active status of each of the multiple split points. The internal usage definition parsing is used to extract the internal calls and external references of each subroutine in the multiple subroutines; and the cross-domain active state analysis is used to determine the storage relationship and loading relationship between subroutines.

[0041] Step 240: Based on the active state of each of the multiple segmentation points, obtain corresponding multiple coroutine frames.

[0042] In one embodiment, the parser converts the abstract syntax tree (AST) corresponding to the coroutine written in the domain-specific language into a fluent static single assignment (SSA) intermediate representation (IR). After that, the parser performs multiple calculation processes to obtain the subroutines divided by the coroutine. This process is described in detail below.

[0043] 1. Preprocessing.

[0044] 1) First, through control flow normalization, the parser will simplify complex control flows such as GenericLoop, Break, Continue, and Return into if and do-while loops. Redundant statements will be simplified so that only Loop has a reverse edge in the control flow graph (CFG).

[0045] 2) Then, to reduce the active state of each suspension point, active state simplification is performed. Variables are reduced to their lifetime by declaring them in the latest basic block, and the loading of aggregates is reduced.

[0046] 2. Subroutine extraction.

[0047] First, the original coroutine is expressed as a CFG graph, which describes the overall control flow process of the coroutine, including basic nodes, control flow nodes, and termination nodes. By traversing the CFG graph, the reachable nodes of each subroutine can be determined. Finally, to ensure the correctness and simplicity of the control flow after division, the parser will restart the subroutine from the suspension point in the nested loop through conditional replay. After these operations, the nodes in the CFG are properly assigned to different suspension points and subroutines corresponding to the entry.

[0048] 3. The coroutine frame is concretized.

[0049] In order to ensure that different subroutines can run correctly after suspension, the context of the program, that is, the coroutine frame, needs to be passed between subroutines. Directly storing all variables will result in excessive memory overhead, so only necessary data will be saved in the coroutine frame: the values ​​used by the current subroutine that reference external definitions need to be loaded, and the values ​​loaded by other subroutines defined by the current subroutine need to be stored. To this end, this embodiment performs two data flow analysis processes: internal use-definition parsing and cross-domain active state analysis, and finally merges all variable sets to form a coroutine frame.

[0050] 1) Internal use-definition parsing extracts all internal calls and external references in the subroutine. The standard SSA form basically covers this information, but the local storage operation of the Local instruction still requires special processing. For each subroutine domain, the set of variables covered up to a certain node, the set of variables that reference external definitions, and the set of variables that may be modified are maintained during the traversal process.

[0051] 2) Cross-domain active state analysis finally determines the store-load relationship between subroutines. First, all subroutines are organized into a coroutine transfer graph. After that, the active state of each subroutine is determined in turn during the traversal process, and the variables read and stored by each subroutine are inferred based on this.

[0052] 4. Post-processing.

[0053] After the above processing, the subroutine will be instantiated as a function, the CFG will be reconstructed into an intermediate representation, and the coroutine-related intrinsic keywords will be reduced to operations such as reading and loading coroutine frames.

[0054] Step 300: Based on the multiple coroutine frames, the multiple subroutines after segmentation are respectively allocated to multiple threads of the GPU for parallel execution.

[0055] It should be noted that step 300 is specifically implemented by the scheduler of the coroutine task. The scheduler is responsible for actually executing the coroutine task and managing related resources. Users can design special-purpose schedulers according to their needs, or directly call the built-in general high-performance scheduler. For a custom scheduler, the user needs to implement the _dispatch method in the inherited class, which is used to create and assign a certain number of coroutine instances to the instruction stream. This embodiment provides two built-in general high-performance schedulers, the wavefront scheduler and the persistent thread scheduler.

[0056] Wavefront Scheduler: is a direct generalization of the wavefront path tracing technique. The basic idea is to decompose the state machine into multiple sub-kernels, each of which handles a subroutine. Coroutine frames are stored in a global buffer, loaded by the subroutine when it resumes, and updated when it suspends. Transfers between subroutines are tracked via the suspend position field in the frame.

[0057] In each iteration, the running thread index is established from the global frame buffer. This embodiment uses a stable multi-segmentation algorithm to cluster the index by the suspension location field to ensure physical consistency and reduce scheduling overhead. The scheduler then dispatches the subroutine kernel to process the instance corresponding to the index. When the coroutine reaches termination, a new instance is generated in the original frame buffer block. This embodiment provides a variety of detailed settings to further improve performance in some cases: 1. Structure of Arrays (SoA) layout. The structure of arrays (SoA) layout is the transpose of the structure array (AoS) layout, storing each field of the state frame as a separate scalar buffer. This enables the sub-kernel to load and store only the necessary state frame fields according to the information in the subroutine conversion graph, reducing the required memory bandwidth and being more suitable for cache units on modern GPUs, but it may also affect the performance of random access.

[0058] 2. Frame buffer compression. Coroutine instances usually have uneven lifecycles and therefore terminate at different times, leaving gaps in the frame buffer and compromising the locality of memory access. Users can enable compression to collect all active instances to the beginning of the buffer when the number of unterminated coroutine instances (the percentage of non-terminated coroutine instances) is below a certain threshold. However, the relocation of a large number of frames may consume considerable memory bandwidth.

[0059] Persistent Thread Scheduler: In modern GPU architectures, threads are organized in blocks on streaming multiprocessors. Therefore, the persistent thread scheduler tries to leverage fast block shared memory to store state frames instead of frequent and expensive global memory accesses. The scheduler also batches coroutine instances to run the state machine within a block to improve the consistency of threads within the block. In this scheduling approach, the thread lifecycle lasts for multiple task batches until a group of tasks ends.

[0060] Task acquisition: When a thread block decides to generate a new task, it acquires a batch of pending tasks. This request is made by the leader thread in the block to the global task index counter.

[0061] State machine execution within a block: Subroutines are organized into a single kernel state machine, executed synchronously within a block. At each step, the leader thread looks at the subroutine counter and selects the most common continuing subroutine in the block. Important instance indices are collected into a queue but stored in fast shared memory. All threads then run the same subroutine, processing the collected instances. The relevant frames are loaded from shared memory to local storage before the call and written back afterwards. The scheduler also provides a variety of customization options: 1. SoA layout to avoid conflicts: When threads in a thread cluster access different addresses in the same memory cache at the same time, bank conflicts will occur in the GPU shared memory, resulting in performance degradation. To alleviate this problem, the persistent thread scheduler of this embodiment can be configured to use the SoA memory layout to store state frames, reducing the possibility of bank overlap caused by the alignment structure.

[0062] 2. Global memory extension: If the persistent thread implementation only keeps all frames in shared memory, then the available shared memory size will partially limit parallelism because only a portion of the threads in a block may participate in execution. To bypass this limitation, this embodiment uses a global buffer as an extension of the state frame storage, which together with the shared memory keeps enough frames to ensure that each iteration fills all threads in the entire block. When the size of the shared memory is not enough to accommodate the frames of all instances selected in the state machine step, some currently unused frames will be swapped to the global memory. This extension sacrifices a small amount of global bandwidth for better thread occupancy.

[0063] The coroutine implementation method for GPU programming provided by the embodiment of the present invention expands the basic capabilities of GPU programming and realizes support for coroutines; it can automatically divide and schedule computing tasks expressed by coroutines, improve program running efficiency and simplify maintenance difficulty for developers; it simplifies the programming difficulty of inserting additional processes into the original task; and it adds asynchronous programming capabilities to GPU programming.

[0064] The above is a step description of the coroutine implementation method for GPU programming provided by the present invention. From the description of the above steps, it can be seen that according to the coroutine implementation method for GPU programming provided by the present invention, by obtaining the coroutine formula code written by the user based on the GPU programming language; wherein the coroutine formula code includes at least one suspension node, and the suspension node is used to define the suspension behavior and recovery behavior of the coroutine; the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transfer information between the multiple subroutines; based on the multiple coroutine frames, the multiple subroutines after the division are respectively allocated to multiple threads of the GPU for parallel execution. It can be seen from this that the present invention automatically processes the division of subroutines and determines the coroutine frame storing intermediate data according to the coroutine formula code written by the user, and runs the coroutine according to the parsing results, so that a large number of coroutines can be efficiently executed in parallel.

[0065] The coroutine implementation device for GPU programming provided by the present invention is described below. The coroutine implementation device for GPU programming described below and the coroutine implementation method for GPU programming described above can be referenced to each other.

[0066] Figure 6 is a schematic diagram of the structure of the coroutine implementation device for GPU programming provided by the present invention, such as Figure 6 As shown, the coroutine implementation device for GPU programming provided by the present invention includes: An acquisition module 601 is used to acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine; A segmentation module 602 is used to segment the computing task corresponding to the coroutine according to the suspended nodes of the coroutine formula code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transfer information between the multiple subroutines; The scheduling module 603 is used to allocate the divided multiple subroutines to multiple threads of the GPU for parallel execution based on the multiple coroutine frames.

[0067] The coroutine implementation device for GPU programming provided by the present invention obtains the coroutine formula code written by the user based on the GPU programming language; wherein the coroutine formula code includes at least one suspension node, and the suspension node is used to define the suspension behavior and recovery behavior of the coroutine; the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transfer information between the multiple subroutines; based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution. It can be seen from this that the present invention automatically processes the division of subroutines and determines the coroutine frame storing intermediate data according to the coroutine formula code written by the user, runs the coroutine according to the parsing result, and can efficiently execute a large number of coroutines in parallel.

[0068] Based on the above embodiment, in this embodiment, the segmentation module 602 is specifically used for: Converting the coroutine program code into an intermediate representation; Based on the intermediate representation and the suspended nodes of the coroutine program code, a plurality of preset calculation rules are executed to obtain a plurality of subroutines divided based on the calculation tasks corresponding to the coroutine.

[0069] Based on the above embodiment, in this embodiment, the device further includes a conversion module, which is specifically used for: The abstract syntax tree corresponding to the coroutine program code is converted into a control flow graph, and the control flow graph is simplified to obtain a simplified control flow graph; wherein the simplified control flow graph is used to describe the overall control flow process of the coroutine, and the simplified control flow graph includes: basic nodes, control flow nodes and termination nodes.

[0070] Based on the above embodiment, in this embodiment, the segmentation module 602 is specifically used for: Traversing the simplified control flow graph, determining a plurality of potential subroutines, and forming a reachable node set based on reachable nodes of each potential subroutine in the plurality of potential subroutines; Based on the reachable node set and the suspended nodes of the coroutine program code, a plurality of subroutines divided based on the computing tasks corresponding to the coroutine are obtained.

[0071] Based on the above embodiment, in this embodiment, the segmentation module 602 is specifically used for: The computing tasks corresponding to the coroutine are divided according to the suspended nodes of the coroutine formula code, and data flow analysis is performed on the divided coroutines to obtain the active state of each of the multiple division points; Based on the active state of each of the multiple segmentation points, a corresponding plurality of coroutine frames are obtained.

[0072] Based on the above embodiment, in this embodiment, the data flow analysis includes: internal usage definition parsing and cross-domain active status analysis; The device also includes an analysis module, which is specifically used for: Perform internal usage definition analysis and cross-domain active status analysis on the split coroutines to obtain the active status of each of the multiple split points. The internal usage definition parsing is used to extract the internal calls and external references of each subroutine in the multiple subroutines; and the cross-domain active state analysis is used to determine the storage relationship and loading relationship between subroutines.

[0073] Figure 7 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 7 As shown, the electronic device may be a robot or other electronic device, and the electronic device may include: a processor 710, a communications interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communications interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the coroutine implementation method for GPU programming, including: Acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine; The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transfer information between the plurality of subroutines; Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.

[0074] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0075] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the coroutine implementation method for GPU programming provided by the above methods, including: Acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine; The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transfer information between the plurality of subroutines; Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.

[0076] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the coroutine implementation method for GPU programming provided by the above methods, including: Acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine; The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transfer information between the plurality of subroutines; Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.

[0077] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0078] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A coroutine implementation method for GPU programming, characterized in that: include: Acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine; The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transfer information between the plurality of subroutines; Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.

2. The coroutine implementation method for GPU programming according to claim 1, characterized in that: The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine formula code to obtain multiple subroutines, including: Converting the coroutine program code into an intermediate representation; Based on the intermediate representation and the suspended nodes of the coroutine program code, a plurality of preset calculation rules are executed to obtain a plurality of subroutines divided based on the calculation tasks corresponding to the coroutine.

3. The coroutine implementation method for GPU programming according to claim 2, characterized in that: The converting the coroutine program code into an intermediate representation comprises: The abstract syntax tree corresponding to the coroutine program code is converted into a control flow graph, and the control flow graph is simplified to obtain a simplified control flow graph; wherein the simplified control flow graph is used to describe the overall control flow process of the coroutine, and the simplified control flow graph includes: basic nodes, control flow nodes and termination nodes.

4. The coroutine implementation method for GPU programming according to claim 3, characterized in that: The suspended node based on the intermediate representation and the coroutine program code executes a plurality of preset calculation rules to obtain a plurality of subroutines divided based on the calculation tasks corresponding to the coroutine, including: Traversing the simplified control flow graph, determining a plurality of potential subroutines, and forming a reachable node set based on reachable nodes of each potential subroutine in the plurality of potential subroutines; Based on the reachable node set and the suspended nodes of the coroutine program code, a plurality of subroutines divided based on the computing tasks corresponding to the coroutine are obtained.

5. The coroutine implementation method for GPU programming according to claim 1, characterized in that: The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple coroutine frames, including: The computing tasks corresponding to the coroutine are divided according to the suspended nodes of the coroutine formula code, and data flow analysis is performed on the divided coroutines to obtain the active state of each of the multiple division points; Based on the active state of each of the multiple segmentation points, a corresponding plurality of coroutine frames are obtained.

6. The coroutine implementation method for GPU programming according to claim 5, characterized in that: The data flow analysis includes: internal usage definition analysis and cross-domain active status analysis; The data flow analysis is performed on the split coroutine to obtain the active state of each of the multiple split points, including: Perform internal usage definition analysis and cross-domain active status analysis on the split coroutines to obtain the active status of each of the multiple split points. The internal usage definition parsing is used to extract the internal calls and external references of each subroutine in the multiple subroutines; and the cross-domain active state analysis is used to determine the storage relationship and loading relationship between subroutines.

7. A coroutine implementation device for GPU programming, characterized in that: include: An acquisition module, used to acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and the resume behavior of the coroutine; A segmentation module, used for segmenting the computing task corresponding to the coroutine according to the suspended nodes of the coroutine formula code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used for transmitting information between the plurality of subroutines; The scheduling module is used to allocate the divided multiple subroutines to multiple threads of the GPU for parallel execution based on the multiple coroutine frames.

8. The coroutine implementation device for GPU programming according to claim 7, characterized in that: The segmentation module is specifically used for: Converting the coroutine program code into an intermediate representation; Based on the intermediate representation and the suspended nodes of the coroutine program code, a plurality of preset calculation rules are executed to obtain a plurality of subroutines divided based on the calculation tasks corresponding to the coroutine.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the coroutine implementation method for GPU programming as described in any one of claims 1 to 6 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the coroutine implementation method for GPU programming as claimed in any one of claims 1 to 6 is implemented.

Images