Eye pattern index analysis method, computer readable recording medium, and electronic device

Abstract

The invention provides an eye pattern index analysis method, a computer readable recording medium and an electronic device. The eye diagram index analysis method comprises the following steps: calculating a transfer function of a plurality of coupling lines; converting the transfer function into a pulse wave response; calculating an eye diagram index according to the pulse wave response; and correcting the eye pattern index according to the peak distortion analysis.

Description

Technical Field

[0001] The invention relates to an eye diagram index analysis method, a computer-readable recording medium and an electronic device. Background Art

[0002] With the rapid development of technology, all kinds of electronic products have gradually become an indispensable part of life. Electronic products close to personal life, such as wearable devices, computers, mobile phones, and tablets, are constantly being introduced, and double data rate (DDR) synchronous dynamic random access memory (SDRAM) is an essential part of these products. With the evolution of DDR modules, their speed has gradually increased. As the bandwidth of DDR modules is getting higher and higher, how to effectively transmit data becomes more important.

[0003] DDR modules, as the main bridge between storage and processors, realize data transmission through multiple transmission lines, but these lines will couple with each other, thus generating crosstalk. Especially when there are many channels, the Far-End Crosstalk (FEXT) caused by the crosstalk aggressor at the receiving end becomes one of the bottlenecks for increasing the data transmission rate. At the same time, when the transmitting end and the receiving end do not match, FEXT and Near-End Crosstalk (NEXT) will also have an adverse effect on signal integrity.

[0004] In this case, in order to ensure high-quality transmission of the DDR module, the signal integrity needs to be analyzed and measured, and the worst sequence on multiple transmission lines needs to be found quickly. In the prior art, it is very time-consuming to simulate the eye diagram using a pseudorandom binary sequence (PRBS). Since the inter-symbol interference (ISI) caused by FEXT and NEXT requires a specific sequence to generate the worst eye diagram, it is very difficult to obtain the worst sequence for different lines at the same time if PRBS is used. Therefore, it is necessary to develop a fast method to find the worst sequence on multiple transmission lines to ensure high-quality transmission of the DDR module. Summary of the invention

[0005] The embodiment of the present invention provides an eye diagram index analysis method, a computer readable recording medium and an electronic device, wherein the eye diagram index analysis method can effectively find the worst sequence mode on multiple transmission lines in multiple channels.

[0006] The eye diagram index analysis method of the embodiment of the present invention includes: calculating the transfer functions of multiple coupled lines; converting the transfer functions into pulse responses; calculating the eye diagram index according to the pulse responses; and correcting the eye diagram index according to the peak distortion analysis.

[0007] The computer-readable recording medium of the embodiment of the present invention includes a computer program, which enables a computer to execute the above-mentioned eye diagram index analysis method after executing the computer program.

[0008] The electronic device of the embodiment of the present invention comprises a processor and a storage component. The storage component stores a computer program, and enables the processor to execute the eye diagram index analysis method after executing the computer program.

[0009] In order to make the above content easier to understand, several embodiments accompanied by drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure includes accompanying drawings to provide a further understanding of the present disclosure, and the accompanying drawings are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0011] Figure 1 Schematic representation of an eye icon showing good signal quality.

[0012] Figure 2 Schematic diagram of an eye icon showing poor signal quality.

[0013] Figure 3 A schematic diagram showing a signal path overview of an insertion loss response of an embodiment of the present invention.

[0014] Figure 4 A schematic diagram showing the signal paths of a far-range crosstalk response according to an embodiment of the present invention.

[0015] Figure 5 A schematic diagram showing the insertion loss response of an embodiment of the present invention.

[0016] Figure 6 A schematic diagram showing a far-range crosstalk response according to an embodiment of the present invention.

[0017] Figure 7 A schematic diagram showing a main light target according to an embodiment of the present invention is shown.

[0018] Figure 8 A schematic diagram showing the worst eye height at the main cursor sampling time point according to an embodiment of the present invention.

[0019] Fig. 9 A schematic diagram showing a single transmission line with no matching at both the transmitting end and the receiving end according to an embodiment of the present invention.

[0020] Fig.10 A schematic diagram showing a plurality of coupled lines with unmatched sides according to an embodiment of the present invention.

[0021] Fig.11 A schematic diagram showing a transmitter and a receiver both connected in parallel with capacitors according to an embodiment of the present invention is shown.

[0022] Fig.12 A schematic diagram showing a DDR4 circuit according to an embodiment of the present invention.

[0023] Fig.13 A schematic diagram showing a CMOS output buffer according to an embodiment of the present invention.

[0024] Fig.14 A schematic diagram showing a linear equivalent circuit of a transmitter according to an embodiment of the present invention.

[0025] Fig.15 A schematic diagram showing a linear equivalent circuit of a receiver according to an embodiment of the present invention.

[0026] Fig.16 A schematic diagram showing a linear equivalent circuit of a SOC and a DRAM end in a 'write' mode according to an embodiment of the present invention.

[0027] Fig.17 A schematic diagram showing a linear equivalent circuit of a SOC and a DRAM end in a 'read' mode according to an embodiment of the present invention.

[0028] Fig.18 A schematic diagram showing a DDR4 circuit according to another embodiment of the present invention.

[0029] Fig.19 A schematic diagram showing S parameters of a power line port according to an embodiment of the present invention is shown.

[0030] Fig. 20 A schematic diagram showing a clock signal sequence according to an embodiment of the present invention.

[0031] Fig.21 A schematic diagram showing a worst sequence eye diagram according to an embodiment of the present invention.

[0032] Fig. 22 A block diagram of an electronic device according to an embodiment of the present invention is shown.

[0033] Fig.23 A flowchart showing the steps of the eye diagram index analysis method according to an embodiment of the present invention is shown.

[0034] Fig.24 A block diagram of an electronic device according to another embodiment of the present invention is shown.

[0035] Fig.25A schematic diagram showing the worst eye width according to an embodiment of the present invention.

[0036] Fig.26 A schematic diagram showing the central worst eye height according to an embodiment of the present invention.

[0037] Fig. 27 A schematic diagram showing the cell eye width according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0039] The embodiment of the present invention provides an eye diagram index analysis method, which can effectively find the worst sequence mode on multiple transmission lines in multiple channels. The existing method needs to consider a large number of sequence combinations, which is very computationally intensive and time-consuming. Therefore, the embodiment of the present invention proposes an eye diagram index based on the peak distortion analysis (PDA) method of pulse response. By extending the pulse response to multiple transmission lines, the worst sequence mode on multiple transmission lines can be quickly found, and the eye diagram index can be calculated to quickly analyze the signal integrity. This method can find the worst sequence mode in a short time to calculate the eye diagram index, thereby saving a lot of time and calculation for simulating eye diagrams.

[0040] Take the double data rate (DDR) module as an example. DDR module is one of the most common memory modules in computer motherboards and other devices today. With the development of integrated circuit manufacturing technology, the data transmission rate of DDR is getting higher and higher, reaching the level of gigabytes per second (Gbps). However, the higher and higher data transmission rate and the shorter and shorter signal rise and fall time bring challenges to the system signal integrity. In the design of DDR modules, the signal is transmitted by multiple transmission lines at the same time, and the transmission lines are often very close due to cost considerations. Therefore, special attention should be paid to problems such as transmission delay, reflection, crosstalk, etc. These problems will damage the integrity of the signal, and then lead to data error transmission or reduced transmission rate. Eye diagrams can be used to evaluate the signal integrity of DDR modules, which can help designers understand the transmission status and damage degree of the signal so as to take corresponding optimization measures in the design. For example, if the eye diagram opening becomes smaller or deformed, the designer can consider increasing the power of the driver or reducing the length of the transmission line to improve the signal integrity.

[0041] The embodiment of the present invention proposes an eye diagram index analysis method. By inputting S parameters, the pulse response of the boundary containing non-matching linear components can be calculated through the derived transfer function, and the eye diagram index can be calculated based on PDA.

[0042] The eye diagram is composed of a series of overlapping pulse responses, each waveform represents a signal sample at a different time point. When a continuous digital signal is interfered or distorted during transmission, the shape of the signal waveform will change. By combining these waveforms together, the deformation of the signal can be seen.

[0043] The main purpose of eye diagrams is to evaluate the signal quality of high-speed data transmission systems and to detect problems in data transmission. For example, eye diagrams can be used to detect problems such as signal distortion, timing offset, and spurious interference. By analyzing eye diagrams, we can further understand the characteristics of the signal, thereby optimizing the design of the transmission system and improving the quality of the signal. Figure 1 , Figure 2 , you can see Figure 1 Have eyes that are wider apart, both in height and width Figure 2 The big one represents Figure 1 The system has better signal integrity.

[0044] Generally, PRBS (Pseudorandom Binary Sequence) is used to simulate the eye diagram. However, the amount of data generated by PRBS is very large, and its analysis and evaluation process often requires a lot of time and resources. Therefore, in order to improve efficiency, the PDA method can be used to analyze the worst eye diagram. PRBS stands for Pseudorandom Binary Sequence, which is a digital signal. PRBS is a binary sequence generated by a set of pseudorandom number generators. And it has random statistical properties, such as the number of "0" and "1" in the PRBS signal is roughly equal. PRBS is often used as the input signal for simulating eye diagrams to evaluate the performance of digital systems. However, in actual situations, there are usually many channels. Since the eye diagram generated by PRBS is representative only when the length is long enough, it will be very time-consuming to simulate the eye diagram using PRBS for multiple channels. And the ISI of crosstalk on the main signal requires a specific sequence to generate the worst eye diagram. In the case of multiple channels, it is the current trend to find the worst sequence through peak distortion analysis (PDA) based on pulse response.

[0045] In a linear time-invariant (LTI) system, the pulse responses of the system at different times are superimposed on each other, so that the inter-symbol interference can be calculated from a single pulse response, and then the worst sequence of the eye diagram can be found. An LTI system means that there is a linear relationship between the input and output of the system, but the system parameters do not change over time. In other words, the system's response to the input is fixed and does not change over time.

[0046] In the LTI system, a series of signals can be regarded as the superposition of many signals. If a symbol is transmitted but its waveform has not completely disappeared, it will interfere with the transmission of the next symbol. This interference is called inter-symbol interference. The impact of inter-symbol interference can be calculated by analyzing the pulse response.

[0047] In the LTI digital system, if the input signal is a series of "1" and "0", because it is an LTI system, this series of signals can be regarded as a single trapezoidal wave at many different times as the input signal and then superimposed together. In a multi-transmission line circuit, the pulse response can be divided into two parts. The first is the insertion loss response. Figure 3 As shown in the figure, a single trapezoidal wave signal, that is, a signal sequence of "0100000", is sent out by the transmitting end of the main signal line, and what is received by the receiving end of the main signal line is the insertion loss response. The second is the Far-end Crosstalk Response (FEXT Response). Figure 4 The single trapezoidal wave signal, that is, the signal sequence of "0100000", is sent by the transmitter of the crosstalk active end, and what the main signal line receiving end receives is the long-range crosstalk response.

[0048] like Figure 5 Insertion loss response, define a cursor as the main cursor. The time before the main cursor is defined as the precursor cursor, and the time after the main cursor is defined as the nth post cursor. th The UI represents the unit interval between two consecutive bits. Due to the system response, the previous cursor and the nth postcursor do not return to the zero level, and these interferences are called inter-symbol interference. The sampling point greater than 0 is defined as ISI+, such as Figure 5 The second post cursor, the sampling point less than 0 is defined as ISI-, such as Figure 5 The first back cursor.

[0049] In a circuit with multiple transmission lines, crosstalk can also cause inter-symbol interference, as can be seen. Figure 6 At the same sampling point as the previous insertion loss response, there is ISI XT + sampling point, such as the first post cursor, and ISI XT - sampling points, such as the main cursor and the second rear cursor. Then, the worst case 1 and the worst case 0 can be listed:

[0050] Worst case 0=∑|ISI + |+∑|ISI XT + | (1)

[0051] Worst case 1=cursor-∑|ISI - |-∑|ISI xT - | (2)

[0052] From (1), we can see that for the worst bit 1, it is only affected by the cursor and negative ISI, so negative ISI corresponds to bit 1, and positive ISI corresponds to bit 0; the worst bit 0 is the opposite.

[0053] exist Figure 5 The insertion loss response is not considered for the time being because the front light target value is 0. The worst bit 1 at the transmitting end of the main signal line is "011". First, the main cursor corresponds to the cursor, so the last bit of the worst bit 1 is "1", the first rear cursor corresponds to the negative ISI, so the second to last bit of the worst bit 1 is "1", and the second rear cursor corresponds to the positive ISI, so the third to last bit of the worst bit 1 is "0"; and the worst bit 0 is the inverse of the worst bit 1: "100".

[0054] exist Figure 6 The remote crosstalk response is not considered temporarily because the front light target value is also 0. The worst bit 1 of the transmitter at the active end of the crosstalk is "101". The main cursor, the first rear cursor, and the second rear cursor correspond to negative, positive, and negative ISI respectively, so the last bit, the second to last bit, and the third to last bit of the worst bit 1 correspond to "1", "0", and "1"; and the worst bit 0 is "010".

[0055] After obtaining the worst bit 1 and the worst bit 0 of the main signal line and all coupled lines, they can be connected in series as the worst eye diagram sequence of each line, and used as the input signal of the transmitter of each line to obtain the worst eye diagram.

[0056] The following first explains the eye diagram indicators, then derives the transfer function of a single transmission line, and then extends it to the transfer function of multiple coupled lines to quickly establish the pulse response of multiple transmission lines and calculate the eye diagram indicators.

[0057] First, the eye diagram index is described. In the embodiment of the present invention, the eye diagram index at least includes the worst eye width and the worst eye height at the center, which are described as follows.

[0058] From (1) and (2), the worst 1 level and 0 level can be calculated. Therefore, the worst eye height at the main cursor sampling time point can be calculated by subtracting the worst 1 level from the worst 0 level as shown in (3). Figure 7 The dotted line represents the main cursor. Figure 8 The dashed line and marker indicate the worst eye height at this key light target sampling point.

[0059] Worst eye height

[0060] = cursor-∑|ISI - |-∑|ISI xT - |-∑|ISI + |-∑|ISI XT + | (3)

[0061] It can be seen that when calculating the worst eye height, whether it is positive or negative ISI, the absolute value will be added and then subtracted. Therefore, we can also use the values ​​of different sampling points to rewrite (3) to obtain (4):

[0062] Worst eye height

[0063] =main cursor-Z|postcursor|-Z|precursor|

[0064] -∑∑|xtk cursor j | (4)

[0065] Among them, main cursor represents the cursor value of the main signal line, postcursor represents the values ​​of different post-light target ISIs of the main signal line, precursor represents the values ​​of different pre-light target ISIs of the main signal line, and xtkcursor represents the ISI values ​​of each sampling point on all coupled lines.

[0066] The values ​​of the cursor and post-cursor in (4) can be calculated using (5) to obtain (6) and (7):

[0067]

[0068] Among them, V SBR (t) is the pulse response, but in practical applications, the bandwidth of the transfer function is limited, like the S parameter of limited bandwidth, so it can only be estimated using the integral of limited frequency. Vi(f) is the input signal, that is, a single trapezoidal wave. H(f) is the transfer function of the system.

[0069]

[0070]

[0071] Where main represents the value of the cursor and post cursor of the main signal line, xtk represents the xtk cursor, and k and 1 represent different sampling points. For example, k = 0 represents the main cursor, k = 1 represents the first post cursor, Hmain (f) and Hxtk (f) represent the transfer functions of the insertion loss response and the remote crosstalk response, respectively, Vi (f) is the input signal, that is, a single trapezoidal wave, τ represents the time delay of the main signal line from the transmitter to the receiver plus the time difference of different main cursor sampling points.

[0072] In (6) and (7), we can see that the integration range is from -f0 to f0. However, the transfer functions Hmain(f) and Hxtk(f) in the integration include S parameters. In reality, S parameters do not include negative frequencies. However, we can use the properties of the signal's pulse function h(t) and the single trapezoidal wave Vi(t) that only has values ​​when t>0 to obtain (8) and (9). Then we can list (10) and (11):

[0073] H(-f)=H * (f) (8)

[0074] V i (-f) = V i * (f) (9)

[0075]

[0076]

[0077] Among them, (10) and (11) can be calculated using fast Fourier transform. In order to reduce the interval △t in the time domain and improve the resolution of the time domain, we can use zero padding to increase the total number of points to the required number of points N, which can be listed as (12):

[0078]

[0079] Where △t is the specified time domain interval point, △f is the frequency domain interval point, and N is the total number of points after zero filling. Finally, (10) and (11) can be rewritten as fast Fourier transform forms (13) and (14):

[0080]

[0081]

[0082] Where main represents the insertion loss response of the main signal line, and xtk represents the remote crosstalk response caused by the coupled line. Then (4) can be rewritten as (15):

[0083]

[0084] Where N represents the number of post-cursors considered on the main signal line, L represents the number of pre-cursors considered on the main signal line, M represents the number of xtk cursors considered on the coupling line, P represents the number of xtk pre-cursors considered on the coupling line, and j represents different coupling lines.

[0085] Then, the worst eye height at different sampling time points can be obtained from (15), where the positions where the worst eye height on both sides of the eye is equal to zero are the left and right endpoints, and their sampling time points are τ right , τ left , subtracting these two sampling time points, we get the worst eye width (16), and then by calculating the midpoint of the left and right endpoints (17), we can also get the worst eye height (18) at the center. We can list (16), (17) and (18) respectively:

[0086] Index width =τ right -τ left (16)

[0087]

[0088]

[0089] Therefore, in the embodiment of the present invention, the eye diagram indicators at least include the worst eye width and the worst eye height at the center.

[0090] Next, we will explain the transfer function of a single transmission line. In order to obtain the transfer function that is not matched at both the transmitter and the receiver, we can first consider a single transmission line such as Fig. 9 As shown. The S parameter matrix can be defined as:

[0091]

[0092] Among them, a1 and a2 are the transmitted waves of the transmitting end and the receiving end respectively; b1 and b2 are the reflected waves of the transmitting end and the receiving end respectively.

[0093] In terms of transmission lines, the distortion of signals transmitted from the transmitter to the receiver must be within an acceptable range. S parameters can be used to measure the impact of transmission line interconnection on signals in the frequency domain, that is, the frequency domain characteristics of signals can be observed through S parameters. Electronic components between transmission lines can be equivalently described as an S parameter matrix and are used to simulate the behavior of electronic components at different frequencies.

[0094] The transfer function V2 / V of a single transmission line that is not matched at both the transmitter and receiver ends S It can be deduced as:

[0095]

[0096] Among them, Γ S , Γ L is the reflection coefficient between the transmitter and the receiver, The matrix is ​​as follows:

[0097]

[0098] Next, we will explain the transfer function of multiple coupled lines (i.e., transmission lines). In order to obtain the transfer function of insertion loss response and remote crosstalk response Where k = 1~n, m = 1~n, we can Fig. 9 The single transmission line architecture is extended to multiple coupled lines, such as Fig.10 As shown, there are n coupled lines.

[0099] First, it can be defined by the S parameter matrix:

[0100]

[0101] in, is a 1，i The column vector, b 1，i represents the reflected wave of the i-th (where i=1, ..., n) transmission line at the transmitting end. By analogy, it is the column vector composed of the reflected waves at the receiving end; and are the column vectors composed of the transmitted waves of the transmitting end and the receiving end respectively.

[0102] Since there is no voltage source at the receiving end, the transmitted wave is the reflected wave multiplied by the reflection coefficient, so it can be listed as:

[0103]

[0104] There are voltage sources at the transmitter, which can be listed as:

[0105]

[0106] in is the voltage source V at the transmitter S，i The column vector formed can then be substituted into (21) by (22) and (23) to form:

[0107]

[0108] in represents an n×n zero matrix, represents the n×n identity matrix, represent Placed above this 2n×n matrix, is placed below this 2n×n matrix. The diagonal matrix of reflection coefficients can then be defined as

[0109]

[0110] Substituting (24) back into (21), we can obtain:

[0111]

[0112] The matrix on the left is defined as

[0113]

[0114] Then By making an inverse matrix, we can get the relationship between the reflected wave and each voltage source:

[0115]

[0116] Consider the reflected wave at the receiving end and the voltage V at the receiving end 2，k The relationship between them can be obtained:

[0117]

[0118] in is the voltage at the receiving end V 2，i Then substitute (26) back into (25) and we can get:

[0119]

[0120] in represent Placed on the left side of this n×2n matrix, Placed on the right side of this n×2n matrix. So we can get a transfer function matrix of size n×n

[0121] in The elements of are the transfer functions of insertion loss response and long-range crosstalk response

[0122] When k=m, it is the transfer function of the insertion loss response of the kth signal line. When k≠m, it represents the transfer function of the remote crosstalk caused by the mth signal line to the kth line. Therefore, we only need to substitute (27) back into (10) and (11) to obtain the insertion loss response and remote crosstalk response.

[0123] Next, the transfer function with parallel circuit boundaries is explained. Taking the DDR module as an example, the main storage structure of the DDR module is DRAM, and DRAM is composed of capacitors and transistors. Therefore, in the linear equivalent circuit, both the transmitter and the receiver will have additional parallel capacitors, such as Fig.11 As shown. Among them, Z L C The resistance R at the receiving end L With capacitor C L Parallel, Z S The resistor R at the transmitter S .

[0124] Transfer Function with Parallel Circuit Boundaries It can be deduced as:

[0125]

[0126] The parameters are:

[0127]

[0128] Z S =R S

[0129]

[0130]

[0131]

[0132]

[0133]

[0134]

[0135] The following uses the DDR4 circuit as an example to explain the eye diagram indicator analysis. Fig.12 The DDR4 circuit used for verification of the embodiment of the present invention, the transmission path of DDR4 can be roughly divided into CPU, package (PKG), printed circuit board (PCB) and DRAM, wherein PCB transmits data through multiple transmission lines of equal length, and DQ, DM and DQS are several key signal lines for transmitting data, and DQ stands for "Data" or "Data Lines", which is used to transmit data; DM stands for "Data Mask", which is used to indicate whether the data transmitted by each DQ online is valid. If the DM online signal is low, it means that the data transmitted by the corresponding DQ online is invalid; DQS stands for "Data Strobe", which is used to indicate the timing of data transmission. DDR memory uses the DQS signal to synchronize the transmission timing during data transmission. Fig.12 In the figure, the S parameters of the package (PKG) and printed circuit board (PCB) are considered, which include DQ 0 to DQ 31, DM 0, DQS0, a total of 44 lines. Fig.12 The triangle on the left represents the linear equivalent circuit of the SOC (System on a Chip) side, and the triangle on the right represents the linear equivalent circuit of the DRAM side. Since in this DDR circuit, the read and write modes share the same signal line, the circuits on the SOC and DRAM sides will switch to the transmitter or receiver mode according to the read and write mode, so the linear equivalent circuits on both ends will be different in the read and write modes.

[0136] The transmitter circuit can be represented by a simple CMOS output buffer, such as Fig.13 As shown. Then, the resistance of the inverter can be equivalent through the current-voltage relationship of the inverter. Therefore, the linear equivalent circuit of the transmitter finally becomes as follows Fig.14 As shown in the figure, an ideal pulse power supply and resistor are used to equalize CMOS. The linear equivalent circuit of the receiver includes an ODT (On-Die Termination) plus a capacitor C equivalent to the parasitic capacitance effect, as shown in the figure. Fig.15 As shown. Since DDR transmits data through multiple transmission lines of equal length in PCB, adjacent transmission lines will cause serious crosstalk. At the same time, if the ports are not matched, the crosstalk will also produce multiple reflections at the passive end, which will have a serious impact on the signal integrity. The principle of ODT is to add a terminal resistor to the output end inside the DRAM chip to match the impedance of the output end, thereby eliminating reflections and crosstalk.

[0137] In the "write" mode, the SOC side is in transmitter mode and the DRAM side is in receiver mode, such as Fig.16 As shown in the figure, the linear equivalent circuit of the SOC end is composed of an ideal pulse power supply including an internal resistor and a capacitor in parallel. The linear equivalent circuit of the DRAM end includes ODT and a storage capacitor. In the "read" mode, the SOC end is in receiver mode and the DRAM end is in transmitter mode, as shown in the figure. Fig.17 shown.

[0138] Next, we will explain the S parameter preprocessing and peak distortion analysis including clock signals. First, we will explain the S parameter preprocessing. Fig.18 The circuit includes the S parameters of PKG and PCB, but does not include PWR and CAP ports. Fig.12 The circuit is used for verification, and Fig.18 The difference lies in the S parameters of the PCB. Fig.12 The S parameters of the PCB include the ports of the power line PWR and the decoupling capacitor CAP. Therefore, this embodiment processes the S parameters of the PCB and reduces them to S parameters that do not include the power line PWR and the decoupling capacitor CAP.

[0139] Here with Fig.19 For example, ports V1 and V2 are the first signal line, ports V3 and V4 are the second signal line, ports V5 and V6 can represent the power line and the port of the decoupling capacitor respectively. Finally, we want to get the S parameters that are reduced to only ports V1, V2, V3, and V4 and consider the effects of ports V5 and V6. First, the S parameter matrix S1 can be listed as:

[0140]

[0141] The 6×6 S parameter matrix S1 is split into four matrices: A, B, C, and D, which can be listed as follows:

[0142]

[0143] The relationship between a5, b5 and a6, b6 is as follows:

[0144] a5=Γ5b5

[0145]

[0146] a6=Γ6b6

[0147]

[0148] Among them, Z5 and Z6 are ports V5 and V6. Fig.19The load impedance is shown, Z0 is the system impedance of the S parameter, Γ5 and Γ6 are the reflection coefficients at the receiving end. Then, from (29), (30), the relationship between a5, b5 and a6, b6 can be obtained:

[0149]

[0150] After rearranging the above formula, we can get:

[0151]

[0152] The matrix E is:

[0153]

[0154] Next, perform an inverse matrix operation on matrix E to obtain the relationship between a1 to a6:

[0155]

[0156] Substituting the above formula back into (29) and (30), we can obtain:

[0157]

[0158] From the relationship between b1 to b4 and a1 to a4, the S parameter matrix S2 can be obtained as:

[0159] S2 4×4 =A 4×4 +B 4×2 (E 2×2 ) -1 C 2×4

[0160] Where S2 is the S parameter matrix including the effect of ports V5 and V6 and reduced to only ports V1, V2, V3, and V4. The derivation method of this embodiment can be extended to multiple signal lines and multiple power line ports or decoupling capacitor ports, and is not limited to the case of two signal lines, so it can solve Fig.12 In the problem, the S parameters of the PCB have several additional power line ports and decoupling capacitor ports.

[0161] Next, the peak distortion analysis including the clock signal will be described. Fig.12 The DQS in the figure is a differential signal line used to indicate the timing, so the input sequence is as follows: Fig. 20As shown. Since DQS is a pair of differential signal lines, the sequence of the positive and negative ends is inverted; in formula (15), the worst eye height can be obtained by deducting the absolute value of all ISI from the cursor of the main signal line. However, since the DQS signal is fixed to '1010...' and '0101...', if the original formula (15) is used, the actual eye height will be underestimated. Therefore, a correction will be made here for the peak distortion analysis including the clock signal.

[0162] Therefore, for equation (15), considering the total crosstalk of DQS and the crosstalk caused by the remaining coupled lines, it can be listed as:

[0163]

[0164] Among them, Xtk DQS Represents the total crosstalk of DQS, N represents the number of postcursors considered for the main signal line, L represents the number of predecessors considered for the main signal line, M represents the number of Xtk cursors considered on the coupling line, P represents the number of Xtkprecursors considered on the coupling line, and j represents different coupling lines.

[0165] Xtk DQS To calculate the worst case 1 and worst case 0 of DQS p and n, in which sequences have the worst ISI sum, as shown in Table 1.

[0166]

[0167] Table 1

[0168] In addition, considering the total crosstalk of DQS and the crosstalk caused by other coupled lines, equations (1) and (2) can be modified as follows:

[0169] Worst_0=∑|ISI + |+∑|ISI XT + |+|ISI DQS + | (32)

[0170] Worst_1=cursor-∑|ISI - |-∑|ISI XT - |-|ISI DQS - | (33)

[0171] Among them, ISID QS -To calculate the worst case 1 of DQS p and n, in which sequence the sum of ISI is relatively small; ISID QS + To calculate the worst case 0 of DQS p and n, under what sequence the sum of ISI is relatively large.

[0172] Fig.21 This is the worst sequence eye diagram obtained by using the eye diagram index analysis method of the embodiment of the present invention. In this embodiment, the eye diagram index analysis method can quickly (for example, only 0.8 seconds) obtain eye diagram indicators such as eye height and eye width, which can greatly save calculation and simulation time. Compared with the eye diagram obtained by using positive and negative PRBS and independent PRBS, the eye diagram index analysis method is fast and has a small error.

[0173] Fig. 22 A block diagram of an electronic device according to an embodiment of the present invention is shown. Fig.23 The flowchart of the eye diagram index analysis method according to the embodiment of the present invention is shown. Fig. 22 and Fig.23 , the electronic device 100 includes a processor 110 and a storage component 120. In an embodiment, the electronic device 100 is, for example, a computer, and the storage component 120 is, for example, a computer-readable recording medium, which includes a computer program, so that the computer executes the computer program. Fig.23 The eye diagram index analysis method of this embodiment is suitable for analyzing various electronic circuit architectures with multiple transmission lines to find the worst sequence mode in a short time to calculate the eye diagram index.

[0174] Specifically, in step S100, the processor 110 calculates Fig.10 The transfer function of the transmission line structure with multiple coupled lines is shown, for example, in equation (27), and the transfer function includes the transfer function of the insertion loss response and the remote crosstalk response. For example, when k = m, it is the transfer function of the insertion loss response of the k-th signal line, and when k ≠ m, it represents the transfer function of the remote crosstalk caused by the m-th signal line to the k-th line. In addition, the transfer function includes an S parameter matrix, which is used to describe the frequency domain characteristics of the electronic components between the transmission lines.

[0175] For example, the eye diagram analysis method of this embodiment can be used to analyze a DDR 4 memory circuit, wherein the DDR 4 memory circuit has a transmission line structure with multiple coupled lines. The S parameter matrix can be used to describe the frequency domain characteristics of electronic components in the DDR 4.

[0176] In step S110, the processor 110 substitutes equation (27) back into equations (10) and (11) to convert the transfer function into a pulse response, such as equation (5). The pulse response includes the pulse responses of the insertion loss response and the remote crosstalk response.

[0177] In step S120, the processor 110 calculates eye diagram indicators according to the pulse wave response, such as equations (15) to (18). The eye diagram indicators include worst eye height (15), worst eye width (16), and center worst eye height (18).

[0178] In step S130, the processor 110 modifies the eye diagram index according to the peak distortion analysis, such as formula (31). The peak distortion analysis includes the peak distortion analysis of the clock signal. That is, for formula (15), the processor 110 can further consider the sum of the crosstalk of the DQS and the crosstalk caused by the other coupled lines, and modify formula (15) to formula (31).

[0179] In an embodiment, for equations (1) and (2), the processor 110 may also consider the total crosstalk of DQS and the crosstalk caused by other coupled lines, and modify equations (1) and (2) into equations (32) and (33).

[0180] In an embodiment, the processor 110 is, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose micro control unit (MCU), microprocessor, digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), graphics processing unit (GPU), image signal processor (ISP), image processing unit (IPU), arithmetic logic unit (ALU), complex programmable logic device (CPLD), field programmable gate array (FPGA), or other similar components or combinations of the above components.

[0181] In an embodiment, the storage component 120 is used to store various software, data and various program codes required for the operation of the electronic device 100. The storage medium 120 is, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid state drive (SSD) or similar components or a combination of the above components, and is used to store multiple modules or various application programs that can be executed by the processor 110. In an embodiment, the storage component 120 may further include a database.

[0182] In addition, the eye diagram index analysis method of this embodiment can be obtained by Figures 1 to 21 Sufficient teachings, suggestions and implementation instructions are obtained from the description of the embodiments of the present invention, so they are not repeated here.

[0183] Fig.24 A block diagram of an electronic device according to another embodiment of the present invention is shown. Fig.23 and Fig.24 The electronic device 200 of this embodiment includes a processor 210, a storage component 220, and an input / output interface 230. The input / output interface 230 is used to receive circuit parameters and output the circuit parameters. Fig.23 The eye diagram is calculated using the eye diagram indicator analysis method.

[0184] Specifically, the circuit to be operated by the computer program of this embodiment is, for example, Fig.12 The DDR4 circuit includes the S parameters of the package (PKG), printed circuit board (PCB), and the linear equivalent circuit of the SOC end and the linear equivalent circuit of the DRAM end. According to the different read and write modes, the equivalent circuits at both ends are as follows: Fig.16 and Fig.17 The computer program of this embodiment can calculate the eye diagram indicators of DQ0-31 and DM0-3 under this circuit, including Fig.25 The worst eye width shown, such as Fig.26 The center worst eye height shown and Fig. 27 The box eye width (Box Eyewidth) shown. The input / output interface 230 is, for example, a display device, which can be used to display the above eye diagram indicators.

[0185] The user can enter S parameters and Fig.16 and Fig.17 The values ​​of the components in the linear equivalent circuit and the parameters of the voltage source are shown in Table 2 below:

[0186]

[0187]

[0188] Table 2

[0189] The input / output interface 230 is, for example, a display device, which can be used to display a program window so that the user can input various parameters through a keyboard, a mouse, or touch.

[0190] Therefore, this embodiment writes a program based on the eye diagram index analysis method and establishes a graphical user interface (GUI), so that users can calculate eye diagram indicators in a simple and intuitive operating environment, and the results will not only be directly presented in the interface, but also stored in a file for further analysis by the user.

[0191] In addition, the eye diagram index analysis method of this embodiment can be obtained by Figures 1 to 23 Sufficient teachings, suggestions and implementation instructions are obtained from the description of the embodiments of the present invention, so they are not repeated here.

[0192] An application scenario of the eye diagram index analysis method of an embodiment of the present invention is described below. The eye diagram index analysis method of an embodiment of the present invention can be used to verify whether the quality of the signal transmitted by the package and printed circuit board carrying the chip meets the requirements after the chip circuit is designed. There are several reasons that affect the quality of the signal transmitted by the package and printed circuit board: loss, reflection, crosstalk and equivalent load at the circuit end.

[0193] The general method of verifying signal quality is to connect the chip circuit model, PKG model, and PCB model in series and simulate them with circuit simulation software. However, such a simulation verification method requires more time if multiple signal lines are to be verified. Therefore, the eye diagram index analysis method of the embodiment of the present invention can first screen out signal lines that may have poor transmission signal quality, and then check their packaging and printed circuit board layout design and modify them.

[0194] In an embodiment, the eye diagram indicator analysis method can be integrated into an electronic design automation (EDA) tool, and can even provide the EDA tool as a reference for modification. In an embodiment, the input data required for the eye diagram indicator analysis method includes a package channel model of the carrier chip, a printed circuit board channel model connected to the chip package, and input parameters. Among them, the input parameters vary depending on the circuit to be tested and the function. Taking DDR transmission quality testing as an example, the parameters that need to be input are voltage source, transmission rate, write mode, read mode, circuit equivalent resistance load, circuit equivalent capacitance load, and eye height voltage.

[0195] In summary, in an embodiment of the present invention, an eye diagram index analysis method for multiple coupled transmission lines is proposed. First, the transfer function under the mismatch boundary is derived, and then its pulse response can be obtained by inverse Fourier transform, and based on peak distortion analysis, various indicators of the eye diagram can be obtained, which can greatly improve the design and optimization efficiency. Compared with other methods, the eye diagram index analysis method of the embodiment of the present invention can more effectively and correctly judge the signal integrity of different signal lines.

[0196] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An eye diagram index analysis method, comprising: Calculate transfer functions for multiple coupled lines; converting the transfer function into a pulse wave response; Calculating eye diagram indicators based on the pulse wave response; as well as The eye diagram indicators are modified based on peak distortion analysis. 2 . The eye diagram indicator analysis method according to claim 1 , wherein the transfer function comprises an S parameter matrix, and the S parameter matrix is ​​used to describe the frequency domain characteristics of electronic components between transmission lines.

3. The eye diagram indicator analysis method according to claim 2, wherein the electronic component is an electronic component in a double data rate memory circuit. 4 . The eye diagram indicator analysis method according to claim 1 , wherein the transfer function comprises a transfer function of an insertion loss response and a remote crosstalk response. 5 . The eye diagram index analysis method according to claim 1 , wherein the pulse response comprises the pulse responses of the insertion loss response and the far-range crosstalk response. 6 . The eye diagram index analysis method according to claim 1 , wherein the eye diagram index comprises at least one of worst eye height, worst eye width, center worst eye height and box eye width. 7 . The eye diagram index analysis method according to claim 1 , wherein the peak distortion analysis includes a peak distortion analysis of a clock signal.

8. A computer-readable recording medium comprising a computer program, causing a computer to execute the eye diagram index analysis method according to any one of claims 1 to 7 after executing the computer program.

9. An electronic device comprising a processor and a storage component, wherein the storage component stores a computer program, so that the processor executes the eye diagram indicator analysis method according to any one of claims 1 to 7 after executing the computer program. 10 . The electronic device as claimed in claim 9 , further comprising an input / output interface for receiving circuit parameters and outputting an eye diagram calculated using the eye diagram indicator analysis method.

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