A method and system for mitigating non-volatile memory write interference based on block selection

Abstract

This invention discloses a method and system for mitigating write interference in non-volatile memory based on block selection. It stores the model and metadata required for block selection on traditional DRAM memory, utilizes the characteristics of write interference to process and classify old data, and selects appropriate write locations for new data to be written to reduce write interference errors. A write interference tendency vector extraction technique can abstract the maximum number of write interference errors when each bit of old data is written. An old data block classification technique uses a clustering algorithm to group old data blocks with similar write interference tendencies into the same category. A write category selection technique first extracts an attack vector for new data based on whether each bit will cause a write interference error during writing, and then uses the attack vector to select the old data category. An intra-category write location selection technique uses a hash algorithm to select the most suitable write location for new data to further reduce write interference errors.

Description

Technical Field

[0001] This invention relates to the field of non-volatile memory reliability technology, specifically to a method and system for mitigating non-volatile memory write interference based on block selection. Background Technology

[0002] As the physical limits of traditional memory technology are gradually approached, DRAM is proving inadequate to handle the rapidly increasing volume of data. Non-volatile memory (NVM), with its DRAM-like access speeds, disk-like persistence, and high storage density, offers hope for further memory expansion. However, NVM still faces the technical challenge of write interference in its applications. Write interference causes erroneous value changes in NVM cells during writing, severely impacting memory reliability and reducing access performance. Furthermore, NVM's pursuit of higher storage density through reduced cell spacing makes write interference a major obstacle to its widespread adoption. Therefore, researching and exploring effective write interference mitigation strategies is crucial to promoting the practical application of NVM in modern memory centers.

[0003] Currently, Verify and Correct (VnC) is the most commonly used error correction method to address write interference. This technology works by reading the original data from memory cells susceptible to write interference before writing data. After the write operation is complete, the data in these cells is read again and compared with the original data. If inconsistencies are found, the original data is rewritten until all memory cells contain accurate data. While VnC effectively reduces errors caused by write interference, it also introduces additional read and write operations, further widening the performance and lifespan gap between NVM and DRAM. Besides VnC, Error Correction Code (ECC) is also used to address write interference. However, ECC requires a large amount of memory to store verification information, and even with its strong error correction capabilities, it may not be able to completely correct all errors as write interference errors accumulate. Therefore, balancing error correction capability and memory usage is a key issue that ECC technology needs to address in practical applications. To address the challenges posed by traditional technologies and mitigate performance and reliability issues caused by write disturbance errors, existing research mainly focuses on the following three aspects: (1) Employing data encoding techniques to reduce the probability of data patterns that may cause write disturbance errors, thereby reducing the number of write disturbance error cells (L. Jiang, Y. Zhang, and J. Yang. Mitigating write disturbance in superdense phase change memories. In DSN, 2014; R. Wang, L. Jiang, Y. Zhang, L. Wang, and J. Yang. Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory. In DAC, 2015; MK Tavana and D. Kaeli. Cost-effective write disturbance mitigation techniques for advancing pcm density. In ICCAD, 2017; M. Imran, T. Kwon, and J. Yang. Effective write disturbance mitigation encoding scheme for high-density pcm. In DATE, 2020; M. Imran, T. Kwon, NA Touba, and J.-S. Yang.(1) Cent: An efficient architecture to eliminate intra-array write disturbance in pcm. IEEE Transactions on Computers, 2021); (2) By optimizing the verification method, the error correction overhead of write disturbance errors can be masked, reducing the impact on write performance (R. Wang, L. Jiang, Y. Zhang, and J. Yang. Sd-pcm: Constructing reliable super dense phase change memory under write disturbance. In ASPLOS, 2015; S. Swami and K. Mohanram. Adam: Architecture for write disturbance mitigation inscaled phase change memory. In DATE, 2018); (3) Use page mapping or write private cache to avoid frequent writing to the same memory region, so as to avoid memory temperature rise and increase the probability of write disturbance errors (R. Wang, S. Mittal, Y. Zhang, and J. Yang. Decongest: Accelerating super-dense pcm underwrite disturbance by hot page remapping. IEEE Computer Architecture Letters, 2017; J.Jang, W.Shin, J.Choi, Y.Kim, and L.-S.Kim. Sparse-insertion write cache tomitigate write disturbance errors in phase change memory.(IEEE Transactions on Computers, 2019). Existing research typically considers mitigating write interference in the case of local updates, where new data directly overwrites the original data, making write interference errors dependent on the difference in patterns between the old and new data (i.e., the difference in RESET cell distribution). However, NVM is also deployed in large-scale storage systems, where off-site updates are more commonly used to achieve better performance, such as key-value stores, log-structured file systems, hash indexes, and split memory scenarios. Therefore, analyzing the differences in data writing and patterns in off-site write scenarios, and how to design a write interference mitigation framework based on the characteristics of off-site writes, remains a valuable challenge in the field of NVM reliability. Summary of the Invention

[0004] To address the aforementioned technical problems, this application aims to propose a non-volatile memory write interference mitigation method and system based on block selection. It stores the model and metadata required for block selection on traditional DRAM memory, utilizes the characteristics of write interference to process and classify old data, and selects an appropriate write location for new data to be written to reduce write interference errors. The write interference tendency vector extraction technique can abstract the maximum number of write interference errors when each bit of old data is written; the old data block classification technique uses a clustering algorithm to group old data blocks with similar write interference tendencies into the same category; the write category selection technique first extracts an attack vector for new data based on whether each bit will cause a write interference error during writing, and uses the attack vector to select the old data category; the intra-category write location selection technique uses a hash algorithm to select the most suitable write location for new data to further reduce write interference errors.

[0005] The technical solution of the present invention is as follows.

[0006] Firstly, a non-volatile memory write interference mitigation method based on block selection includes the following steps:

[0007] In the write interference tendency vector extraction step S1, a write interference tendency vector is generated and stored for each read old data block; the write interference tendency vector represents the number of write interference errors that may be caused when the old data block is overwritten.

[0008] In the old data block classification step S2, the write interference tendency vector of the old data block is classified based on the clustering algorithm to obtain the clustering label and divide the old data block into multiple categories. The write interference tendency distribution of each category is similar.

[0009] Step S3 for selecting the new data block write class: Extract the write interference attack vector of the new data block to be written, and select the old data class with the smallest inner product as the new data write class;

[0010] In step S4, the new data block is shuffled according to a predetermined hash function, and the hash value is obtained. The write address is then selected from the available address table based on the hash value. The available address table stores the hash value and clustering label of the old data block.

[0011] Preferably, the step S1 for extracting the writing interference tendency vector specifically includes:

[0012] S11, for available old data blocks, read them into DRAM and record their addresses in NVM;

[0013] S12, for each old data block read, check whether its writing may cause write interference errors, and generate a write interference tendency vector;

[0014] S13, set each value of the write interference tendency vector to the maximum number of write interference errors that may be caused in the same word line when each bit in the old data block is written.

[0015] Preferably, the old data block classification step S2 specifically includes:

[0016] S21, Determine the parameters of the clustering algorithm, including the number of clusters and the clustering algorithm to be selected;

[0017] S22, use the initial clustering algorithm to classify the tendency vectors of old data blocks so that old data blocks with similar write interference tendency vectors can be classified into the same class;

[0018] S23, For each class, calculate the mean of the tendency vectors of all old data blocks in that class as the basis for subsequent class selection; initialize the available data block address table, record the addresses of available old data blocks, and the class corresponding to each address.

[0019] Preferably, the new data block write class selection step S3 specifically includes:

[0020] S31, based on the characteristics of write interference, extract the write interference attack vector of the new data block to be written, that is, the bits that may cause word line write interference when writing.

[0021] S32, calculate the inner product of the write interference attack vector of the new data block and each old data class respectively, so as to represent the average number of maximum write interference errors when the new data block is written to each class;

[0022] S33: Select the old data category with the smallest inner product as the write category for the new data to probabilistically reduce write interference errors.

[0023] Preferably, the intra-class write location selection step S4 specifically includes:

[0024] S41, determine the number of hash functions to be selected, and generate a permutation function for each hash function for subsequent shuffling of data blocks;

[0025] S42, calculate the hash value of each old data block, that is, shuffle the old data block using a permutation function and set the position of its first bit 1 as its hash value;

[0026] S43, store the hash value of each old data block into the available data address table, and use it together with the category value as an index for the address;

[0027] S44, calculate the hash value of the new data block to be written, and combine it with the value of the selected category to select the old data address from the address table for writing.

[0028] Secondly, a block-selection-based non-volatile memory write interference mitigation system includes:

[0029] The write interference tendency vector extraction module is used to generate and store a write interference tendency vector for each read old data block; the write interference tendency vector represents the number of write interference errors that may be caused when the old data block is overwritten.

[0030] The old data block classification module is used to classify the write interference tendency vector of old data blocks based on the clustering algorithm, obtain cluster labels, and divide the old data blocks into multiple categories, with similar write interference tendency distributions in each category;

[0031] The new data block write class selection module is used to extract the write interference attack vector of the new data block to be written and select the old data class with the smallest inner product as the write class of the new data.

[0032] The in-class write location selection module is used to shuffle the new data block according to a predetermined hash permutation function, obtain the hash value, and select the write address from the available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) The write interference mitigation scheme based on block selection proposed in this invention can complement existing research to further reduce the number of write interference errors;

[0035] (2) The old data tendency vector extraction technology proposed in this invention utilizes the write interference characteristics to represent the maximum number of write interference errors that may be caused when an old data block is written, effectively representing the write interference tendency of the old data block.

[0036] (3) The old data block classification technology proposed in this invention can dynamically classify old data blocks with similar write interference tendencies into one category and can represent the write interference tendency distribution of each category.

[0037] (4) The write category selection technology proposed in this invention uses inner product to select the appropriate write category, which can probabilistically reduce the number of write interference errors.

[0038] (5) The intra-class address selection technology proposed in this invention uses a hash algorithm to select similar old data blocks for writing new data, which can improve the write endurance of NVM. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating the non-volatile memory write interference mitigation method based on block selection according to an embodiment of the present invention.

[0041] Figure 2 This is an example diagram of the write interference tendency vector extraction technique according to an embodiment of the present invention;

[0042] Figure 3 This is an example diagram of the old data block classification technology based on clustering algorithm according to an embodiment of the present invention;

[0043] Figure 4 This is an example diagram illustrating the selected technology for the new data block writing class in an embodiment of the present invention;

[0044] Figure 5 This is an example diagram of the hash-based intra-class write location selection technology according to an embodiment of the present invention;

[0045] Figure 6 This is an overall overview diagram of an embodiment of the present invention;

[0046] Figure 7 The simulation results of the number of write interference errors in the block selection frame according to an embodiment of the present invention are shown in the figure.

[0047] Figure 8 The simulation results of the write overhead of the block selection framework in an embodiment of the present invention are shown in the figure.

[0048] Figure 9 The simulation results of the write power consumption of the block selection framework in an embodiment of the present invention are shown in the figure.

[0049] Figure 10Simulation experiment result graph of the write latency of the block selection framework according to an embodiment of the present invention;

[0050] Figure 11 Structural block diagram of a non-volatile memory write interference mitigation system based on block selection according to an embodiment of the present invention. Detailed implementation manners

[0051] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0052] Figure 1 An embodiment of the present application provides a non-volatile memory write interference mitigation method based on block selection, including the following steps.

[0053] Write interference tendency vector extraction step S1: For each read old data block, generate a write interference tendency vector and store it; the write interference tendency vector represents the number of write interference errors that may be caused when the old data block is overwritten.

[0054] The specific implementation of the write interference tendency vector extraction step S1 is as follows.

[0055] S11: Read available old data blocks into the DRAM in the background, and record the address of each old data block at the same time.

[0056] S12: For each old data block, calculate in sequence whether a write interference error will occur when the block (l-bit data block) is written, and generate a write interference tendency vector D[i] (1 < i < l). If the old data bit value is 0, or the bit value is 1 and its two adjacent bits are both 1, then set the tendency vector corresponding to the data bit to 0, indicating that no write interference error of the same word line will be caused when the data bit is written; if the old data bit value is 1 and there is a bit 0 stored in its adjacent bits, then the tendency vector corresponding to the data bit will be set to the number of bit 1s stored around it (that is, 1 or 2).

[0057] S13: Store each tendency vector in the DRAM, that is, the maximum number of write interference errors that may be caused when each old data block is written, for subsequent classification of old data.

[0058] As shown above, step S1, the write interference tendency vector extraction, calculates the write interference tendency vector based on the characteristics of write interference. When a bit 1 in old data is overwritten by a bit 0 in new data, it may interfere with surrounding stored bits 0. Therefore, tendency vector extraction can be performed on the old data block based on this to understand the number of write interference errors that may be caused when the old data block is written. Figure 2 The diagram illustrates an example of a write interference bias vector extraction technique. For an 8-bit data block, the bit value of each data bit is multiplied by the number of surrounding 0 bits. For example, if the third bit has a value of 1 and two surrounding 0 bits, the corresponding bias vector is set to 2. This process is repeated to extract the bias vector value for each bit.

[0059] In the old data block classification step S2, the write interference tendency vector of the old data block is classified based on the clustering algorithm to obtain the clustering label, and the old data block is divided into multiple categories, with similar write interference tendency distributions in each category.

[0060] The specific implementation of step S2, which classifies old data blocks, is as follows.

[0061] S21. Select a suitable clustering algorithm and choose parameters based on the characteristics of the algorithm. For example, if the K-means algorithm is selected, it is necessary to determine the number of categories the data will be divided into, the number of iterations during training, and other parameters.

[0062] S22, when performing clustering of old data blocks, firstly, k tendency vectors extracted from the old data blocks in S12 are randomly selected as cluster centers, and all tendency vectors are used as input to train the clustering algorithm. In each iteration, the mean of the tendency vectors contained in each class is used as the new cluster center. The iteration continues until the cluster centers no longer change or the upper limit of the number of iterations is reached.

[0063] S23. After clustering is completed, obtain the label of each tendency vector, that is, the number of the class to which it is divided, and initialize the available address table based on the clustering label and the corresponding address to represent the class where each old data address is located.

[0064] In the new data block write class selection step S3, the write interference attack vector of the new data block to be written is extracted, and the old data class with the smallest inner product is selected as the new data write class.

[0065] As shown above, the old data block classification step S2 is responsible for classifying the old data blocks into categories. Based on the previously obtained write interference tendency vector, the old data blocks can be divided into multiple categories, ensuring that the write interference tendency distribution is similar across each category, thus facilitating the rapid selection of write blocks. Figure 3The example shown illustrates clustering of old data blocks. To divide the tendency vectors of five old data blocks into two classes, the first and fourth blocks are selected as cluster centers. The Euclidean distance from each tendency vector to the two cluster centers is calculated, and the class with the smallest Euclidean distance is selected. After iteration, the cluster centers are updated to the mean of all vectors in the class. Further iterations show no change in the cluster centers, thus ending the old data clustering training.

[0066] The specific implementation of step S3, which involves selecting the class for writing new data blocks, is as follows.

[0067] S31. Since the write interference problem is caused by the RESET operation interfering with the surrounding stored idle bits 0, that is, writing 0 may affect the surrounding stored bits 0. Based on this, the attack vector A of the new data block is extracted: when the new data block has 0 bits and there are 0s in the surrounding stored data, the corresponding attack vector is set to 1; otherwise, the corresponding attack vector is set to 0.

[0068] S32, the attack vector indicates whether a write interference error will occur when new data is written, while the tendency vector indicates the number of write interference errors that may be caused when old data is overwritten. Therefore, the attack vector A of the new data and the k cluster centers C are calculated respectively. i The inner product of (1<=i<=k) represents the average number of write interference errors that may occur when new data overwrites a certain type.

[0069] S33 selects the cluster center with the smallest inner product as the final category for writing new data, in order to probabilistically reduce the number of write interference errors.

[0070] As shown above, the new data block write class selection step S3 is responsible for selecting a suitable write class for the new data. Since write interference is caused by the RESET operation interfering with the surrounding idle bits 0, if there are 0s surrounding the new data bit 0, the corresponding attack vector is set to 1. Furthermore, the inner product of the attack and bias vectors represents the average number of write interference errors for the new data write class. Figure 4 The diagram illustrates an example of extracting attack vectors and determining categories. For a new data block, if the second bit is 0 and its surrounding bits are 1, the corresponding vector value is set to 0. If the fourth bit is 0 and its surrounding bits are also 0, the corresponding vector value is set to 1, and so on, to obtain the attack tendency vector. Then, the inner product of the attack vector to each class center is calculated sequentially, and finally, category 1 is selected as the class for writing new data.

[0071] In step S4, the new data block is shuffled according to a predetermined hash function, and the hash value is obtained. The write address is then selected from the available address table based on the hash value. The available address table stores the hash value and clustering label of the old data block.

[0072] The specific implementation of step S4, which involves selecting the writing location within a class, is as follows.

[0073] S41, determine the number h of hash functions to be used, and the number of bits b occupied by each hash function. For each hash function, generate a permutation function to shuffle the data block, and store each hash function.

[0074] S42, for each old data block, shuffle the bits of the old data block using h hash functions respectively. The hash value considers the position of the first bit 1. If the first bit 1 is in the second... b If the position is less than or equal to 1, the hash value is the actual position of the first 1; otherwise, the hash value is set to 2. b .

[0075] S43, the hash value of the old data block is also stored in the available address table, and together with the cluster label, it is used as an index of the old data address in the available address table, so as to quickly locate the appropriate write position from the table.

[0076] S44: For newly written data blocks, use h hash functions to calculate hash values, and combine them with the write category determined in S33 to select appropriate old data addresses to reduce write interference errors.

[0077] As shown above, step S4, the intra-class write location selection step, is responsible for choosing a specific write location from the class. First, the new data block is shuffled according to a pre-determined hash function, and the hash value is obtained. Then, the write address is selected from the available address table based on the hash value, such as... Figure 5 The diagram illustrates an example of a hash-based write location selection technique. For a new data block B', a hash value of 2 is calculated, and it should be written to class 1. Therefore, a data address with class 1 and hash value 2 is selected from the table for writing to find a more similar older data block.

[0078] In summary, the core of this invention is to utilize the discovery that appropriate write block selection can mitigate write interference errors, and to achieve highly reliable and high-performance NVM memory based on the characteristics of clustering algorithms and block selection.

[0079] The prototype system structure implemented by this invention is as follows: Figure 6 As shown, it includes a write interference tendency vector extraction step, an old data block classification step based on a clustering algorithm, a new data block write class selection step, and a hash-based intra-class write location selection step. The write interference tendency vector extraction step extracts the write interference tendency distribution of the old data. The old data block classification step based on a clustering algorithm divides old data blocks with similar write interference tendencies into the same class. The new data block write class selection step uses the inner product of the attack vector and the tendency vector to select a suitable write class for the new data. The hash-based intra-class write location selection module uses locality hashing to select the most similar old data block for writing to the new data.

[0080] The performance testing process and results of this invention are given below.

[0081] The simulation experiments of this invention used 15 real datasets from the UCI Machine Learning Database and the Kaggle Database, covering data types such as text, multimedia, and numerical data. The NVM data block size was set to 512-bit, and a 128-bit parallel write method was considered. The simulation used 9.9% and 11.5% to evaluate the write interference error rate of word lines and bit lines, respectively, and set the write power consumption of RESET and SET operations to 0.013733nJ / bit and 0.0268nJ / bit, respectively, and the write latency to 100ns / time and 200ns / time, respectively. In addition, the read operation latency and power consumption were set to 100ns / time and 1.075nJ / cache line, respectively. Since this scheme is complementary to the existing coding scheme, the experimental comparison scheme is (1) RandSel, which randomly selects an old data block from the available old data blocks for writing; (2) LearnWD, which represents the combination of the modules of this invention. To verify complementarity, the above two schemes were combined with the following encoding schemes: (1) DCW, which reads old data in advance and only writes the change bits between new and old data to reduce bit flips; (2) DIN, which uses an extended encoding scheme based on FPC to mitigate write interference and adds a 20-bit BCH code to protect the encoded data; (3) DMPart, which selects the data pattern with the lowest frequency as the mask pattern for data encoding to reduce the number of data patterns with consecutive 0s to mitigate write interference errors; and (4) MinWD, which uses level-shift (i.e., moving every 2 bits of the data pattern) to minimize the number of victim cells and the number of bit flips. To track the writes to the dataset, 50,000 blocks were first selected from each dataset as old data blocks, and their addresses were recorded in the available address table. Then, data was extracted from the dataset to simulate another 50,000 write requests. Only write access operations were considered, and the number of write interference errors, write overhead, write power consumption, and write latency were considered separately.

[0082] 1. Simulation test of the number of memory write interference errors.

[0083] The write interference error simulation test used 15 datasets to evaluate the number of write interference errors of the present invention and other comparative systems under different data. The test results are as follows: Figure 7As shown, when combined with four representative data encoding methods, LearnWD further reduces the number of write interference errors by 9.5-31.2% across different datasets compared to RandSel. Specifically, when deployed on top of DCW, DIN, DMPart, and MinWD, LearnWD can further reduce write interference errors by an average of 31.2%, 28.4%, 9.5%, and 11.1%, respectively. This indicates that LearnWD is complementary to existing encoding mechanisms and can help them further reduce the number of write interference errors.

[0084] 2. Memory write overhead simulation test.

[0085] The memory write overhead simulation test used 15 datasets, where the write overhead was set such that the cost of two RESET operations was equal to the cost of one SET operation. The test evaluated the write overhead of this invention and other comparative systems under different datasets. The test results are as follows: Figure 8 As shown, when deployed using existing data encoding methods, LearnWD will further reduce write overhead by 21.9%.

[0086] 3. Memory write power consumption simulation test.

[0087] The memory write power consumption simulation test used 15 datasets to evaluate the write power consumption of the present invention and other comparative systems under different benchmarks. The simulation results are as follows: Figure 9 As shown, the results for the same dataset are presented as the average. Because LearnWD reduces the number of write interference errors and write overhead, it reduces the power consumption required for verification and writing. Experimental results show that when combined with DCW, DIN, DMPart, and MinWD, LearnWD reduces write power consumption by an average of 15.6%, 13.4%, 4.5%, and 7.8%, respectively.

[0088] 4. Memory write latency simulation test.

[0089] The memory write latency simulation test used 15 datasets to evaluate the write latency of the present invention and other comparative systems under different benchmarks. The simulation results are as follows: Figure 10 As shown, the results for datasets of the same type are presented as the average. For different data types, when deploying DCW, DIN, DMPart, and MinWD simultaneously, LearnWD further reduces write latency by an average of 16.4%, 14.3%, 5.2%, and 8.1% compared to RandSel. This is because LearnWD effectively reduces the number of verifications required to ensure data reliability.

[0090] This invention leverages write block selection to reduce the detection of write interference errors and proposes a write interference mitigation framework based on machine learning and off-site write methods (where block selection is used in off-site write scenarios; clustering algorithm is a machine learning algorithm). Existing write interference mitigation schemes typically only consider local write scenarios and do not consider reducing write interference errors by selecting the write location. This invention utilizes the characteristics of write interference to propose an effective write block selection mechanism that can combine with existing encoding mechanisms to further reduce write interference errors and optimize the access performance and lifespan of NVM memory.

[0091] Further as Figure 11 As shown in the figures above, this application provides an embodiment of a non-volatile memory write interference mitigation system based on block selection, which is similar to... Figure 1 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0092] This application provides a non-volatile memory write interference mitigation system based on block selection, including:

[0093] The write interference tendency vector extraction module 1101 is used to generate and store a write interference tendency vector for each read old data block; the write interference tendency vector represents the number of write interference errors that may be caused when the old data block is overwritten.

[0094] The old data block classification module 1102 is used to classify the write interference tendency vector of old data blocks based on the clustering algorithm, obtain cluster labels, divide the old data blocks into multiple categories, and the write interference tendency distribution of each category is similar.

[0095] The new data block write class selection module 1103 is used to extract the write interference attack vector of the new data block to be written and select the old data class with the smallest inner product as the write class of the new data.

[0096] The in-class write location selection module 1104 is used to shuffle the new data block according to a predetermined hash permutation function, obtain the hash value, and select the write address from the available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

[0097] The specific implementation of each module of a block selection-based non-volatile memory write interference mitigation system is the same as the block selection-based non-volatile memory write interference mitigation method, and will not be described again in this embodiment.

[0098] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for mitigating non-volatile memory write interference based on block selection, characterized in that, Includes the following steps: In the write interference tendency vector extraction step S1, a write interference tendency vector is generated and stored for each read old data block; the write interference tendency vector represents the number of write interference errors that may be caused when the old data block is overwritten. In the old data block classification step S2, the write interference tendency vector of the old data block is classified based on the clustering algorithm to obtain the clustering label and divide the old data block into multiple categories. The write interference tendency distribution of each category is similar. Step S3 for selecting the new data block write class: Extract the write interference attack vector of the new data block to be written, and select the old data class with the smallest inner product as the new data write class; In step S4, the new data block is shuffled according to a predetermined hash function, the hash value is obtained, and the write address is selected from the available address table according to the hash value. The available address table stores the hash values ​​and clustering labels of old data blocks; The new data block write class selection step S3 specifically includes: S31, based on the characteristics of write interference, extract the write interference attack vector of the new data block to be written, that is, the bits that may cause word line write interference when writing. S32, calculate the inner product of the write interference attack vector of the new data block and each old data class respectively, so as to represent the average number of maximum write interference errors when the new data block is written to each class; S33, select the old data category with the smallest inner product as the write category of the new data to probabilistically reduce write interference errors; The intra-class write location selection step S4 specifically includes: S41, determine the number of hash functions to be used, and generate a permutation function for each hash function for subsequent shuffling of data blocks; S42, calculate the hash value of each old data block, that is, shuffle the old data block using a permutation function and set the position of its first bit 1 as its hash value; S43, store the hash value of each old data block into the available data address table, and use it together with the category value as an index for the address; S44, calculate the hash value of the new data block to be written, and combine it with the value of the selected category to select the old data address from the address table for writing.

2. The method for mitigating non-volatile memory write interference based on block selection according to claim 1, characterized in that, The step S1 for extracting the writing interference tendency vector specifically includes: S11, for available old data blocks, read them into DRAM and record their addresses in NVM; S12, for each old data block read, check whether its writing may cause write interference errors, and generate a write interference tendency vector; S13, set each value of the write interference tendency vector to the maximum number of write interference errors that may be caused in the same word line when each bit in the old data block is written.

3. The method for mitigating non-volatile memory write interference based on block selection according to claim 1, characterized in that, The old data block classification step S2 specifically includes: S21, Determine the parameters of the clustering algorithm, including the number of clusters and the clustering algorithm to be selected; S22, use the initial clustering algorithm to classify the tendency vectors of old data blocks so that old data blocks with similar write interference tendency vectors can be classified into the same class; S23, For each class, calculate the mean of the tendency vectors of all old data blocks in that class as the basis for subsequent class selection; initialize the available data block address table, record the addresses of available old data blocks, and the class corresponding to each address.

4. A non-volatile memory write interference mitigation system based on block selection, characterized in that, The method based on any one of claims 1 to 3 includes: The write interference tendency vector extraction module is used to generate and store a write interference tendency vector for each read old data block; the write interference tendency vector represents the number of write interference errors that may be caused when the old data block is overwritten. The old data block classification module is used to classify the write interference tendency vector of old data blocks based on the clustering algorithm, obtain cluster labels, and divide the old data blocks into multiple categories, with similar write interference tendency distributions in each category; The new data block write class selection module is used to extract the write interference attack vector of the new data block to be written and select the old data class with the smallest inner product as the write class of the new data. The in-class write location selection module is used to shuffle the new data block according to a predetermined hash permutation function, obtain the hash value, and select the write address from the available address table according to the hash value; the available address table stores the hash value and clustering label of the old data block.

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