Data prefetching method and device

Abstract

The invention provides a data prefetching method and device. The data prefetching method comprises the steps that parameters of a read request for a storage device in a prefetching time window are obtained, and the parameters of the read request comprise features of the read request and logic block address information of the read request; according to the characteristics of the read requests, determining the prefetch number of subsequent read requests for the storage device; according to the logic block address information of the read request, determining the prefetch heap block addresses of the prefetch quantity of the subsequent read request; and pre-fetching the data of the pre-fetching heap block addresses of the storage device according to the pre-fetching number.

Description

Technical Field

[0001] The present disclosure relates to the fields of artificial intelligence and computer storage technology. More specifically, the present disclosure relates to a data pre-fetching method and device. Background Art

[0002] In order to improve the efficiency of data reading, there are many caches in each level of the system. In order to improve the cache hit rate, various pre-fetching technologies are further adopted. The existing pre-fetching technologies can be roughly divided into two types: one is rule-based pre-fetching technology, such as time-based and space-based; the other is machine learning-based pre-fetching technology. However, both technologies have their own shortcomings. Although the rule-based pre-fetching technology is simple and easy to implement, the accuracy of pre-fetching is relatively low. Although the accuracy of pre-fetching based on machine learning technology is greatly improved compared with the rule-based pre-fetching technology, it is very troublesome and limited to implement because the machine learning algorithm requires a lot of storage resources and computing resources. With the development of new devices, in order to accelerate the device, caches have been deployed on the device side. How to improve the hit rate of such caches has become an urgent problem to be solved.

[0003] The Compute Express Link (CXL) interface is an open standard for high-speed, high-capacity connections between processors and memory. Memory semantics (MS)-Solid State Disk (SSD) is a new type of storage device or equipment developed using the Compute Express Link interface. The Memory semantics-SSD is equipped with a large-capacity NAND flash memory and a corresponding capacity of Dynamic Random Access Memory (DRAM). Through the Compute Express Link interface, the Memory semantics-SSD can be used in three modes: high-performance mode, persistent memory mode, and tiered memory mode, which are suitable for different application scenarios.

[0004] In high-performance mode, the dynamic random access memory (DRAM) can be used as a cache for the underlying NAND flash memory, and block-based write requests can be sent to the memory semantics-SSD through the CXL.IO interface. Byte-based read requests can be sent to the memory semantics-SSD through the CXL.MEM interface. At this time, the read request can first determine whether the data is in the dynamic random access memory cache (DRAM Cache). If the cache hits, the data is directly returned, thereby improving the processing speed of the read request and reducing the delay.

[0005] Rule-based prefetching technology can be simply divided into two categories: one is based on time rules, and the other is based on space rules. The premise of time rule-based prefetching is that the data access of the application has a high time correlation. For example, based on the principle of temporal locality, the data to be accessed can be the data currently being accessed. For such applications, time prefetching technology can be used to prefetch data into the cache. The premise of spatial rule-based prefetching is that applications widely use data objects with regular and fixed layouts, which leads to repeated access patterns on memory areas. Spatial data prefetching technology uses this phenomenon to prefetch future memory references and hide the long latency of NAND flash access. Although rule-based prefetching technology is simple and easy to implement, the accuracy of prefetching is not good, only 9% to 76%.

[0006] There is a machine learning-based prefetching technology that treats prefetching as a classification problem of sequence prediction. The machine learning-based prefetching technology uses fine-grained address segments as input to reduce the vocabulary size and uses incremental bitmaps for multiple outputs to predict a set of unordered future addresses. The machine learning-based prefetching technology uses an attention-based network to learn the relationship between the input and output of the mapping. Although the machine learning-based prefetching technology can improve the accuracy of prefetching, it is very demanding on computing resources.

[0007] In summary, the above two prefetching technologies are not suitable for use in memory semantics-SSDs. It is necessary to find a prefetching technology that has low computing resource requirements and high cache hit rate. Summary of the invention

[0008] An exemplary embodiment of the present disclosure is to provide a data pre-fetching method and device to provide a pre-fetching technology with low requirements on computing resources and high cache hit rate.

[0009] According to an exemplary embodiment of the present disclosure, there is provided a data prefetching method, comprising: obtaining parameters of a read request for a storage device within a prefetch time window, wherein the parameters of the read request include at least characteristics of the read request and logical block address information of the read request; determining a prefetch quantity of subsequent read requests for the storage device based on the characteristics of the read request; determining a prefetch quantity of prefetch stack block addresses of the subsequent read requests based on the logical block address information of the read request; and prefetching data of the prefetch quantity of the prefetch stack block addresses of the storage device.

[0010] Optionally, the parameters of the read request may also include heat information of the read request, wherein the step of determining the prefetch quantity and prefetch stack block addresses of the subsequent read request may include: predicting the attribute of the subsequent read request based on the logical block address information of the read request; based on the prediction that the attribute of the subsequent read request is the first attribute, predicting the prefetch quantity and prefetch stack block addresses of the subsequent read request by inputting the heat information of the read request into a heat prediction model.

[0011] Optionally, the step of predicting the pre-fetch quantity of pre-fetched heap block addresses of the subsequent read request by inputting the heat information of the read request into the heat prediction model may include: predicting the heat of each heap block address of the storage device at the next moment by inputting the heat information of the read request into the heat prediction model; sorting the heap block addresses of the storage device in descending order based on the heat at the next moment; and taking the pre-fetch quantity of heap block addresses with the highest heat among the heap block addresses of the storage device as the pre-fetched heap block addresses.

[0012] Optionally, the step of determining the prefetch quantity of prefetch stack block addresses for the subsequent read request may further include: based on predicting that the attribute of the subsequent read request is the second attribute, determining the prefetch quantity of prefetch stack block addresses based on the subsequent logical block address of the logical block address information.

[0013] Optionally, the data prefetching method may further include: determining a prefetching frequency for subsequent read requests for the storage device based on characteristics of the read request, wherein the step of prefetching data of the prefetching number of the prefetching stack block addresses may include: prefetching data of the prefetching number of the prefetching stack block addresses of the storage device based on the prefetching frequency.

[0014] Optionally, the heat prediction model may be trained by using the heat of read requests to the storage device within a preset time period as training data.

[0015] According to an exemplary embodiment of the present disclosure, there is provided a data prefetching device, comprising: a parameter acquiring unit, configured to acquire parameters of a read request for a storage device within a prefetching time window, wherein the parameters of the read request include at least characteristics of the read request and logical block address information of the read request; a quantity determining unit, configured to determine the prefetch quantity of subsequent read requests for the storage device according to the characteristics of the read request; a prefetch address determining unit, configured to determine the prefetch quantity of prefetch stack block addresses of the subsequent read request according to the logical block address information of the read request; and a data prefetching unit, configured to prefetch data of the prefetch quantity of the prefetch stack block addresses of the storage device.

[0016] Optionally, the parameters of the read request may also include heat information of the read request, wherein the prefetch address determination unit may be configured to: predict the attribute of the subsequent read request based on the logical block address information of the read request; based on the prediction that the attribute of the subsequent read request is the first attribute, predict the prefetch quantity of prefetch stack block addresses of the subsequent read request by inputting the heat information of the read request into a heat prediction model.

[0017] Optionally, the prefetch address determination unit can also be configured to: predict the heat of each stack block address of the storage device at the next moment by inputting the heat information of the read request into the heat prediction model; sort the stack block addresses of the storage device in descending order based on the size of the heat at the next moment; and use the prefetch number of stack block addresses with the largest heat among the stack block addresses of the storage device as the prefetch stack block addresses.

[0018] Optionally, the prefetch address determination unit may be further configured to: based on predicting that the attribute of the subsequent read request is the second attribute, determine the prefetch quantity of prefetch heap block addresses based on the subsequent logical block address of the logical block address information.

[0019] Optionally, the data prefetch device may further include: a prefetch frequency determination unit, configured to determine the prefetch frequency of subsequent read requests for the storage device based on the characteristics of the read request, wherein the data prefetch unit may be configured to: prefetch data of the prefetch quantity of the prefetch stack block addresses of the storage device based on the prefetch frequency.

[0020] Optionally, the heat prediction model may be trained by using the heat of read requests to the storage device within a preset time period as training data.

[0021] According to an exemplary embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the data prefetching method according to the exemplary embodiment of the present disclosure is implemented.

[0022] According to an exemplary embodiment of the present disclosure, a computing device is provided, including: at least one processor; and at least one memory storing a computer program, wherein when the computer program is executed by the at least one processor, a data prefetching method according to an exemplary embodiment of the present disclosure is implemented.

[0023] According to an exemplary embodiment of the present disclosure, a computer program product is provided, and instructions in the computer program product can be executed by a processor of a computer device to implement a data prefetching method according to an exemplary embodiment of the present disclosure.

[0024] According to an exemplary embodiment of the present disclosure, a host is provided, including: a memory storing instructions, and a processor, wherein when the instructions are executed by the processor, a data prefetching method according to an exemplary embodiment of the present disclosure is implemented.

[0025] According to an exemplary embodiment of the present disclosure, there is provided a system to which a storage device is applied, including: a main processor; a memory; and the storage device, wherein the main processor is configured to execute a data pre-fetching method according to an exemplary embodiment of the present disclosure.

[0026] According to an exemplary embodiment of the present disclosure, a host storage system is provided, including: a host; and a storage device, wherein the host is configured to execute a data pre-fetching method according to an exemplary embodiment of the present disclosure.

[0027] According to an exemplary embodiment of the present disclosure, a data center system is provided, comprising: a plurality of application servers; and a plurality of storage servers, wherein each storage server comprises a storage device, wherein each of the plurality of application servers is configured to execute a data pre-fetching method according to an exemplary embodiment of the present disclosure.

[0028] According to the data prefetching method and device of the exemplary embodiments of the present disclosure, by obtaining parameters of a read request for a storage device within a prefetch time window, wherein the parameters of the read request include at least characteristics of the read request and logical block address information of the read request, the prefetch quantity of subsequent read requests for the storage device is determined according to the characteristics of the read request, and the prefetch quantity and prefetch stack block addresses of the subsequent read requests are determined according to the logical block address information of the read request, and data of the prefetch quantity and the prefetch stack block addresses of the storage device are prefetched, thereby improving the cache hit rate without increasing computing resources.

[0029] Additional aspects and / or advantages of the present general inventive concept will be set forth in part in the following description and in part will be apparent from the description or may be learned through practice of the present general inventive concept. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects and features of the exemplary embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings which exemplarily illustrate the embodiments, in which:

[0031] Figure 1 A flow chart showing a data pre-fetching method according to an exemplary embodiment of the present disclosure;

[0032] Figure 2 A schematic diagram showing a data pre-fetching system according to an exemplary embodiment of the present disclosure;

[0033] Figure 3 A block diagram showing a data pre-fetching apparatus according to an exemplary embodiment of the present disclosure; and

[0034] Figure 4 A schematic diagram showing a computing device according to an exemplary embodiment of the present disclosure;

[0035] Figure 5 is a schematic diagram illustrating a system to which a storage device is applied according to an exemplary embodiment of the present disclosure;

[0036] Figure 6 is a block diagram illustrating a host storage system according to an exemplary embodiment of the present disclosure;

[0037] Figure 7 is a diagram illustrating a data center to which a storage device is applied according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein like reference numerals refer to like parts throughout. The embodiments will be described below with reference to the drawings in order to explain the present disclosure.

[0039] Figure 1 A flow chart of a data prefetching method according to an exemplary embodiment of the present disclosure is shown. Figure 2 A schematic diagram showing a data prefetching system according to an exemplary embodiment of the present disclosure is shown.

[0040] Reference Figure 1 In step S101, parameters of a read request for a storage device within a pre-fetch time window are obtained. Here, the parameters of the read request may at least include characteristics of the read request and logical block address (LBA) information of the read request.

[0041] In an exemplary embodiment of the present disclosure, the parameters of the read request may further include heat information of the read request.

[0042] Specifically, if Figure 2As shown, the input / output (IO) capture module can be used to collect read requests using a predetermined interface (for example, but not limited to the CXL.MEM interface) in a pre-fetch time window with chunks as the granularity, and obtain parameters such as the features, logical block address information, and heat information of these collected read requests. The selection of features can use a correlation analysis algorithm, and the heat of a chunk is represented by the number of read requests falling within the chunk. In an exemplary embodiment of the present disclosure, the features of a read request may include, for example, but not limited to, the size of the read request, the read / write type, the number, the number of bytes, the read / write ratio, the bandwidth, the throughput, etc.

[0043] In step S102 , the pre-fetch quantity for subsequent read requests of the storage device is determined according to the characteristics of the read request.

[0044] In an exemplary embodiment of the present disclosure, the method may further include: determining a prefetch frequency for subsequent read requests to the storage device according to the characteristics of the read request, thereby dynamically adjusting the prefetch frequency and the prefetch quantity to suit various workloads. In addition, the data prefetch method according to the exemplary embodiment of the present disclosure can be applied to most scenarios without modification through the dynamic adaptive parameter adjustment function.

[0045] As an example, Figure 2 As shown, through the input and output monitoring module (ie, Figure 2 The IO monitoring module in the prefetch time window) monitors the input / output intensity (the total input / output size within the prefetch time window) and the input / output density (the number of input / output within the prefetch time window) of the storage device. If the input / output intensity is high, the prefetch quantity is increased; if the input / output intensity is low, the prefetch quantity is reduced. If the input / output density is high, the prefetch frequency is increased; if the input / output density is low, the prefetch frequency is reduced. At the same time, the input / output monitoring module (i.e., Figure 2 The IO monitoring module in the storage device) transmits the pre-fetch quantity and pre-fetch frequency to the input and output analysis module, and transmits the pre-fetch quantity to the sending module. The pre-fetch quantity is used to guide the pre-fetch request to pre-fetch how many heap block data from the flash memory (e.g., NAND flash memory) of the storage device to the dynamic random access memory cache (DRAM Cache) each time, so as to use different pre-fetch strategies for different types of workloads to achieve the purpose of reducing power consumption and avoiding resource waste.

[0046] In step S103, the pre-fetch quantity and the pre-fetch stack block addresses of the subsequent read requests are determined according to the logical block address information of the read request.

[0047] In an exemplary embodiment of the present disclosure, the step of determining the prefetch quantity and prefetch stack block addresses of a subsequent read request may include: predicting the attribute of the subsequent read request based on the logical block address information of the read request; based on the prediction that the attribute of the subsequent read request is the first attribute, predicting the prefetch quantity and prefetch stack block addresses of the subsequent read request by inputting the heat information of the read request into the heat prediction model, thereby determining the prefetch stack block address based on the predicted heat. Here, the attribute of the subsequent read request may be a sequential attribute or a random attribute, that is, whether the subsequent read request is sequential or random. For example, the first attribute may be a random attribute.

[0048] In an exemplary embodiment of the present disclosure, the step of determining the pre-fetch quantity of the pre-fetched heap block addresses of the subsequent read request may further include: based on the prediction that the attribute of the subsequent read request is the second attribute, determining the pre-fetch quantity of the pre-fetched heap block addresses based on the logical block address information and the subsequent logical block address, thereby determining the pre-fetched heap block addresses based on the order of the logical block addresses. For example, the second attribute may be an order attribute.

[0049] As an example, Figure 2 As shown, through the input-output analysis module (i.e., Figure 2 The IO analysis module in the IO capture module predicts whether the subsequent read request is sequential or random based on the logical block address information of the read request. If it is sequential, the subsequent heap block address is directly sent to the storage device (e.g., memory semantic-solid state drive (MS-SSD)) in the form of a pre-fetch request; if it is random, a request is sent to the input and output capture module to start the predictor to predict the heap block address to be pre-fetched.

[0050] In an exemplary embodiment of the present disclosure, the step of predicting the pre-fetch quantity of pre-fetched heap block addresses of subsequent read requests by inputting the heat information of the read request into the heat prediction model may include: predicting the heat of each heap block address of the storage device at the next moment by inputting the heat information of the read request into the heat prediction model; sorting the heap block addresses of the storage device in descending order based on the size of the heat at the next moment; and taking the pre-fetch quantity of heap block addresses with the largest heat among the heap block addresses of the storage device as the pre-fetched heap block addresses, thereby improving the accuracy of the pre-fetched heap block addresses to improve the pre-fetching precision.

[0051] In an exemplary embodiment of the present disclosure, the heat prediction model may be trained by using the heat of read requests to the storage device within a preset time period as training data.

[0052] As an example, Figure 2 As shown, through the predictor module (i.e., Figure 2 The predictor in ) uses an input-output capture module (i.e., Figure 2First, the input and output capture module collects the read requests (i.e., workload data) of the storage device over a period of time, selects the characteristics and heat information of the read requests, and trains the heat prediction model (i.e., Figure 2 Then, using the heat prediction model (i.e., Figure 2 The predictor in ( ) predicts the heat of each heap block at the next moment.

[0053] In step S104, data of a prefetch number of prefetched heap block addresses of the storage device are prefetched.

[0054] In an exemplary embodiment of the present disclosure, the step of prefetching data of a prefetch number of prefetch stack block addresses may include: prefetching data of a prefetch number of prefetch stack block addresses of a storage device based on a prefetch frequency, thereby improving read performance and reducing read latency.

[0055] As an example, Figure 2 As shown, through the transmitter module (ie, Figure 2 The sender in the memory module selects the hottest pre-fetch number of heap blocks from the heap block heats predicted by the predictor module. These heap block addresses are sent to the storage device (e.g., memory semantics-solid state drive (MS-SSD)) in the form of pre-fetch requests through a predetermined interface (e.g., but not limited to the CXL.IO interface). The pre-fetch controller of the storage device (e.g., memory semantics-solid state drive (MS-SSD)) processes the pre-fetch request and copies the data from the NAND flash memory of the storage device to the dynamic random access memory cache (DRAM Cache).

[0056] The above has been combined Figure 1 and Figure 2 A data prefetching method according to an exemplary embodiment of the present disclosure is described. Figure 3 A data pre-fetching apparatus and units thereof according to an exemplary embodiment of the present disclosure are described.

[0057] Figure 3 A block diagram showing a data pre-fetching apparatus according to an exemplary embodiment of the present disclosure is shown.

[0058] Reference Figure 3 The data pre-fetching device includes a parameter obtaining unit 31, a quantity determining unit 32, a pre-fetching address determining unit 33 and a data pre-fetching unit 34.

[0059] The parameter acquisition unit 31 is configured to acquire parameters of a read request for a storage device within a pre-fetch time window. Here, the parameters of the read request may at least include characteristics of the read request and logical block address information of the read request.

[0060] In an exemplary embodiment of the present disclosure, the parameters of the read request may further include heat information of the read request.

[0061] The number determination unit 32 is configured to determine the prefetch number of subsequent read requests for the storage device according to the characteristics of the read request.

[0062] In an exemplary embodiment of the present disclosure, the data pre-fetching device may further include: a pre-fetching frequency determining unit (not shown) configured to determine a pre-fetching frequency of subsequent read requests for the storage device according to the characteristics of the read request.

[0063] The prefetch address determination unit 33 is configured to determine the prefetch quantity of prefetch stack block addresses of the subsequent read request according to the logical block address information of the read request.

[0064] In an exemplary embodiment of the present disclosure, when the parameters of a read request also include heat information of the read request, the prefetch address determination unit 33 may be configured to: predict the attribute of the subsequent read request based on the logical block address information of the read request; based on the prediction that the attribute of the subsequent read request is the first attribute, predict the prefetch quantity of prefetch stack block addresses of the subsequent read request by inputting the heat information of the read request into a heat prediction model.

[0065] In an exemplary embodiment of the present disclosure, the prefetch address determination unit 33 may also be configured to: predict the heat of each stack block address of the storage device at the next moment by inputting the heat information of the read request into the heat prediction model; sort the stack block addresses of the storage device in descending order based on the heat at the next moment; and use the prefetched number of stack block addresses with the largest heat among the stack block addresses of the storage device as the prefetched stack block addresses.

[0066] In an exemplary embodiment of the present disclosure, the heat prediction model may be trained by using the heat of read requests to the storage device within a preset time period as training data.

[0067] In an exemplary embodiment of the present disclosure, the prefetch address determination unit 33 may also be configured to: based on predicting that the attribute of the subsequent read request is the second attribute, determine the prefetch quantity of prefetch stack block addresses based on the subsequent logical block address of the logical block address information.

[0068] The data pre-fetch unit 34 is configured to pre-fetch data of the pre-fetch number of the pre-fetched heap block addresses of the storage device.

[0069] In an exemplary embodiment of the present disclosure, when the data prefetch device includes a prefetch frequency determination unit, the data prefetch unit 34 may be configured to prefetch data of the prefetch number of the prefetch stack block addresses of the storage device based on the prefetch frequency.

[0070] In addition, according to an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium on which a computer program is stored. When the computer program is executed, the data prefetching method according to the exemplary embodiment of the present disclosure is implemented.

[0071] In an exemplary embodiment of the present disclosure, the computer-readable storage medium may carry one or more programs, and when the computer program is executed, the following steps may be implemented: obtaining parameters of a read request for a storage device within a prefetch time window, wherein the parameters of the read request include characteristics of the read request and logical block address information of the read request; determining a prefetch quantity of subsequent read requests for the storage device based on the characteristics of the read request; determining a prefetch quantity of prefetch stack block addresses of the subsequent read requests based on the logical block address information of the read request; and prefetching data of the prefetch quantity of the prefetch stack block addresses of the storage device.

[0072] The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In an embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a computer program that may be used by or in conjunction with an instruction execution system, device or device. The computer program contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof. The computer-readable storage medium may be contained in any device; it may also exist alone without being assembled into the device.

[0073] In addition, according to an exemplary embodiment of the present disclosure, a computer program product is also provided. Instructions in the computer program product can be executed by a processor of a computer device to implement the data prefetching method according to an exemplary embodiment of the present disclosure.

[0074] The above has been combined Figure 3The data pre-fetching device according to the exemplary embodiment of the present disclosure is described. Figure 4 A computing device according to an exemplary embodiment of the present disclosure is described.

[0075] Figure 4 A schematic diagram illustrating a computing device according to an exemplary embodiment of the present disclosure.

[0076] Reference Figure 4 According to the exemplary embodiment of the present disclosure, the computing device 4 includes a memory 41 and a processor 42. The memory 41 stores a computer program. When the computer program is executed by the processor 42, the data prefetching method according to the exemplary embodiment of the present disclosure is implemented.

[0077] In an exemplary embodiment of the present disclosure, when the computer program is executed by the processor 42, the following steps can be implemented: obtaining parameters of a read request for a storage device within a prefetch time window, wherein the parameters of the read request include characteristics of the read request and logical block address information of the read request; determining a prefetch quantity of subsequent read requests for the storage device based on the characteristics of the read request; determining a prefetch quantity of prefetch stack block addresses of the subsequent read requests based on the logical block address information of the read request; and prefetching data of the prefetch quantity of the prefetch stack block addresses of the storage device.

[0078] The computing device in the embodiments of the present disclosure may include, but is not limited to, devices such as mobile phones, laptop computers, PDAs (personal digital assistants), PADs (tablet computers), desktop computers, and the like. Figure 4 The computing device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0079] The above has been referred to Figures 1 to 4 The data pre-fetching method and apparatus according to the exemplary embodiments of the present disclosure are described. However, it should be understood that: Figure 3 The data pre-fetching device and its units shown in the figure may be respectively configured as software, hardware, firmware or any combination of the above items to perform specific functions. Figure 4 The computing device shown in is not limited to including the components shown above, but some components may be added or deleted as needed, and the above components may also be combined.

[0080] Figure 5 is a schematic diagram illustrating a system 1000 to which a storage device is applied according to an exemplary embodiment of the present disclosure.

[0081] Figure 5The system 1000 may basically be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, Figure 5 The system 1000 is not necessarily limited to a mobile system, and may be a PC, a laptop, a server, a media player, or an automotive device (eg, a navigation device).

[0082] Reference Figure 5 , the system 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). In addition, the system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0083] The main processor 1100 may control all operations of the system 1000, and more specifically, may control operations of other components included in the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, an application processor, or the like.

[0084] The main processor 1100 may include at least one central processing unit (CPU) core 1110, and further include a controller 1120 for controlling the memories 1200a and 1200b and / or the storage devices 1300a and 1300b. In some example embodiments, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations, etc. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), etc., and is implemented as a chip physically separated from other components of the main processor 1100.

[0085] The memories 1200a and 1200b may be used as main storage devices of the system 1000. Although the memories 1200a and 1200b may include volatile memories, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), etc., the memories 1200a and 1200b may include non-volatile memories, such as flash memory, phase change random access memory (PRAM), and / or resistive random access memory (RRAM), etc. The memories 1200a and 1200b may be implemented in the same package as the main processor 1100.

[0086] The storage devices 1300a and 1300b may be used as non-volatile storage devices, which are configured to store data regardless of whether they are powered on and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include memory controllers (STRG CTRL) 1310a and 1310b and non-volatile memories (NVM) 1320a and 1320b, respectively, which are configured to store data via the control of the memory controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include V-NAND flash memories having a two-dimensional (2D) or three-dimensional (3D) structure, the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM, etc.

[0087] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the system 1000, or may be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a type of solid-state devices (SSDs) or memory cards, and may be removably combined with other components of the system 100 through an interface such as a connection interface 1480 to be described later. The storage devices 1300a and 1300b may be devices to which a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or NVMe is applied, but are not limited thereto.

[0088] The image capture device 1410 can capture still images or moving images. The image capture device 1410 may include a camera, a camcorder, and / or a webcam, etc.

[0089] The user input device 1420 may receive various types of data input by a user of the system 1000 and includes a touch pad, a keypad, a keyboard, a mouse, a microphone, and the like.

[0090] The sensor 1430 may detect various types of physical quantities that may be acquired from the outside of the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor, etc.

[0091] The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, a modem, or the like.

[0092] Display 1450 and speaker 1460 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 1000 .

[0093] The power supply device 1470 may appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000 .

[0094] The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and is capable of transmitting and receiving data to and from the system 1000. The connection interface 1480 may be implemented by using various interface schemes, for example, Advanced Technology Attachment (ATA), Serial ATA (SATA), External Serial ATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, UFS interface, Embedded UFS (eUFS) interface, Compact Flash (CF) card interface, and the like.

[0095] Figure 6 is a block diagram illustrating a host storage system 10 according to an exemplary embodiment of the present disclosure.

[0096] The host storage system 10 may include a host 100 and a storage device 200. In addition, the storage device 200 may include a memory controller 210 and an NVM 220. According to an example embodiment of the present disclosure, the host 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory configured to temporarily store data to be transmitted to or received from the storage device 200.

[0097] The storage device 200 may include a storage medium configured to store data in response to a request from the host 100. As an example, the storage device 200 may include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 may be a device that complies with the NVMe standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device that complies with the UFS standard or the eMMC standard. Both the host 100 and the storage device 200 may generate a packet and send the packet according to the adopted standard protocol.

[0098] When the NVM 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include various other types of NVM. For example, the storage device 200 may include a magnetic random access memory (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, a RRAM, and various other types of memory.

[0099] According to an example embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some example embodiments, the host controller 110 and the host memory 120 may be integrated in the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor (AP). The AP may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory included in the AP or a memory module external to the AP.

[0100] The host controller 110 may manage an operation of storing data (eg, write data) of the buffer area of ​​the host memory 120 in the NVM 220 or an operation of storing data (eg, read data) of the NVM 220 in the buffer area.

[0101] The memory controller 210 may include a host interface 211, a memory interface 212, and a CPU 213. In addition, the memory controller 210 may further include a flash translation layer (FTL), a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) engine 218. The memory controller 210 may further include a working memory (not shown) in which the FTL 214 is loaded. The CPU 213 may execute the FTL 214 to control data write and read operations on the NVM 220.

[0102] The host interface 211 may transmit and receive packets to and from the host 100. The packets transmitted from the host 100 to the host interface 211 may include commands or data to be written to the NVM 220, etc. The packets transmitted from the host interface 211 to the host 100 may include responses to commands or data read from the NVM 220, etc. The memory interface 212 may transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 212 may be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0103] The FTL 214 may perform various functions, such as an address mapping operation, a wear leveling operation, and a garbage collection operation. The address mapping operation may be an operation of converting a logical address received from the host 100 into a physical address for actually storing data in the NVM 220. The wear leveling operation may be a technique for preventing excessive degradation of a specific block by allowing the blocks of the NVM 220 to be used evenly. As an example, the wear leveling operation may be implemented by using a firmware technique that balances the erase counts of physical blocks. The garbage collection operation may be a technique for ensuring available capacity in the NVM 220 by erasing an existing block after copying valid data of the existing block to a new block.

[0104] The packet manager 215 may generate a packet according to a protocol agreed to an interface of the host 100, or parse various types of information from a packet received from the host 100. In addition, the buffer memory 216 may temporarily store data to be written to or read from the NVM 220. Although the buffer memory 216 may be a component included in the memory controller 210, the buffer memory 216 may be outside the memory controller 210.

[0105] The ECC engine 217 may perform error detection and correction operations on read data read from the NVM 220. More specifically, the ECC engine 217 may generate parity bits for write data to be written to the NVM 220, and the generated parity bits may be stored together with the write data in the NVM 220. During reading of data from the NVM 220, the ECC engine 217 may correct errors in the read data by using the read data and the parity bits read from the NVM 220, and output the error-corrected read data.

[0106] The AES engine 218 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 210 by using a symmetric key algorithm.

[0107] Figure 7 is a diagram illustrating a data center 3000 to which a storage device is applied according to an exemplary embodiment of the present disclosure.

[0108] Platform part - server (application / storage)

[0109] Reference Figure 7, the data center 3000 may be a facility that collects various types of data and provides services, and is referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used by a company (e.g., a bank) or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. According to example embodiments, the number of applications 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0110] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. Now, the storage server 3200 will be described as an example. The processor 3210 may control all operations of the storage server 3200, access the memory 3220, and execute instructions and / or data loaded into the memory 3220. The memory 3220 may be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a non-volatile DIMM (NVMDIMM). In some example embodiments, the number of processors 3210 and memories 3220 included in the storage server 3200 may be selected differently. In an example embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an example embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. In some embodiments, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. According to the embodiment, the number of storage devices 3250 included in the storage server 3200 may be selected differently.

[0111] Platform part - Network

[0112] The application servers 3100 to 3100n can communicate with the storage servers 3200 to 3200m through the network 3300. The network 3300 can be implemented by using a fiber channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission, and an optical switch with high performance and high availability can be used. According to the access method of the network 3300, the storage servers 3200 to 3200m can be set to file storage, block storage, or object storage.

[0113] In one embodiment, the network 3300 may be a network dedicated to storage, such as a storage area network (SAN). For example, the SAN may be an FC-SAN, which uses an FC network and is implemented according to the FC protocol (FCP). As another example, the SAN may be an Internet Protocol (IP)-SAN, which uses a transmission control protocol (TCP) / IP network and is implemented according to the SCSI or Internet SCSI (iSCSI) protocol over TCP / IP. In another embodiment, the network 3300 may be a general network, such as a TCP / IP network. For example, the network 3300 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), and NVMe over fabric (NVMe-oF).

[0114] Hereinafter, the application server 3100 and the storage server 3200 will be mainly described. The description of the application server 3100 may be applied to another application server 3100n, and the description of the storage server 3200 may be applied to another storage server 3200m.

[0115] The application server 3100 may store data requested to be stored by a user or client in one of the storage servers 3200 to 3200m through the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 may be implemented as a network server or a database management system (DBMS).

[0116] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n through the network 3300. Alternatively, the application server 3100 may access a memory 3220 to 3220m or a storage device 3250 to 3250m included in the storage servers 3200 to 3200m through the network 3300. Therefore, the application server 3100 may perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute an instruction for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, data may be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m through the storage 3220 to 3220m of the storage servers 3200 to 3200m or directly to the storage 3120 to 3120n of the application servers 3100 to 3100n. The data moved through the network 3300 may be data encrypted for security or privacy.

[0117] Organic Relationship-Interface Structure / Type

[0118] The storage server 3200 will now be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 can be implemented using a direct attached storage (DAS) solution, where the storage device 3250 is directly connected to a dedicated cable. For example, the interface 3254 can be implemented using various interface solutions, such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and CF card interface.

[0119] The storage server 3200 may further include a switch 3230 and a network interconnect (NIC) 3240. The switch 3230 may selectively connect the processor 3210 to the storage device 3250 or selectively connect the NIC 3240 to the storage device 3250 via the control of the processor 3210.

[0120] In one embodiment, the NIC 3240 may include a network interface card and a network adapter. The NIC 3240 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 3240 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the above examples of the interface 3254. In one embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0121] Organic Relationship-Interface Operation

[0122] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor may send a command to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m and program or read data. In this case, the data may be data in which an error is corrected by an ECC engine. The data may be data on which a data bus inversion (DBI) operation or a data masking (DM) operation is performed, and may include cyclic redundancy coding (CRC) information. The data may be data encrypted for security or privacy.

[0123] The storage devices 3150 to 3150n and 3250 to 3250m may send control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. Therefore, when data is read from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal, and thus, the data may be output to the DQ bus. The data strobe signal DQS may be generated using the RE signal. Depending on the rising edge or falling edge of the write enable (WE) signal, the command and address signals may be latched in the page buffer.

[0124] Product section - Basic operation of SSD

[0125] The controller 3251 may control all operations of the storage device 3250. In one embodiment, the controller 3251 may include an SRAM. The controller 3251 may write data to the NAND flash memory device 3252 in response to a write command, or read data from the NAND flash memory device 3252 in response to a read command. For example, a write command and / or a read command may be provided from a processor 3210 of the storage server 3200, a processor 3210m of another storage server 3200m, or processors 3110 and 3110n of application servers 3100 and 3100n. The DRAM 3253 may temporarily store (or buffer) data to be written to the NAND flash memory device 3252 or data to be read from the NAND flash memory device 3252. And, the DRAM 3253 may store metadata. Here, the metadata may be user data or data generated by the controller 3251 for managing the NAND flash memory device 3252. The storage device 3250 may include a secure element (SE) for security or privacy.

[0126] According to the data prefetching method and device of the exemplary embodiments of the present disclosure, by obtaining parameters of a read request for a storage device within a prefetch time window, wherein the parameters of the read request include at least characteristics of the read request and logical block address information of the read request, the prefetch quantity of subsequent read requests for the storage device is determined according to the characteristics of the read request, and the prefetch quantity and prefetch stack block addresses of the subsequent read requests are determined according to the logical block address information of the read request, and data of the prefetch quantity and the prefetch stack block addresses of the storage device are prefetched, thereby improving the cache hit rate without increasing computing resources.

[0127] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A data pre-fetching method, comprising: Acquire parameters of a read request for a storage device within a pre-fetch time window, wherein the parameters of the read request at least include characteristics of the read request and logical block address information of the read request; determining, based on the characteristics of the read request, a pre-fetch quantity for subsequent read requests to the storage device; Determining the pre-fetch quantity of pre-fetched heap block addresses of the subsequent read request according to the logical block address information of the read request; Prefetching data of the prefetch number of the prefetch stack block addresses of the storage device.

2. The method according to claim 1, wherein: The parameters of the read request also include the heat information of the read request. The step of determining the pre-fetch quantity of pre-fetched heap block addresses of the subsequent read request includes: predicting an attribute of the subsequent read request based on the logical block address information of the read request; Based on predicting that the attribute of the subsequent read request is the first attribute, the prefetch quantity of prefetched heap block addresses of the subsequent read request is predicted by inputting the heat information of the read request into a heat prediction model.

3. The method according to claim 2, wherein: The step of predicting the pre-fetch quantity of pre-fetched heap block addresses of the subsequent read request by inputting the heat information of the read request into a heat prediction model comprises: Predicting the heat of each heap block address of the storage device at a next moment by inputting the heat information of the read request into the heat prediction model; Sort the heap block addresses of the storage device in descending order based on the heat at the next moment; The pre-fetched number of heap block addresses with the greatest heat among the heap block addresses of the storage device are used as the pre-fetched heap block addresses.

4. The method according to claim 2, wherein: The step of determining the pre-fetch quantity of pre-fetched heap block addresses for the subsequent read request also includes: Based on predicting that the attribute of the subsequent read request is the second attribute, the pre-fetch quantity of pre-fetched heap block addresses is determined based on the subsequent logical block address of the logical block address information.

5. The method according to claim 1, further comprising: determining a prefetch frequency of subsequent read requests for the storage device according to the characteristics of the read request, The step of prefetching the data of the prefetched number of the prefetched heap block addresses comprises: Prefetching data of the prefetch number of the prefetch heap block addresses of the storage device is performed based on the prefetch frequency.

6. The method according to claim 2, wherein: The heat prediction model is trained by using the heat of read requests to the storage device within a preset time period as training data.

7. A data pre-fetching device, comprising: A parameter acquisition unit, configured to acquire parameters of a read request for a storage device within a pre-fetch time window, wherein the parameters of the read request at least include characteristics of the read request and logical block address information of the read request; a quantity determination unit configured to determine a pre-fetch quantity for subsequent read requests for the storage device according to a feature of the read request; a prefetch address determination unit configured to determine the prefetch quantity of prefetch heap block addresses of the subsequent read request according to the logical block address information of the read request; and The data pre-fetch unit is configured to pre-fetch data of the pre-fetch number of the pre-fetched stack block addresses of the storage device.

8. A computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the data pre-fetching method according to any one of claims 1 to 6 is implemented.

9. A computing device comprising: at least one processor; At least one memory stores a computer program, and when the computer program is executed by the at least one processor, the data pre-fetching method according to any one of claims 1 to 6 is implemented.

10. A host, comprising: Memory, which stores instructions, and A processor, wherein when the instruction is executed by the processor, the data prefetching method according to any one of claims 1 to 6 is implemented.

11. A system using a storage device, comprising: Main processor; Memory; as well as storage device, The main processor is configured to execute the data pre-fetching method according to any one of claims 1 to 6.

12. A host storage system, comprising: Host; as well as storage device, The host is configured to execute the data pre-fetching method as claimed in any one of claims 1 to 6.

13. A data center system, comprising: Multiple application servers; as well as Multiple storage servers, Each storage server includes a storage device, and each of the plurality of application servers is configured to execute the data pre-fetching method according to any one of claims 1 to 6.

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