Method, system and computer readable medium for designing integrated circuit

Abstract

A method for designing an integrated circuit includes identifying, through at least one IR drop analysis, a first circuit component exhibiting a voltage (IR) drop equal to or greater than an IR drop threshold; dividing the plurality of timing paths into timing paths of a first subset and timing paths of a second subset based on a timing margin threshold; and adding a second circuit member, the second circuit member disposed along the second subset timing path, while leaving the first circuit member disposed along the first subset timing path. The first circuit member may be disposed along a plurality of timing paths, each of the plurality of timing paths being disposed extending from the first storage node to the second storage node, and each of the plurality of timing paths being associated with a timing margin.

Description

Technical Field

[0001] The present invention relates to a method, a system and a computer readable medium for designing an integrated circuit. Background Art

[0002] In designing or integrated circuits, various cells with predetermined functions are used. Pre-designed layouts of standard cells or memory cells are stored in a cell library. During the integrated circuit design process, the pre-designed layouts in the standard cells are retrieved from the cell library and placed in selected locations in the integrated circuit layout. Then, wiring is performed to interconnect the components of the standard cells using interconnect lines. Due to the complexity of various designs, electronic design automation (EDA) tools are used in some instances to simulate and verify integrated circuits at various levels of abstraction under the direction of the designer. EDA tools perform various tasks such as design rule checking, layout and schematic checking, layout parasitic extraction, and resistance-capacitance (RC) extraction. Summary of the invention

[0003] An embodiment of the present invention provides a method for designing an integrated circuit. The method for designing an integrated circuit includes: identifying a first circuit component through at least one voltage drop analysis, the first circuit component presenting a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extending from a first storage node to a second storage node, and each of the plurality of timing paths is associated with a timing margin; based on the timing margin threshold, the plurality of timing paths are divided into a first subset of timing paths and a second subset of timing paths; and adding a second circuit component, the second circuit component being arranged along the timing paths of the second subset, while retaining the first circuit component being arranged along the timing paths of the first subset.

[0004] An embodiment of the present invention provides a system for designing an integrated circuit. The system for designing an integrated circuit includes: a non-volatile storage medium, which is encoded with an instruction set; and a hardware processor, which is communicatively coupled to the non-volatile storage medium and configured to execute the instruction set, wherein the instruction set is configured to enable the hardware processor to: identify a first circuit component through at least one voltage drop analysis, wherein the first circuit component presents a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extends from a first storage node to a second storage node, and each of the plurality of timing paths is associated with a timing margin; based on the timing margin threshold, the plurality of timing paths are divided into a first subset of timing paths and a second subset of timing paths; and add a second circuit component, wherein the second circuit component is arranged along the timing paths of the second subset, while retaining the first circuit component arranged along the timing paths of the first subset.

[0005] An embodiment of the present invention provides a non-volatile computer-readable medium. The non-volatile computer-readable medium stores a computer program code for designing an integrated circuit. The computer program code is configured to enable a system having at least one processor to perform: identifying a first circuit component through at least one voltage drop analysis, wherein the first circuit component presents a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extends from a first storage node to a second storage node, and each of the plurality of timing paths is associated with a timing margin; based on the timing margin threshold, the plurality of timing paths are divided into a first subset of timing paths and a second subset of timing paths; and replacing the first circuit component with a third circuit component, wherein the third circuit component presents an updated voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is an exemplary block diagram of an integrated circuit according to some embodiments of the present disclosure.

[0007] Figure 2 is a flowchart of a method of designing an integrated circuit according to some embodiments of the present disclosure.

[0008] Figure 3 is an exemplary block diagram of an integrated circuit according to some embodiments of the present disclosure.

[0009] Figure 4 is an exemplary block diagram of an integrated circuit according to some embodiments of the present disclosure.

[0010] Figure 5 is an exemplary block diagram of an integrated circuit according to some embodiments of the present disclosure.

[0011] Figure 6 A demonstration of splitting load according to some embodiments of the present disclosure is shown.

[0012] Figure 7 is a flow chart of a design flow for an integrated circuit according to some embodiments of the present disclosure.

[0013] Figure 8 is a functional block diagram of an integrated circuit design system according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," "top," "bottom," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0016] In the field of integrated circuit design, mitigating the impact of voltage (IR (current resistance)) drop (IR Drop) on instances has always been a focus of optimizing performance and power consumption. Some strategies, such as reducing cell size and reducing switching (threshold voltage (VT) devices), have been used to address the IR drop problem. However, the effectiveness of these strategies depends largely on the range of timing margin available on critical paths. When these paths approach their limits in terms of timing margin, the feasibility of existing methods will weaken.

[0017] When timing margin is exhausted, critical limitations emerge, hindering the effectiveness of scaling and VT device swapping as viable solutions. Once timing margin resources are exhausted, addressing instances of IR violations no longer applies these traditional strategies. This gap requires a new perspective that not only addresses IR drop, but also recognizes the interconnectedness of timing margins during the optimization process. This background clarifies the challenges posed by existing strategies and highlights the urgent need for an innovative approach to move beyond the limitations imposed by diminishing timing margins.

[0018] In integrated circuit design, achieving optimal performance while minimizing power consumption remains a challenging task. To address this challenge, the present disclosure provides a breakthrough voltage (IR) optimization strategy that creates additional timing margin by additionally reducing IR drop by splitting load. The split load strategy not only focuses on IR reduction (IR-aware), but also weighs timing factors (timing-aware), thereby improving overall design efficiency. One of the key goals of the strategy is to minimize the need for manual intervention in determining useful margins throughout the design flow. The split load procedure that forms the core of this method is designed to be both fast and lightweight, further enhancing its practicality and feasibility for implementation in semiconductor manufacturing processes.

[0019] Figure 1 1 is an exemplary block diagram of an integrated circuit 100 according to some embodiments of the present disclosure. The integrated circuit 100 may include a first storage node 102, a second storage node 104, a first circuit component 106, a plurality of timing paths 108, and a second circuit component 110. The first circuit component 106 may be arranged along the plurality of timing paths 108, each of the plurality of timing paths extending from the first storage node 102 to the second storage node 104 and each of the plurality of timing paths being associated with a timing margin (e.g., a timing slack).

[0020] The first storage node 102 and the second storage node 104 may each include, but are not limited to, a combination of a flip-flop circuit, a latch circuit, a drive circuit, or a logic circuit. The first circuit member 106 may be a standard cell. A standard cell may include at least one functional cell and at least one non-functional cell (e.g., an engineering change order (ECO) cell) for various applications. Functional cells are designed to perform specific functions, such as logic functions or storage functions. The design of the ECO cell has no specific function, but is programmable to provide a specific function. During the integrated circuit design, the design layout of one or more functional cells is read out from the cell library and placed into the initial layout.

[0021] The first circuit component 106 may exhibit a voltage (IR) drop. When current flows through the first circuit component 106, according to Ohm's law, a portion of the applied voltage may fall into the first circuit component 106. The amount of voltage drop may be V=I*R, referred to as IR drop. IR drop analysis is a process used in semiconductor design to evaluate the voltage drop on a circuit component due to current flow. Excessive IR drop can affect performance and reliability. It may involve the use of specialized software to simulate and analyze the voltage drop, and make design adjustments to alleviate the problem. In order to mitigate IR drop and improve IC performance, strategies including cell size reduction and switching devices may be adopted. In some embodiments, the driving current capability of the first circuit component 106 may be determined based on the threshold voltage (VT) of one or more transistors (e.g., the first circuit component 106 or the second circuit component 110) within the circuit component. In some embodiments, the threshold voltage VT may be at least divided into a high threshold voltage (HVT), a low threshold voltage (LVT), or a standard threshold voltage (SVT). In some embodiments, the HVT may be at least greater than the LVT or the SVT. In some embodiments, the SVT may be greater than the LVT. For example, through at least one IR drop analysis, when the IR drop of the first circuit component 106 (e.g., the IR drop of the device under testing (DUT) has an IR drop of about 18%) is equal to or greater than an IR drop threshold (e.g., about 10%), it may be an IR violated instance with many fanout loads. The first circuit component 106 can be reduced in size or replaced from a first cell to a second cell. The reduction in the IR drop of the first circuit component 106 results in a reduction from about 18% to about 9%. However, it may simultaneously reduce the remaining timing margin on the path from about 25 picoseconds (ps) to about 3ps. The reduction in the remaining timing margin may cause the margin to be exhausted / depleted.

[0022] Static timing analysis is a method of verifying the timing performance of a design by checking whether all possible timing paths have timing violations under worst-case conditions. Static timing analysis can be performed by various EDA software at different design stages described above, such as but not limited to DESIGN COMPILER, ENCOUNTER, ICCOMPILER, or PRIMETIME. For example, each timing path starts from a first storage node 102 (e.g., flip-flop 1) and ends at a second storage node 104 (e.g., flip-flop 2) of the integrated circuit 100. For example, by traversing all timing paths / nodes (L_U1, L_U2, L_U3…, L_U4) from the first storage node 102 to the second storage node 104 one by one. k , ..., L_U N ), multiple timing paths can be identified. In some embodiments, L_U N There may be load instances of a DUT with a label N. These load instances are sorted by timing margin (sometimes called "slack" or "slk"). N ” may represent the timing margin (eg, margin) of the load instance L_U N , "ex" can represent L_U N The dominant DUT's exhausted timing margin (eg, margin), while “ctm” may stand for critical timing margin.

[0023] The plurality of timing paths 108 may include a first subset of timing paths 108a and a second subset of timing paths 108b. The plurality of timing paths 108 may include one or more nodes (eg, L_U1, L_U2, L_U3, ..., L_U k , …, L_U N). Each node can be any appropriate combinational logic of the integrated circuit, such as AND, OR, NOR, etc. The margin associated with each timing path can be the difference between the required time and the arrival time, and can be determined by static timing analysis known in the art. All timing paths with margin values ​​less than a predetermined value can be considered to be timing-critical paths in static timing analysis. The value of the margin can be a time unit, such as picoseconds (ps). For example, if the predetermined value is about 0ps, all timing paths with negative margins are considered to be timing-critical paths. A positive margin value at a flip-flop indicates that the arrival time at the flip-flop may increase its value without affecting the overall performance of the circuit. Conversely, a negative margin means that the timing path is too slow, and if the entire circuit is to work at the required speed, the timing path must be accelerated (or the reference signal delayed). Therefore, the timing-critical path in this example is a timing path that does not meet the timing requirements.

[0024] To ensure that the designed integrated circuit meets the specific speed requirements, the timing performance of the designed integrated circuit is verified in the timing analysis stage by checking the timing violations (i.e., timing constraints) of all possible paths under worst-case conditions. If the timing analysis stage determines that the integrated circuit cannot operate within the required clock frequency range, a split load process is required to modify the design through one or more IR optimization and timing optimization strategies. The split load process can include, for example, splitting the multiple timing paths / nodes into a first subset of timing paths 108a and a second subset of timing paths 108b based on a timing margin threshold (e.g., ctm). The value of the timing margin can be a time unit, such as picoseconds (ps). In some embodiments, when the first circuit component 106 may have an IR violation (e.g., IR drop = about 14.0%), the multiple timing paths 108 can be split based on a critical timing margin (ctm) of about 10ps. Timing paths having a timing margin equal to or less than about 10 ps (e.g., timing-critical paths) may be grouped into a first subset of timing paths 108 a, while those having a timing margin exceeding about 10 ps (e.g., non-timing-critical paths) may be grouped into a second subset of timing paths 108 b.

[0025] The key concept of the split-load methodology revolves around creating additional margin within the design by addressing the issues of slack-depleted paths. The split-load process may involve identifying situations where IR violations occur due to a large number of branching loads. These loads are then categorized based on their timing importance. For those loads that are not considered to be timing critical, the split-load technique can be used as an optimization strategy and improve the overall performance of the design. The split-load methodology can be used to improve timing performance and IR violations at the clock-tree synthesis (CTS) stage, routing stage, and / or any other suitable stage in the design flow.

[0026] In some embodiments, the second circuit component 110 can be identical to the first circuit component 106. The second circuit component 110 (e.g., a split SP) can be a duplicated instance of a load split from the first circuit component 106 (e.g., a device under test DUT). In some embodiments, the second circuit component 110 can be arranged along the timing paths 108b of the second subset while retaining the first circuit component 106 arranged along the timing paths 108a of the first subset.

[0027] Figure 2 is a flow chart of a method 200 of designing an integrated circuit 100 according to some embodiments of the present disclosure. Figure 3-5 FIG. 1 shows a method for resolving IR violations according to some embodiments of the present disclosure. Figure 2 An exemplary block diagram of the integrated circuit 100 of the method 200 is shown. A person skilled in the art will appreciate that Figure 2 In some embodiments, additional operations are performed before, during, and / or after the depicted method 200. In some embodiments, a place and route electronic design automation (EDA) tool may be used to design an initial layout to form one or more circuit patterns of a semiconductor device.

[0028] like Figure 2 and Figure 3As shown, the method 200 may include operation 210. In operation 210, a first circuit component 106 may be identified. The first circuit component 106 exhibits a voltage (IR) drop equal to or greater than an IR drop threshold. A hardware computer (e.g., an EDA tool) may identify the first circuit component 106 having an IR violation through at least one IR drop analysis. For example, the IR drop threshold is set to about 10%, and the first circuit component 106 exhibits / exhibits an IR drop of about 14.0%, then the first circuit component 106 may be identified as an IR violation instance. The minimum slack of the first circuit component 106 is about 3ps, indicating that the timing path therein is too slow. In order to achieve the desired circuit speed, the timing path must be accelerated (or the reference signal must be delayed) to create additional timing margin. In some embodiments, the first circuit component 106 may be arranged along a plurality of timing paths 108, each of the plurality of timing paths 108 extending from the first storage node 102 to the second storage node 104. The first storage node 102 and the second storage node 104 may each include a flip-flop circuit or a latch circuit. Each of the plurality of timing paths 108 is associated with a timing margin (e.g., margin). For example, the timing margin of L_U1 may be about 3ps. The timing margin of L_U2 is about 3ps. The timing margin of L_U3 is about 5ps. The timing margin of L_U8 is about 10ps. The timing margin of L_U9 is about 17ps. The timing margin of L_U 10 The timing margin is about 21ps. 18 In some embodiments, the plurality of timing paths may be arranged from the lowest timing margin (eg, L_U1 having approximately 3 ps) to the highest timing margin (eg, L_U2 having approximately 49 ps). 18 ) to arrange.

[0029] like Figure 2 and Figure 4 As shown, the method 200 continues with operation 220. In operation 220, the plurality of timing paths 108 may be divided into a first subset of timing paths 108a and a second subset of timing paths 108b based on a timing margin threshold. In some embodiments, the hardware computer may compare the timing margin of each of the plurality of timing paths 108 to a timing margin threshold (e.g., approximately 10 ps). In response to determining that the timing margin of a first timing path (e.g., L_U8) of the plurality of timing paths is less than the timing margin threshold (e.g., approximately 10 ps), the first timing paths (e.g., L_U1-L_U8) may be grouped into the first subset of timing paths 108a. In response to determining that the timing margin of a second timing path (e.g., L_U9-L_U10) of the timing paths is less than the timing margin threshold (e.g., approximately 10 ps), the first timing paths (e.g., L_U1-L_U8) may be grouped into the first subset of timing paths 108a. 18) has a timing margin equal to or greater than a timing margin threshold (eg, approximately 10 ps), the second timing paths may be grouped into a second subset of timing paths 108 b.

[0030] In the context of the split load method, this operation 220 illustrates the process of relaxing timing margins. The timing-critical components of the device under test (DUT) 106 and their loads (e.g., L_U1 to L_U8) remain in their original locations and their routing is preserved. At the same time, the non-timing-critical loads (e.g., L_U9 to L_U 18 ) is rerouted to the newly added second circuit component 110 (e.g., split SP). After splitting the load, the IR drop of the first circuit component 106 becomes about 14.6%, and the minimum margin of the first circuit component 106 is improved to about 14ps, which represents the creation of additional timing margin.

[0031] like Figure 2 and Figure 4 As shown, the method 200 continues with operation 230. In operation 230, a second circuit component 110 (e.g., SP) can be additively disposed along the timing path 108b of the second subset while retaining the first circuit component 106 disposed along the timing path 108a of the first subset. In some embodiments, the second circuit component 110 can be identical to the first circuit component 106. The IR drop of the second circuit component 110 is approximately 12.4%, and the minimum margin of the second circuit component 110 is approximately 29ps. This approach allows for more flexible timing adjustments while maintaining critical timing integrity.

[0032] After obtaining timing margin from the in-placed DUT and the decomposed SP components, a second round of downsizing and IR optimization becomes effective. Figure 5 As shown, method 200 may continue with additional operations. In the additional operations, the first circuit member 106 may be replaced with a third circuit member 112 (e.g., DUT'). The third circuit member 112 may present an updated IR drop (e.g., approximately 12.7%). The minimum margin of the third circuit member 112 is approximately 11ps. In some embodiments, the third circuit member 112 (e.g., cell = D6) may have a lower driving power than the first circuit member 106 (e.g., cell = D12). The second circuit member 110 may be replaced with a fourth circuit member 114 (e.g., SP'). The fourth circuit member 114 may present an updated IR drop (e.g., approximately 8.1%) that is less than an IR drop threshold (e.g., approximately 10%). The minimum margin of the fourth circuit member 114 is approximately 13ps. In some embodiments, the fourth circuit member 114 (e.g., cell = D3) may have a lower driving power than the second circuit member 110 (e.g., cell = D12).

[0033] Figure 6 A demonstration 600 with split loads according to some embodiments of the present disclosure is shown. In an example including a total of 190,000 designs, the split load method proves its efficiency and has several significant advantages. Specifically, the -split load process only takes 0.01 times the runtime to process, reflecting its fast execution. Of the 382 IR-violating devices under test (DUTs) within the design, the split load was applied to only 21 DUTs. Compared to the optimization process without split loads, the disclosed method can reduce the number of violating DUTs by an additional approximately 16%. These findings emphasize the effectiveness of split loads in optimizing design performance and ensuring compliance with timing constraints.

[0034] Figure 7 700 is a functional flow chart of at least a portion of the IC design and manufacturing process 200 according to some embodiments. The design and manufacturing process 700 uses one or more electronic design automation (EDA) tools to generate, optimize and / or verify the design of the IC before manufacturing the IC. The EDA tool in some embodiments is a set of one or more sets of executable instructions for execution by a processor or controller or programmed computer to perform the indicated functions. In at least one embodiment, the IC design and manufacturing process 700 is performed by Figure 7 The IC manufacturing system under discussion is executed by the design house.

[0035] At the beginning, the design of the IC is provided by a circuit designer. In some embodiments, the design of the IC includes an IC schematic, i.e., an electrical diagram of the IC. In some embodiments, the schematic is generated or provided in the form of a schematic netlist, such as a Simulation Program with Integrated Circuit Emphasis (SPICE) netlist. Other data formats for describing the design may also be used in some embodiments. In some embodiments, the design is pre-layout simulated to determine whether the design meets predetermined specifications. When the design does not meet the predetermined specifications, the IC needs to be redesigned. In at least one embodiment, the design is redesigned from Figure 7 In at least one embodiment, the method 700 further includes performing a pre-layout simulation.

[0036] In Automatic Placement and Routing (APR) operations 710-740, a layout diagram of the IC is generated based on the IC schematic. The IC layout diagram includes the physical locations of each circuit element of the IC and the physical locations of each network of interconnected circuit elements. For example, the IC layout diagram is generated in the form of a graphic design system (GDS) or GDSII file. Other data formats for describing IC designs are within the scope of various embodiments. Figure 7In an example configuration, an IC layout diagram is generated by an EDA tool (e.g., an APR tool). The APR tool receives a design of the IC in the form of a netlist, as described herein. The APR tool performs floor planning to identify circuit elements that are electrically connected to each other and are placed close to each other to reduce the area of ​​the IC and / or reduce the delay time of signals traveling on internal connections or networks connecting electrically connected circuit elements. In some embodiments, the APR tool performs partitioning to divide the design of the IC into multiple blocks or groups, such as clock and logic groups. Figure 7 In the example configuration in FIG. 7 , the APR tool performs one or more of a power planning operation 710 , a cell placement operation 720 , a clock tree optimization (CTS) operation 730 , or a routing operation 740 .

[0037] In power planning operation 710, the APR tool performs power planning based on the partitioning and / or floor plan of the IC design to generate a power grid structure including multiple conductive layers (e.g., metal layers). In some embodiments, one of the metal layers includes power lines or power rails extending in one direction, such as horizontally extending in a plan view. In some embodiments, another of the metal layers includes power lines or power rails extending along an orthogonal direction, such as vertically extending in a plan view.

[0038] During cell placement operation 720, the APR tool performs cell placement. For example, standard cells (also referred to herein as "cells") are configured to provide predefined functions and have pre-designed layouts stored in one or more cell libraries. The APR tool retrieves cells from one or more cell libraries and places the cells in an adjacent manner to generate an IC layout corresponding to the IC schematic.

[0039] The generated IC layout diagram includes a power grid structure and a plurality of cells, each cell including one or more circuit elements and / or one or more networks. In some embodiments, each cell includes more than one flip-flop or more than one bit flip-flop. In some embodiments, the cell includes a logic gate cell. In some embodiments, the logic gate cell includes AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, flip-flop, BUFF, latch, delay, clock cell or the like. In some embodiments, the cell includes a memory cell. In some embodiments, the memory cell includes a static random access memory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), a magnetoresistive RAM (MRAM), a read-only memory (ROM), etc. In some embodiments, the circuit element is an active element or a passive element. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFET / NFET), or similar, fin field effect transistors, planar MOS transistors, raised source / drain, etc. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors. Examples of networks include, but are not limited to, vias, conductive pads, conductive traces, and conductive redistribution layers, etc.

[0040] At the clock tree optimization (CTS) operation 730, the APR tool performs the CTS to minimize the tilt and / or delay that may occur due to the placement of circuit elements in the IC layout diagram. The CTS includes an optimization process to ensure that signals are transmitted and / or arrive at the appropriate time. For example, during the optimization process within the CTS, one or more buffers are inserted into the IC layout diagram to add and / or eliminate margin (timing of signal arrival) to achieve the desired timing. In some embodiments, operation 730 includes performing a timing analysis of one or more critical paths including one or more multi-bit flip-flops to determine timing violations in one or more critical paths. The described CTS or operation 730 is an example. Other arrangements or operations are within the scope of various embodiments. For example, in one or more embodiments, one or more of the described operations will be repeated or omitted.

[0041] At the routing operation 740, the APR tool performs routing to route various networks interconnected with the placed circuit elements. Routing is performed to ensure that the internal connections or networks of the routing meet a set of constraints. For example, the routing operation 740 includes global routing, track allocation, and detailed routing. During global routing, routing resources for internal connections or networks are allocated. For example, the routing area is divided into multiple sub-areas, the pins of the placed circuit elements are mapped to the sub-areas, and the network is constructed as a collection of sub-areas, where the internal connections are physically routable. During track allocation, the APR tool assigns the internal connections or networks to the corresponding conductive layers of the IC layout diagram. During detailed routing, the APR tool routes the internal connections or networks within the specified conductive layers and global routing resources. For example, the detailed physical internal connections are generated within the corresponding sub-area groups defined at the global routing and the conductive layers defined at the track allocation. After the routing operation 740, the APR tool outputs the IC layout diagram, including the power grid structure, the layout circuit elements, and the routing network. The APR tool described is an example. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more of the described operations may be omitted.

[0042] In the ECO operation 750 considering timing / power / area / IR, at least one ECO cell can be programmed to provide a specific function. Standard cells may include functional cells and engineering change order (ECO) cells. Functional cells are pre-designed to have specific functions, such as logic functions. ECO cells are pre-designed without specific functions, but are programmable to provide specific functions. In order to design an IC, a pre-designed layout of one or more functional cells is read out from a standard cell library and placed into an initial IC layout. Routing is performed to connect the functional cells using one or more metal layers. The IC layout also includes one or more ECO cells that are not connected to the functional cells. When the IC layout is to be modified, one or more ECO cells are programmed to provide the intended function and routed to the functional cells. The programming of ECO cells involves modifying multiple layers of the IC layout and / or mask used to manufacture the IC.

[0043] In some embodiments, IR drop analysis and / or timing analysis may be applied to any operation in the design and manufacturing flow 700. Once IR violation instances are identified, split load entity optimization that takes IR into account may be applied to those operations (e.g., operations 730, 740, or 750). Thus, one or more embodiments of the present disclosure are designed to optimize IR while addressing timing violations. This results in lower power consumption for the integrated circuit (IC) and reduces the need for manual intervention. Furthermore, in certain embodiments, the disclosures are constructed to optimize IR while providing for generating additional timing margin to simplify the design and manufacturing flow 700. This approach involves fewer steps than other approaches involving shrinking and down-swapping threshold voltage (VT) devices, particularly those that do not address one or more IR violations.

[0044] During the sign-off operation 760, one or more physical and / or timing verifications are performed. For example, the sign-off operation 760 includes resistance and capacitance (RC) extraction, layout-versus-schematic (LVS) checking, design rule checking (DRC), or timing sign-off checking (also known as post-layout simulation). In some embodiments, other verification processes are performed.

[0045] In some embodiments, RC extraction is performed, for example, through an EDA tool to determine parasitic parameters of components in the IC layout diagram, such as parasitic resistance and parasitic capacitance, for timing simulation in subsequent operations. In some embodiments, an LVS check is performed to ensure that the generated IC layout diagram corresponds to the design of the IC. Specifically, the LVS check tool, i.e., the EDA tool, identifies the electrical components and connections in the space between the patterns of the generated IC layout diagram. The LVS check tool then generates and lays out a netlist representing the identified electrical components and connections. The LVS check tool compares the layout netlist generated from the IC layout diagram with the schematic netlist of the IC design. If the two netlists match within a matching tolerance range, the LVS check passes. Otherwise, at least one of the IC layout diagram or the IC design is corrected by returning the process to the IC design operation and / or the APR operation.

[0046] In some embodiments, DRC is performed, for example, through an EDA tool to ensure that the IC layout diagram meets certain manufacturing design rules, that is, to ensure the manufacturability of the IC. If one or more design rules are violated, at least one of the IC layout diagram or the design is corrected by returning the process to the IC design operation and / or the APR operation. Examples of design rules include, but are not limited to, width rules that specify a minimum width of a pattern in an IC layout diagram, spacing rules that specify a minimum spacing between adjacent patterns in an IC layout diagram, area rules that specify a minimum area in an IC layout diagram, and the like.

[0047] In some embodiments, a timing sign-off check is performed (after layout simulation), such as through an EDA tool, to determine whether the IC layout meets predetermined specifications of one or more timing requirements, taking into account the extracted parasitic parameters. If the simulation indicates that the IC layout does not meet the predetermined specifications, for example, if the parasitic parameters cause unexpected delays, at least one of the IC layout or the design is corrected by returning processing to the IC design operation. Otherwise, the IC layout will enter manufacturing or additional verification processes.

[0048] Figure 8 8 is a functional block diagram of an integrated circuit design system 800 according to one or more embodiments of the present disclosure. The integrated circuit design system 800 includes a first computer system 810, a second computer system 820, a network storage device 830, and a network 840 connecting the first computer system 810, the second computer system 820, and the network storage device 830. In some embodiments, one or more of the second computer system 820, the network storage device 830, and the network 840 may be omitted.

[0049] The first computer system 810 includes a hardware processor 812 communicatively coupled to a non-volatile computer readable storage medium 814, the computer readable storage medium 814 encoding (i.e., storing) the generated integrated layout 814a, circuit design 814b, and computer program code 814c, i.e., an executable instruction set. The hardware processor 812 is communicatively coupled to the computer readable storage medium 814. The hardware processor 812 is configured to execute a set of instruction sets 814c encoded in the computer readable storage medium 814 so that the first computer system 810 can be used as a placement and routing tool for performing a portion or all of the operations 210-230 as shown in the figure. In some embodiments, the hardware processor 812 is configured to execute the instruction set 814c for generating an integrated circuit layout based on a layout IR drop standard of a cell and a timing margin threshold corresponding to a predetermined semiconductor manufacturing process. In some embodiments, the hardware processor 812 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or an appropriate processing unit.

[0050] In some embodiments, the computer readable storage medium 814 is an electronic system, a magnetic system, an optical system, an electromagnetic system, an infrared system, and / or a semiconductor system (or device or apparatus). In some embodiments, the computer readable storage medium 814 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In some embodiments using optical disks, the computer readable storage medium 814 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0051] In some embodiments, the storage medium 814 stores computer program code 814c configured to cause the first computer system 810 to perform the method 200, such as Figure 3-7 In some embodiments, the storage medium 814 also stores information required to perform the method 200 or information generated during the performance of the method 200 .

[0052] The first computer system 810 may include an input / output interface 816 and a display unit 817. The input / output interface 816 may be coupled to the hardware processor 812 and may allow a circuit designer to manipulate the first computer system 810 to perform the method 200. At least in some embodiments, the display unit 817 may display the status of the operation or method 200 in a real-time manner and preferably provide a graphical user interface (GUI). In some embodiments, the input / output interface 816 and the display unit 817 may allow an operator to manipulate the first computer system 810 in an interactive manner.

[0053] In some embodiments, the first computer system 810 may further include a network interface 818 coupled to the hardware processor 812. The network interface 818 may allow the first computer system 810 to communicate with a network 840, to which one or more other computer systems 820 and a network storage device 830 are connected. The network interface 818 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, WCDMA, etc.; or a wired network interface such as Ethernet, USB, or IEEE-1394. In some embodiments, the method 200 is implemented in two or more computer systems 810 and 820 and / or a network storage device 830, and information such as an integrated circuit layout 814a, a circuit design 814b, a computer program code 814c, and a cell library 814d may be exchanged between different computer systems 810 and 820 and / or a network storage device 830 via the network 840.

[0054] In one aspect of the present disclosure, a method for designing an integrated circuit includes: identifying a first circuit component through at least one voltage drop analysis, the first circuit component presenting a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extends from a first storage node to a second storage node, and each of the plurality of timing paths is associated with a timing margin; based on a timing margin threshold, dividing the plurality of timing paths into a first subset of timing paths and a second subset of timing paths; and adding a second circuit component, the second circuit component being arranged along the timing paths of the second subset, while retaining the first circuit component being arranged along the timing paths of the first subset.

[0055] In a related embodiment, the first storage node and the second storage node each include a flip-flop circuit or a latch circuit.

[0056] In a related embodiment, the method further includes comparing the timing margin of each of the plurality of timing paths to the timing margin threshold.

[0057] In a related embodiment, the method further includes: in response to determining that the timing margin of a first timing path of the plurality of timing paths is less than the timing margin threshold, grouping the first timing path into the first subset of timing paths.

[0058] In a related embodiment, the method further includes: in response to determining that the timing margin of a second timing path of the timing paths is equal to or greater than the timing margin threshold, grouping the second timing paths into the second subset of timing paths.

[0059] In a related embodiment, the second circuit component is identical to the first circuit component.

[0060] In a related embodiment, the method further includes: replacing the first circuit component with a third circuit component, the third circuit component presenting an updated voltage drop, the updated voltage drop being less than the voltage drop threshold; and replacing the second circuit component with a fourth circuit component, the fourth circuit component presenting the updated voltage drop.

[0061] In a related embodiment, the third circuit component has a lower driving power than the first circuit component.

[0062] In a related embodiment, the fourth circuit component has a lower driving power than the second circuit component.

[0063] In a related embodiment, the method further includes arranging the plurality of timing paths from lowest timing margin to highest timing margin.

[0064] In one aspect of the present disclosure, a system for designing an integrated circuit includes: a non-volatile storage medium encoded with an instruction set; and a hardware processor communicatively coupled to the non-volatile storage medium and configured to execute the instruction set, wherein the instruction set is configured to cause the hardware processor to: identify, through at least one voltage drop analysis, a first circuit component presenting a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extending from a first storage node to a second storage node, and each of the plurality of timing paths is associated with a timing margin; divide the plurality of timing paths into a first subset of timing paths and a second subset of timing paths based on the timing margin threshold; and add a second circuit component, wherein the second circuit component is arranged along the timing paths of the second subset, while retaining the arrangement of the first circuit component along the timing paths of the first subset.

[0065] In a related embodiment, the first storage node and the second storage node each include a flip-flop circuit or a latch circuit.

[0066] In a related embodiment, the instruction set is configured to further cause the hardware processor to: compare the timing margin of each of the plurality of timing paths to the timing margin threshold.

[0067] In a related embodiment, the instruction set is configured to further cause the hardware processor to: in response to determining that the timing margin of a first timing path of the plurality of timing paths is less than the timing margin threshold, group the first timing path into the first subset of timing paths.

[0068] In a related embodiment, the instruction set is configured to further cause the hardware processor to: in response to determining that the timing margin of a second timing path of the plurality of timing paths is equal to or greater than the timing margin threshold, group the second timing path into the timing paths of the second subset.

[0069] In a related embodiment, the second circuit component is identical to the first circuit component.

[0070] In a related embodiment, the instruction set is configured to further cause the hardware processor to: replace the first circuit component with a third circuit component, the third circuit component presenting an updated voltage drop, the updated voltage drop being less than the voltage drop threshold; and replace the second circuit component with a fourth circuit component, the fourth circuit component presenting the updated voltage drop.

[0071] In a related embodiment, the instruction set is configured to further cause the hardware processor to: sort the plurality of timing paths from lowest timing margin to highest timing margin.

[0072] In one aspect of the present disclosure, a non-volatile computer-readable medium stores computer program code for designing an integrated circuit. The computer program code is configured to cause a system having at least one processor to perform: identifying a first circuit component through at least one voltage drop analysis, the first circuit component presenting a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extending from a first storage node to a second storage node, and each of the plurality of timing paths is associated with a timing margin; dividing the plurality of timing paths into a first subset of timing paths and a second subset of timing paths based on the timing margin threshold; and replacing the first circuit component with a third circuit component, the third circuit component presenting an updated voltage drop.

[0073] In a related embodiment, the computer program code is further configured to cause the system having at least one processor to perform: adding a second circuit component, the second circuit component along the timing path of the second subset, while retaining the third circuit component arranged along the timing path of the first subset.

[0074] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies within 10-30% of that value (e.g., 10%, ±20%, or ±30% of that value). ).

[0075] The above overview of features and embodiments is intended to enable those skilled in the art to better understand the aspects of the present invention. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for designing an integrated circuit, characterized in that include: identifying, through at least one voltage drop analysis, a first circuit component that exhibits a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extending from a first storage node to a second storage node, and each of the plurality of timing paths being associated with a timing margin; Based on a timing margin threshold, the plurality of timing paths are divided into a first subset of timing paths and a second subset of timing paths; as well as A second circuit component is added, the second circuit component being arranged along the timing path of the second subset, while the first circuit component is retained to be arranged along the timing path of the first subset.

2. The method according to claim 1, characterized in that The first storage node and the second storage node each include a flip-flop circuit or a latch circuit.

3. The method according to claim 1, characterized in that Further including: The timing margin of each of the plurality of timing paths is compared to the timing margin threshold.

4. The method according to claim 3, characterized in that: Further including: In response to determining that the timing margin of a first timing path of the plurality of timing paths is less than the timing margin threshold, the first timing path is grouped into the first subset of timing paths.

5. The method according to claim 3, characterized in that: Further including: In response to determining that the timing margin of a second timing path of the timing paths is equal to or greater than the timing margin threshold, the second timing paths are grouped into the second subset of timing paths.

6. The method according to claim 1, characterized in that: The second circuit component is the same as the first circuit component.

7. The method according to claim 6, characterized in that Further including: replacing the first circuit component with a third circuit component, the third circuit component exhibiting an updated voltage drop, the updated voltage drop being less than the voltage drop threshold; as well as The second circuit member is replaced with a fourth circuit member, the fourth circuit member exhibiting the updated voltage drop.

8. The method according to claim 7, characterized in that The third circuit component has a lower driving power than the first circuit component.

9. A system for designing an integrated circuit, characterized in that: include: A non-volatile storage medium encoded with an instruction set; as well as a hardware processor communicatively coupled to the non-volatile storage medium and configured to execute the instruction set, the instruction set being configured to cause the hardware processor to: identifying, through at least one voltage drop analysis, a first circuit component exhibiting a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extending from a first storage node to a second storage node, and each of the plurality of timing paths being associated with a timing margin; Based on a timing margin threshold, the plurality of timing paths are divided into a first subset of timing paths and a second subset of timing paths; as well as A second circuit component is added, the second circuit component being arranged along the timing path of the second subset, while the first circuit component is retained to be arranged along the timing path of the first subset.

10. A non-volatile computer readable medium, characterized in that: A computer program code for designing an integrated circuit is stored, the computer program code being configured to cause a system having at least one processor to execute: identifying, through at least one voltage drop analysis, a first circuit component that exhibits a voltage drop equal to or greater than a voltage drop threshold, wherein the first circuit component is arranged along a plurality of timing paths, each of the plurality of timing paths extending from a first storage node to a second storage node, and each of the plurality of timing paths being associated with a timing margin; Based on a timing margin threshold, the plurality of timing paths are divided into a first subset of timing paths and a second subset of timing paths; as well as The first circuit member is replaced with a third circuit member, the third circuit member exhibiting an updated voltage drop.

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