Method, device, medium and program product for layout processing

Abstract

According to the embodiment of the invention, a layout processing method and device, a medium and a program product are provided. In the method, based on a splitting condition related to layout splitting of an initial layout, region associated information for a plurality of regions in the initial layout is determined, and the region associated information indicates whether two adjacent regions in the plurality of regions are related or not in the layout splitting; in response to the fact that the area association information indicates that a first area and a second area which are adjacent in the multiple areas are related in layout splitting, the coloring result of the first area and the coloring result of the second area are determined on the basis of the correlation between the first area and the second area, and the color of the graph indicates the sub-layouts to which the graph is split.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to the field of integrated circuits, and more particularly to methods, apparatuses, computer-readable storage media, and computer program products for layout processing. Background Art

[0002] The circuit layout (also referred to as the layout) is a series of graphics converted from the designed and simulated optimized circuit, which contains physical information data related to the device, such as the size of the integrated circuit, the topology definition of each layer, etc. The integrated circuit manufacturer manufactures the mask based on this data. The layout pattern on the mask determines the size of the device or the physical layer of the connection on the chip.

[0003] Double patterning technology divides the pattern that cannot be achieved with a single exposure, and uses multiple exposures and etching to define a higher density pattern. The introduction of double patterning technology enables chip manufacturing to break through the size limitation of single exposure and achieve higher density pattern definition. In chip manufacturing, it is expected to effectively split the layout to use double patterning technology or multiple patterning technology. Summary of the invention

[0004] In a first aspect of the present disclosure, a layout processing method is provided. The method comprises: determining region association information for multiple regions in the initial layout based on a splitting condition related to the layout splitting of the initial layout, the region association information indicating whether two adjacent regions in the multiple regions are related in the layout splitting; and in response to the region association information indicating that the adjacent first region and the second region in the multiple regions are related in the layout splitting, determining a coloring result of the first region and a coloring result of the second region based on the correlation between the first region and the second region, wherein the color of the graphic indicates the sub-layout to which the graphic will be split.

[0005] In a second aspect of the present disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory, the at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. When the instructions are executed by the at least one processing unit, the device executes the method of the first aspect.

[0006] In a third aspect of the present disclosure, a computer-readable storage medium is provided. The computer program product includes computer-executable instructions, which, when executed by a processor, implement the method according to the first aspect of the present disclosure.

[0007] In a fourth aspect of the present disclosure, a computer program product is provided, which includes computer executable instructions, which, when executed by a processor, implement the method according to the first aspect of the present disclosure.

[0008] It should be understood that the contents described in this content section are not intended to limit the key features or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein: Figure 1 A schematic diagram showing an example environment in which embodiments of the present disclosure can be implemented; Figure 2 A flowchart showing a process for layout processing according to some embodiments of the present disclosure is shown; Figure 3 A schematic diagram showing an example of two adjacent regions according to some embodiments of the present disclosure; and Figure 4 A block diagram of an electronic device is shown in which one or more embodiments of the present disclosure may be implemented. DETAILED DESCRIPTION

[0010] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0011] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below.

[0012] Herein, unless explicitly stated, executing a step “in response to A” does not mean executing the step immediately after “A” but may include one or more intermediate steps.

[0013] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and relevant provisions.

[0014] Figure 1A schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. The example environment 100 may include an electronic device 110.

[0015] like Figure 1 As shown, the electronic device 110 obtains an initial layout 120. The layout may include a graphical representation formed by placing and routing various electronic components and interconnects on a plane according to certain rules and requirements. Here, the initial layout 120 may be an original layout that has not been split.

[0016] In some embodiments, the electronic device 110 can use a tool or application to split the initial layout 120 based on the splitting condition 130, so that the multiple sub-layouts obtained after the splitting (for example, can include sub-layout 125-1, sub-layout 125-2, ...) can be used for double or multiple patterning technology. For example, in the double patterning technology, the initial layout 120 needs to be split into two sub-layouts. Correspondingly, in the multiple patterning technology, the initial layout 120 needs to be split into multiple sub-layouts. It should be understood that the number of layout splits can be set according to the requirements of the corresponding lithography technology, and no limitation is intended here.

[0017] In some embodiments, the splitting condition 130 may include a splitting condition defined according to a design rule check (DRC) rule, or may include a user-defined splitting condition. It should be understood that the splitting condition 130 may include any appropriate condition required for layout splitting in the corresponding lithography technology.

[0018] The electronic device 110 may be any type of device with computing capabilities, including a terminal device or a server device. The terminal device may be any type of mobile terminal, fixed terminal or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / camcorder, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. The server device may include, for example, a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and the like.

[0019] It should be understood that the structure and function of the various elements in the environment 100 are described for exemplary purposes only and do not imply any limitation on the scope of the present disclosure.

[0020] As briefly mentioned above, in the chip design stage of the semiconductor process, as the size of semiconductor devices continues to shrink, single-exposure lithography technology becomes no longer applicable after reaching a certain size limit, so double patterning technology is introduced. Double patterning technology divides patterns that were originally impossible to achieve with a single exposure, and uses multiple exposures and etching to define higher-density patterns. The introduction of double patterning technology enables chip manufacturing to break through the size limitations of single exposure and achieve higher-density pattern definition, but it also brings new design challenges and complexities. For chip manufacturers and designers, how to effectively split the layout into two or more sub-layouts is an important challenge in current chip manufacturing.

[0021] Double exposure splitting is a two-color coloring problem based on DRC rules. Through DRC rules, the graphics that violate the rules on the same layer are divided into different layers. Traditional splitting technology requires the creation of a set of all graphics marked by the DRC splitting rules, and then converting them into a two-color coloring problem. However, with the advancement of the process, the number of graphics is increasing, and storing and calculating these graphics requires a lot of computing and storage resources, which leads to certain usage restrictions of the tool in certain processes.

[0022] In view of this, according to an embodiment of the present disclosure, an improved scheme for layout processing is proposed. According to the scheme of the embodiment of the present disclosure, based on the splitting conditions related to the layout splitting of the initial layout, the region association information for multiple regions in the initial layout is determined, and the region association information indicates whether two adjacent regions in the multiple regions are related in the layout splitting. In response to the region association information indicating that the adjacent first region and the second region in the multiple regions are related in the layout splitting, based on the correlation between the first region and the second region, the coloring result of the first region and the coloring result of the second region are determined, wherein the color of the graphic indicates the sub-layout to which the graphic will be split.

[0023] In this way, by combining the splitting conditions to determine the association information of multiple areas in the initial layout, and determining the coloring results of the associated areas, the splitting results for the initial layout can be determined. Such a layout splitting scheme can speed up the efficiency and accuracy of layout splitting. In addition, according to the correlation or irrelevance of adjacent areas in multiple areas, the associated adjacent areas and the separate areas that are not associated with other areas can be respectively corresponded to distributed nodes. In this way, calculations for different areas can be performed in parallel through the corresponding distributed nodes. By synchronizing the calculation results of each distributed node, the effect of accelerating calculations and reducing memory can be achieved, and the memory and running time of the initial layout are effectively reduced on advanced nodes.

[0024] Some example embodiments of the present disclosure will be described below with continued reference to the accompanying drawings.

[0025] Figure 2 FIG. 2 is a flowchart of a process 200 for layout processing according to some embodiments of the present disclosure. Figure 1 These embodiments are described with reference to the environment 100 of FIG. Figure 1 It should be understood that the method 200 may further include additional blocks not shown and / or may omit one (or some) of the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0026] In block 210, based on the splitting conditions related to the layout splitting of the initial layout, the electronic device 110 determines the region association information for the multiple regions in the initial layout. The layout may include a graphical representation formed by placing and routing various electronic components and interconnects on a plane according to certain rules and requirements. Here, the initial layout 120 may be an original layout that has not been split. The initial layout 120 may include multiple divided regions.

[0027] In some embodiments, the electronic device 110 may divide the initial layout 120 into a plurality of regions based on the configuration information of the initial layout 120. The configuration information of the initial layout 120 may include information of the initial layout 120 itself, such as electronic components, layout, wiring, etc., and may also include information of some configurations of the initial layout 120 defined by the user.

[0028] In some embodiments, the configuration information may include hierarchy information and cell information of the initial layout 120. The hierarchy information may include, for example, information about the top level, intermediate level, bottom level, etc. of the layout. Cell information is a type of attribute information of the layout itself. Cells may include, for example, basic elements such as transistors and resistors, or circuit modules such as AND gates and triggers that are composed of multiple basic elements and have specific logical functions. Accordingly, based on the hierarchy information and cell information of the initial layout 120, the initial layout 120 may be divided into multiple cells. For example, in this embodiment, multiple regions may refer to multiple cells.

[0029] Alternatively or additionally, in some embodiments, the configuration information may include type information of the initial layout 120. The type information may include, for example, metal layer information (e.g., may include the 0th metal layer M0, the 1st metal layer M1, the 2nd metal layer M2, or other special types of metal layers) of the initial layout 120, via layer information (e.g., may include a V0 layer for connecting the M0 and M1 layers, a V1 layer for connecting higher-level metal layers such as the M1 and M2 layers), etc., without limitation herein. Accordingly, based on the type information of the initial layout 120, the initial layout 120 may be appropriately divided into a plurality of regions.

[0030] Alternatively or additionally, in some embodiments, the configuration information may include custom information about the layout division size. Such a division size may be, for example, the size of a tile. Accordingly, based on the custom information about the layout split size of the initial layout 120, the initial layout 120 may be divided into a plurality of tiles.

[0031] Alternatively or additionally, in some embodiments, the configuration information may include relevant information of dividing the initial layout 120 according to multiple functions in the initial layout 120 based on the constraints of the splitting conditions. Such functions may include, for example, storage functions, computing functions, etc., and the modules in which they are located may be storage modules, computing modules, etc. It should be noted that when the initial layout 120 is divided according to functional modules, it is necessary to be constrained by splitting conditions such as DRC rules. For example, if two modules have different functions, but both are constrained by DRC rules, the two need to be associated in some and not divided into two areas. Accordingly, based on the constraints of the splitting conditions and the division of relevant information of the initial layout 120 according to multiple functions in the initial layout 120, the initial layout 120 can be divided into multiple areas.

[0032] Thus, the initial layout 120 can be divided into multiple regions according to any one of the above multiple methods or a combination thereof. It should be understood that for different layout division methods, the shape, size, etc. of each of the multiple divided regions are not limited here. This allows users to select different region division methods according to different layouts, thereby preparing for the subsequent splitting of the layout to match with the corresponding mask.

[0033] In some embodiments, the splitting condition may include at least a design rule check DRC rule. The splitting condition may also include other rules for limiting layout splitting. The splitting condition may, for example, include requirements for layout splitting restrictions on geometric rules, electrical rules, process-related rules, etc. in the layout. For example, requirements on the width of lines, the spacing between lines, the size of various graphics (such as rectangles, polygons, etc.), short circuits and open circuits, etc. in the layout. It should be understood that the splitting condition may include any appropriate rules or requirements for limiting layout splitting, which are not limited here.

[0034] Here, the region association information indicates whether two adjacent regions among the multiple regions are related in the layout splitting. It should be noted that the region association information may indicate whether any two adjacent regions among the multiple regions are related in the layout splitting. That is, for each region, whether it is associated with the adjacent region. Figure 3 Let’s discuss in detail how to determine whether two adjacent regions are related in the layout splitting.

[0035] Figure 3 A schematic diagram of an example structure 300 of two adjacent regions according to some embodiments of the present disclosure is shown. The example structure 300 may be located at Figure 1 The example structure 300 may be within the initial layout 120 in the environment 100. Figure 2 An example structure of two adjacent regions involved in process 200.

[0036] like Figure 3 As shown, in some embodiments, two adjacent regions may include an adjacent first region 310 and a second region 320, and the first region 310 and the second region 320 may have a common partition boundary 330. In order to determine region association information for multiple regions, the electronic device 110 may determine whether a first boundary graphic in the first region 310 close to the partition boundary 330 and a second boundary graphic in the second region 320 close to the partition boundary 330 are subject to the splitting condition.

[0037] by Figure 3 For example, the graphics near the partition boundary 330 in the first area 310 include graphics 317 and graphics 318, which can be respectively referred to as first boundary graphics. The graphics near the partition boundary 330 in the second area 320 include graphics 327 and graphics 328, which can be respectively referred to as second boundary graphics. It can be determined whether the graphics 317 and graphics 318 are respectively subject to the splitting conditions such as DRC rules with graphics 327 and graphics 328.

[0038] For example, according to the DRC rules, if the graphics 317 and the graphics 327 need to comply with the DRC rules, then the graphics 317 and the graphics 327 are constrained by the DRC rules. If the graphics 317 and the graphics 327 do not need to comply with any DRC rules, that is, the two are not related, then the graphics 317 and the graphics 327 are not constrained by the DRC rules. Similar judgment methods can also be used for other boundary graphics in the first area 310 and other boundary graphics in the second area 320, which will not be repeated here.

[0039] In some embodiments, if the first boundary graphic and the second boundary graphic are subject to the splitting condition, the electronic device 110 may determine that the first region 310 and the second region 320 are related in the layout splitting. It should be understood that if there is at least one pair of first boundary graphics and second boundary graphics subject to the splitting condition, it may be determined that the first region 310 and the second region 320 are related in the layout splitting. Figure 3 For example, for the boundary graphics in the first region 310 and the second region 320, if only the graphics 317 and the graphics 327 are constrained by the splitting condition, it can be determined that the first region 310 and the second region 320 are related in the layout splitting.

[0040] In some embodiments, if the first boundary graphic and the second boundary graphic are not constrained by the splitting condition, the electronic device 110 can determine that the first area 310 and the second area 320 are not related in the layout splitting. It should be understood that in the first area 310 and the second area 320, if there is no pair of first boundary graphics and second boundary graphics that are constrained by the splitting condition, it can be determined that the first area 310 and the second area 320 are not related in the layout splitting. For example, if the graphics 317 and the graphics 318 are not constrained by the splitting condition with the graphics 327 and the graphics 328 respectively, it can be determined that the first area 310 and the second area 320 are not related in the layout splitting.

[0041] In addition to determining whether two adjacent regions among the multiple regions are related in layout splitting in the above manner, the following exemplary determination manners may also be used. For example, whether two adjacent regions among the multiple regions are related in layout splitting may be determined based on the circuit function of the initial layout 120, the annotation of the layout design, and the like.

[0042] For example, in terms of circuit function, it is possible to determine whether two adjacent regions are related based on the circuit connection relationship of the initial layout 120. Another example is to determine whether there is a logical functional association between two adjacent regions, such as the input port and the output port of the AND gate are respectively in two adjacent regions, and so on. It can be determined that the two adjacent regions are related and cannot be split. In the annotation of the layout design, there may be some annotation information such as symbols, text, colors, etc., which indicate that the two adjacent regions cannot be split, thereby determining the correlation between the two adjacent regions. It should be understood that there can be a variety of suitable ways to determine the correlation of regions.

[0043] In some embodiments, the first boundary graphic near the partition boundary 330 in the first area 310 and the second boundary graphic near the partition boundary 330 in the second area 320 can be determined in the following manner. Specifically, based on the splitting condition, the electronic device 110 can determine the outward expansion size for each area of ​​the multiple areas. Then, based on the outward expansion size and the partition boundary 330, the electronic device 110 can respectively determine the first outward expansion area 325 located in the second area 320 for the first area 310, and the second outward expansion area 315 located in the first area 310 for the second area 320. Accordingly, the electronic device 110 can determine the graphic located in the second outward expansion area 315 in the first area 310 as the first boundary graphic, and determine the graphic located in the first outward expansion area 325 in the second area 320 as the second boundary graphic.

[0044] In some embodiments, in order to determine the expansion size, the electronic device 110 may determine the maximum graphic spacing indicated by the splitting condition as the expansion size. Figure 3 In the example, the outward expansion size may be a horizontal size. It should be understood that the size and expansion direction of the outward expansion size may be determined based on two adjacent regions of different layouts and sizes, etc., and no limitation is made here. By using the maximum graphic spacing as the outward expansion size, the boundary graphic of each region can be accurately, conveniently and quickly determined.

[0045] Return to reference Figure 2 In block 220, if the region association information indicates that the adjacent first region and the second region in the plurality of regions are related in the layout splitting, a coloring result of the first region and a coloring result of the second region are determined based on the correlation between the first region and the second region. Here, the color of the graphic indicates the sub-layout into which the graphic will be split.

[0046] In some embodiments, in order to determine the coloring result of the first area and the coloring result of the second area, based on the splitting condition, the electronic device 110 can perform graphic coloring based on at least two colors on the multiple areas respectively. Then, based on the graphic coloring of the first area and the second area and the correlation between the first area and the second area, the electronic device 110 can determine the coloring result of the first area and the coloring result of the second area.

[0047] In such an embodiment, the multiple regions of the initial layout may be uniformly colored first, and then the first region and the second region may be colored. Here, at least two colors may correspond to at least two sub-layouts, respectively. As an example, if a double patterning technique is to be used, a plurality of regions may be respectively colored based on two colors, so that the colored colors of the two sub-layouts correspond to the two masks, respectively. If a multiple patterning technique is to be used, a plurality of regions may be respectively colored based on multiple colors, so that the colored colors of the plurality of sub-layouts correspond to the plurality of masks, respectively.

[0048] Exemplarily, the electronic device 110 may detect the splitting conditions for the result after the graphic coloring to verify the correlation of adjacent areas. In some embodiments, if the area association information indicates that the third area among the multiple areas is not related to the adjacent areas of the third area in the layout splitting, based on the graphic coloring of the third area, the electronic device 110 may determine the coloring result for the third area. That is to say, for a certain area or some areas among the multiple areas, if they are not correlated with the adjacent areas in the layout splitting, they can be treated as separate areas. As an example, the coloring results of such separate areas can be saved separately.

[0049] In some embodiments, based at least on the coloring result of the first area and the coloring result of the second area, the electronic device 110 may determine the splitting result for the initial layout 120. The splitting result may indicate that each graphic in the initial layout 120 is split into at least two sub-layouts. As an example, if the splitting of the initial layout 120 is for the purpose of using a double patterning technique, the splitting result may indicate that each graphic in the initial layout 120 is split into two sub-layouts. If the splitting of the initial layout 120 is for the purpose of using a multi-patterning technique, the splitting result may indicate that each graphic in the initial layout 120 is split into multiple sub-layouts. It should be understood that the number of sub-layouts into which the initial layout 120 is split can be set according to the lithography technology to be used.

[0050] Here, the coloring result of the first area and the coloring result of the second area can be used as at least a part of the split result. The coloring result of the third area can be used as at least another part of the split result. Thus, for the adjacent areas with correlation in the multiple areas, and the separate areas that are not related to the adjacent areas, each has its own coloring result. Accordingly, by merging these coloring results of the multiple areas, the split result of the initial layout 120 can be determined.

[0051] In some embodiments, in order to further determine the coloring result of the first area 310 and the coloring result of the second area 320, the electronic device 110 can align the colors of the first boundary graphic and the second boundary graphic constrained by the splitting condition in the first area 310 and the second area 320. Because the coloring of the graphics based on at least two colors is performed on multiple areas respectively as discussed above, it belongs to the initial coloring, and the initial coloring does not take into account the graphics located in different areas constrained by the splitting condition. Since the first boundary graphic and the second boundary graphic constrained by the splitting condition will correspond to the same mask, the coloring needs to be updated to make the coloring colors of the two consistent. How to align the colors of the first boundary graphic and the second boundary graphic constrained by the splitting condition will be discussed in detail below.

[0052] Then, the electronic device 110 can determine the target boundary graphic whose color changes through color alignment from the first boundary graphic and the second boundary graphic. Further, based on the color change of the target boundary graphic, the electronic device 110 can perform a coloring transformation on the target area where the target boundary graphic is located to determine the coloring result of the target area. The target area can be the first area 310 or the second area 320.

[0053] by Figure 3 For example, if the coloring color of the graphic 317 is the first color and the coloring color of the graphic 327 is the second color during the initial coloring, assuming that the coloring colors of the two are to be aligned to the first color during the coloring update, then the target boundary graphic that undergoes color change through the color alignment can be determined to be the graphic 327. Furthermore, based on the coloring color of the graphic 327 being transformed from the second color to the first color, a coloring transformation (also referred to as color flipping) can be performed on the second region 320 where the graphic 327 is located, thereby determining the coloring result of the second region 320. Taking the non-boundary graphic 322 in the second region 320 as an example, assuming that the graphic 322 and the graphic 327 are subject to the splitting condition, and the initial coloring color of the graphic 322 is the first color, then after the coloring transformation of the second region 320, the coloring color of the graphic 322 will be updated to the second color.

[0054] Thus, by sequentially performing initial coloring, update coloring, and color flipping, the coloring effect of multiple regions can be ensured, and coloring confusion or coloring errors can be avoided, which further ensures the accuracy of the layout splitting.

[0055] In addition to determining the coloring result of the first area and the coloring result of the second area by initial coloring, updated coloring, and color flipping as discussed above, there may be other ways to determine the coloring result of the first area and the coloring result of the second area. In other embodiments, in order to determine the coloring result of the first area and the coloring result of the second area, the electronic device 110 may determine the coloring result of the first area and the coloring result of the second area based on the correlation between the first area and the second area, and then perform graphic coloring on other areas of the multiple areas except the first area and the second area with correlation to determine the coloring result of the other areas. As an example, the electronic device 110 may first align the colors of the first boundary graphic and the second boundary graphic constrained by the splitting condition in the first area and the second area, and then for each area in the multiple areas, perform a coloring transformation on other graphics in the area based on the coloring color of the respective boundary graphics, that is, flip the color.

[0056] In some embodiments, in order to align the colors of the first boundary graphic and the second boundary graphic, based on the first boundary graphic and the second boundary graphic, the electronic device 110 can construct a structured representation corresponding to at least the first area and the second area. Then, the electronic device 110 can color the graphics in the structured representation to align the colors of the first boundary graphic and the second boundary graphic.

[0057] It should be understood that the structured representation is not for individual regions that are not related to adjacent regions. As an example, the structured representation can be an undirected weighted graph. In other examples, the structured representation can also be any other appropriate type of representation for a layout graphic. In such an embodiment, the structured representation can be equivalent to abstracting the initial layout 120 into a representation that includes at least a first boundary graphic and a second boundary graphic.

[0058] In some embodiments, the structured representation may include: nodes (Node) corresponding to the first boundary graphic and the second boundary graphic respectively; a first link (also called the same link) representing the association between the first boundary graphic and the second boundary graphic; a second link (also called a combined link) representing the association between the first boundary graphic and other graphics in the first area where it is located; and a second link representing the association between the second boundary graphic and other graphics in the second area where it is located.

[0059] In such an embodiment, each pair of first boundary graphs and second boundary graphs constrained by the splitting condition in multiple regions can be abstracted as nodes, the association relationship between the first boundary graph and the second boundary graph can be abstracted as a first link, and the association relationship between the first boundary graph and other graphs in the first region and the association relationship between the second boundary graph and other graphs in the second region can be abstracted as second links. Thus, a structured representation of the initial layout 120 can be constructed. Then, by updating and coloring the graphs in the structured representation, the colors of the first boundary graph and the second boundary graph can be aligned.

[0060] In some embodiments, the first link may be configured with a corresponding weight. For example, when the structured representation is an undirected weighted graph, a corresponding weight may be configured for each first link. In order to color the graph in the structured representation, if there are multiple first links between the first region and the second region, and the weight of the target first link among the multiple first links is greater than the weights of the other first links, the electronic device 110 may color the graph in the structured representation based on the first boundary graph and the second boundary graph corresponding to the target first link.

[0061] Since there may be multiple first boundary graphics in the first area and multiple second boundary graphics in the second area, when updating the coloring, it is necessary to select a pair of first boundary graphics and second boundary graphics to determine the color of the updated coloring. As an example, the first link with the largest weight can be selected from multiple first links, so as to update the coloring based on the first boundary graphics and the second boundary graphics corresponding to the first link with the largest weight. This can improve the efficiency and effectiveness of updating the coloring of adjacent areas with correlation.

[0062] Therefore, by abstracting the structured representation of the initial layout, it is convenient to update the graphic coloring of the associated adjacent areas, which further speeds up the efficiency of layout splitting.

[0063] In some embodiments, based on the split result of the initial layout, the electronic device 110 may perform a test on the first boundary graphic and the second boundary graphic associated through the first link regarding the split condition to verify the split result. In order to determine that the association between the first area and the second area is based on the split condition, rather than being erroneously associated for other reasons, a test on the split condition or a conflict test may be performed on the associated first boundary graphic and the second boundary graphic.

[0064] As an example, if it is detected that two associated regions are not based on the splitting condition, and the boundary graphics of the two regions are not constrained by the splitting condition, the two regions can be treated as separate regions. Accordingly, the coloring and color inversion of the two regions can be updated. If it is detected that each pair of associated regions in multiple regions is based on the splitting condition, it is determined that the splitting result is correct. Such further verification can ensure the accuracy of the splitting result.

[0065] The embodiments of the present disclosure determine the association information of multiple areas divided by the initial layout by combining the splitting conditions, and determine the coloring results of the associated areas, so as to determine the splitting results for the initial layout. Such a layout splitting scheme can speed up the efficiency and accuracy of layout splitting. In addition, according to the correlation or irrelevance of adjacent areas in multiple areas, the associated adjacent areas and the separate areas that do not have associations with other areas can be respectively corresponded to distributions. In this way, calculations for different areas can be performed in parallel by corresponding distributed nodes. By synchronizing the calculation results of each distributed node, the effects of accelerating calculations and reducing memory can be achieved, and the memory and running time of the initial layout are effectively reduced on advanced nodes.

[0066] Figure 4 4 shows a block diagram of an electronic device 400 in which one or more embodiments of the present disclosure may be implemented. It should be understood that Figure 4 The electronic device 400 shown is merely exemplary and should not constitute any limitation on the functionality and scope of the embodiments described herein. Figure 4 The electronic device 400 shown can be used to implement Figure 1 An electronic device 110.

[0067] like Figure 4 As shown, the electronic device 400 is in the form of a general electronic device. The components of the electronic device 400 may include, but are not limited to, one or more processors or processing units 410, a memory 420, a storage device 430, one or more communication units 440, one or more input devices 450, and one or more output devices 460. The processing unit 410 may be an actual or virtual processor and is capable of performing various processes according to a program stored in the memory 420. In a multi-processor system, multiple processing units execute computer executable instructions in parallel to improve the parallel processing capability of the electronic device 400.

[0068] The electronic device 400 typically includes a plurality of computer storage media. Such media may be any accessible media accessible to the electronic device 400, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 420 may be a volatile memory (e.g., a register, a cache, a random access memory (RAM)), a non-volatile memory (e.g., a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 430 may be a removable or non-removable medium, and may include a machine-readable medium, such as a flash drive, a disk, or any other medium, which may be capable of being used to store information and / or data (e.g., training data for training) and may be accessed within the electronic device 400.

[0069] The electronic device 400 may further include additional removable / non-removable, volatile / non-volatile storage media. Figure 4 As shown in , a disk drive for reading or writing from a removable, non-volatile disk (e.g., a "floppy disk") and an optical drive for reading or writing from a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to the bus (not shown) by one or more data media interfaces. The memory 420 may include a computer program product 425 having one or more program modules that are configured to perform various methods or actions of various embodiments of the present disclosure.

[0070] The communication unit 440 implements communication with other electronic devices through a communication medium. Additionally, the functions of the components of the electronic device 400 can be implemented in a single computing cluster or multiple computing machines that can communicate through a communication connection. Therefore, the electronic device 400 can operate in a networked environment using a logical connection with one or more other servers, a network personal computer (PC), or another network node.

[0071] The input device 450 may be one or more input devices, such as a mouse, a keyboard, a tracking ball, etc. The output device 460 may be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 400 may also communicate with one or more external devices (not shown) through the communication unit 440 as needed, such as a storage device, a display device, etc., communicate with one or more devices that allow a user to interact with the electronic device 400, or communicate with any device (e.g., a network card, a modem, etc.) that allows the electronic device 400 to communicate with one or more other electronic devices. Such communication may be performed via an input / output (I / O) interface (not shown).

[0072] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, wherein the computer-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the method described above.

[0073] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices, equipment, and computer program products implemented according to the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0074] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0075] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0076] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple implementations of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some implementations as replacements, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0077] The above descriptions of various implementations of the present disclosure are exemplary, non-exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The selection of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to the technology in the marketplace, or to enable other persons of ordinary skill in the art to understand the various implementations disclosed herein.

Claims

1. A layout processing method, characterized in that: The method comprises: Determining, based on a splitting condition related to layout splitting of an initial layout, region association information for a plurality of regions in the initial layout, the region association information indicating whether two adjacent regions in the plurality of regions are related in the layout splitting; and In response to the region association information indicating that adjacent first and second regions among the multiple regions are related in the layout splitting, based on the correlation between the first region and the second region, a coloring result of the first region and a coloring result of the second region are determined, wherein the color of the graphic indicates the sub-layout into which the graphic will be split.

2. The method according to claim 1, characterized in that The first area and the second area have a common division boundary, and determining the area association information for the plurality of areas includes: determining whether a first boundary graphic close to the division boundary in the first region and a second boundary graphic close to the division boundary in the second region are constrained by the splitting condition; and In response to the first boundary graphic and the second boundary graphic being constrained by the splitting condition, it is determined that the first region and the second region are related in layout splitting.

3. The method according to claim 2, characterized in that The method further includes determining a first boundary graphic close to the partition boundary in the first region and a second boundary graphic close to the partition boundary in the second region by: Based on the splitting condition, determining an outward expansion size for each of the multiple regions; Based on the expansion size and the division boundary, respectively determine a first expansion region located in the second region for the first region and a second expansion region located in the first region for the second region; as well as A graphic in the first region that is located within the second expanded region is determined as the first boundary graphic, and a graphic in the second region that is located within the first expanded region is determined as the second boundary graphic.

4. The method according to claim 3, characterized in that: Determining the external expansion size includes: The maximum graphic spacing indicated by the splitting condition is determined as the external expansion size.

5. The method according to claim 1, characterized in that Determining a coloring result of the first area and a coloring result of the second area includes: Based on the splitting condition, respectively performing graphic coloring based on at least two colors on the multiple regions, wherein the at least two colors correspond to the at least two sub-layouts respectively; and Based on the graphic coloring of the first region and the second region and the correlation between the first region and the second region, a coloring result of the first region and a coloring result of the second region are determined.

6. The method according to claim 5, characterized in that The method further comprises: In response to the region association information indicating that a third region among the multiple regions is not related to adjacent regions of the third region in layout splitting, a coloring result for the third region is determined based on coloring the graph of the third region.

7. The method according to claim 5, characterized in that Determining the coloring result of the first area and the coloring result of the second area further includes: Aligning the colors of a first boundary graphic and a second boundary graphic in the first area and the second area that are subject to the splitting condition; determining a target boundary graphic whose color is changed by the color alignment from the first boundary graphic and the second boundary graphic; and Based on the color change of the target boundary graphic, a coloring transformation is performed on a target region where the target boundary graphic is located to determine a coloring result of the target region, where the target region is the first region or the second region.

8. The method according to claim 7, characterized in that Aligning the colors of the first boundary graphic and the second boundary graphic includes: constructing a structured representation corresponding to at least the first region and the second region based on the first boundary graphic and the second boundary graphic; and The graphics in the structured representation are colored so that the colors of the first boundary graphic and the second boundary graphic are aligned.

9. The method according to claim 8, characterized in that The structured representation includes: nodes corresponding to the first boundary graph and the second boundary graph respectively; a first link representing an association between the first boundary graphic and the second boundary graphic; a second link representing an association between the first boundary graphic and other graphics in the first region where the first boundary graphic is located; and A second link representing an association between the second boundary graphic and other graphics in the second area where the second boundary graphic is located.

10. The method according to claim 9, characterized in that The first links are configured with corresponding weights, and coloring the graph in the structured representation comprises: If there are multiple first links between the first area and the second area, and the weight of the target first link among the multiple first links is greater than the weights of other first links, the graph in the structured representation is colored based on the first boundary graph and the second boundary graph corresponding to the target first link.

11. The method according to claim 1, characterized in that: The method further comprises: Based at least on the coloring result of the first area and the coloring result of the second area, a splitting result for the initial layout is determined, and the splitting result indicates that each graphic in the initial layout is split into at least two sub-layouts.

12. The method according to claim 9, characterized in that The method further comprises: Based on the splitting result of the initial layout, the first boundary graphic and the second boundary graphic associated through the first link are checked for the splitting condition to verify the splitting result, wherein the splitting result indicates that each graphic in the initial layout is split into at least two sub-layouts.

13. The method according to claim 1, characterized in that The method further comprises: Based on the configuration information of the initial layout, the initial layout is divided into the multiple areas, The configuration information includes at least one of the following: The hierarchical structure information and unit information of the initial layout, The type information of the initial layout, Customized information about the size of the layout division, or related information about dividing the initial layout according to multiple functions in the initial layout based on the constraints of the splitting conditions.

14. The method according to claim 1, characterized in that The splitting condition at least includes a design rule check (DRC) rule.

15. An electronic device, characterized in that: include: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 14 when executed by the at least one processing unit.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executable by a processor to implement the method according to any one of claims 1 to 14.

17. A computer program product comprising computer executable instructions, characterized in that: The computer executable instructions implement the method according to any one of claims 1 to 14 when executed by a processor.

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