Gate drive circuit, display panel and display device

Abstract

The invention relates to a gate drive circuit, a display panel and a display device, and relates to the technical field of display. The gate driving circuit comprises a driving module which is electrically connected with a bias module of a pixel circuit and is used for providing a bias control signal; the control module is electrically connected with the driving module, and a bias module and an anode reset module of the pixel circuit, and is used for receiving a bias control signal, a first light-emitting control signal, a first power supply signal and a second power supply signal and outputting a grid control signal; wherein the first light-emitting control signal and a second light-emitting control signal received by the pixel circuit are provided by two different light-emitting control circuits, and the effective pulse width of the grid control signal is smaller than the effective pulse width of the bias control signal. By multiplexing the bias control signal and the first floating light control signal, the grid control signal with the effective pulse width smaller than that of the bias control signal can be output, the color cast phenomenon is improved, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display panels are more and more widely used, and users have higher and higher requirements for the display quality of display panels. However, existing display panels still have the problem of poor display effects and cannot fully meet the application requirements of display panels. Summary of the invention

[0003] Based on this, it is necessary to provide a gate driving circuit, a display panel and a display device, which are helpful to improve the display effect of the display panel.

[0004] In a first aspect, an embodiment of the present application provides a gate driving circuit, including:

[0005] A driving module, electrically connected to the bias module of the pixel circuit, for providing a bias control signal;

[0006] A control module, electrically connected to the driving module, and the bias module and the anode reset module of the pixel circuit, respectively, for receiving the bias control signal, the first light emitting control signal, the first power supply signal and the second power supply signal, and outputting a gate control signal;

[0007] The first light-emitting control signal and the second light-emitting control signal received by the pixel circuit are provided by two different light-emitting control circuits, and the effective pulse width of the gate control signal is smaller than the effective pulse width of the bias control signal.

[0008] In a second aspect, an embodiment of the present application provides a display panel, which includes a pixel circuit and a gate driving circuit as described above.

[0009] In a third aspect, an embodiment of the present application provides a display device, which includes the display panel as described above.

[0010] The gate driving circuit, display panel and display device provided in the embodiments of the present application provide a bias control signal for the bias module in the pixel circuit through the driving module, and output the gate control signal through the control module according to the bias control signal, the first light control signal, the first power signal and the second power signal to provide it to the anode reset module of the pixel circuit, which can meet the anode reset requirement of the light-emitting element electrically connected to the pixel circuit. Since the effective pulse width of the gate control signal is smaller than the effective pulse width of the bias control signal, the problem of color deviation caused by the wide effective pulse width of the signal provided to the anode reset module is improved. Compared with the method of directly providing the bias control signal to the anode reset module to reset the anode of the light-emitting element, the present application regulates the bias control signal through the first light control signal on the basis of multiplexing the bias control signal, so as to obtain a gate control signal with an effective pulse width smaller than the bias control signal, which can meet both the bias reset requirement of the pixel circuit and the anode reset requirement of the light-emitting element, thereby facilitating the improvement of the display effect of the display panel. In addition, the first light control signal and the second light control signal received by the pixel circuit are provided by two different light control circuits, that is, by multiplexing the light control signal in the display panel, there is no need to set a new signal, which helps to achieve a narrow frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application;

[0012] Figure 2 A schematic diagram of the structure of a pixel circuit and a light-emitting element provided in an embodiment of the present application;

[0013] Figure 3 One of the timing diagrams of a bias control signal, a first light-emitting control signal, a second light-emitting control signal and a gate-controlled signal provided in an embodiment of the present application;

[0014] Figure 4 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0015] Figure 5 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0016] Figure 6 A second timing diagram of a bias control signal, a first light-emitting control signal, a second light-emitting control signal and a gate-controlled signal provided in an embodiment of the present application;

[0017] Figures 7 to 16 They are schematic diagrams of the structures of the control modules provided in the embodiments of the present application;

[0018] Figures 17 to 30Schematic diagrams of the timing of the bias control signal, the first light-emitting control signal, the second light-emitting control signal and the gate control signal provided in the embodiments of the present application;

[0019] Fig.31 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0020] Description of reference numerals:

[0021] Gate drive circuit 10, drive module 11, control module 12, first control unit 121, first regulating subunit 1211, second control unit 122, second regulating subunit 1221, third regulating subunit 1222, pixel circuit 20, bias module 21, anode reset module 22, light emitting control module 23, light emitting control circuit 30, display panel 100, display device 1000. DETAILED DESCRIPTION

[0022] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0024] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0025] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0026] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0027] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0028] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0029] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0030] The display panel in the related art is prone to color deviation and poor display effect. The inventor found that the reason for the above phenomenon is that in the pixel circuit of the display panel, the anode reset module realizes narrow frame by reusing the bias control signal of the bias module, wherein the bias module performs bias reset (OBS) on the driving transistor under the control of the bias control signal, and the anode reset module resets the anode of the light-emitting element by reusing the bias control signal. However, in order to meet the bias reset requirements of the driving transistor, the effective pulse width of the bias control signal is relatively wide, which will cause the anode of the light-emitting element to be brushed for a long time, and the coupling capacitor between the light-emitting element and other structures in the display panel will be reset at a deep energy level, resulting in color deviation problems, especially in high temperature and RA (Reliability-Ageing, reliability aging test) The color brightness is more different from that at normal temperature, resulting in obvious deterioration of performance such as heating and RA color deviation.

[0031] Based on the above technical problems, the inventors have found that by providing a bias control signal through a driving module, and generating a gate control signal through a control module according to the bias control signal and the light-emitting control signal, the effective pulse width of the gate control signal is less than the effective pulse width of the bias control signal, and compared with directly using the bias control signal to the anode of the light-emitting element, the effective pulse width of the gate control signal is reduced, thereby improving the color shift phenomenon. Based on this, the inventors further studied the technical solution of the embodiment of the present application. Specifically, the gate driving circuit provided in the embodiment of the present application includes a driving module and a control module, wherein the driving module is electrically connected to the bias module of the pixel circuit, the driving module is used to provide a bias control signal, the control module is electrically connected to the driving module, and the bias module and anode reset module of the pixel circuit, respectively, and the control module is used to receive the bias control signal, the first light-emitting control signal, the first power supply signal and the second power supply signal, and output the gate control signal, wherein the first light-emitting control signal and the second light-emitting control signal received by the pixel circuit are provided by two different light-emitting control circuits, and the effective pulse width of the gate control signal is less than the effective pulse width of the bias control signal. By adopting the above technical solution, the control module multiplexes the bias control signal provided by the driving module and the first light-emitting control signal in the display panel, and outputs a gate control signal with an effective pulse width less than the bias control signal. This improves the phenomenon of color deviation caused by a long reset time of the anode of the light-emitting element due to the wide effective pulse width caused by directly using the bias control signal. This helps to improve the display effect of the display panel, can meet the bias reset requirements of the pixel circuit, and can also meet the anode reset requirements of the pixel circuit. There is no need to set a new signal, which helps to achieve a narrow border.

[0032] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] Figure 1 A schematic diagram of the structure of a gate drive circuit 10 provided in an embodiment of the present application is shown in FIG. Figure 2 A schematic diagram of the structure of a pixel circuit 20 and a light-emitting element D provided in an embodiment of the present application is shown in FIG. Figure 3 A timing diagram of a bias control signal SPX, a first light emitting control signal EM(n), a second light emitting control signal EM and a gate control signal SPX1 provided in an embodiment of the present application. Figures 1 to 3 As shown, in one embodiment, a gate driving circuit 10 is provided. The gate driving circuit 10 includes a driving module 11 and a control module 12 .

[0034] The driving module 11 is electrically connected to the bias module 21 of the pixel circuit 20, and the driving module 11 is used to provide a bias control signal SPX. It should be noted that the driving module 11 is intended to provide the bias control signal SPX, and the driving module 11 can adopt any suitable circuit structure, which is not limited too much here. Among them, the bias module 21 is used to bias reset the driving transistor T0 in the pixel circuit 20 under the control of the bias control signal SPX. Exemplarily, the bias module 21 includes a bias transistor T1, the driving module 11 is electrically connected to the gate of the bias transistor T1, the first electrode of the bias transistor T1 is electrically connected to the first electrode of the driving transistor T0 in the pixel circuit 20, and the second electrode of the bias transistor T1 is used to receive the bias signal DVH, and the bias transistor T1 is used to be in a conductive state in response to the enable pulse of the bias control signal SPX, and bias reset the driving transistor T0 through the bias signal DVH.

[0035] The control module 12 is electrically connected to the driving module 11, and the bias module 21 and the anode reset module 22 of the pixel circuit 20, respectively. The input end of the control module 12 is electrically connected to the driving module 11 and the bias module 21, respectively, and the first output end OUT of the control module 12 is electrically connected to the anode reset module 22. The control module 12 is used to receive the bias control signal SPX, the first light-emitting control signal EM(n), the first power supply signal and the second power supply signal, and output the gate control signal SPX1. The anode reset module 22 is used to reset the anode of the light-emitting element D electrically connected to the anode reset module 22 under the control of the gate control signal SPX1. The first power supply signal and the second power supply signal are different. One of the first power supply signal and the second power supply signal is a high level signal VGH, and the other is a low level signal VGL. Exemplarily, the anode reset module 22 includes an anode reset transistor T2, the control module 12 is electrically connected to the gate of the anode reset transistor T2, the first electrode of the anode reset transistor T2 is used to receive the anode reset signal Vref1, the second electrode of the anode reset transistor T2 is electrically connected to the anode of the light-emitting element D, and the anode reset transistor T2 is used to be in a conductive state in response to the enable pulse of the gate control signal SPX1, and reset the anode of the light-emitting element D through the anode reset signal Vref1.

[0036] The first light-emitting control signal EM(n) and the second light-emitting control signal EM received by the pixel circuit 20 are provided by two different light-emitting control circuits 30. The light-emitting control circuit 30 is used to provide a light-emitting control signal. Different light-emitting control circuits 30 are electrically connected to the light-emitting control modules 23 of different pixel circuits 20 in the display panel. The light-emitting control module 23 is used to control the light-emitting element D under the control of the second light-emitting control signal EM. The two light-emitting control circuits 30 that respectively provide the first light-emitting control signal EM(n) and the second light-emitting control signal EM are cascaded with each other. Moreover, of the two light-emitting control circuits 30 that respectively provide the first light-emitting control signal EM(n) and the second light-emitting control signal EM, one light-emitting control circuit 30 is electrically connected to the control module 12 in the gate driving circuit 10 to provide the first light-emitting control signal EM(n), and the other light-emitting control circuit 30 is electrically connected to the light-emitting control module 23 in the pixel circuit 20 that is electrically connected to the gate driving circuit 10 to provide the second light-emitting control signal EM. Exemplarily, the light-emitting control module 23 includes a first light-emitting control transistor T3 and a second light-emitting control transistor T4, wherein the first electrode of the first light-emitting control transistor T3 receives the first level signal PVDD, the second electrode of the first light-emitting control transistor T3 is electrically connected to the first electrode of the driving transistor T0 and the second electrode of the bias transistor T1, respectively, the first electrode of the second light-emitting control transistor T4 is electrically connected to the second electrode of the driving transistor T0, the second electrode of the second light-emitting control transistor T4 is electrically connected to the second electrode of the anode reset transistor T2 and the anode of the light-emitting element D, respectively, and the gate of the first light-emitting control transistor T3 and the gate of the second light-emitting control transistor T4 receive the second light-emitting control signal EM, respectively.

[0037] The effective pulse width d1 of the gate control signal SPX1 is smaller than the effective pulse width d2 of the bias control signal SPX. The effective pulse width d1 of the gate control signal SPX1 is respectively related to the effective pulse width d2 of the bias control signal SPX and the effective pulse width of the first light-emitting control signal EM(n). The effective pulse width d1 of the gate control signal SPX1 can be specifically set according to factors such as the anode reset requirement of the light-emitting element D and the display effect requirement of the display panel, which are not limited here. In the application, after determining the effective pulse width d1 of the gate control signal SPX1 according to the requirements, the appropriate first light-emitting control signal EM(n) can be selected to output the gate control signal SPX1 that meets the effective pulse width design requirements.

[0038] The gate driving circuit 10 provided in the above embodiment provides a bias control signal SPX to the bias module 21 in the pixel circuit 20 through the driving module 11, and outputs a gate control signal SPX1 to the anode reset module 22 of the pixel circuit 20 according to the bias control signal SPX, the first light emitting control signal EM(n), the first power supply signal and the second power supply signal through the control module 12, so as to meet the anode reset requirement of the light emitting element D electrically connected to the pixel circuit 20. Since the effective pulse width d1 of the gate control signal SPX1 is smaller than the effective pulse width d2 of the bias control signal SPX, the problem of the anode reset module 22 being caused by the wide effective pulse width of the signal provided to the anode reset module 22 is improved. Regarding the color deviation problem, compared with the method of directly providing the bias control signal SPX to the anode reset module 22 to reset the anode of the light-emitting element D, the present application uses the control module 12 to adjust the bias control signal SPX according to the first light-emitting control signal EM(n) on the basis of the bias control signal SPX, and obtains the gate control signal SPX1 with an effective pulse width less than the bias control signal SPX, which can meet the bias reset requirements of the pixel circuit 20 and the anode reset requirements of the light-emitting element D, thereby helping to improve the display effect of the display panel. In addition, this solution reuses the light-emitting control signals existing in the display panel without setting new signals, which helps to achieve a narrow border.

[0039] Please continue reading Figure 3 In one embodiment, the effective pulse width d2 of the bias control signal SPX overlaps with the effective pulse width of the first light-emitting control signal EM(n), and the effective pulse width d1 of the gate control signal SPX1 is equal to the overlap width between the effective pulse width d2 of the bias control signal SPX and the effective pulse width of the first light-emitting control signal EM(n), and the overlap width is smaller than the effective pulse width d2 of the bias control signal SPX. In applications, the overlap width between the effective pulse width d2 of the bias control signal SPX and the effective pulse width of the first light-emitting control signal EM(n) can be adjusted by adjusting the timing relationship between the bias control signal SPX and the first light-emitting control signal EM(n), thereby effectively adjusting the effective pulse width d1 of the gate control signal SPX1, so as to obtain the gate control signal SPX1 whose effective pulse width is smaller than the bias control signal SPX, thereby improving the color deviation caused by the wide effective pulse width of the signal provided to the anode reset module 22, and helping to improve the display effect of the display panel.

[0040] Figure 4 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Figure 5 A schematic diagram of the structure of another display panel provided in an embodiment of the present application. Figures 1 to 5In one embodiment, the first light control signal EM(n) is provided by the i+n-th level light control circuit 30, and the second light control signal EM is provided by the i-th level light control circuit 30. That is, the i+n-th level light control circuit 30 provides the first light control signal EM(n) to the driving module 11, and the i-th level light control circuit 30 provides the second light control signal EM to the pixel circuit 20 electrically connected to the driving module 11. The i+n-th level light control circuit 30 and the i-th level light control circuit 30 are cascaded. There are n levels between the i+n-th level light control circuit 30 and the i-th level light control circuit 30.

[0041] The effective pulse width d1 of the gate control signal SPX1 output by the control module 12 is related to n. The value of n affects the timing relationship between the bias control signal SPX and the first light-emitting control signal EM(n) received by the control module 12, thereby affecting the overlap width between the effective pulse width d2 of the bias control signal SPX and the effective pulse width of the first light-emitting control signal EM(n), and further affecting the effective pulse width d1 of the gate control signal SPX1.

[0042] Wherein, n is an integer not equal to 0. n can be a positive integer or a negative integer. When n is a positive integer, the i+nth level light emitting control circuit 30 providing the first light emitting control signal EM(n) is the nth level after the i-th level light emitting control circuit 30 providing the second light emitting control signal EM; for example, Figure 4 The display panel shown in FIG. 1 is a display panel in which n is 1. When n is a negative integer, the i+nth level light emitting control circuit 30 providing the first light emitting control signal EM(n) is the first n levels of the i-th level light emitting control circuit 30 providing the second light emitting control signal EM; for example, Figure 5 In the display panel shown, n is -1. The specific value of n can be determined according to factors such as the effective pulse width required by the gate control signal SPX1, the effective pulse width d2 of the bias control signal SPX, and the effective pulse width of the first light emitting control signal EM(n).

[0043] In the application, after determining the effective pulse width d1 of the gate control signal SPX1 according to the pulse width requirement, the timing relationship between the bias control signal SPX received by the control module 12 and the first light-emitting control signal EM(n) is adjusted by adjusting the size of n, until the overlapping width between the effective pulse width d2 of the bias control signal SPX and the effective pulse width of the first light-emitting control signal EM(n) satisfies the effective pulse width d1 of the gate control signal SPX1, thereby determining the value of n.

[0044] The above-mentioned gate driving circuit 10 provides a first light-emitting control signal EM(n) to the driving module 11 through the i+n-th level light-emitting control circuit 30, and provides a second light-emitting control signal EM to the pixel circuit 20 electrically connected to the driving module 11 through the i-th level light-emitting control circuit 30. In this way, for the electrically connected gate driving circuit 10 and the pixel circuit 20, two light-emitting control circuits 30 that are offset by n levels are used to provide the first light-emitting control signal EM(n) to the gate control circuit, and to provide the second light-emitting control signal EM to the pixel circuit 20, so as to obtain a gate control signal SPX1 whose effective pulse width meets the requirements, thereby achieving the purpose of improving the display performance of the display panel.

[0045] Please continue reading Figure 3 and Figure 4 In one embodiment, the effective pulse width d1 of the gate control signal SPX1 is equal to the time interval between the start time of the enable pulse of the bias control signal SPX and the end time of the enable pulse of the first light-emitting control signal EM(n), and n is a positive integer. The end time of the enable pulse of the bias control signal SPX is earlier than the end time of the enable pulse of the first light-emitting control signal EM(n), so as to ensure that the effective width of the gate control signal SPX1 is less than the effective pulse width d2 of the bias control signal SPX, so as to improve the display effect of the display panel. When n is a positive integer, the i+nth level light-emitting control circuit 30 that provides the first light-emitting control signal EM(n) is the nth level after the i-th level light-emitting control circuit 30 that provides the second light-emitting control signal EM. In this case, the first light-emitting control signal EM(n) provided to the control module 12 lags behind the second light-emitting control signal EM provided to the pixel circuit 20 electrically connected to the control module 12.

[0046] Figure 6 Another timing diagram of the bias control signal SPX, the first light emitting control signal EM(n), the second light emitting control signal EM and the gate control signal SPX1 provided in the embodiment of the present application. Figure 5 and Figure 6In one embodiment, the effective pulse width d1 of the gate control signal SPX1 is equal to the time interval between the end time of the enable pulse of the bias control signal SPX and the start time of the enable pulse of the first light-emitting control signal EM(n), and n is a negative integer. The start time of the enable pulse of the bias control signal SPX is earlier than the start time of the enable pulse of the first light-emitting control signal EM(n), so as to ensure that the effective width of the gate control signal SPX1 is less than the effective pulse width d2 of the bias control signal SPX, so as to improve the display effect of the display panel. When n is a negative integer, the i+nth level light-emitting control circuit 30 that provides the first light-emitting control signal EM(n) is the nth level after the i-th level light-emitting control circuit 30 that provides the second light-emitting control signal EM. In this case, the second light-emitting control signal EM provided to the pixel circuit 20 electrically connected to the control module 12 lags behind the first light-emitting control signal EM(n) provided to the control module 12.

[0047] Figures 7 to 16 They are schematic diagrams of the structure of the control module 12 provided in the embodiments of the present application. Figures 1 to 16 In one embodiment, the control module 12 includes a first input terminal IN1, a second input terminal IN2 and a first output terminal OUT. Among them, one of the first input terminal IN1 and the second input terminal IN2 is electrically connected to the driving module 11 and receives the bias control signal SPX, and the other receives the first light-emitting control signal EM(n). Exemplarily, the first input terminal IN1 of the control module 12 is electrically connected to the driving module 11 and receives the bias control signal SPX provided by the driving module 11, and the second input terminal IN2 of the control module 12 receives the first light-emitting control signal EM(n). In another exemplary embodiment, the second input terminal IN2 of the control module 12 is electrically connected to the driving module 11 and receives the bias control signal SPX provided by the driving module 11, and the first input terminal IN1 of the control module 12 receives the first light-emitting control signal EM(n). The first output terminal OUT of the control module 12 is used to be electrically connected to the anode reset module 22 in the pixel circuit 20.

[0048] The control module 12 also includes a first control unit 121 and a second control unit 122. The first control unit 121 is electrically connected to the first input terminal IN1, the first node N1, and the second node N2, respectively. The first control unit 121 is used to control the first node signal of the first node N1 and the second node signal of the second node N2, respectively, according to the received first power signal and the control signal of the first input terminal IN1. The second control unit 122 is electrically connected to the second input terminal IN2, the first node N1, the second node N2, and the first output terminal OUT, respectively. The second control unit 122 is used to control the gate control signal SPX1 output by the first output terminal OUT, according to the received second power signal, the control signal of the second input terminal IN2, the first node signal, and the second node signal. One of the control signal of the first input terminal IN1 and the control signal of the second input terminal IN2 is the bias control signal SPX, and the other is the first light-emitting control signal EM(n).

[0049] The above-mentioned gate drive circuit 10 can effectively control the first node signal and the second node signal through the first control unit 121 according to the first power supply signal and the control signal of the first input terminal IN1, and can effectively control the gate control signal SPX1 through the second control unit 122 according to the second power supply signal, the control signal of the second input terminal IN2, the first node signal and the second node signal, so as to output the gate control signal SPX1 with an effective pulse width smaller than the bias control signal SPX, thereby achieving the purpose of improving the display effect of the display panel.

[0050] Please continue reading Figures 7 to 16 In one embodiment, the first control unit 121 includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is electrically connected to the gate of the second transistor M2. The gate of the first transistor M1 is used to be electrically connected to the first input terminal IN1. Exemplarily, the first transistor M1 is directly electrically connected to the first input terminal IN1. In another exemplary embodiment, the first transistor M1 is indirectly electrically connected to the first input terminal IN1, and the details can be found in the following related introduction. The first electrode of the first transistor M1 receives a first power supply signal. The second electrode of the first transistor M1 is electrically connected to the first node N1 and the first end of the second control unit 122, respectively. The first electrode of the second transistor M2 is electrically connected to the second node N2 and the second end of the second control unit 122, respectively. The second electrode of the second transistor M2 receives a second power supply signal.

[0051] In the above-mentioned gate drive circuit 10, the first control unit 121 realizes effective control of the first node signal and the second node signal through the first transistor M1 and the second transistor M2, thereby realizing effective control of the gate control signal SPX1 in combination with the second control unit 122, and further realizing a gate control signal SPX1 with controllable effective pulse width, so that the effective pulse width d1 of the gate control signal SPX1 is smaller than the bias control signal SPX, thereby improving the phenomenon that the effective pulse width d1 of the gate control signal SPX1 is larger and the anode of the light-emitting element D is brushed for a long time, resulting in color deviation, so as to improve the display effect of the display panel.

[0052] Please continue reading Figures 7 to 16 In one embodiment, the first transistor M1 and the second transistor M2 have different conductivity types. One of the first transistor M1 and the second transistor M2 is a P-type transistor, and the other is an N-type transistor. The power signal received by the P-type transistor is a high-level signal VGH, and the power signal received by the N-type transistor is a low-level signal VGL.

[0053] For example, Figure 7 , Fig. 9 , Fig.11 , Fig.13 and Fig.15 As shown, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor; in this case, the first power signal is a high level signal VGH, and the second power signal is a low level signal VGL. Figure 8 , Fig.10 , Fig.12 , Fig.14 and Fig.16 As shown, the first transistor M1 is an N-type transistor, and the second transistor M2 is a P-type transistor; in this case, the first power signal is a low-level signal VGL, and the second power signal is a high-level signal VGH. In applications, the conductivity types of the first transistor M1 and the second transistor M2 can be selected according to actual scenarios, and the level states of the first power signal and the second power signal can be set accordingly, which will not be limited too much here.

[0054] In the above-mentioned gate driving circuit 10 , the first transistor M1 and the second transistor M2 have different conductivity types, and the conductivity types of the first transistor M1 and the second transistor M2 can be flexibly selected to be applicable to various application scenarios, with high flexibility and applicability.

[0055] Please continue reading Fig. 9 , Fig.10 , Fig.15 and Fig.16In one embodiment, the first control unit 121 further includes a first regulating subunit 1211, which is electrically connected to the first input terminal IN1, the gate of the first transistor M1, and the gate of the second transistor M2, respectively; in this case, the gate of the first transistor M1 is indirectly electrically connected to the first input terminal IN1 through the first regulating subunit 1211.

[0056] The first regulating subunit 1211 receives the control signal of the first input terminal IN1, the first power signal, and the second power signal, respectively, and outputs a first regulating signal. The first regulating signal is opposite to the potential of the control signal (bias control signal SPX or first light emitting control signal EM(n)) of the first input terminal IN1. That is, the first regulating subunit 1211 is used to reverse the potential of the control signal received by the first input terminal IN1 and output the first regulating signal. Exemplarily, if the control signal of the first input terminal IN1 is a low level signal VGL, the first regulating signal is a high level signal VGH. In another exemplary embodiment, if the control signal of the first input terminal IN1 is a high level signal VGH, the first regulating signal is a low level signal VGL.

[0057] It can be understood that transistors of different conductivity types in the pixel circuit 20 have different corresponding enable levels. Specifically, the enable level of the P-type transistor is a low level, and the enable level of the N-type transistor is a high level. In addition, the effective level of the control signal of the first input terminal IN1 may be a high level or a low level. In order to meet the driving requirements of transistors of different conductivity types, the effective level of the gate control signal SPX1 may be a high level or a low level. In this regard, the embodiment of the present application reversely processes the potential of the control signal of the first input terminal IN1 through the first regulating subunit 1211, and outputs the gate control signal SPX1 with an effective level of a suitable potential to meet application requirements, with high flexibility and applicability.

[0058] Please continue reading Fig. 9 , Fig.10 , Fig.15 and Fig.16 In one embodiment, the first regulating subunit 1211 includes a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is electrically connected to the gate of the fourth transistor M4 and the first input terminal IN1 respectively, the first electrode of the third transistor M3 is electrically connected to the first electrode of the first transistor M1, the second electrode of the third transistor M3 is electrically connected to the first electrode of the fourth transistor M4, the gate of the first transistor M1 and the gate of the second transistor M2 respectively, the second electrode of the third transistor M3 outputs the first regulating signal, and the second electrode of the fourth transistor M4 is electrically connected to the second electrode of the second transistor M2.

[0059] In the above-mentioned gate driving circuit 10, the first regulating subunit 1211 realizes the reverse processing of the potential of the control signal of the first input terminal IN1 through the third transistor M3 and the fourth transistor M4 to output the gate control signal SPX1 with an effective level having a suitable potential, thereby meeting the driving requirements of transistors of various conductive types in the pixel circuit 20, and having high flexibility and applicability. In application, the specific structure of the first control unit 121 can be selected according to the control signal of the first input terminal IN1, the control signal of the second input terminal IN2 and the effective level type of the gate control signal SPX1, and the specific introduction can be referred to the relevant introduction below.

[0060] Please continue reading Fig. 9 , Fig.10 , Fig.15 and Fig.16 In one embodiment, the third transistor M3 and the first transistor M1 have the same conductivity type, the fourth transistor M4 and the second transistor M2 have the same conductivity type, and the third transistor M3 and the fourth transistor M4 have different conductivity types. The power signal received by the P-type transistor is a high-level signal VGH, and the power signal received by the N-type transistor is a low-level signal VGL.

[0061] For example, Fig. 9 and Fig.15 As shown, the first transistor M1 and the third transistor M3 are P-type transistors, and the second transistor M2 and the fourth transistor M4 are N-type transistors; in this case, the first power supply signal is a high level signal VGH, and the second power supply signal is a low level signal VGL. Fig.10 and Fig.16 As shown, the first transistor M1 and the third transistor M3 are N-type transistors, and the second transistor M2 and the fourth transistor M4 are P-type transistors; in this case, the first power supply signal is a low-level signal VGL, and the second power supply signal is a high-level signal VGH. In applications, the conductivity types of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be selected according to actual scenarios, and the level states of the first power supply signal and the second power supply signal can be set accordingly, which will not be excessively limited here.

[0062] In the above-mentioned gate drive circuit 10, the third transistor M3 and the first transistor M1 have the same conductivity type, the fourth transistor M4 and the second transistor M2 have the same conductivity type, and the third transistor M3 and the fourth transistor M4 have different conductivity types, wherein the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 can be flexibly selected to adapt to a variety of application scenarios, with strong flexibility and high applicability.

[0063] Please continue reading Figures 7 to 16In one embodiment, the second control unit 122 includes a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 is electrically connected to the gate of the sixth transistor M6 and the second input terminal IN2 respectively. The first electrode of the fifth transistor M5 is electrically connected to the first node N1, and the second electrode of the fifth transistor M5 is electrically connected to the second node N2. The second electrode of the sixth transistor M6 receives the second power supply signal.

[0064] In the above-mentioned gate drive circuit 10, the second control unit 122 realizes effective control of the gate control signal SPX1 through the fifth transistor M5 and the sixth transistor M6, and in combination with the first control unit 121, thereby realizing a gate control signal SPX1 with controllable effective pulse width, so that the effective pulse width d1 of the gate control signal SPX1 is smaller than the bias control signal SPX, thereby improving the phenomenon that the effective pulse width d1 of the gate control signal SPX1 is large and the anode of the light-emitting element D is brushed for a long time, resulting in color deviation, so as to improve the display effect of the display panel.

[0065] Please continue reading Figures 7 to 16 In one embodiment, one of the fifth transistor M5 and the sixth transistor M6 is a P-type transistor and the other is an N-type transistor. The power signal received by the P-type transistor is a high level signal VGH, and the power signal received by the N-type transistor is a low level signal VGL.

[0066] For example, Figure 7 , Fig. 9 , Fig.11 , Fig.13 and Fig.15 As shown, the fifth transistor M5 is a P-type transistor, and the sixth transistor M6 is an N-type transistor; in this case, the first power signal is a high-level signal VGH, and the second power signal is a low-level signal VGL. Figure 8 , Fig.10 , Fig.12 , Fig.14 and Fig.16 As shown, the fifth transistor M5 is an N-type transistor, and the sixth transistor M6 is a P-type transistor; in this case, the first power signal is a low-level signal VGL, and the second power signal is a high-level signal VGH. In applications, the conductivity types of the fifth transistor M5 and the sixth transistor M6 can be selected according to actual scenarios, and the level states of the first power signal and the second power signal can be set accordingly, which will not be limited too much here.

[0067] In the above gate driving circuit 10 , the conductivity types of the fifth transistor M5 and the sixth transistor M6 are different, and the conductivity types of the fifth transistor M5 and the sixth transistor M6 can be flexibly selected to be applicable to various application scenarios, with high flexibility and applicability.

[0068] Please continue reading Fig.11 , Fig.12 , Fig.15 and Fig.16 In one embodiment, the second control unit 122 further includes a second regulating subunit 1221, which is electrically connected to the second node N2 and the first output terminal OUT, respectively. The second regulating subunit 1221 receives the second node signal, the first power signal, and the second power signal, respectively. The second regulating subunit 1221 is used to control the gate control signal SPX1 output by the first output terminal OUT according to the received second node signal, the first power signal, and the second power signal. The second node signal has an opposite potential to the gate control signal SPX1. That is, the second regulating subunit 1221 is used to reverse the potential of the second node signal and output the second regulating signal. Exemplarily, if the second node signal is a low-level signal VGL, the second regulating signal is a high-level signal VGH. In another exemplary embodiment, if the second node signal is a high-level signal VGH, the second regulating signal is a low-level signal VGL.

[0069] The embodiment of the present application reversely processes the potential of the control signal of the first input terminal IN1 through the first regulating subunit 1211, and outputs a gate control signal SPX1 with an effective level having a suitable potential to meet application requirements, with high flexibility and applicability.

[0070] Please continue reading Fig.11 , Fig.12 , Fig.15 and Fig.16 In one embodiment, the second regulating subunit 1221 includes a seventh transistor M7 and an eighth transistor M8, the gate of the seventh transistor M7 is electrically connected to the gate of the eighth transistor M8 and the second node N2, the first electrode of the seventh transistor M7 receives a first power supply signal, the second electrode of the seventh transistor M7 is electrically connected to the first electrode of the eighth transistor M8 and the first output terminal OUT, and the second electrode of the eighth transistor M8 receives a second power supply signal.

[0071] In the above-mentioned gate drive circuit 10, the second regulating subunit 1221 reversely processes the potential of the second node signal through the seventh transistor M7 and the eighth transistor M8 to output a gate control signal SPX1 with an effective level having a suitable potential, thereby meeting the driving requirements of transistors of various conductive types in the pixel circuit 20, with high flexibility and applicability.

[0072] Please continue reading Fig.11 , Fig.12 , Fig.15 and Fig.16In one embodiment, the fifth transistor M5 and the seventh transistor M7 have the same conductivity type, the sixth transistor M6 and the eighth transistor M8 have the same conductivity type, and the fifth transistor M5 and the sixth transistor M6 have different conductivity types. The power signal received by the P-type transistor is a high-level signal VGH, and the power signal received by the N-type transistor is a low-level signal VGL.

[0073] For example, Fig.11 and Fig.15 As shown, the fifth transistor M5 and the seventh transistor M7 are P-type transistors, and the sixth transistor M6 and the eighth transistor M8 are N-type transistors; in this case, the first power supply signal is a high level signal VGH, and the second power supply signal is a low level signal VGL. Fig.12 and Fig.16 As shown, the fifth transistor M5 and the seventh transistor M7 are N-type transistors, and the sixth transistor M6 and the eighth transistor M8 are P-type transistors; in this case, the first power signal is a low level signal, and the second power signal is a high level signal VGH. In the application, the conductivity type of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 can be selected according to the actual scenario, and the level state of the first power signal and the second power signal can be set accordingly, which is not limited too much here.

[0074] In the above-mentioned gate drive circuit 10, the fifth transistor M5 and the seventh transistor M7 have the same conductivity type, the sixth transistor M6 and the eighth transistor M8 have the same conductivity type, and the fifth transistor M5 and the sixth transistor M6 have different conductivity types, wherein the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 can be flexibly selected to adapt to a variety of application scenarios, with strong flexibility and high applicability.

[0075] Please continue reading Fig.11 As shown, in one embodiment, the second control unit 122 further includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is electrically connected to the first electrode of the seventh transistor M7 and the gate of the seventh transistor M7, respectively, and the second capacitor C2 is electrically connected to the second electrode of the eighth transistor M8 and the gate of the eighth transistor M8, respectively. In this way, by adding the first capacitor C1 and the second capacitor C2, it is helpful to improve the stability of the gate control signal SPX1, so as to further improve the display effect of the display panel.

[0076] Please continue reading Fig.13 and Fig.14In one embodiment, the second control unit 122 further includes a third regulating subunit 1222, which is electrically connected to the second input terminal IN2, the gate of the fifth transistor M5, and the gate of the sixth transistor M6, respectively. The third regulating subunit 1222 is used to receive the control signal of the first input terminal IN1, the first power supply signal, and the second power supply signal, and output a third regulating signal. Among them, the third regulating signal is opposite to the potential of the control signal (bias control signal SPX or first light-emitting control signal EM (n)) of the second input terminal IN2. That is, the third regulating subunit 1222 is used to reverse the potential of the control signal of the second input terminal IN2 and output the third regulating signal. Exemplarily, if the control signal of the second input terminal IN2 is a high-level signal VGH, the third regulating signal is a low-level signal VGL. In another exemplary embodiment, if the control signal of the second input terminal IN2 is a low-level signal VGL, the third regulating signal is a high-level signal VGH.

[0077] The embodiment of the present application reversely processes the potential of the control signal of the second input terminal IN2 through the third regulating subunit 1222 to output a gate control signal SPX1 with an effective level having a suitable potential, thereby meeting the driving requirements of transistors of various conductive types in the pixel circuit 20, with high flexibility and applicability.

[0078] Please continue reading Fig.13 and Fig.14 In one embodiment, the third regulating subunit 1222 includes a ninth transistor M9 and a tenth transistor M10, the gate of the ninth transistor M9 is electrically connected to the gate of the tenth transistor M10 and the second input terminal IN2, the first electrode of the ninth transistor M9 receives the first power supply signal, the second electrode of the ninth transistor M9 is electrically connected to the first electrode of the tenth transistor M10, the gate of the fifth transistor M5 and the gate of the sixth transistor M6, the second electrode of the ninth transistor M9 outputs the second regulating signal, and the second electrode of the tenth transistor M10 receives the second power supply signal.

[0079] In the above-mentioned gate drive circuit 10, the third regulating subunit 1222 reverses the potential of the control signal of the second input terminal IN2 through the ninth transistor M9 and the tenth transistor M10 to output a gate control signal SPX1 with an effective level having a suitable potential, thereby meeting the driving requirements of transistors of various conductive types in the pixel circuit 20, with high flexibility and applicability.

[0080] Please continue reading Fig.13 and Fig.14In one embodiment, the fifth transistor M5 and the ninth transistor M9 have the same conductivity type, the sixth transistor M6 and the tenth transistor M10 have the same conductivity type, and the fifth transistor M5 and the sixth transistor M6 have different conductivity types.

[0081] For example, Fig.13 As shown, the fifth transistor M5 and the ninth transistor M9 are P-type transistors, and the sixth transistor M6 and the tenth transistor M10 are N-type transistors; in this case, the first power supply signal is a high level signal VGH, and the second power supply signal is a low level signal VGL. Fig.14 As shown, the fifth transistor M5 and the ninth transistor M9 are N-type transistors, and the sixth transistor M6 and the tenth transistor M10 are P-type transistors; in this case, the first power supply signal is a low-level signal VGL, and the second power supply signal is a high-level signal VGH. In applications, the conductivity types of the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, and the tenth transistor M10 can be selected according to actual scenarios, and the level states of the first power supply signal and the second power supply signal can be set accordingly, without making too many restrictions here.

[0082] In the above-mentioned gate drive circuit 10, the fifth transistor M5 and the ninth transistor M9 have the same conductivity type, the sixth transistor M6 and the tenth transistor M10 have the same conductivity type, and the fifth transistor M5 and the sixth transistor M6 have different conductivity types, wherein the fifth transistor M5, the sixth transistor M6, the ninth transistor M9 and the tenth transistor M10 can be flexibly selected to suit a variety of application scenarios, with strong flexibility and high applicability.

[0083] Figures 17 to 30 This is a timing diagram provided in the embodiment of the present application. Figures 7 to 16 The structural diagram of various control modules 12 provided below is combined with Figures 17 to 30 , the timings corresponding to different level types of the bias control signal SPX, the first light emitting control signal EM(n) and the gate control signal SPX1 are described respectively.

[0084] like Figure 7 In the control module 12 shown in FIG. 1 , one of the first input terminal IN1 and the second input terminal IN2 receives the bias control signal SPX, and the other receives the first light emitting control signal EM(n). Fig.17 and Fig.18 As shown, when the enable levels of the bias control signal SPX and the first light emitting control signal EM(n) are low levels respectively, the enable level of the gate control signal SPX1 is high level; Fig.17As shown, when n>0, that is, the light emitting control circuit 30 providing the first light emitting control signal EM(n) is the nth stage after the light emitting control circuit 30 providing the second light emitting control signal EM, in this case, the effective pulse width d1 of the gate control signal SPX1 is equal to the time interval between the start time of the enable pulse of the bias control signal SPX and the end time of the enable pulse of the first light emitting control signal EM(n), wherein the rising edge of the first light emitting control signal EM(n) is fixed; Fig.18 As shown, when n is less than 0, that is, the light-emitting control circuit 30 that provides the first light-emitting control signal EM(n) is the first n stages of the light-emitting control circuit 30 that provides the second light-emitting control signal EM. In this case, the effective pulse width d1 of the gate control signal SPX1 is equal to the time interval between the end time of the enable pulse of the bias control signal SPX and the start time of the enable pulse of the first light-emitting control signal EM(n), wherein the falling edge of the first light-emitting control signal EM(n) is fixed.

[0085] like Figure 8 In the control module 12 shown in FIG. 1 , one of the first input terminal IN1 and the second input terminal IN2 receives the bias control signal SPX, and the other receives the first light emitting control signal EM(n). Fig.19 and Fig. 20 As shown in FIG. 1 , when the enable levels of the bias control signal SPX and the first light emitting control signal EM(n) are both high, the enable level of the gate control signal SPX1 is low. Fig.19 As shown in FIG. 1 , when n>0, the falling edge of the first light emitting control signal EM(n) is fixed. Fig. 20 As shown, when n<0, the rising edge of the first light emitting control signal EM(n) is fixed.

[0086] like Fig. 9 The control module 12 shown in FIG. 1 is configured such that the first input terminal IN1 receives the bias control signal SPX, the second input terminal IN2 receives the first light emitting control signal EM(n), and as shown in FIG. Fig.21 and Fig. 22 As shown, when the enable level of the bias control signal SPX is high and the enable level of the first light emitting control signal EM(n) is low, the enable level of the gate control signal SPX1 is high; Fig.21 As shown, in the case of n>0, the rising edge of the first light emitting control signal EM(n) is fixed; Fig. 22 As shown, when n is less than 0, the falling edge of the first light emitting control signal EM(n) is fixed. When the first input terminal IN1 receives the first light emitting control signal EM(n), the second input terminal IN2 receives the bias control signal SPX, and as Fig.23 and Fig.24As shown, when the enable level of the bias control signal SPX is low and the enable level of the first light emitting control signal EM(n) is high, the enable level of the gate control signal SPX1 is high; Fig.23 As shown, in the case of n>0, the falling edge of the first light emitting control signal EM(n) is fixed; Fig.24 As shown, when n<0, the rising edge of the first light emitting control signal EM(n) is fixed.

[0087] like Fig.10 The control module 12 shown in FIG. 1 is configured such that the first input terminal IN1 receives the bias control signal SPX, the second input terminal IN2 receives the first light emitting control signal EM(n), and as shown in FIG. Fig.29 and Fig.30 As shown, when the enable level of the bias control signal SPX is low and the enable level of the first light emitting control signal EM(n) is high, the enable level of the gate control signal SPX1 is low; Fig.29 As shown, in the case of n>0, the falling edge of the first light emitting control signal EM(n) is fixed; Fig.30 As shown in FIG. 1 , when n is less than 0, the rising edge of the first light emitting control signal EM(n) is fixed. When the first input terminal IN1 receives the first light emitting control signal EM(n) and the second input terminal IN2 receives the bias control signal SPX, as shown in FIG. Fig. 27 and Fig.28 As shown, when the enable level of the bias control signal SPX is high and the enable level of the first light emitting control signal EM(n) is low, the enable level of the gate control signal SPX1 is low; Fig. 27 As shown, in the case of n>0, the rising edge of the first light emitting control signal EM(n) is fixed; Fig.28 As shown, when n<0, the falling edge of the first light emitting control signal EM(n) is fixed.

[0088] like Fig.11 In the control module 12 shown in the figure, one of the first input terminal IN1 and the second input terminal IN2 receives the bias control signal SPX, and the other receives the first light emitting control signal EM(n). Figure 3 and Figure 6 As shown in FIG. 1 , when the enable level of the bias control signal SPX is low and the enable level of the first light emitting control signal EM(n) is low, the enable level of the gate control signal SPX1 is low. Figure 3 As shown in FIG. 1 , when n>0, the rising edge of the first light emitting control signal EM(n) is fixed. Figure 6 As shown, when n<0, the falling edge of the first light emitting control signal EM(n) is fixed.

[0089] like Fig.12 In the control module 12 shown in the figure, one of the first input terminal IN1 and the second input terminal IN2 receives the bias control signal SPX, and the other receives the first light emitting control signal EM(n). Fig.25 and Fig.26 As shown in FIG. 1 , when the enable level of the bias control signal SPX is high and the enable level of the first light emitting control signal EM(n) is high, the enable level of the gate control signal SPX1 is high. Fig.25 As shown in FIG. 1 , when n>0, the falling edge of the first light emitting control signal EM(n) is fixed. Fig.26 As shown, when n<0, the rising edge of the first light emitting control signal EM(n) is fixed.

[0090] like Fig.13 The control module 12 shown in FIG. 1 is configured such that the first input terminal IN1 receives the bias control signal SPX, the second input terminal IN2 receives the first light emitting control signal EM(n), and as shown in FIG. Fig.21 and Fig. 22 As shown, when the enable level of the bias control signal SPX is low and the enable level of the first light emitting control signal EM(n) is high, the enable level of the gate control signal SPX1 is high; Fig.21 As shown, in the case of n>0, the rising edge of the first light emitting control signal EM(n) is fixed; Fig. 22 As shown in FIG. 1 , when n is less than 0, the falling edge of the first light emitting control signal EM(n) is fixed. When the first input terminal IN1 receives the first light emitting control signal EM(n), and the second input terminal IN2 receives the bias control signal SPX, and as shown in FIG. Fig.23 and Fig.24 As shown, when the enable level of the bias control signal SPX is high and the enable level of the first light emitting control signal EM(n) is low, the enable level of the gate control signal SPX1 is high; Fig.23 As shown, in the case of n>0, the falling edge of the first light emitting control signal EM(n) is fixed; Fig.24 As shown, when n<0, the rising edge of the first light emitting control signal EM(n) is fixed.

[0091] like Fig.14 The control module 12 shown in FIG. 1 receives the bias control signal SPX at the first input terminal IN1 and receives the first light emitting control signal EM(n) at the second input terminal IN2. Fig. 27 and Fig.28As shown, when the enable level of the bias control signal SPX is high and the enable level of the first light emitting control signal EM(n) is low, the enable level of the gate control signal SPX1 is low; Fig. 27 As shown, in the case of n>0, the rising edge of the first light emitting control signal EM(n) is fixed; Fig.28 As shown in FIG. 1 , when n is less than 0, the falling edge of the first light emitting control signal EM(n) is fixed. When the first input terminal IN1 receives the first light emitting control signal EM(n), and the second input terminal IN2 receives the bias control signal SPX, and as shown in FIG. Fig.29 and Fig.30 As shown, when the enable level of the bias control signal SPX is low and the enable level of the first light emitting control signal EM(n) is high, the enable level of the gate control signal SPX1 is low; Fig.29 As shown, in the case of n>0, the falling edge of the first light emitting control signal EM(n) is fixed; Fig.30 As shown, when n<0, the rising edge of the first light emitting control signal EM(n) is fixed.

[0092] like Fig.15 The control module 12 shown in FIG. 1 is configured to receive the bias control signal SPX at the first input terminal IN1 and to receive the first light emission control signal EM(n) at the second input terminal IN2. Fig. 27 and Fig.28 As shown, when the enable level of the bias control signal SPX is high and the enable level of the first light emitting control signal EM(n) is low, the enable level of the gate control signal SPX1 is low; Fig. 27 As shown, in the case of n>0, the rising edge of the first light emitting control signal EM(n) is fixed; Fig.28 As shown, when n is less than 0, the falling edge of the first light emitting control signal EM(n) is fixed. When the first input terminal IN1 is used to receive the first light emitting control signal EM(n), and the second input terminal IN2 is used to receive the bias control signal SPX, and as Fig.29 and Fig.30 As shown, when the enable level of the bias control signal SPX is low and the enable level of the first light emitting control signal EM(n) is high, the enable level of the gate control signal SPX1 is low; Fig.29 As shown, in the case of n>0, the falling edge of the first light emitting control signal EM(n) is fixed; Fig.30 As shown, when n<0, the rising edge of the first light emitting control signal EM(n) is fixed.

[0093] like Fig.16The control module 12 shown in FIG. 1 is configured to receive the bias control signal SPX at the first input terminal IN1 and to receive the first light emission control signal EM(n) at the second input terminal IN2. Fig.23 and Fig.24 As shown, when the enable level of the bias control signal SPX is low and the enable level of the first light emitting control signal EM(n) is high, the enable level of the gate control signal SPX1 is high; Fig.23 As shown, in the case of n>0, the rising edge of the first light emitting control signal EM(n) is fixed; Fig.24 As shown, when n is less than 0, the falling edge of the first light emitting control signal EM(n) is fixed. When the first input terminal IN1 is used to receive the first light emitting control signal EM(n), and the second input terminal IN2 is used to receive the bias control signal SPX, and as Fig.21 and Fig. 22 As shown, when the enable level of the bias control signal SPX is high and the enable level of the first light emitting control signal EM(n) is low, the enable level of the gate control signal SPX1 is high; Fig.21 As shown, in the case of n>0, the falling edge of the first light emitting control signal EM(n) is fixed; Fig. 22 As shown, when n<0, the rising edge of the first light emitting control signal EM(n) is fixed.

[0094] It should be noted that the above is only an exemplary description, and the control module 12 may also have other structures. For example, the control module 12 includes the first to tenth transistors M10. The partial structures of the control module 12 introduced above can be freely combined according to the actual application scenario and are not excessively limited here.

[0095] Based on the same application concept, the present application embodiment also provides a display panel. Figure 4 and Figure 5 As shown, the display panel includes the gate drive circuit 10 in any of the above embodiments. The display panel has the beneficial effects of the gate drive circuit 10 in the above embodiments, and the similarities can be understood by referring to the explanation of the gate drive circuit 10 above, which will not be repeated below.

[0096] Please continue reading Figure 4 and Figure 5In one embodiment, the display panel includes a plurality of rows of pixel circuits 20 arranged in an array and a plurality of cascaded gate driving circuits 10. The display panel also includes a plurality of cascaded light-emitting control circuits 30. The light-emitting control circuit 30 is used to provide a light-emitting control signal. Among them, the driving module 11 of the i-th gate driving circuit 10 is electrically connected to the bias module 21 of the j-th row pixel circuit 20. The control module 12 of the i-th gate driving circuit 10 is electrically connected to the driving module 11 of the i-th gate driving circuit 10, the i+n-th light-emitting control circuit 30, and the anode reset module 22 of the j-th row pixel circuit 20, respectively. Among them, the input end of the control module 12 of the i-th gate driving circuit 10 is electrically connected to the driving module 11 of the i-th gate driving circuit 10 and the i+n-th light-emitting control circuit 30, respectively, and the first output end OUT of the control module 12 of the i-th gate driving circuit 10 is electrically connected to the anode reset module 22 of the j-th row pixel circuit 20. The i-th stage light emitting control circuit 30 is electrically connected to the light emitting control module 23 of the j-th row of pixel circuits 20 .

[0097] The i+n-th level light-emitting control circuit 30 is used to provide a first light-emitting control signal EM(n), and the i-th level light-emitting control circuit 30 is used to provide a second light-emitting control signal EM. That is, the i+n-th level light-emitting control circuit 30 is used to provide a first light-emitting control signal EM(n) for the control module 12 of the i-th level gate driving circuit 10, and the i-th level light-emitting control circuit 30 is used to provide a second light-emitting control signal EM for the light-emitting control module 23 of the j-th row pixel circuit 20. Among them, the i+n-th level light-emitting control circuit 30 is also used to provide a second light-emitting control signal EM for the light-emitting control module 23 of the a*i-a+1-th row pixel circuit 20. The i-th level light-emitting control circuit 30 is also used to provide a first light-emitting control signal EM(n) for the control module 12 of the in-th level gate driving circuit 10.

[0098] Wherein, n is an integer not equal to 0, i is a positive integer, a*i-a+1≤j≤i, and j traverses from a*i-a+1 to i. a is a positive integer, and a can be understood as the number of rows of pixel circuits 20 electrically connected to the gate driving circuit 10.

[0099] The above-mentioned display panel provides a light-emitting control signal to the pixel circuit 20 through the light-emitting control circuit 30, which can meet the light-emitting control driving requirements of the pixel circuit 20 for the light-emitting element D, and provides a bias control signal SPX to the pixel circuit 20 through the driving module 11 in the gate driving circuit 10, which can meet the bias reset requirements of the pixel circuit 20, and provides a gate control signal SPX1 to the pixel circuit 20 through the control module 12 in the gate bias circuit, which can meet the anode reset requirements of the light-emitting element D, and can also improve the color deviation caused by directly using the bias reset signal for anode reset, thereby improving the display effect of the display panel; in addition, the control module 12 of the gate control circuit realizes the adjustable effective pulse width d1 of the gate control signal SPX1 by multiplexing the bias control signal SPX and the light-emitting control signal, without setting a new signal and circuit structure, which is conducive to further realizing a narrow frame.

[0100] Please continue reading Figure 2 In one embodiment, the pixel circuit 20 includes a driving transistor T0, a bias transistor T1, an anode reset transistor T2, a first light emission control transistor T3, a second light emission control transistor T4, a data writing transistor T5, a threshold compensation transistor T6, an initialization transistor T7 and a storage capacitor Cst.

[0101] The gate of the driving transistor T0 is electrically connected to the first electrode of the initialization transistor T7, the first electrode of the threshold compensation transistor T6, and the first end of the storage capacitor Cst, respectively. The first electrode of the driving transistor T0 is electrically connected to the second electrode of the first light-emitting control transistor T3, the second electrode of the data writing transistor T5, and the first electrode of the anode reset transistor T2, respectively. The second electrode of the driving transistor T0 is electrically connected to the second electrode of the threshold compensation transistor T6 and the first electrode of the second light-emitting control transistor T4. The second electrode of the bias transistor T1 receives the anode reset signal Vref1, the gate of the bias transistor T1 is electrically connected to the driving module 11 of the gate driving circuit 10, and the gate of the bias transistor T1 receives the bias control signal SPX. The gate of the anode reset transistor T2 is electrically connected to the driving module 11 of the gate driving circuit 10, the first electrode of the anode reset transistor T2 receives the anode reset signal Vref1, and the second electrode of the anode reset transistor T2 is electrically connected to the second electrode of the second light-emitting control transistor T4 and the anode of the light-emitting element D, respectively. The first electrode of the first light-emitting control transistor T3 receives the first level signal PVDD, and the gate of the first light-emitting control transistor T3 and the gate of the second light-emitting control transistor T4 respectively receive the second light-emitting control signal EM provided by the light-emitting control circuit 30. The gate of the data-writing transistor T5 and the gate of the threshold compensation transistor T6 respectively receive the second scanning signal Scan2, and the first electrode of the data-writing transistor T5 receives the data signal VData. The second electrode of the initialization transistor T7 receives the initialization signal Vref2, and the gate of the initialization transistor T7 receives the first scanning signal Scan1. Among them, the threshold compensation transistor T6 and the initialization transistor T7 can be dual-gate transistors.

[0102] In applications, the pixel circuit 20 may adopt the aforementioned 8T1C structure, or may adopt other structures such as 9T1C, 9T2C, etc., which are not specifically limited here.

[0103] Please continue reading Figure 4 In one embodiment, the display panel includes 2N rows of pixel circuits 20, N cascaded gate driving circuits 10, and N+n cascaded light emitting control circuits 30, wherein, when a=2 and n>0, 0<i≤N, 2i-1≤j≤2i. Wherein, a=2, indicating that the number of rows of pixel circuits 20 to which the gate driving circuit 10 and the light emitting control circuit 30 are electrically connected is 2, that is, the pixel circuits 20 are driven in a one-to-two manner. n>0, indicating that the control module 12 in the gate driving circuit 10 is electrically connected to the driving circuit of the same gate driving circuit 10, and the light emitting control circuit 30 which is offset by n stages backward relative to the control module 12. Figure 4 In the display panel shown, n=1.

[0104] The light-emitting control circuit 30 includes a first light-emitting output terminal and a second light-emitting output terminal, the first light-emitting output terminal of the light-emitting control circuit is used to be electrically connected to the pixel circuit 20, and the second light-emitting output terminal of the light-emitting control circuit 30 is used to be electrically connected to the gate control circuit. The second light-emitting output terminal of the first n-stage light-emitting control circuit 30 and the first light-emitting output terminal of the last n-stage light-emitting control circuit 30 are in a suspended state (dummy).

[0105] For the first n-stage light-emitting control circuits 30, the first light-emitting output end of each stage of the light-emitting control circuit 30 is electrically connected to the corresponding two rows of pixel circuits 20, and the second light-emitting output end of each stage of the light-emitting control circuit 30 is in a suspended state; for the n+1th to Nth stage of light-emitting control circuits 30, the first light-emitting output end of each stage of the light-emitting control circuit 30 is electrically connected to the corresponding two rows of pixel circuits 20, and the second light-emitting output end of each stage of the light-emitting control circuit 30 is electrically connected to the control module 12 of the gate control circuit that is offset n stages forward relative to the light-emitting control circuit 30; for the next n-stage light-emitting control circuits 30, the first light-emitting output end of each stage of the light-emitting control circuit 30 is in a suspended state, and the second light-emitting output end of each stage of the light-emitting control circuit 30 is electrically connected to the control module 12 of the corresponding gate control circuit that is offset n stages forward relative to the light-emitting control circuit 30. Among them, the gate control circuit that is offset n stages forward relative to the light-emitting control circuit 30 refers to the i-th stage gate control circuit relative to the i+n-th stage of light-emitting control circuit 30, and n>0.

[0106] In the above-mentioned display panel, the gate driving circuit 10 and the light-emitting control circuit 30 respectively drive the corresponding two rows of pixel circuits 20 in a one-drive-two manner, which can reduce the occupied area of ​​the circuit structure and is conducive to achieving a narrow frame. In addition, the gate driving circuit 10 is electrically connected to the light-emitting control circuit 30 that is backward displaced by n levels, and the light-emitting output end of the light-emitting control circuit 30 that is not electrically connected to the driving circuit is set to a suspended state. In this way, the gate driving circuit 10 can provide the pixel circuit 20 with a bias control signal SPX and a gate control signal SPX1 with an adjustable effective pulse width, respectively, to improve the color deviation phenomenon and enhance the display effect. There is no need to set up new signals and circuit structures, which is conducive to further achieving a narrow frame.

[0107] Please continue reading Figure 5In one embodiment, the display panel includes 2N rows of pixel circuits 20, N cascaded gate drive circuits 10, and N+n cascaded light-emitting control circuits 30, wherein, when a=2 and n<0, 0<i≤N, 2i-1≤j≤2i. Wherein, a=2, indicating that the number of rows of pixel circuits 20 to which the gate drive circuit 10 and the light-emitting control circuit 30 are electrically connected is 2, that is, the pixel circuits 20 are driven in a one-to-two manner. n<0, indicating that the control circuit in the gate drive circuit 10 is electrically connected to the drive circuit of the same gate drive circuit 10, and the light-emitting control circuit 30 that is n stages forwardly displaced relative to the control module 12. Figure 5 In the display panel shown, n=-1.

[0108] The light-emitting control circuit 30 includes a first light-emitting output terminal and a second light-emitting output terminal, the first light-emitting output terminal of the light-emitting control circuit is used to be electrically connected to the pixel circuit 20, and the second light-emitting output terminal of the light-emitting control circuit 30 is used to be electrically connected to the gate control circuit. The first light-emitting output terminal of the first n-stage light-emitting control circuit 30 and the second light-emitting output terminal of the second n-stage light-emitting control circuit 30 are in a suspended state.

[0109] For the first n-stage light-emitting control circuits 30, the first light-emitting output end of each stage of the light-emitting control circuit 30 is in a suspended state, and the second light-emitting output end of each stage of the light-emitting control circuit 30 is respectively electrically connected to the control module 12 of the gate control circuit that is offset by n stages backward relative to the light-emitting control circuit 30; for the n+1th to Nth stage of light-emitting control circuits 30, the first light-emitting output end of each stage of the light-emitting control circuit 30 is respectively electrically connected to the corresponding two rows of pixel circuits 20, and the second light-emitting output end of each stage of the light-emitting control circuit 30 is electrically connected to the control module 12 of the gate control circuit that is offset by n stages backward; for the last n-stage light-emitting control circuits 30, the first light-emitting output end of each stage of the light-emitting control circuit 30 is respectively electrically connected to the corresponding two rows of pixel circuits 20, and the second light-emitting output end of each stage of the light-emitting control circuit 30 is in a suspended state. Among them, the gate control circuit that is offset by n stages backward relative to the light-emitting control circuit 30 refers to the i-th stage gate control circuit relative to the i+n-th stage of light-emitting control circuit 30, and n<0.

[0110] In the above-mentioned display panel, the gate driving circuit 10 and the light-emitting control circuit 30 respectively drive the corresponding two rows of pixel circuits 20 in a one-drive-two manner, which can reduce the occupied area of ​​the circuit structure and is conducive to achieving a narrow frame. In addition, the gate driving circuit 10 is electrically connected to the light-emitting control circuit 30 that is forward-shifted by n levels, and the light-emitting output end of the light-emitting control circuit 30 that is not electrically connected to the driving circuit is set to a suspended state. In this way, the gate driving circuit 10 can provide the pixel circuit 20 with a bias control signal SPX and a gate control signal SPX1 with an adjustable effective pulse width, respectively, thereby improving the color deviation phenomenon and enhancing the display effect. There is no need to set up new signals and circuit structures, which is conducive to further achieving a narrow frame.

[0111] Based on the same application concept, an embodiment of the present application also provides a display device. Fig.31 A schematic diagram of the structure of a display device 1000 provided in an embodiment of the present application is shown in FIG. Fig.31 As shown, the display device 1000 includes the display panel 100 in any of the above embodiments. Therefore, the display device 1000 also has the beneficial effects of the display panel 100 in the above embodiments, and the similarities can be understood by referring to the above explanation of the display panel 10, which will not be repeated below.

[0112] The display device 1000 provided in the embodiment of the present application can be Fig.31 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.

[0113] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A gate drive circuit, characterized in that: include: A driving module, electrically connected to the bias module of the pixel circuit, for providing a bias control signal; A control module, electrically connected to the driving module, and the bias module and the anode reset module of the pixel circuit, respectively, for receiving the bias control signal, the first light emitting control signal, the first power supply signal and the second power supply signal, and outputting a gate control signal; The first light-emitting control signal and the second light-emitting control signal received by the pixel circuit are provided by two different light-emitting control circuits, and the effective pulse width of the gate control signal is smaller than the effective pulse width of the bias control signal.

2. The gate driving circuit according to claim 1, characterized in that: The effective pulse width of the gate control signal is equal to an overlapping width between an effective pulse width of the bias control signal and an effective pulse width of the first light emitting control signal.

3. The gate driving circuit according to claim 1, characterized in that: The first light-emitting control signal is provided by the i+nth level light-emitting control circuit, and the second light-emitting control signal is provided by the i-th level light-emitting control circuit, wherein the i+nth level light-emitting control circuit and the i-th level light-emitting control circuit are cascaded, and the effective pulse width of the gate control signal is related to n, and n is an integer not equal to 0.

4. The gate driving circuit according to claim 3, characterized in that: The effective pulse width of the gate control signal is equal to the time interval between the start time of the enable pulse of the bias control signal and the end time of the enable pulse of the first light emitting control signal, wherein n is a positive integer.

5. The gate driving circuit according to claim 3, characterized in that: The effective pulse width of the gate control signal is equal to the time interval between the end time of the enable pulse of the bias control signal and the start time of the enable pulse of the first light emitting control signal, wherein n is a negative integer.

6. The gate driving circuit according to claim 1, characterized in that: The control module comprises a first input terminal, a second input terminal and a first output terminal, wherein one of the first input terminal and the second input terminal is electrically connected to the driving module and receives the bias control signal, and the other receives the first light-emitting control signal. The control module further comprises: a first control unit, electrically connected to the first input terminal, the first node, and the second node, respectively, and configured to control a first node signal of the first node and a second node signal of the second node respectively according to the received first power signal and the control signal of the first input terminal; A second control unit is electrically connected to the second input terminal, the first node, the second node and the first output terminal, respectively, and is used to control the gate control signal output by the first output terminal according to the received second power supply signal, the control signal of the second input terminal, the first node signal and the second node signal.

7. The gate driving circuit according to claim 6, characterized in that: The first control unit includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the gate of the second transistor, the gate of the first transistor is used to be electrically connected to the first input terminal, the first electrode of the first transistor receives the first power supply signal, the second electrode of the first transistor is respectively electrically connected to the first node and the first terminal of the second control unit, the first electrode of the second transistor is respectively electrically connected to the second node and the second terminal of the second control unit, and the second electrode of the second transistor receives the second power supply signal.

8. The gate driving circuit according to claim 7, characterized in that: One of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor, wherein the power signal received by the P-type transistor is a high-level signal, and the power signal received by the N-type transistor is a low-level signal.

9. The gate driving circuit according to claim 7, characterized in that: The first control unit also includes a first regulating subunit, which is electrically connected to the first input terminal, the gate of the first transistor, and the gate of the second transistor, respectively, receives the control signal of the first input terminal, the first power supply signal, and the second power supply signal, and outputs a first regulating signal; wherein the first regulating signal has an opposite potential to the control signal of the first input terminal.

10. The gate driving circuit according to claim 9, characterized in that: The first regulating subunit includes a third transistor and a fourth transistor, the gate of the third transistor is electrically connected to the gate of the fourth transistor and the first input terminal respectively, the first electrode of the third transistor is electrically connected to the first electrode of the first transistor, the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor, the gate of the first transistor and the gate of the second transistor respectively, the second electrode of the third transistor outputs the first regulating signal, and the second electrode of the fourth transistor is electrically connected to the second electrode of the second transistor.

11. The gate driving circuit according to claim 10, characterized in that: The third transistor and the first transistor have the same conductivity type, the fourth transistor and the second transistor have the same conductivity type, and the third transistor and the fourth transistor have different conductivity types.

12. The gate driving circuit according to claim 6, characterized in that: The second control unit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is electrically connected to the gate of the sixth transistor and the second input terminal respectively, the first electrode of the fifth transistor is electrically connected to the first node, the second electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the sixth transistor receives the second power supply signal.

13. The gate driving circuit according to claim 12, characterized in that: One of the fifth transistor and the sixth transistor is a P-type transistor, and the other is an N-type transistor; wherein, When the sixth transistor is a P-type transistor, the second power supply signal received by the sixth transistor is a high level signal; When the sixth transistor is an N-type transistor, the second power signal received by the sixth transistor is a low level signal.

14. The gate driving circuit according to claim 12, characterized in that: The second control unit also includes a second regulating subunit, which is electrically connected to the second node and the first output terminal respectively, and receives the second node signal, the first power signal, and the second power signal respectively. The second regulating subunit is used to control the gate control signal output by the first output terminal according to the received second node signal, the first power signal, and the second power signal; wherein the second node signal has an opposite potential to the gate control signal.

15. The gate driving circuit according to claim 14, characterized in that: The second regulating subunit includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is electrically connected to the gate of the eighth transistor and the second node respectively, the first electrode of the seventh transistor receives the first power supply signal, the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor and the first output terminal respectively, and the second electrode of the eighth transistor receives the second power supply signal.

16. The gate driving circuit according to claim 15, characterized in that: The fifth transistor and the seventh transistor have the same conductivity type, the sixth transistor and the eighth transistor have the same conductivity type, and the fifth transistor and the sixth transistor have different conductivity types.

17. The gate driving circuit according to claim 15, characterized in that: The second control unit further includes a first capacitor and a second capacitor, wherein the first capacitor is electrically connected to the first electrode and the gate of the seventh transistor respectively, and the second capacitor is electrically connected to the second electrode and the gate of the eighth transistor respectively.

18. The gate driving circuit according to claim 12, characterized in that: The second control unit also includes a third regulating subunit, which is electrically connected to the second input terminal, the gate of the fifth transistor, and the gate of the sixth transistor, respectively, receives the control signal of the first input terminal, the first power supply signal and the second power supply signal, and outputs a second regulating signal; wherein the second regulating signal has an opposite potential to the control signal of the second input terminal.

19. The gate driving circuit according to claim 18, characterized in that: The third regulating subunit includes a ninth transistor and a tenth transistor, the gate of the ninth transistor is electrically connected to the gate of the tenth transistor and the second input terminal respectively, the first electrode of the ninth transistor receives the first power supply signal, the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor, the gate of the fifth transistor and the gate of the sixth transistor respectively, the second electrode of the ninth transistor outputs the second regulating signal, and the second electrode of the tenth transistor receives the second power supply signal.

20. The gate driving circuit according to claim 19, characterized in that: The fifth transistor and the ninth transistor have the same conductivity type, the sixth transistor and the tenth transistor have the same conductivity type, and the fifth transistor and the sixth transistor have different conductivity types.

21. A display panel, characterized in that: The display panel comprises a pixel circuit and a gate driving circuit as described in any one of claims 1-20.

22. The display panel according to claim 21, characterized in that: The display panel includes a plurality of rows of pixel circuits arranged in an array and a plurality of cascaded gate driving circuits. The display panel also includes a plurality of cascaded light-emitting control circuits, and the light-emitting control circuits are used to provide a light-emitting control signal, wherein the driving module of the i-th gate driving circuit is electrically connected to the bias module of the j-th row of pixel circuits, the control module of the i-th gate driving circuit is electrically connected to the driving module of the i-th gate driving circuit, the i+n-th light-emitting control circuit, and the anode reset module of the j-th row of pixel circuits, respectively, the i-th light-emitting control circuit is electrically connected to the light-emitting control module of the j-th row of pixel circuits, the i+n-th light-emitting control circuit is used to provide the first light-emitting control signal, and the i-th light-emitting control circuit is used to provide the second light-emitting control signal, wherein n is an integer not equal to 0, i is a positive integer, a*i-a+1≤j≤a*i, and a is a positive integer.

23. The display panel according to claim 22, characterized in that: The display panel includes 2N rows of pixel circuits, N cascaded gate drive circuits and N+n cascaded light emitting control circuits, wherein: When a=2 and n>0, 0<i≤N, 2i-1≤j≤2i, wherein the light-emitting control circuit includes a first light-emitting output terminal and a second light-emitting output terminal, the first light-emitting output terminal of the light-emitting control circuit is used to be electrically connected to the pixel circuit, and the second light-emitting output terminal of the light-emitting control circuit is used to be electrically connected to the gate control circuit, wherein the second light-emitting output terminal of the first n-stage light-emitting control circuit and the first light-emitting output terminal of the last n-stage light-emitting control circuit are in a suspended state.

24. The display panel according to claim 22, characterized in that: The display panel includes 2N rows of pixel circuits, N cascaded gate drive circuits and N+n cascaded light emitting control circuits, wherein: When a=2 and n<0, 0<i≤N, 2i-1≤j≤2i, wherein the light-emitting control circuit includes a first light-emitting output terminal and a second light-emitting output terminal, the first light-emitting output terminal of the light-emitting control circuit is used to be electrically connected to the pixel circuit, and the second light-emitting output terminal of the light-emitting control circuit is used to be electrically connected to the gate control circuit, wherein the first light-emitting output terminal of the first n-level light-emitting control circuit and the second light-emitting output terminal of the last n-level light-emitting control circuit are in a suspended state.

25. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 21 to 24.

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