Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a substrate, a plurality of pixel circuit groups on the substrate, each of the pixel circuit groups comprising two pixel circuits, each of the pixel circuits comprising a first functional element and a second functional element, the first functional elements in the two pixel circuits in the same pixel circuit group being arranged along a first direction, the second functional elements in the two pixel circuits in the same pixel circuit group being arranged along a second direction, the first direction intersecting the second direction, a plurality of first gate lines arranged along the first direction and extending along the second direction, and the second functional elements in the two pixel circuits in the same pixel circuit group being electrically connected to the same first gate line. The technical scheme of the application improves the use performance of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] This invention provides a display panel and a display device to improve the performance of the display panel.

[0005] According to one aspect of the present invention, a display panel is provided, the display panel comprising:

[0006] Substrate;

[0007] Multiple pixel circuit groups are located on a substrate; each pixel circuit group includes two pixel circuits, each pixel circuit includes a first functional element and a second functional element, in the same pixel circuit group, the first functional elements of the two pixel circuits are arranged along a first direction, and the second functional elements of the two pixel circuits are arranged along a second direction, the first direction and the second direction intersect.

[0008] Multiple first gate lines are arranged along a first direction and extend along a second direction, and the second functional elements in two pixel circuits in the same pixel circuit group are electrically connected to the same first gate line.

[0009] Optionally, in two adjacent pixel circuit groups arranged along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit. The first functional elements in the first and second pixel circuits are arranged along the first direction, the first functional elements in the third and fourth pixel circuits are arranged along the first direction, the first functional elements in the first and third pixel circuits are arranged along the second direction, the first functional elements in the second and fourth pixel circuits are arranged along the second direction, and the second functional elements in the second pixel circuit, the first pixel circuit, the third pixel circuit, and the fourth pixel circuit are arranged sequentially along the second direction; or, the second functional elements in the first pixel circuit, the second functional elements in the second pixel circuit, the second functional elements in the fourth pixel circuit, and the second functional elements in the third pixel circuit are arranged sequentially along the second direction.

[0010] Optionally, in two adjacent pixel circuit groups arranged along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit. The first functional elements in the first pixel circuit and the second pixel circuit are arranged along the first direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the first functional elements in the first pixel circuit and the third pixel circuit are arranged along the second direction, the first functional elements in the second pixel circuit and the fourth pixel circuit are arranged along the second direction, and the second functional elements in the first pixel circuit, the second functional elements in the second pixel circuit, the second functional elements in the third pixel circuit, and the second functional elements in the fourth pixel circuit are arranged sequentially along the second direction.

[0011] Optionally, the first functional element includes a driving transistor, and the second functional element includes an initialization transistor;

[0012] Alternatively, the second functional elements in different pixel circuits may have the same function.

[0013] Optionally, the second functional element includes a first initialization transistor.

[0014] The first initialization transistor is electrically connected to the gate of the driving transistor, or...

[0015] The pixel circuit includes a compensation transistor connected between the first terminal and the gate of the driving transistor, and a first initialization transistor electrically connected to the first terminal of the driving transistor.

[0016] Optionally, the display panel may also include multiple first initialization sub-signal lines arranged along a first direction and extending along a second direction.

[0017] The first initialization transistors in two pixel circuits within the same pixel circuit group are electrically connected to the same first initialization sub-signal line;

[0018] The first initialization sub-signal line includes a first sub-segment and a second sub-segment arranged alternately along its own extension direction, and the first sub-segment and the second sub-segment are set in different layers;

[0019] Optionally, the first initialization transistor includes an N-type transistor or a P-type transistor;

[0020] Optionally, the compensation transistor may include an N-type transistor or a P-type transistor.

[0021] Optionally, the display panel also includes a plurality of light-emitting elements, and the second functional element includes a second initialization transistor, which is electrically connected to the first electrode of the light-emitting element.

[0022] Optionally, the second functional element includes a third initialization transistor, which is electrically connected to the first or second terminal of the driving transistor.

[0023] Optionally, the display panel also includes multiple initialization signal lines arranged along a first direction and extending along a second direction.

[0024] The second functional elements in two pixel circuits within the same pixel circuit group are electrically connected to the same initialization signal line.

[0025] Optionally, the pixel circuit also includes a third functional element.

[0026] In two adjacent pixel circuit groups arranged along a first direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a fifth pixel circuit and a sixth pixel circuit. The first functional element of the first pixel circuit, the first functional element of the second pixel circuit, the first functional element of the fifth pixel circuit, and the first functional element of the sixth pixel circuit are arranged sequentially along the first direction.

[0027] The display panel also includes: a plurality of second gate lines arranged along a first direction and extending along a second direction;

[0028] In two adjacent pixel circuit groups arranged along the first direction, the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are arranged along the first direction and electrically connected to different second gate lines.

[0029] Optionally, the first functional element includes a driving transistor.

[0030] One of the second and third functional elements includes a first initialization transistor electrically connected to the gate of the driving transistor; or, the pixel circuit includes a compensation transistor connected between the first terminal and the gate of the driving transistor, and the first initialization transistor is electrically connected to the first terminal of the driving transistor.

[0031] The other of the second and third functional elements includes a second initialization transistor.

[0032] The display panel also includes multiple light-emitting elements, and the second initialization transistor is electrically connected to the first electrode of the light-emitting element;

[0033] Optionally, the pixel circuit also includes a third initialization transistor, the first terminal of which is electrically connected to the first or second terminal of the driving transistor.

[0034] The display panel also includes multiple second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate lines;

[0035] Optionally, the second initialization transistor and the third initialization transistor have the same channel type;

[0036] Optionally, the second initialization transistor includes a P-type transistor; the third initialization transistor includes a P-type transistor.

[0037] Optionally, the display panel further includes multiple first initialization sub-signal lines arranged along a first direction and extending along a second direction.

[0038] The second functional elements in two pixel circuits within the same pixel circuit group are electrically connected to the same first initialization sub-signal line;

[0039] The display panel also includes multiple second initialization sub-signal lines, arranged along the first direction and extending along the second direction.

[0040] In two adjacent pixel circuit groups arranged along the first direction, the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are electrically connected to the same second initialization sub-signal line;

[0041] Optionally, the display panel also includes multiple third initialization sub-signal lines arranged along the second direction and extending along the first direction; the third initialization sub-signal lines are electrically connected to the first initialization sub-signal lines.

[0042] The first initialization sub-signal line includes a first sub-segment and a second sub-segment arranged alternately along its own extension direction, and the first sub-segment and the second sub-segment are set in different layers;

[0043] The display panel also includes multiple fourth initialization sub-signal lines, arranged along the second direction and extending along the first direction; the fourth initialization sub-signal lines are electrically connected to the second initialization sub-signal lines; the orthographic projection of the second sub-segment on the substrate overlaps with the orthographic projection of the fourth initialization sub-signal line on the substrate, and the second sub-segment and the fourth initialization sub-signal lines are disposed on different layers;

[0044] Optionally, the first sub-segment, the third initialization sub-signal line, and the fourth initialization sub-signal line are set on the same layer, and the second sub-segment and the second initialization sub-signal line are set on the same layer.

[0045] Optionally, the first sub-segment and the second sub-segment are connected through a first via, and the first sub-segment is connected to the second functional element through a second via;

[0046] Optionally, the second vias corresponding to the second functional elements in two pixel circuits in the same pixel circuit group are located on opposite sides of the first sub-segment along the first direction.

[0047] Optionally, the display panel further includes a first gate driving circuit, which includes a plurality of cascaded first shift registers. The second functional elements in the first pixel circuit and the second functional elements in the second pixel circuit are electrically connected to the output terminal of the same first shift register. The second functional elements in the fifth pixel circuit and the second functional elements in the sixth pixel circuit are electrically connected to the output terminal of the same first shift register. The second functional elements in the second pixel circuit and the second functional elements in the fifth pixel circuit are electrically connected to the output terminals of different first shift registers.

[0048] Optionally, the display panel further includes a second gate driving circuit, which includes multiple cascaded second shift registers. The third functional element in the first pixel circuit and the third functional element in the second pixel circuit are electrically connected to the output terminal of the same second shift register. The third functional element in the fifth pixel circuit and the third functional element in the sixth pixel circuit are electrically connected to the output terminal of the same second shift register. The third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are electrically connected to the output terminals of different second shift registers.

[0049] Optionally, the third functional element includes an initialization transistor.

[0050] In two adjacent pixel circuit groups arranged along the first direction, the active portion of the third functional element in the second pixel circuit and the active portion of the third functional element in the fifth pixel circuit are connected.

[0051] Optionally, the pixel circuit includes a driving transistor and a third initialization transistor, wherein the first terminal of the third initialization transistor is electrically connected to the first or second terminal of the driving transistor.

[0052] The second electrode of the third initialization transistor in two pixel circuits within the same pixel circuit group is electrically connected;

[0053] And / or, the active portions of the third initialization transistors in two pixel circuits within the same pixel circuit group are connected;

[0054] And / or, in two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit and the second pixel circuit is connected;

[0055] And / or, in two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit and the second pixel circuit are connected;

[0056] And / or, in two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit and the third pixel circuit are connected;

[0057] And / or, in two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected;

[0058] And / or, in two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit is connected;

[0059] And / or, in two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected.

[0060] Optionally, the pixel circuit includes a component group, which includes a first functional element.

[0061] The component groups in two adjacent pixel circuits arranged along the first direction are mirror-symmetrically positioned.

[0062] Optionally, the component groups in two adjacent pixel circuits arranged along the second direction are mirror-symmetrically configured;

[0063] Optionally, the pixel circuits are arranged in a mirror-symmetric configuration along the second direction and adjacent pixels are mirror-symmetric.

[0064] Optionally, the first functional element includes a driving transistor, and the element group further includes a data writing transistor, a compensation transistor, a first light-emitting control transistor, and a second light-emitting control transistor;

[0065] Optionally, the display panel further includes multiple third gate lines arranged along the first direction and extending along the second direction; the gate of the compensation transistor is electrically connected to the third gate lines.

[0066] The third gate line of the compensation transistor electrical connection in two pixel circuits in the same pixel circuit group is symmetrical about the first gate line;

[0067] Optionally, the display panel further includes multiple fourth gate lines arranged along the first direction and extending along the second direction; the gate of the data writing transistor is electrically connected to the fourth gate lines.

[0068] The fourth gate line of the data write transistor electrical connection in two pixel circuits in the same pixel circuit group is symmetrical about the first gate line;

[0069] Optionally, the display panel also includes a data cable, a first data connection cable and a second data connection cable, wherein the first data connection cable is connected between the second data connection cable and the data cable, and the data cable is connected to the data writing transistor;

[0070] The pixel circuit also includes a third initialization transistor; the display panel also includes multiple fifth initialization sub-signal lines; the gate of the third initialization transistor is connected to the second gate line, and the second terminal of the third initialization transistor is electrically connected to the fifth initialization sub-signal line;

[0071] The second gate line, the fifth initialization sub-signal line and the first data connection line extend in the same direction;

[0072] Along the thickness direction of the display panel, the fifth initialization sub-signal line is located between the second gate line and the first data connection line;

[0073] Optionally, the display panel also includes connection traces, wherein the active portions of the data writing transistors in two pixel circuits in the same pixel circuit group are connected to the connection traces through a third via, and the connection traces are connected to the corresponding data lines through the same fourth via.

[0074] Optionally, at least two partially adjacent first data connection lines are located on opposite sides of the second initialization sub-signal line along the first direction, and at least two partially adjacent first data connection lines are symmetrical about the second initialization sub-signal line.

[0075] Optionally, the pixel circuit includes a driving transistor and a third initialization transistor, wherein the first terminal of the third initialization transistor is electrically connected to the first or second terminal of the driving transistor.

[0076] The display panel also includes multiple fifth initialization sub-signal lines arranged along the first direction and extending along the second direction; the second terminal of the third initialization transistor is electrically connected to the fifth initialization sub-signal lines.

[0077] The display panel also includes multiple second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate lines, and the orthographic projection of the second gate lines on the substrate overlaps with the orthographic projection of the fifth initialization sub-signal line on the substrate;

[0078] Optionally, the display panel also includes multiple sixth initialization sub-signal lines arranged along the second direction and extending along the first direction; the sixth initialization sub-signal lines are electrically connected to the fifth initialization sub-signal lines.

[0079] Optionally, the third initialization transistor includes at least two transistors connected in series.

[0080] Optionally, the pixel circuit includes a driving transistor and a first light-emitting control transistor.

[0081] The display panel also includes a first power line, and a first light-emitting control transistor is connected between the second electrode of the driving transistor and the first power line.

[0082] The active portion of the first light-emitting control transistor in the first pixel circuit and the active portion of the first light-emitting control transistor in the third pixel circuit are connected.

[0083] The active portion of the first light-emitting control transistor in the second pixel circuit and the active portion of the first light-emitting control transistor in the fourth pixel circuit are connected.

[0084] Optionally, the display panel also includes a light-emitting control line electrically connected to the gate of the first light-emitting control transistor;

[0085] The light-emitting control lines of the first light-emitting control transistors in the two pixel circuits of the same pixel circuit group are symmetrical about the first gate line.

[0086] According to another aspect of the present invention, a display panel is provided, the display panel comprising:

[0087] Substrate;

[0088] Multiple pixel circuit groups are located on a substrate; each pixel circuit group includes two pixel circuits, each pixel circuit includes a driving transistor and a third initialization transistor, and the first terminal of the third initialization transistor is electrically connected to the first or second terminal of the driving transistor.

[0089] In two adjacent pixel circuit groups arranged along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit. The driving transistors in the first pixel circuit and the second pixel circuit are arranged along the first direction, the driving transistors in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the driving transistors in the first pixel circuit and the third pixel circuit are arranged along the second direction, and the driving transistors in the second pixel circuit and the fourth pixel circuit are arranged along the second direction; the first direction and the second direction intersect.

[0090] In two adjacent pixel circuit groups arranged along the second direction, the second poles of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected.

[0091] And / or, in two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected.

[0092] Optionally, in two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit is connected;

[0093] And / or, in two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected.

[0094] According to another aspect of the present invention, a display device is provided, the display device comprising the display panel described in any embodiment of the present invention.

[0095] The technical solution of this invention reduces the number of first gate lines in the display panel by arranging the second functional elements in two pixel circuits in the same pixel circuit group along a second direction and electrically connecting them to the same first gate line, thereby improving the light transmittance of the display panel and thus improving the display effect of the display panel.

[0096] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0097] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0098] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of the present invention;

[0099] Figure 2 This is a schematic diagram of the arrangement of a second functional element provided in an embodiment of the present invention;

[0100] Figure 3 This is a schematic diagram of another arrangement of the second functional elements provided in an embodiment of the present invention;

[0101] Figure 4A This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0102] Figure 4B This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0103] Figure 5 This is a top view structural diagram of another display panel provided in an embodiment of the present invention;

[0104] Figure 6 This is a top view structural diagram of another display panel provided in an embodiment of the present invention;

[0105] Figure 7 This is a top view structural diagram of another display panel provided in an embodiment of the present invention;

[0106] Figure 8 This is a top view structural diagram of another display panel provided in an embodiment of the present invention;

[0107] Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0108] Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0109] Figure 11 This is a partial top view of the display panel provided in an embodiment of the present invention;

[0110] Figure 12 This is another partial top view of the display panel provided in an embodiment of the present invention;

[0111] Figure 13 This is a top view structural diagram of another display panel provided in an embodiment of the present invention;

[0112] Figure 14 This is a top view structural diagram of another display panel provided in an embodiment of the present invention;

[0113] Figure 15 yes Figure 14 A sectional view along the a1-a2 direction;

[0114] Figure 16 yes Figure 12 A partial top-view structural schematic diagram;

[0115] Figure 17 This is a top view structural diagram of another display panel provided in an embodiment of the present invention;

[0116] Figure 18 yes Figure 13 A sectional view along the b1-b2 direction;

[0117] Figure 19 This is a schematic diagram of the layout structure of the first conductive layer and the first active layer of the display panel provided in an embodiment of the present invention;

[0118] Figure 20 This is a schematic diagram of the layout structure of the second conductive layer of the display panel provided in an embodiment of the present invention;

[0119] Figure 21 This is a schematic diagram of the layout structure of the second conductive layer, the second active layer, and the third conductive layer of the display panel provided in an embodiment of the present invention;

[0120] Figure 22 This is a schematic diagram of the layout structure of the fourth conductive layer of a display panel provided in an embodiment of the present invention;

[0121] Figure 23 This is a schematic diagram of the layout structure of the fifth conductive layer of a display panel provided in an embodiment of the present invention;

[0122] Figure 24 This is a schematic diagram of the layout structure of the sixth conductive layer of the display panel provided in an embodiment of the present invention;

[0123] Figure 25 yes Figure 13 Another sectional view along the b1-b2 direction;

[0124] Figure 26 yes Figure 14 A sectional view along the e1-e2 direction;

[0125] Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0126] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0127] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0128] The display panel includes a photosensitive element, which is typically located under the screen. This photosensitive element may include a fingerprint recognition module, a camera, an infrared sensor, and an ambient light detection module. A higher pixel density in the display panel can reduce its transmittance, affecting the light-sensing performance of the photosensitive element.

[0129] To address the aforementioned technical problems, embodiments of the present invention provide a display panel. Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of the present invention, for reference. Figure 1 The display panel includes:

[0130] Substrate 100;

[0131] Multiple pixel circuit groups 200 are located on the substrate 100; each pixel circuit group 200 includes two pixel circuits 210, each pixel circuit 210 includes a first functional element 211 and a second functional element 212. In the same pixel circuit group 200, the first functional elements 211 in the two pixel circuits 210 are arranged along a first direction Y, and the second functional elements 212 in the two pixel circuits 210 are arranged along a second direction X. The first direction Y and the second direction X intersect, for example, perpendicularly.

[0132] Multiple first gate lines S1 are arranged along a first direction Y and extend along a second direction X. Second functional elements 212 in two pixel circuits 210 in the same pixel circuit group 200 are electrically connected to the same first gate line S1. For example, the orthographic projections of the second functional elements 212 in two pixel circuits 210 in the same pixel circuit group 200 on the substrate overlap with the orthographic projections of the same first gate line S1 on the substrate.

[0133] The substrate 100 serves to support, protect, and buffer the image. The substrate 100 can be a flexible substrate or a rigid substrate; this embodiment does not limit its application. The first direction Y can be a column direction, and the second direction X can be a row direction. In some other embodiments, the first direction Y can also be a row direction, and the second direction X can be a column direction. The pixel circuit 210 can be a 2T1C pixel circuit or a variation thereof, or a 7T1C pixel circuit or a variation thereof; this is not limited here. The display panel may also include light-emitting elements. The pixel circuit 210 can be connected to the corresponding light-emitting element, providing a driving current to the light-emitting element, causing the light-emitting element to emit light in response to the driving current, thereby enabling the display panel to display an image. Multiple pixel circuit groups 200 can be arranged in an array, for example, multiple pixel circuit groups 200 arranged along the first direction Y, and multiple pixel circuit groups 200 arranged along the second direction X.

[0134] Specifically, the first functional element 211 and the second functional element 212 can be transistors in the pixel circuit 210. The second functional element 212 is connected to the first gate line S1, and the first gate line S1 can provide a gate drive signal to the second functional element 212, thereby controlling the second functional element 212 to be turned on or off, that is, controlling the conduction timing of the second functional element 212, and thus controlling the timing of the pixel circuit 210. By arranging the second functional elements 212 in the two pixel circuits 210 in the same pixel circuit group 200 along the second direction X and electrically connected to the same first gate line S1, the number of first gate lines S1 in the display panel can be reduced, thereby improving the light transmittance of the display panel, so that the photosensitive devices in the display panel can better detect ambient light or perform fingerprint recognition or photography, etc.

[0135] In the same pixel circuit group 200, the first functional elements 211 in the two pixel circuits 210 are arranged along the first direction Y. In the same pixel circuit group 200, the second functional elements 212 in the two pixel circuits 210 are arranged along the second direction X, which facilitates the connection of the second functional elements 212 with the first gate line S1, reduces the connection traces, and can further improve the transmittance of the display panel, thereby improving the performance of the display panel.

[0136] The technical solution of this embodiment, by setting the second functional elements in two pixel circuits in the same pixel circuit group to be arranged along the second direction and electrically connected to the same first gate line, can reduce the number of first gate lines in the display panel, thereby improving the light transmittance of the display panel and thus improving the display effect of the display panel.

[0137] Based on the above technical solutions, the arrangement of the second functional element 212 in different pixel circuits will be further explained below, but this is not intended to limit the present application.

[0138] Optionally, refer to Figure 1 In two adjacent pixel circuit groups 200 arranged along the second direction X, one pixel circuit group 200 includes a first pixel circuit 210A and a second pixel circuit 210B, and the other pixel circuit group 200 includes a third pixel circuit 210C and a fourth pixel circuit 210D. The first functional elements 211 in the first pixel circuit 210A and the second pixel circuit 210B are arranged along the first direction Y, the first functional elements 211 in the third pixel circuit 210C and the fourth pixel circuit 210D are arranged along the first direction Y, the first functional elements 211 in the first pixel circuit 210A and the third pixel circuit 210C are arranged along the second direction X, and the first functional elements 211 in the second pixel circuit 210B and the fourth pixel circuit 210D are arranged along the second direction X. For example, the first functional elements 211 in two adjacent pixel circuits 210 arranged along the first direction Y are arranged along the first direction Y and are symmetrically arranged. Similarly, the first functional elements 211 in two adjacent pixel circuits 210 arranged along the second direction X are arranged along the second direction X and are symmetrically arranged. This makes it easier to save space and simplify wiring.

[0139] In one implementation, such as Figure 1As shown, the second functional element 212 in the second pixel circuit 210B, the second functional element 212 in the first pixel circuit 210A, the second functional element 212 in the third pixel circuit 210C, and the second functional element 212 in the fourth pixel circuit 210D are arranged sequentially along the second direction X. For example, the second functional elements 212 in two adjacent pixel circuits 210 are arranged symmetrically along the second direction X. For example, the second functional elements 212 in the (2n-1)th and 2nth row pixel circuits 210 are arranged along the second direction X and connected to the same first gate line S1, reducing the number of connection traces and further improving the transmittance of the display panel. For example, the orthographic projection of the second functional elements 212 in the (2n-1)th and 2nth row pixel circuits 210 onto the substrate overlaps with the orthographic projection of the same first gate line S1 onto the substrate. For example, n is an integer greater than or equal to 1, such as n = 1, 2, 3, ... For example, the row direction is parallel to the second direction, and the column direction is parallel to the first direction. For example, the second functional element 212 in the pixel circuit 210 of the 2nth row and 2k-1th column, the second functional element 212 in the pixel circuit 210 of the 2n-1th row and 2k-1th column, the second functional element 212 in the pixel circuit 210 of the 2n-1th row and 2k-1th column, and the second functional element 212 in the pixel circuit 210 of the 2nth row and 2k-1th column are arranged along the second direction X and connected to the same first gate line S1. For example, k is an integer greater than or equal to 1, such as k = 1, 2, 3, ... In another embodiment, Figure 2 This is a schematic diagram of the arrangement of a second functional element provided in an embodiment of the present invention. Optionally, refer to... Figure 2 The second functional element 212 in the first pixel circuit 210A, the second functional element 212 in the second pixel circuit 210B, the second functional element 212 in the fourth pixel circuit 210D, and the second functional element 212 in the third pixel circuit 210C are arranged sequentially along the second direction X. For example, the second functional elements 212 in two adjacent pixel circuits 210 are arranged symmetrically along the second direction X. Furthermore, the second functional element 212 of the first pixel circuit 210A can be placed closer to other devices in the first pixel circuit 210A, and the second functional element 212 of the second pixel circuit 210B can be placed closer to other devices in the second pixel circuit 210B, thereby facilitating wiring design. For example, the second functional element 212 in the pixel circuit 210 of the 2n-1th row and 2k-1th column, the second functional element 212 in the pixel circuit 210 of the 2nth row and 2k-1th column, the second functional element 212 in the pixel circuit 210 of the 2nth row and 2k-1th column, and the second functional element 212 in the pixel circuit 210 of the 2n-1th row and 2k-1th column are arranged along the second direction X and connected to the same first gate line S1.

[0140] In yet another implementation, Figure 3This is a schematic diagram of another arrangement of the second functional elements provided in an embodiment of the present invention. Optionally, refer to... Figure 3 The second functional elements 212 in the first pixel circuit 210A, the second functional elements 212 in the second pixel circuit 210B, the second functional elements 212 in the third pixel circuit 210C, and the second functional elements 212 in the fourth pixel circuit 210D are arranged sequentially along the second direction X. This arrangement of adjacent second functional elements 212 in multiple pixel circuits 210 along the second direction X facilitates connection of these elements to the first gate line S1, reduces wiring, and further improves the transmittance of the display panel. For example, the second functional elements 212 in the 2n-1 row and 2k-1 column of the pixel circuit 210, the 2n row and 2k-1 column of the pixel circuit 210, the 2n-1 row and 2k column of the pixel circuit 210, and the 2n row and 2k column of the pixel circuit 210 are arranged along the second direction X and connected to the same first gate line S1. For example, the second functional element 212 in the pixel circuit 210 of the 2nth row and 2k-1th column, the second functional element 212 in the pixel circuit 210 of the 2n-1th row and 2k-1th column, the second functional element 212 in the pixel circuit 210 of the 2nth row and 2k-1th column, and the second functional element 212 in the pixel circuit 210 of the 2nth row and 2k-1th column are arranged along the second direction X and connected to the same first gate line S1.

[0141] Based on the above technical solutions, the following describes the devices that may be included in the pixel circuit 210, but this is not intended to limit the scope of this application.

[0142] Optionally, the first functional element 211 includes a driving transistor T1, and the second functional element 212 includes an initialization transistor. For example, the second functional element 212 in different pixel circuits 210 may have the same function. The driving transistor T1 can generate a driving current, causing the light-emitting element to emit light in response to the driving current. The initialization transistor can be used to initialize, for example, the gate of the driving transistor T1 or the first electrode of the light-emitting element, or other electrodes of the driving transistor T1, such as the first or second electrode of the driving transistor T1. This can clear residual charge, allowing the light-emitting element to emit light better.

[0143] Based on the above technical solution, the transistors that the second functional element 212 may include will be described below, but this is not intended to limit the scope of this application.

[0144] In some implementations, the second functional element 212 includes a first initialization transistor T2.

[0145] In one implementation, Figure 4A This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 4A The first initialization transistor T2 is electrically connected to the gate of the driving transistor T1. This allows the first initialization transistor T2 to initialize the gate of the driving transistor T1, preventing residual charge on the gate of the driving transistor T1 from affecting the driving current generated by the driving transistor T1, thus enabling the light-emitting element to better respond to the driving current and emit light.

[0146] In another implementation, Figure 4B This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Optionally, refer to... Figure 4B The pixel circuit 210 includes a compensation transistor T3, which is connected between the first electrode and the gate of the driving transistor T1, and the first initialization transistor T2 is electrically connected to the first electrode of the driving transistor T1.

[0147] Among them, the compensation transistor T3 can transmit the voltage related to the threshold voltage and data voltage of the driving transistor T1 to the gate of the driving transistor T1, so that the driving current generated by the driving transistor T1 is independent of the threshold voltage of the driving transistor T1. Thus, the change of the threshold voltage of the driving transistor T1 will not affect the driving current generated by the driving transistor T1, ensuring the stability of the driving current and thereby improving the stability of the light emission of the light-emitting element.

[0148] Specifically, the compensation transistor T3 is connected between the first terminal of the driving transistor T1 and the gate of the driving transistor T1. When the compensation transistor T3 and the first initialization transistor T2 are turned on, the first initialization transistor T2 can transmit the first initialization voltage to the gate of the driving transistor T1 through the compensation transistor T3, thereby initializing the gate of the driving transistor T1.

[0149] Figure 5 This is a top view structural diagram of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 5 The display panel also includes multiple first initialization sub-signal lines Vref1, arranged along the first direction Y and extending along the second direction X.

[0150] The first initialization transistor T2 in the two pixel circuits 210 in the same pixel circuit group 200 is electrically connected to the same first initialization sub-signal line Vref1;

[0151] The first initialization sub-signal line Vref1 includes a first sub-segment V11 and a second sub-segment V12 arranged alternately along its own extension direction, with the first sub-segment V11 and the second sub-segment V12 being set in different layers.

[0152] Specifically, the first initialization sub-signal line Vref1 can provide a first initialization voltage to the first initialization transistor T2, allowing the first initialization transistor T2 to transmit the first initialization voltage on the first initialization sub-signal line Vref1 to the gate of the driving transistor T1 when it is turned on, thus initializing the gate of the driving transistor T1. By configuring the first initialization sub-signal line Vref1 to include a first sub-segment V11 and a second sub-segment V12 on different layers, the first initialization sub-signal line Vref1 can be jumpered when it encounters other signal lines, avoiding contact with other signal lines, thereby preventing short circuits or crosstalk, and ensuring the reliability and accuracy of signal transmission.

[0153] Optionally, the first initialization transistor T2 includes an N-type transistor or a P-type transistor.

[0154] Specifically, when the first initialization transistor T2 is an N-type transistor, the leakage current of the gate of the driving transistor T1 can be reduced, thereby ensuring the stability of the driving current of the driving transistor T1. When the first initialization transistor T2 is a P-type transistor, the cost can be reduced and the size of the pixel circuit 210 can be decreased. Figure 4A , Figure 4B and Figure 5 The example shows the case where the first initialization transistor T2 is an N-type transistor, but it is not limited to that case.

[0155] Optionally, the compensation transistor T3 includes an N-type transistor or a P-type transistor.

[0156] Specifically, when the compensation transistor T3 is an N-type transistor, the leakage current of the gate of the driving transistor T1 can be reduced, thereby ensuring the stability of the driving current of the driving transistor T1. When the compensation transistor T3 is a P-type transistor, the cost can be reduced and the size of the pixel circuit 210 can be decreased. Figure 4A , Figure 4B and Figure 5 The example shown illustrates the case where the compensation transistor T3 is an N-type transistor, but it is not a limitation.

[0157] In some implementations... Figure 6 This is a top view structural diagram of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 6The display panel also includes multiple light-emitting elements D1. The second functional element 212 includes a second initialization transistor T4, which is electrically connected to the first electrode of the light-emitting element D1. The second initialization transistor T4 can initialize the first electrode of the light-emitting element D1. The first electrode of the light-emitting element D1 can be an anode, and the second electrode can be a cathode; or, the first electrode of the light-emitting element D1 can be a cathode, and the second electrode can be an anode. Since the second functional element 212 includes the second initialization transistor T4, the element groups of the same pixel circuit group 200 can be symmetrically arranged about the first gate line S1 corresponding to the second initialization transistor T4, facilitating wiring design.

[0158] like Figure 6 As shown, the pixel circuit may also include a data writing transistor T6, a first light-emitting control transistor T7, and a second light-emitting control transistor T8, with the first light-emitting control transistor T7 and the second light-emitting control transistor T8 connected to the light-emitting control line EM. Figure 6 The document does not specify the connection relationships of transistors in pixel circuits. For example... Figure 6 As shown, the pixel circuit may further include a third functional element 213. When the second functional element 212 includes the second initialization transistor T4, the third functional element 213 may include the first initialization transistor T2. The third functional element 213 is connected to the second gate line S2. The compensation transistor T3 is connected to the third gate line S3, and the data writing transistor T6 is connected to the fourth gate line S4. The third gate line S3 and the fourth gate line S4 may be the same gate line.

[0159] In some implementations... Figure 7 This is a top view structural diagram of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 7 The second functional element 212 includes a third initialization transistor T5, which is electrically connected to either the first or second terminal of the driving transistor T1. The third initialization transistor T5 can initialize either the first or second terminal of the driving transistor T1. Specifically, the first terminal of the driving transistor T1 is the source, and the second terminal is the drain; or, the first terminal of the driving transistor T1 is the drain, and the second terminal is the source. Since the second functional element 212 includes the third initialization transistor T5, the element groups of the same pixel circuit group 200 can be symmetrically arranged about the first gate line S1 corresponding to the third initialization transistor T5, facilitating wiring design.

[0160] like Figure 7 As shown, the pixel circuit 210 may also include a data writing transistor T6, a first light-emitting control transistor T7, and a second light-emitting control transistor T8, wherein the first light-emitting control transistor T7 and the second light-emitting control transistor T8 are connected to the light-emitting control line EM. Figure 7 The document does not specify the connection relationships of transistors in pixel circuits. For example... Figure 7 As shown, the pixel circuit 210 may further include a third functional element 213. When the second functional element 212 includes a third initialization transistor T5, the third functional element 213 may include a first initialization transistor T2. The third functional element 213 is connected to the second gate line S2. The compensation transistor T3 is connected to the third gate line S3, and the data writing transistor T6 is connected to the fourth gate line S4.

[0161] In some other implementations, such as Figure 7 As shown, the second functional element 212 may also include a second initialization transistor T4.

[0162] like Figure 4A As shown, the third initialization transistor T5 is connected to the second terminal of the driving transistor T1, as follows. Figure 4B As shown, the third initialization transistor T5 is connected to the first terminal of the driving transistor T1.

[0163] Based on the above technical solutions, optionally, the display panel further includes multiple initialization signal lines arranged along a first direction Y and extending along a second direction X. The second functional elements 212 in two pixel circuits 210 within the same pixel circuit group 200 are electrically connected to the same initialization signal line. For example, the orthographic projections of the second functional elements 212 in two pixel circuits 210 within the same pixel circuit group 200 on the substrate overlap with the orthographic projections of the same initialization signal line electrically connected to them on the substrate. Similarly, the orthographic projections of the gate lines connected to the second functional elements 212 in two pixel circuits 210 within the same pixel circuit group 200 on the substrate overlap with the orthographic projections of the same initialization signal line electrically connected to them on the substrate.

[0164] Specifically, the initialization signal line can be connected to the first initialization transistor T2, the second initialization transistor T4, or the third initialization transistor T5. For example... Figure 5 As shown, the initialization signal line is the first initialization sub-signal line Vref1, which can provide the first initialization voltage to the first initialization transistor T2. By setting the second functional element 212 in two pixel circuits 210 in the same pixel circuit group 200 to be electrically connected to the same initialization signal line, the number of initialization signal lines can be reduced, which is beneficial to improving the transmittance of the display panel and thus further improving the performance of the display panel. For example... Figure 3 As shown, the first pixel circuit 210A and the second pixel circuit 210B share the same first initialization sub-signal line Vref1, which reduces the number of first initialization sub-signal lines Vref1.

[0165] Based on the above technical solutions, the following description may also include the structure of the pixel circuit 210, but it is not intended to limit this application.

[0166] Figure 8 This is a top view structural diagram of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 8 The pixel circuit 210 further includes a third functional element 213. In two adjacent pixel circuit groups 200 arranged along the first direction Y, one pixel circuit group 200 includes a first pixel circuit 210A and a second pixel circuit 210B, and the other pixel circuit group 200 includes a fifth pixel circuit 210E and a sixth pixel circuit 210F. The first functional element 211 in the first pixel circuit 210A, the first functional element 211 in the second pixel circuit 210B, the first functional element 211 in the fifth pixel circuit 210E, and the first functional element 211 in the sixth pixel circuit 210F are arranged sequentially along the first direction Y.

[0167] The display panel also includes: multiple second gate lines S2, arranged along the first direction Y and extending along the second direction X.

[0168] In two adjacent pixel circuit groups 200 arranged along the first direction Y, the third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E are arranged along the first direction Y and electrically connected to different second gate lines S2.

[0169] Specifically, the third functional element 213 can be a transistor in the pixel circuit 210. The second gate line S2 can provide a gate drive signal to the third functional element 213, thereby controlling the third functional element 213 to be turned on or off, and thus controlling the turn-on timing of the third functional element 213, which facilitates the control of the pixel circuit 210. By arranging the third functional elements 213 in the second pixel circuit 210B and the third functional elements 213 in the fifth pixel circuit 210E along the first direction Y and electrically connecting them to different second gate lines S2, the wiring design can be facilitated.

[0170] Based on the above technical solutions, optionally, refer to Figure 8 The first functional element 211 includes a driving transistor T1.

[0171] One of the second functional element 212 and the third functional element 213 includes a first initialization transistor T2, which is electrically connected to the gate of the driving transistor T1; or, the pixel circuit 210 includes a compensation transistor T3, which is connected between the first terminal and the gate of the driving transistor T1, and the first initialization transistor T2 is electrically connected to the first terminal of the driving transistor T1.

[0172] The other of the second functional element 212 and the third functional element 213 includes a second initialization transistor T4.

[0173] The display panel also includes multiple light-emitting elements D1, and the second initialization transistor T4 is electrically connected to the first electrode of the light-emitting element D1.

[0174] Specifically, one of the second functional element 212 and the third functional element 213 includes a first initialization transistor T2, and the other includes a second initialization transistor T4. That is, the two pixel circuits 210 in the same pixel circuit group 200 can be symmetrical about the gate line corresponding to the first initialization transistor T2, or they can be symmetrical about the gate line corresponding to the second initialization transistor T4. Therefore, the gate line corresponding to the first initialization transistor T2 of the two pixel circuits 210 in the same pixel circuit group 200 can be shared, or the gate line corresponding to the second initialization transistor T4 can be shared.

[0175] Optionally, refer to Figure 8 The pixel circuit 210 also includes a third initialization transistor T5, the first terminal of which is electrically connected to the first or second terminal of the driving transistor T1.

[0176] The display panel also includes multiple second gate lines S2, arranged along the first direction Y and extending along the second direction X; the gate of the third initialization transistor T5 is electrically connected to the second gate lines S2.

[0177] Specifically, the third initialization transistor T5 can initialize the first or second terminal of the driving transistor T1, thereby eliminating residual charge on the first or second terminal of the driving transistor T1, making it easier for the driving transistor T1 to generate driving current. Furthermore, it can adjust the bias state of the driving transistor T1, improving its characteristics and enabling it to generate driving current stably.

[0178] Optionally, the second initialization transistor T4 and the third initialization transistor T5 have the same channel type. Thus, when the second functional element 212 includes the first initialization transistor T2 and the third functional element 213 includes the second initialization transistor T4, that is, when the two pixel circuits 210 in the same pixel circuit group 200 are symmetrical about the gate line corresponding to the first initialization transistor T2, the second initialization transistor T4 and the third initialization transistor T5 can share a gate line, thereby further reducing the number of gate lines, further improving the transmittance of the display panel, and improving the performance of the display panel.

[0179] Optionally, the second initialization transistor T4 includes a P-type transistor; the third initialization transistor T5 also includes a P-type transistor. This reduces cost and the space occupied by the second and third initialization transistors T4 and T5, thereby improving the transmittance of the display panel. Furthermore, the second and third initialization transistors T4 and T5 can share a gate line, further reducing the number of gate lines.

[0180] Based on the above technical solutions, optionally, refer to Figure 8 The display panel also includes multiple first initialization sub-signal lines Vref1, arranged along the first direction Y and extending along the second direction X.

[0181] The second functional element 212 in two pixel circuits 210 in the same pixel circuit group 200 is electrically connected to the same first initialization sub-signal line Vref1;

[0182] The display panel also includes multiple second initialization sub-signal lines Vref2, arranged along the first direction Y and extending along the second direction X.

[0183] In two adjacent pixel circuit groups 200 arranged along the first direction Y, the third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E are electrically connected to the same second initialization sub-signal line Vref2.

[0184] Specifically, the second initialization sub-signal line Vref2 can provide a second initialization voltage to the third functional element 213, so that when the third functional element 213 is turned on, it can transmit the second initialization voltage to the first electrode of the light-emitting element to initialize the first electrode of the light-emitting element. By setting the third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E to the same second initialization sub-signal line Vref2, the number of second initialization sub-signal lines Vref2 can be reduced, that is, the number of signal lines in the display panel is further reduced, thereby further improving the transmittance of the display panel. For example, the voltage magnitudes on the first initialization sub-signal line Vref1 and the second initialization sub-signal line Vref2 are different. For example, the first initialization sub-signal line Vref1 and the second initialization sub-signal line Vref2 are arranged alternately along the first direction Y.

[0185] Optionally, refer to Figure 8 The display panel also includes multiple third initialization sub-signal lines Vref3, arranged along the second direction X and extending along the first direction Y; the third initialization sub-signal lines Vref3 are electrically connected to the first initialization sub-signal lines Vref1.

[0186] The first initialization sub-signal line Vref1 includes a first sub-segment V11 and a second sub-segment V12 arranged alternately along its own extension direction, with the first sub-segment V11 and the second sub-segment V12 being set in different layers;

[0187] The display panel also includes multiple fourth initialization sub-signal lines Vref4, arranged along the second direction X and extending along the first direction Y; the fourth initialization sub-signal lines Vref4 are electrically connected to the second initialization sub-signal lines Vref2; the orthographic projection of the second sub-segment V12 on the substrate 100 overlaps with the orthographic projection of the fourth initialization sub-signal lines Vref4 on the substrate 100, and the second sub-segment V12 and the fourth initialization sub-signal lines Vref4 are disposed in different layers.

[0188] Specifically, by setting a third initialization sub-signal line Vref3, which forms a mesh structure with the first initialization sub-signal line Vref1, the voltage drop across the first initialization sub-signal line Vref1 can be reduced, preventing large fluctuations in the first initialization voltage. Similarly, by setting a fourth initialization sub-signal line Vref4, which forms a mesh structure with the second initialization sub-signal line Vref2, large fluctuations in the second initialization voltage on the second initialization sub-signal line Vref2 can be prevented. By setting the first initialization sub-signal line Vref1 to include a first sub-segment V11 and a second sub-segment V12, and setting the second sub-segment V12 and the fourth initialization sub-signal line Vref4 to be on different layers, the fourth initialization sub-signal line Vref4 can be prevented from overlapping with the first initialization sub-signal line Vref1, thus avoiding signal confusion or short circuits.

[0189] It should be noted that the third initialization sub-signal line Vref3 can be located to the left or right of the fourth initialization sub-signal line Vref4, and this embodiment does not impose any limitation. For example, the third initialization sub-signal line Vref3 and the fourth initialization sub-signal line Vref4 can be arranged alternately along the second direction X.

[0190] Optionally, refer to Figure 8 The first sub-segment V11, the third initialization sub-signal line Vref3, and the fourth initialization sub-signal line Vref4 are set on the same layer, and the second sub-segment V12 and the second initialization sub-signal line Vref2 are set on the same layer. In this way, the number of film layers can be reduced, the thickness of the display panel can be reduced, and it is convenient to make the display panel thinner and lighter.

[0191] Optionally, refer to Figure 8The first sub-segment V11 and the second sub-segment V12 are connected through the first via V01, and the first sub-segment V11 is connected to the second functional element 212 through the second via V02. This connection forms the first initialization sub-signal line Vref1, allowing the first sub-segment V11 to be connected to the second functional element 212 and providing the second functional element 212 with a first initialization voltage.

[0192] Optionally, the second vias V02 corresponding to the second functional elements 212 in two pixel circuits 210 within the same pixel circuit group 200 are located on opposite sides of the first sub-segment V11 along the first direction Y. For example Figure 6 As shown, the second via V02 corresponding to the second functional element 212 in the first pixel circuit 210A is located below the second sub-segment V12, and the second via V02 corresponding to the second functional element 212 in the second pixel circuit 210B is located above the second sub-segment V12. The two second vias V02 are located on opposite sides of the first sub-segment V11 along the first direction Y, so that the first initialization sub-signal line Vref1 can provide the first initialization voltage to the corresponding second functional element 212.

[0193] Based on the above technical solutions, the following describes the structures that the display panel may also include, but this is not intended to limit this application.

[0194] Figure 9 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Optionally, refer to... Figure 9 The display panel also includes a first gate driving circuit 310, which includes multiple cascaded first shift registers 311. The second functional element 212 in the first pixel circuit 210A and the second functional element 212 in the second pixel circuit 210B are electrically connected to the output terminal Out of the same first shift register 311. The second functional element 212 in the fifth pixel circuit 210E and the second functional element 212 in the sixth pixel circuit 210F are electrically connected to the output terminal Out of the same first shift register 311. The second functional element 212 in the second pixel circuit 210B and the second functional element 212 in the fifth pixel circuit 210E are electrically connected to the output terminals Out of different first shift registers 311.

[0195] For example, the first gate drive circuit 310 includes a plurality of first shift registers 311. The input terminal of the first first shift register 311 is connected to the input voltage SIN. The input terminal of the (m+1)th first shift register 311 is connected to the output terminal of the m-th first shift register 311, realizing a cascaded connection. Each first shift register 311 is connected to a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 have the same frequency, but the second clock signal CLK2 is delayed compared to the first clock signal CLK1, i.e., they have different phases, such as opposite phases. The first clock terminal SCK1 of the m-th first shift register 311 is connected to the first clock signal CLK1, and the second clock terminal SCK2 of the m-th first shift register 311 is connected to the second clock signal CLK2. The first clock terminal SCK1 of the (m+1)th first shift register 311 is connected to the second clock signal CLK2, and the second clock terminal SCK2 of the (m+1)th first shift register 311 is connected to the first clock signal CLK1. This facilitates the shifting output of the gate drive signal. Here, m is an integer greater than or equal to 1.

[0196] Specifically, by electrically connecting the second functional element 212 in the first pixel circuit 210A and the second functional element 212 in the second pixel circuit 210B to the same output terminal Out of the first shift register 311, and electrically connecting the second functional element 212 in the fifth pixel circuit 210E and the second functional element 212 in the sixth pixel circuit 210F to the same output terminal Out of the first shift register 311, the number of first gate lines S1 and first shift registers 311 can be reduced, thereby further improving the transmittance of the display panel. For example, the output terminal of each first shift register 311 is connected to at least two rows of pixel circuits or 2i rows of pixel circuits. For example, i is an integer greater than or equal to 1.

[0197] Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Optionally, refer to... Figure 10 The display panel also includes a second gate driving circuit 320, which includes multiple cascaded second shift registers 321. The third functional element 213 in the first pixel circuit 210A and the third functional element 213 in the second pixel circuit 210B are electrically connected to the output terminal OUT of the same second shift register 321. The third functional element 213 in the fifth pixel circuit 210E and the third functional element 213 in the sixth pixel circuit 210F are electrically connected to the output terminal of the same second shift register 321. The third functional element 213 in the second pixel circuit 210B and the third functional element 213 in the fifth pixel circuit 210E are electrically connected to the output terminals OUT of different second shift registers 321.

[0198] Specifically, for example, the second gate drive circuit 320 includes multiple second shift registers 321. The input terminal of the first second shift register 321 is connected to the input voltage SIN'. The input terminal of the (j+1)th second shift register 321 is connected to the output terminal of the j-th second shift register 321, achieving a cascaded connection. Each second shift register 321 is connected to a third clock signal CLK3 and a fourth clock signal CLK4, with the third clock signal CLK3 and the fourth clock signal CLK4 having the same frequency, for example, the fourth clock signal CLK4 being delayed compared to the third clock signal CLK3. The first clock terminal SCK3 of the j-th second shift register 321 is connected to the third clock signal CLK3, and the second clock terminal SCK4 of the j-th second shift register 321 is connected to the fourth clock signal CLK4. The first clock terminal SCK3 of the (j+1)th second shift register 321 is connected to the fourth clock signal CLK4, and the second clock terminal SCK4 of the (j+1)th second shift register 321 is connected to the third clock signal CLK3. This facilitates the shifted output of the gate drive signal. For example, j is an integer greater than or equal to 1.

[0199] By electrically connecting the third functional element 213 in the first pixel circuit 210A and the third functional element 213 in the second pixel circuit 210B to the same output terminal OUT of the second shift register 321, and electrically connecting the third functional element 213 in the fifth pixel circuit 210E and the third functional element 213 in the sixth pixel circuit 210F to the same output terminal OUT of the second shift register 321, the number of second gate lines S2 and the number of second shift registers 321 can be reduced, thereby further improving the transmittance of the display panel. For example, the output terminal of each second shift register 321 is connected to at least two rows of pixel circuits or 2i rows of pixel circuits. For example, i is an integer greater than or equal to 1. For example, the number of pixel circuit rows connected to the output terminal of each second shift register 321 is equal to the number of pixel circuit rows connected to the output terminal of each first shift register 311. For example, the 2i rows of pixel circuits connected to the output terminal of the w-th stage second shift register 321 are the same 2i rows of pixel circuits connected to the output terminal of the w-th stage first shift register 311.

[0200] Based on the above technical solutions, optionally, refer to Figure 8The third functional element 213 includes an initialization transistor. In two adjacent pixel circuit groups 200 arranged along the first direction Y, the active portion T41 of the third functional element 213 in the second pixel circuit 210B and the active portion T41 of the third functional element 213 in the fifth pixel circuit 210E are connected. This allows the drain or source of the third functional element 213 in the second pixel circuit 210B and the fifth pixel circuit 210E to be shared, enabling the third functional element 213 in the second pixel circuit 210B and the fifth pixel circuit 210E to be connected to the same initialization signal line. This facilitates the connection of two adjacent third functional elements 213 to the same initialization signal line, reducing the number of vias used to connect the third functional element 213 to the initialization signal line, thus reducing the space occupied by the third functional element 213 and the number of signal lines, thereby improving the transmittance of the display panel and / or increasing the pixel resolution. For example, at least two third functional elements 213 are connected to the same initialization signal line through the same via.

[0201] Based on the above technical solutions, optionally, the pixel circuit 210 includes a driving transistor T1 and a third initialization transistor T5, wherein the first terminal of the third initialization transistor T5 is electrically connected to the first or second terminal of the driving transistor T1.

[0202] The second electrodes of the third initialization transistors T5 in the two pixel circuits 210 within the same pixel circuit group 200 are electrically connected; and / or, the active portions of the third initialization transistors T5 in the two pixel circuits 210 within the same pixel circuit group 200 are connected. This allows the second electrodes of the third initialization transistors T5 in the two pixel circuits 210 within the same pixel circuit group 200 to be shared, reducing the space occupied by the third initialization transistors T5, reducing the number of vias used to connect the third initialization transistors T5 to the initialization signal line, and further improving the transmittance of the display panel. For example, at least two third initialization transistors T5 are connected to the same initialization signal line through the same via.

[0203] Optionally, in two adjacent pixel circuit groups 200 arranged along the second direction X, the second terminals of the third initialization transistors T5 in the first pixel circuit 210A and the second pixel circuit 210B are connected; and / or, in two adjacent pixel circuit groups 200 arranged along the second direction X, the active portions of the third initialization transistors T5 in the first pixel circuit 210A and the second pixel circuit 210B are connected. This allows the second terminals of the third initialization transistors T5 in the two pixel circuits 210 in each pixel circuit group 200 to be shared, facilitating layout design and improving the transmittance of the display panel.

[0204] Figure 11This is a partial top view of the display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 11 In two adjacent pixel circuit groups 200 arranged along the second direction X, the second terminals T51 of the third initialization transistors T5 in the first pixel circuit 210A and the third pixel circuit 210C are connected; and / or, in two adjacent pixel circuit groups 200 arranged along the second direction X, the active portions T52 of the third initialization transistors T5 in the first pixel circuit 210A and the third pixel circuit 210C are connected. This allows the second terminals T51 of the third initialization transistors T5 in the first pixel circuit 210A and the third pixel circuit 210C to be shared, thereby reducing the space occupied by the third initialization transistors T5 and improving the transmittance of the display panel. For example, at least three third initialization transistors T5 are connected to the same initialization signal line through the same via.

[0205] Figure 12 This is another partial top view of the display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 12 In two adjacent pixel circuit groups 200 arranged along the second direction X, the second terminals of the third initialization transistors T5 in the first pixel circuit 210A, second pixel circuit 210B, third pixel circuit 210C, and fourth pixel circuit 210D are connected; and / or, in two adjacent pixel circuit groups 200 arranged along the second direction X, the active portions of the third initialization transistors T5 in the first pixel circuit 210A, second pixel circuit 210B, third pixel circuit 210C, and fourth pixel circuit 210D are connected. This allows the second terminals of the third initialization transistors T5 in the first pixel circuit 210A, second pixel circuit 210B, third pixel circuit 210C, and fourth pixel circuit 210D to be shared, reducing the space occupied by the third initialization transistors T5 and facilitating wiring design. For example, at least four third initialization transistors T5 can be connected to the same initialization signal line through the same via.

[0206] Based on the above technical solutions, Figure 13 This is a top view structural diagram of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 13 The pixel circuit 210 includes a component group, which includes a first functional element 211. The component groups in two adjacent pixel circuits 210 are arranged mirror-symmetrically along the first direction Y. That is, the component groups are symmetrical about the first gate line S1, which can reduce the number of traces and facilitate improving the transmittance of the display panel. The component group is a part of the structure of the pixel circuit 210.

[0207] Optionally, refer to Figure 13The component groups in two adjacent pixel circuits 210 are arranged in a mirror-symmetrical configuration along the second direction X. This allows some electrodes or traces in the component groups to be shared, which facilitates improved transmittance of the display panel and simplified trace design.

[0208] Optionally, refer to Figure 13 The two adjacent pixel circuits 210 arranged along the second direction X are mirror-symmetrically arranged. That is, the entire structure of the two adjacent pixel circuits 210 arranged along the second direction X can be mirror-symmetrical, so that some electrodes or traces of the two adjacent pixel circuits 210 arranged along the second direction X can be shared, which is conducive to improving the transmittance of the display panel and facilitating the trace design.

[0209] Optionally, refer to Figure 13 The first functional element 211 includes a driving transistor T1, and the element group also includes a data writing transistor T6, a compensation transistor T3, a first light-emitting control transistor T7, and a second light-emitting control transistor T8. For example... Figure 13 As shown, the driving transistor T1 in the first pixel circuit 210A is mirror-symmetrical to the driving transistor T1 in the second pixel circuit 210B; the data writing transistor T6 in the first pixel circuit 210A is mirror-symmetrical to the data writing transistor T6 in the second pixel circuit 210B; the compensation transistor T3 in the first pixel circuit 210A is mirror-symmetrical to the compensation transistor T3 in the second pixel circuit 210B; the first light-emitting control transistor T7 in the first pixel circuit 210A is mirror-symmetrical to the first light-emitting control transistor T7 in the second pixel circuit 210B; and the second light-emitting control transistor T8 in the first pixel circuit 210A is mirror-symmetrical to the second light-emitting control transistor T8 in the second pixel circuit 210B. This allows for the sharing of some electrodes and / or signal lines, thereby reducing the space occupied by the pixel circuit 210 and improving the transmittance of the display panel.

[0210] Optionally, refer to Figure 13 The display panel also includes multiple third gate lines S3, arranged along the first direction Y and extending along the second direction X; the gate of the compensation transistor T3 is electrically connected to the third gate lines S3.

[0211] The third gate line S3 electrically connected to the compensation transistor T3 in the two pixel circuits 210 in the same pixel circuit group 200 is symmetrical about the first gate line S1. This facilitates the connection between the compensation transistor T3 and the third gate line S3. Furthermore, in the two pixel circuits 210 in the same pixel circuit group 200, the corresponding two third gate lines S3 are located on opposite sides of the first gate line S1 along the first direction, and the distance between the corresponding two third gate lines S3 and the first gate line S1 is equal. This ensures that the gate drive signals received by the compensation transistor T3 in the two pixel circuits 210 in the same pixel circuit group 200 are consistent, which helps improve the accuracy of the timing control of the pixel circuit 210 and improves the display uniformity of the display panel. For example, the third gate line S3 includes a third sub-segment and a fourth sub-segment that are alternately arranged along its own extension direction. The third sub-segment of the third gate line S3, which is electrically connected to the compensation transistor T3 in the two pixel circuits 210 in the same pixel circuit group 200, is equidistant from the first gate line S1 by distance d1, and the fourth sub-segment is equidistant from the first gate line S1 by distance d2. d1 may be equal to or not equal to d2, for example, d1 is less than d2.

[0212] Optionally, refer to Figure 13 The display panel also includes multiple fourth gate lines S4, arranged along the first direction Y and extending along the second direction X; the gate of the data writing transistor T6 is electrically connected to the fourth gate lines S4.

[0213] The fourth gate line S4 electrically connected to the data writing transistor T6 in the two pixel circuits 210 of the same pixel circuit group 200 is symmetrical about the first gate line S1. This facilitates the connection between the data writing transistor T6 and the fourth gate line S4. Furthermore, in the two pixel circuits 210 of the same pixel circuit group 200, the corresponding two fourth gate lines S4 are located on opposite sides of the first gate line S1 along the first direction, and the distance between the corresponding two fourth gate lines S4 and the first gate line S1 is equal. This ensures that the gate drive signals received by the data writing transistor T6 in the two pixel circuits 210 of the same pixel circuit group 200 are consistent, which helps improve the accuracy of the timing control of the pixel circuit 210 and improves the display uniformity of the display panel. For example, the fourth gate line S4 includes a fifth sub-segment and a sixth sub-segment that are alternately arranged along its own extension direction. The fifth sub-segment of the fourth gate line S4, which is electrically connected to the compensation transistor T3 in the two pixel circuits 210 in the same pixel circuit group 200, is equidistant from the first gate line S1 by distance d3, and the sixth sub-segment is equidistant from the first gate line S1 by distance d4. d3 may be equal to or not equal to d4, for example, d3 is less than d4.

[0214] Figure 14 This is a top view structural diagram of another display panel provided in an embodiment of the present invention. Figure 15 yes Figure 14A sectional view along the a1-a2 direction, optionally, refer to Figure 14 and Figure 15 The display panel also includes a data line Data, a first data connection line F1 and a second data connection line F2. The first data connection line F1 is connected between the second data connection line F2 and the data line Data. The data line Data is connected to the data writing transistor T4.

[0215] The pixel circuit 210 also includes a third initialization transistor T5; the display panel also includes multiple fifth initialization sub-signal lines Vref5; the gate of the third initialization transistor T5 is connected to the second gate line S2, and the second terminal of the third initialization transistor T5 is electrically connected to the fifth initialization sub-signal line Vref5.

[0216] The second gate line S2, the fifth initialization sub-signal line Vref5 and the first data connection line F1 extend in the same direction;

[0217] Along the thickness direction Z of the display panel, the fifth initialization sub-signal line Vref5 is located between the second gate line S2 and the first data connection line F1. For example, the overlapping area of ​​the orthographic projection of the second gate line S2 on the substrate and the orthographic projection of the first data connection line F1 on the substrate 100 overlaps with the orthographic projection of the fifth initialization sub-signal line Vref5 on the substrate 100. For example, at least two partially adjacent first data connection lines F1 are located on opposite sides of the second initialization sub-signal line Vref2 along the first direction Y, and at least two partially adjacent first data connection lines F1 are symmetrical about the second initialization sub-signal line Vref2, so as to reduce or shield signal interference between adjacent first data connection lines F1 through the second initialization sub-signal line Vref2.

[0218] Specifically, by setting the first data connection line F1 and the second data connection line F2 in the display area of ​​the display panel, the driving voltage output by the corresponding driver chip can be transmitted to the data line Data through the first data connection line F1 and the second data connection line F2. This eliminates the need to set too many fan-shaped traces in the non-display area or the bezel area, reducing the size of the display panel bezel and facilitating the implementation of a narrow bezel. By setting the fifth initialization sub-signal line Vref5 along the thickness direction of the display panel between the second gate line S2 and the first data connection line F1, the voltage on the fifth initialization sub-signal line Vref5 is a DC voltage or power supply voltage, which will not fluctuate, thus achieving a shielding effect. This avoids mutual interference between the gate drive signal on the second gate line S2 and the data voltage on the first data connection line F1, making the signals on the second gate line S2 and the first data connection line F1 more stable. This improves the stability and accuracy of the driving current generated by the pixel circuit 210, which is beneficial to improving the display effect of the display panel.

[0219] Optionally, such as Figure 14 As shown, the display panel also includes a connection trace L1. In the same pixel circuit group 200, the active portions of the data writing transistors T6 in two pixel circuits (e.g., the data writing transistors T6 in the first pixel circuit 210A and the second pixel circuit 210B, which are arranged along the first direction Y and are adjacent to each other) are connected to the connection trace L1 through a third via V3. The connection trace L1 is connected to the corresponding data line Data through the same fourth via V4. In this way, the number of vias can be reduced, the transmittance of the display panel can be improved, and the performance of the display panel can be further improved. The second sub-segment V12 and the connection trace L1 can be arranged on the same layer.

[0220] Among them, such as Figure 15 As shown, the display panel also includes a first active layer 101, which may include the active portion of the driving transistor T1. The display panel also includes a first conductive layer M1.

[0221] Based on the above technical solutions, optionally, refer to Figure 4A , Figure 4B and Figure 13 The pixel circuit 210 includes a driving transistor T1 and a third initialization transistor T5, wherein the first terminal of the third initialization transistor T5 is electrically connected to the first or second terminal of the driving transistor T1.

[0222] The display panel also includes multiple fifth initialization sub-signal lines Vref5, arranged along the first direction Y and extending along the second direction X; the second terminal of the third initialization transistor T5 is electrically connected to the fifth initialization sub-signal line Vref5.

[0223] The display panel also includes multiple second gate lines S2, arranged along the first direction Y and extending along the second direction X. The gate of the third initialization transistor T5 is electrically connected to the second gate lines S2, and the orthographic projection of the second gate lines S2 on the substrate 100 overlaps with the orthographic projection of the fifth initialization sub-signal line Vref5 on the substrate. This facilitates the connection of the third initialization transistor T5 to both the second gate lines S2 and the fifth initialization sub-signal line Vref5, and the fifth initialization sub-signal line Vref5 can shield the second gate line S2 from interference by the signal lines on the side of the fifth initialization sub-signal line Vref5 away from the substrate 100, resulting in smaller fluctuations in the gate drive signal on the second gate line S2, thereby improving the stability of the pixel circuit 210. For example, the voltage magnitudes on the fifth initialization sub-signal line Vref5 and the first initialization sub-signal line Vref1 may be different. For example, the fifth initialization sub-signal line Vref5 and the first initialization sub-signal line Vref1 may be arranged alternately along the first direction Y. For example, the voltage magnitudes on the fifth initialization sub-signal line Vref5 and the second initialization sub-signal line Vref2 may be different. For example, the fifth initialization sub-signal line Vref5 and the second initialization sub-signal line Vref2 are arranged alternately along the first direction Y. The fifth initialization sub-signal line Vref5 and the second sub-segment V12 can be set on the same layer.

[0224] Optionally, refer to Figure 8 The display panel also includes multiple sixth initialization sub-signal lines Vref6, arranged along the second direction X and extending along the first direction Y; the sixth initialization sub-signal lines Vref6 are electrically connected to the fifth initialization sub-signal lines Vref5. Thus, the sixth initialization sub-signal lines Vref6 and the fifth initialization sub-signal lines Vref5 form a mesh structure, which helps to reduce the voltage drop on the fifth initialization sub-signal lines Vref5, thereby improving the accuracy of signal transmission on the fifth initialization sub-signal lines Vref5.

[0225] Figure 16 yes Figure 12 A partial top-view structural diagram, for reference. Figure 16 The third initialization transistor T5 comprises at least two transistors connected in series. For example... Figure 16As shown, the portion where the second gate line S2 overlaps with the first active layer 101 forms the gate of the third initialization transistor T5. The third initialization transistor T5 includes a first sub-transistor T5-1 and a second sub-transistor T5-2, making it a dual-gate transistor. This reduces the leakage current of the driving transistor T1, thereby ensuring the stability of the driving current generated by the driving transistor T1. For example, the sixth initialization sub-signal line Vref6 and the third initialization sub-signal line Vref3 are arranged alternately along the second direction X. Similarly, the sixth initialization sub-signal line Vref6 and the fourth initialization sub-signal line Vref4 are arranged alternately along the second direction X. The sixth initialization sub-signal line Vref6 and the third initialization sub-signal line Vref3 can be arranged on the same layer.

[0226] Based on the above technical solutions, Figure 17 This is a top view structural diagram of another display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 4A , Figure 4B and Figure 17 The pixel circuit 210 includes a driving transistor T1 and a first light-emitting control transistor T7.

[0227] The display panel also includes a first power line VDD, and a first light-emitting control transistor T7 is connected between the second terminal of the driving transistor T1 and the first power line VDD.

[0228] like Figure 5 As shown, the active portion T71 of the first light-emitting control transistor T7 in the first pixel circuit 210A and the active portion of the first light-emitting control transistor T7 in the third pixel circuit 210C are connected.

[0229] The active portion of the first light-emitting control transistor T7 in the second pixel circuit 210B is connected to the active portion of the first light-emitting control transistor T7 in the fourth pixel circuit 210D.

[0230] Specifically, when the first light-emitting control transistor T7 is turned on, it can transmit the first power supply voltage on the first power supply line VDD to the second terminal of the driving transistor T1, enabling the driving transistor T1 to generate a driving current. By connecting the active portion T71 of the first light-emitting control transistor T7 in the first pixel circuit 210A, the active portion T71 of the first light-emitting control transistor T7 in the third pixel circuit 210C, the active portions of the first light-emitting control transistor T7 in the second pixel circuit 210B, and the active portions of the first light-emitting control transistor T7 in the fourth pixel circuit 210D, wiring design is facilitated, the number of vias is reduced, and the first power supply line VDD can be connected to two first light-emitting control transistors T7 through a single via, achieving via sharing and further improving the transmittance of the display panel.

[0231] Optionally, refer to Figure 4A , Figure 4B and Figure 17 The display panel also includes a light-emitting control line EM, which is electrically connected to the gate of the first light-emitting control transistor T7;

[0232] In the same pixel circuit group 200, the first light-emitting control transistors T7 in the two pixel circuits 210 are electrically connected to light-emitting control lines EM that are symmetrical about the first gate line S1. This facilitates the connection between the first light-emitting control transistors T7 and the light-emitting control lines EM. Furthermore, in the two pixel circuits 210 of the same pixel circuit group 200, the corresponding two light-emitting control lines EM are located on opposite sides of the first gate line S1 along the first direction, and the distance between the corresponding two light-emitting control lines EM and the first gate line S1 is equal. This ensures that the gate drive signals received by the first light-emitting control transistors T7 in the two pixel circuits 210 of the same pixel circuit group 200 are consistent, which helps improve the accuracy of the timing control of the pixel circuits 210 and improves the display uniformity of the display panel.

[0233] The following description, in conjunction with schematic diagrams of the layout structure of each film layer of the display panel and a cross-sectional view of the display panel, further illustrates the structure of the display panel, but this is not intended to limit the scope of this application.

[0234] Optionally, the display panel includes one or more of a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5 stacked on the substrate 100, and the display panel also includes one or more of a first active layer 101 and a second active layer 102. The pixel circuit 210 also includes a storage capacitor C1, the first terminal of which is connected to a first power supply line VDD, and the second terminal of which is connected to the gate of the driving transistor T1. For example, any one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 may include a metal layer or a light-transmitting conductive layer (e.g., indium tin oxide ITO). An insulating layer may be disposed between adjacent conductive layers. An insulating layer may be disposed between adjacent conductive layers and the active layer. The active portion may be located in the active layer.

[0235] Figure 18 yes Figure 13 A sectional view along the b1-b2 direction. Figure 19 This is a schematic diagram of the layout structure of the first conductive layer and the first active layer of the display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 18 and Figure 19 The light-emitting control line EM, the second gate line S2, and the fourth gate line S4 are located in the first conductive layer M1, and the first plate C01 of the storage capacitor C1 is located in the first conductive layer M1. The first plate C01 is multiplexed as the gate of the driving transistor T1. Figure 18 As shown, the gate T11 of the driving transistor T1 is located in the first conductive layer M1. The active portion of the driving transistor T1 is located in the first active layer 101. The first electrode T12 and the second electrode T13 of the driving transistor T1 are located in the fourth conductive layer M4. For example, the first active layer 101 may include polycrystalline silicon semiconductor material.

[0236] Figure 20 This is a schematic diagram of the layout structure of the second conductive layer of the display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 20 The first gate line S1, the third gate line S3, and the second electrode CO2 of the storage capacitor C1 are located in the second conductive layer M2. Two adjacent third gate lines S3 arranged along the first direction Y are mirror-symmetrical about the first gate line S1, allowing two adjacent pixel circuits 210 arranged along the first direction Y to share a single first gate line S1, reducing the number of first gate lines S1 and thus improving the transmittance of the display panel. Figure 18 As shown, the first gate line S1 and the third gate line S3 are located in the first conductive layer M1. The portion where the first gate line S1 overlaps with the second active layer 102 forms the first gate T21 of the first initialization transistor T2, and the portion where the third gate line S3 overlaps with the second active layer 102 forms the first gate T31 of the compensation transistor T3. For example, the second active layer 102 may include a metal-oxide-semiconductor material, such as indium gallium zinc oxide (IGZO).

[0237] Figure 21 This is a schematic diagram of the layout structure of the second conductive layer, the second active layer, and the third conductive layer of the display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 18 and Figure 21 The portion of the first gate line S1 overlapping with the second active layer 102 forms the first gate T21 of the first initialization transistor T2. The portion of the gate line S12 in the third conductive layer M3 overlapping with the second active layer 102 and the first gate line S1 forms the second gate T22 of the first initialization transistor T2. The portion of the third gate line S3 overlapping with the second active layer 102 forms the first gate T31 of the compensation transistor T3. The portion of the gate line S32 in the third conductive layer M3 overlapping with the second active layer 102 and the third gate line S3 forms the second gate T32 of the compensation transistor T3. This makes the compensation transistor T3 and the first initialization transistor T2 N-type transistors, which can reduce the leakage current of the driving transistor T1. Furthermore, the first initialization transistors T2 in two adjacent pixel circuits arranged along the first direction Y are arranged along the second direction X, facilitating connection with the first gate line S1 and the compensation transistor T3. Figure 18 As shown, the first electrode T23 and the second electrode T24 of the first initialization transistor T2 are located in the fourth conductive layer M4, and the first electrode T33 and the second electrode T34 of the compensation transistor T3 are located in the fourth conductive layer M4.

[0238] Figure 22 This is a schematic diagram of the layout structure of the fourth conductive layer of a display panel according to an embodiment of the present invention. Optionally, refer to... Figure 22 The first segment V11 of the first initialization sub-signal line Vref1, the third initialization sub-signal line Vref3, the fourth initialization sub-signal line Vref4, and the sixth initialization sub-signal line Vref6 are located in the fourth conductive layer M4. By setting the first initialization sub-signal line Vref1 to include the first segment V11, and ensuring that the first segment V11 does not overlap with the fourth initialization sub-signal line Vref4, interference or short circuits between the signals on the first initialization sub-signal line Vref1 and the signals on the fourth initialization sub-signal line Vref4 can be avoided, thus ensuring the reliability of signal transmission.

[0239] Figure 23 This is a schematic diagram of the layout structure of the fifth conductive layer of a display panel according to an embodiment of the present invention. Optionally, refer to... Figure 23 The second segment V12 of the first data connection line F1 and the first initialization sub-signal line Vref1 is located in the fifth conductive layer M5.

[0240] Figure 24 This is a schematic diagram of the layout structure of the sixth conductive layer of the display panel provided in an embodiment of the present invention. Optionally, refer to... Figure 24 The first power line VDD, the second data connection line F2, and the data line Data are located on the sixth conductive layer M6.

[0241] In some implementations... Figure 25 yes Figure 13 Another sectional view along the b1-b2 direction, optionally, refer to Figure 23 The display panel may further include a shielding layer M0, which is located on the side of the first active layer 101 closest to the substrate 100, i.e., between the substrate 100 and the pixel circuit 210. The orthographic projection of the shielding layer M0 onto the substrate 100 overlaps at least partially with the active portion of the driving transistor T1. Thus, the shielding portion M0 can provide electrostatic shielding for the driving transistor T1, preventing static electricity from affecting the characteristics of the driving transistor T1 and preventing changes in the threshold voltage of the driving transistor T1, thereby ensuring the stability of the driving current of the driving transistor T1. Furthermore, it can prevent electrostatic charges from damaging the gate of the driving transistor T1, achieving the effect of protecting the driving transistor T1. The shielding layer M0 may be a light-shielding layer.

[0242] In some implementations, the shielding layer M0 may also include a portion that overlaps with the active portion of other transistors (e.g., data write transistors) to protect other transistors (e.g., data write transistors).

[0243] Figure 26 yes Figure 14 A sectional view along the e1-e2 direction, optionally, refer to Figure 26 The second data connection line F2 and the data line Data are located on the sixth conductive layer M6.

[0244] Based on the above technical solutions, optionally, refer to Figure 4A and Figure 4B The second electrode of the light-emitting element D1 is connected to the second power supply line VSS.

[0245] It should be noted that the data writing transistor T6 can be an N-type transistor or a P-type transistor, the first light-emitting control transistor T7 can be an N-type transistor or a P-type transistor, and the second light-emitting control transistor T8 can be an N-type transistor or a P-type transistor. Figure 4A , Figure 4B The diagram shows a case where the data writing transistor T6, the first light-emitting control transistor T7, and the second light-emitting control transistor T8 are all P-type transistors, but this is not a limitation.

[0246] Each signal line or trace (e.g., gate line, initialization signal line, power line, data line, data connection line, etc.) may extend in one or more combinations of straight lines, broken lines, curves, irregular shapes (e.g., tree-like) along its own extension direction.

[0247] This invention also provides a display panel, which includes a substrate 100;

[0248] Multiple pixel circuit groups 200 are located on substrate 100; each pixel circuit group 200 includes two pixel circuits 210, each pixel circuit 210 includes a driving transistor T1 and a third initialization transistor T5, the first terminal of the third initialization transistor T5 is electrically connected to the first or second terminal of the driving transistor T1.

[0249] like Figure 5 and Figure 11 As shown, in two adjacent pixel circuit groups 200 arranged along the second direction X, one pixel circuit group 200 includes a first pixel circuit 210A and a second pixel circuit 210B, and the other pixel circuit group includes a third pixel circuit 210C and a fourth pixel circuit 210D. The driving transistors T1 in the first pixel circuit 210A and the second pixel circuit 210B are arranged along the first direction Y, the driving transistors T1 in the third pixel circuit 210C and the fourth pixel circuit 210D are arranged along the first direction Y, the driving transistors T1 in the first pixel circuit 210A and the third pixel circuit 210C are arranged along the second direction X, and the driving transistors T1 in the second pixel circuit 210B and the fourth pixel circuit 210D are arranged along the second direction Y.

[0250] In two adjacent pixel circuit groups 200 arranged along the second direction X, the second pole of the third initialization transistor T5 in the first pixel circuit 210A and the third pixel circuit 210C is connected.

[0251] And / or, in two adjacent pixel circuit groups 200 arranged along the second direction X, the active portions of the third initialization transistor T5 in the first pixel circuit 210A and the third pixel circuit 210C are connected.

[0252] Based on the above technical solutions, optionally, such as Figure 12 As shown, in two adjacent pixel circuit groups 200 arranged along the second direction X, the second pole of the third initialization transistor T5 in the first pixel circuit 210A, the second pixel circuit 210B, the third pixel circuit 210C and the fourth pixel circuit 210D are connected.

[0253] And / or, in two adjacent pixel circuit groups 200 arranged along the second direction X, the active portions of the third initialization transistor T5 in the first pixel circuit 210A, the second pixel circuit 210B, the third pixel circuit 210C, and the fourth pixel circuit 210D are connected.

[0254] This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0255] This embodiment also provides a display device. Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 27 As shown, the display device includes the display panel provided in any of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, or digital camera. Since the display device includes the display panel provided in any embodiment of the present invention, it possesses the same beneficial effects as the display panel provided in any embodiment of the present invention, and will not be elaborated further here.

[0256] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Substrate; Multiple pixel circuit groups are located on the substrate; each pixel circuit group includes two pixel circuits, each pixel circuit includes a first functional element and a second functional element, in the same pixel circuit group, the first functional elements of the two pixel circuits are arranged along a first direction, and the second functional elements of the two pixel circuits are arranged along a second direction, the first direction and the second direction intersect. Each pixel circuit further includes a third initialization transistor, and the first functional element includes a driving transistor; The first terminal of the third initialization transistor is electrically connected to the first or second terminal of the driving transistor; the first terminal of the active portion of the third initialization transistor is electrically connected to the first or second terminal of the driving transistor. In two adjacent pixel circuit groups arranged along the second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit. The first functional elements in the first pixel circuit and the second pixel circuit are arranged along the first direction, the first functional elements in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the first functional elements in the first pixel circuit and the third pixel circuit are arranged along the second direction, and the first functional elements in the second pixel circuit and the fourth pixel circuit are arranged along the second direction. In two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit and the third pixel circuit are connected; In two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected; the second terminal of the active portion of the third initialization transistor in the first pixel circuit is directly connected to the second terminal of the active portion of the third initialization transistor in the third pixel circuit. Multiple first gate lines are arranged along the first direction and extend along the second direction, and the second functional elements in two pixel circuits in the same pixel circuit group are electrically connected to the same first gate line.

2. The display panel according to claim 1, characterized in that, The second functional element is connected to the first gate line, and the first gate line provides a gate drive signal to the second functional element, thereby controlling the second functional element to be turned on or off.

3. The display panel according to claim 1, characterized in that, In two adjacent pixel circuit groups arranged along the second direction, the second functional element in the second pixel circuit, the second functional element in the first pixel circuit, the second functional element in the third pixel circuit, and the second functional element in the fourth pixel circuit are arranged sequentially along the second direction; or, the second functional element in the first pixel circuit, the second functional element in the second pixel circuit, the second functional element in the fourth pixel circuit, and the second functional element in the third pixel circuit are arranged sequentially along the second direction.

4. The display panel according to claim 1, characterized in that, In two adjacent pixel circuit groups arranged along the second direction, the second functional element in the first pixel circuit, the second functional element in the second pixel circuit, the second functional element in the third pixel circuit, and the second functional element in the fourth pixel circuit are arranged sequentially along the second direction.

5. The display panel according to claim 1, characterized in that, The second functional element includes an initialization transistor.

6. The display panel according to claim 1, characterized in that, The second functional element in different pixel circuits has the same function.

7. The display panel according to claim 5, characterized in that, The second functional element includes a first initialization transistor. The first initialization transistor is electrically connected to the gate of the driving transistor, or, The pixel circuit includes a compensation transistor connected between the first electrode and the gate of the driving transistor, and the first initialization transistor is electrically connected to the first electrode of the driving transistor.

8. The display panel according to claim 7, characterized in that, The display panel also includes multiple first initialization sub-signal lines, arranged along the first direction and extending along the second direction. The first initialization transistors in the two pixel circuits of the same pixel circuit group are electrically connected to the same first initialization sub-signal line; The first initialization sub-signal line includes a first sub-segment and a second sub-segment arranged alternately along its own extension direction, and the first sub-segment and the second sub-segment are arranged in different layers.

9. The display panel according to claim 8, characterized in that, The first initialization sub-signal line provides a first initialization voltage to the first initialization transistor, such that when the first initialization transistor is turned on, it transmits the first initialization voltage on the first initialization sub-signal line to the gate of the driving transistor.

10. The display panel according to claim 7, characterized in that, The first initialization transistor includes an N-type transistor or a P-type transistor.

11. The display panel according to claim 7, characterized in that, The compensation transistor includes an N-type transistor or a P-type transistor.

12. The display panel according to claim 5, characterized in that, The display panel also includes a plurality of light-emitting elements, and the second functional element includes a second initialization transistor, which is electrically connected to the first electrode of the light-emitting element.

13. The display panel according to claim 5, characterized in that, The second functional element includes a third initialization transistor, which is electrically connected to either the first or second terminal of the driving transistor.

14. The display panel according to claim 5, characterized in that, The display panel also includes multiple initialization signal lines arranged along the first direction and extending along the second direction. The second functional element in the two pixel circuits of the same pixel circuit group is electrically connected to the same initialization signal line.

15. The display panel according to claim 1, characterized in that, The pixel circuit also includes a third functional element. In two adjacent pixel circuit groups arranged along the first direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a fifth pixel circuit and a sixth pixel circuit. The first functional element in the first pixel circuit, the first functional element in the second pixel circuit, the first functional element in the fifth pixel circuit, and the first functional element in the sixth pixel circuit are arranged sequentially along the first direction. The display panel further includes: a plurality of second gate lines arranged along the first direction and extending along the second direction; In two adjacent pixel circuit groups arranged along the first direction, the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are arranged along the first direction and electrically connected to different second gate lines.

16. The display panel according to claim 15, characterized in that, One of the second functional element and the third functional element includes a first initialization transistor electrically connected to the gate of the driving transistor; or, the pixel circuit includes a compensation transistor connected between the first terminal and the gate of the driving transistor, and the first initialization transistor is electrically connected to the first terminal of the driving transistor. The other of the second and third functional elements includes a second initialization transistor. The display panel also includes multiple light-emitting elements, and the second initialization transistor is electrically connected to the first electrode of the light-emitting element.

17. The display panel according to claim 16, characterized in that, The display panel further includes multiple second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate lines.

18. The display panel according to claim 17, characterized in that, The second initialization transistor and the third initialization transistor have the same channel type.

19. The display panel according to claim 17, characterized in that, The second initialization transistor includes a P-type transistor; the third initialization transistor includes a P-type transistor.

20. The display panel according to claim 15, characterized in that, The display panel also includes multiple first initialization sub-signal lines, arranged along the first direction and extending along the second direction. The second functional element in the two pixel circuits in the same pixel circuit group is electrically connected to the same first initialization sub-signal line; The display panel also includes multiple second initialization sub-signal lines, arranged along the first direction and extending along the second direction. In two adjacent pixel circuit groups arranged along the first direction, the third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are electrically connected to the same second initialization sub-signal line.

21. The display panel according to claim 16, characterized in that, The second initialization sub-signal line provides a second initialization voltage to the third functional element. When the third functional element is turned on, the second initialization voltage is transmitted to the first electrode of the light-emitting element to initialize the first electrode of the light-emitting element.

22. The display panel according to claim 20, characterized in that, The display panel further includes multiple third initialization sub-signal lines arranged along the second direction and extending along the first direction; the third initialization sub-signal lines are electrically connected to the first initialization sub-signal lines. The first initialization sub-signal line includes a first sub-segment and a second sub-segment arranged alternately along its own extension direction, and the first sub-segment and the second sub-segment are arranged in different layers; The display panel further includes multiple fourth initialization sub-signal lines arranged along the second direction and extending along the first direction; the fourth initialization sub-signal lines are electrically connected to the second initialization sub-signal lines; the orthographic projection of the second sub-segment on the substrate overlaps with the orthographic projection of the fourth initialization sub-signal line on the substrate, and the second sub-segment and the fourth initialization sub-signal lines are disposed on different layers.

23. The display panel according to claim 22, characterized in that, The first sub-segment, the third initialization sub-signal line, and the fourth initialization sub-signal line are arranged on the same layer, and the second sub-segment and the second initialization sub-signal line are arranged on the same layer.

24. The display panel according to claim 22, characterized in that, The first sub-segment and the second sub-segment are connected through a first via, and the first sub-segment is connected to the second functional element through a second via.

25. The display panel according to claim 24, characterized in that, The second vias corresponding to the second functional elements in the two pixel circuits of the same pixel circuit group are located on opposite sides of the first sub-segment along the first direction.

26. The display panel according to claim 15, characterized in that, The display panel further includes a first gate driving circuit, which includes a plurality of cascaded first shift registers. The second functional element in the first pixel circuit and the second functional element in the second pixel circuit are electrically connected to the same output terminal of the first shift register. The second functional element in the fifth pixel circuit and the second functional element in the sixth pixel circuit are electrically connected to the same output terminal of the first shift register. The second functional element in the second pixel circuit and the second functional element in the fifth pixel circuit are electrically connected to the output terminals of different first shift registers.

27. The display panel according to claim 26, characterized in that, The display panel further includes a second gate driving circuit, which includes a plurality of cascaded second shift registers. The third functional element in the first pixel circuit and the third functional element in the second pixel circuit are electrically connected to the output terminal of the same second shift register. The third functional element in the fifth pixel circuit and the third functional element in the sixth pixel circuit are electrically connected to the output terminal of the same second shift register. The third functional element in the second pixel circuit and the third functional element in the fifth pixel circuit are electrically connected to the output terminals of different second shift registers.

28. The display panel according to claim 15, characterized in that, The third functional element includes an initialization transistor. In two adjacent pixel circuit groups arranged along the first direction, the active portion of the third functional element in the second pixel circuit and the active portion of the third functional element in the fifth pixel circuit are connected.

29. The display panel according to claim 3 or 4, characterized in that, The second electrode electrical connection of the third initialization transistor in the two pixel circuits of the same pixel circuit group; And / or, the active portions of the third initialization transistors in the two pixel circuits of the same pixel circuit group are connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit and the second pixel circuit is connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistor in the first pixel circuit and the second pixel circuit are connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit and the third pixel circuit is connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistor in the first pixel circuit and the third pixel circuit are connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit is connected; And / or, in two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected.

30. The display panel according to claim 1, characterized in that, The pixel circuit includes a component group, which includes the first functional component. The element groups in two adjacent pixel circuits arranged along the first direction are mirror-symmetrically arranged.

31. The display panel according to claim 30, characterized in that, The element groups in two adjacent pixel circuits arranged along the second direction are mirror-symmetrically arranged.

32. The display panel according to claim 30, characterized in that, The two adjacent pixel circuits arranged along the second direction are mirror-symmetrically configured.

33. The display panel according to claim 30, characterized in that, The component group also includes a data writing transistor, a compensation transistor, a first light-emitting control transistor, and a second light-emitting control transistor.

34. The display panel according to claim 33, characterized in that, The display panel further includes multiple third gate lines arranged along the first direction and extending along the second direction; the gate of the compensation transistor is electrically connected to the third gate lines. The third gate line electrically connected to the compensation transistor in the two pixel circuits in the same pixel circuit group is symmetrical about the first gate line.

35. The display panel according to claim 33, characterized in that, The display panel further includes multiple fourth gate lines arranged along the first direction and extending along the second direction; the gate of the data writing transistor is electrically connected to the fourth gate lines. The fourth gate line of the data write transistor electrically connected in the two pixel circuits of the same pixel circuit group is symmetrical about the first gate line.

36. The display panel according to claim 33, characterized in that, The display panel further includes a data line, a first data connection line and a second data connection line, wherein the first data connection line is connected between the second data connection line and the data line, and the data line is connected to the data writing transistor; The pixel circuit further includes a third initialization transistor; the display panel further includes multiple fifth initialization sub-signal lines; the gate of the third initialization transistor is connected to the second gate line, and the second terminal of the third initialization transistor is electrically connected to the fifth initialization sub-signal line; The second gate line, the fifth initialization sub-signal line, and the first data connection line extend in the same direction. Along the thickness direction of the display panel, the fifth initialization sub-signal line is located between the second gate line and the first data connection line.

37. The display panel according to claim 36, characterized in that, The display panel also includes connection traces. The active portions of the data writing transistors in the two pixel circuits of the same pixel circuit group are connected to the connection traces through a third via. The connection traces are connected to the corresponding data lines through the same fourth via.

38. The display panel according to claim 36, characterized in that, At least two of the first data connection lines that are partially adjacent are located on opposite sides of the second initialization sub-signal line along the first direction, and at least two of the first data connection lines that are partially adjacent are symmetrical about the second initialization sub-signal line.

39. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving transistor and a third initialization transistor, wherein the first terminal of the third initialization transistor is electrically connected to the first or second terminal of the driving transistor. The display panel further includes multiple fifth initialization sub-signal lines arranged along the first direction and extending along the second direction; the second electrode of the third initialization transistor is electrically connected to the fifth initialization sub-signal lines. The display panel further includes multiple second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate lines, and the orthographic projection of the second gate lines on the substrate overlaps with the orthographic projection of the fifth initialization sub-signal line on the substrate.

40. The display panel according to claim 39, characterized in that, The display panel further includes multiple sixth initialization sub-signal lines arranged along the second direction and extending along the first direction; the sixth initialization sub-signal lines are electrically connected to the fifth initialization sub-signal lines.

41. The display panel according to claim 39, characterized in that, The third initialization transistor comprises at least two transistors connected in series.

42. The display panel according to claim 3 or 4, characterized in that, The pixel circuit includes a driving transistor and a first light-emitting control transistor. The display panel further includes a first power line, and the first light-emitting control transistor is connected between the second electrode of the driving transistor and the first power line. The active portion of the first light-emitting control transistor in the first pixel circuit and the active portion of the first light-emitting control transistor in the third pixel circuit are connected. The active portion of the first light-emitting control transistor in the second pixel circuit and the active portion of the first light-emitting control transistor in the fourth pixel circuit are connected.

43. The display panel according to claim 42, characterized in that, The display panel also includes a light-emitting control line, which is electrically connected to the gate of the first light-emitting control transistor; The light-emitting control lines electrically connected to the first light-emitting control transistors in the two pixel circuits of the same pixel circuit group are symmetrical about the first gate line.

44. The display panel according to claim 1, characterized in that, In two adjacent pixel circuit groups arranged along the second direction, the second terminal of the active portion of the third initialization transistor in the second pixel circuit is directly connected to the second terminal of the active portion of the third initialization transistor in the fourth pixel circuit.

45. The display panel according to claim 44, characterized in that, In two adjacent pixel circuit groups arranged along the first direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a fifth pixel circuit and a sixth pixel circuit. The first functional element in the first pixel circuit, the first functional element in the second pixel circuit, the first functional element in the fifth pixel circuit, and the first functional element in the sixth pixel circuit are arranged sequentially along the first direction. In two adjacent pixel circuit groups arranged along the first direction, the second terminal of the active portion of the third initialization transistor in the second pixel circuit and the second terminal of the active portion of the third initialization transistor in the fifth pixel circuit are directly connected.

46. ​​The display panel according to claim 45, characterized in that, The second terminal of the active portion of the third initialization transistor in the second pixel circuit, the second terminal of the active portion of the third initialization transistor in the fourth pixel circuit, and the second terminal of the active portion of the third initialization transistor in the fifth pixel circuit are directly connected.

47. The display panel according to claim 45, characterized in that, In two adjacent pixel circuit groups arranged along the second direction, the third initialization transistor in the first pixel circuit and the third initialization transistor in the third pixel circuit are connected to the same initialization signal line.

48. The display panel according to claim 45, characterized in that, In two adjacent pixel circuit groups arranged along the second direction, the third initialization transistor in the second pixel circuit and the third initialization transistor in the fourth pixel circuit are connected to the same initialization signal line.

49. The display panel according to claim 45, characterized in that, In two adjacent pixel circuit groups arranged along the first direction, the third initialization transistor in the second pixel circuit and the third initialization transistor in the fifth pixel circuit are connected to the same initialization signal line.

50. The display panel according to claim 45, characterized in that, The third initialization transistor in the second pixel circuit, the third initialization transistor in the fourth pixel circuit, and the third initialization transistor in the fifth pixel circuit are connected to the same initialization signal line.

51. The display panel according to claim 45, characterized in that, At least three of the third initialization transistors are connected to the same initialization signal line through the same via.

52. The display panel according to claim 45, characterized in that, At least four of the third initialization transistors are connected to the same initialization signal line through the same via.

53. A display panel, characterized in that, include: Substrate; Multiple pixel circuit groups are located on the substrate; each pixel circuit group includes two pixel circuits, each pixel circuit includes a driving transistor and a third initialization transistor, the first terminal of the third initialization transistor is electrically connected to the first terminal or the second terminal of the driving transistor; the first terminal of the active portion of the third initialization transistor is electrically connected to the first terminal or the second terminal of the driving transistor. In two adjacent pixel circuit groups arranged along a second direction, one pixel circuit group includes a first pixel circuit and a second pixel circuit, and the other pixel circuit group includes a third pixel circuit and a fourth pixel circuit. The driving transistors in the first pixel circuit and the second pixel circuit are arranged along a first direction, the driving transistors in the third pixel circuit and the fourth pixel circuit are arranged along the first direction, the driving transistors in the first pixel circuit and the third pixel circuit are arranged along the second direction, and the driving transistors in the second pixel circuit and the fourth pixel circuit are arranged along the second direction; the first direction and the second direction intersect. In two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit and the third pixel circuit are connected; In two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit and the third pixel circuit are connected; the second terminal of the active portion of the third initialization transistor in the first pixel circuit is directly connected to the second terminal of the active portion of the third initialization transistor in the third pixel circuit.

54. The display panel according to claim 53, characterized in that, In two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit is connected; In two adjacent pixel circuit groups arranged along the second direction, the active portions of the third initialization transistors in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are connected; the second terminals of the active portions of the third initialization transistors in the first pixel circuit, the second terminals of the active portions of the third initialization transistors in the second pixel circuit, the third terminals of the active portions of the third initialization transistors in the third pixel circuit, and the second terminals of the active portions of the third initialization transistors in the fourth pixel circuit are directly connected.

55. The display panel according to claim 53, characterized in that, include: Multiple first gate lines are arranged along the first direction and extend along the second direction, and the third initialization transistors in the two pixel circuits in the same pixel circuit group are electrically connected to the same first gate line.

56. The display panel according to claim 55, characterized in that, The pixel circuit includes a group of components, which are arranged along the first direction and are mirror-symmetrically arranged in two adjacent pixel circuits. The component group also includes: a driving transistor, a data writing transistor, a compensation transistor, a first light-emitting control transistor, and a second light-emitting control transistor.

57. The display panel according to claim 56, characterized in that, The display panel further includes multiple third gate lines arranged along the first direction and extending along the second direction; the gate of the compensation transistor is electrically connected to the third gate lines. The third gate line electrically connected to the compensation transistor in the two pixel circuits in the same pixel circuit group is symmetrical about the first gate line.

58. The display panel according to claim 56, characterized in that, The display panel further includes multiple fourth gate lines arranged along the first direction and extending along the second direction; the gate of the data writing transistor is electrically connected to the fourth gate lines. The fourth gate line of the data write transistor electrically connected in the two pixel circuits of the same pixel circuit group is symmetrical about the first gate line.

59. The display panel according to claim 56, characterized in that, The display panel further includes a data line, a first data connection line and a second data connection line, wherein the first data connection line is connected between the second data connection line and the data line, and the data line is connected to the data writing transistor; The pixel circuit further includes a third initialization transistor; the display panel further includes multiple fifth initialization sub-signal lines; the gate of the third initialization transistor is connected to the second gate line, and the second terminal of the third initialization transistor is electrically connected to the fifth initialization sub-signal line; The second gate line, the fifth initialization sub-signal line, and the first data connection line extend in the same direction. Along the thickness direction of the display panel, the fifth initialization sub-signal line is located between the second gate line and the first data connection line.

60. The display panel according to claim 53, characterized in that, The first terminal of the third initialization transistor is electrically connected to the first or second terminal of the driving transistor; The display panel further includes multiple fifth initialization sub-signal lines arranged along the first direction and extending along the second direction; the second electrode of the third initialization transistor is electrically connected to the fifth initialization sub-signal lines. The display panel further includes multiple second gate lines arranged along the first direction and extending along the second direction; the gate of the third initialization transistor is electrically connected to the second gate lines, and the orthographic projection of the second gate lines on the substrate overlaps with the orthographic projection of the fifth initialization sub-signal line on the substrate.

61. The display panel according to claim 53, characterized in that, The pixel circuit further includes a first initialization transistor, which is electrically connected to the gate of the driving transistor, or... The pixel circuit includes a compensation transistor connected between the first terminal and the gate of the driving transistor, and the first initialization transistor is electrically connected to the first terminal of the driving transistor. The display panel also includes multiple light-emitting elements, and the pixel circuit further includes a second initialization transistor, which is electrically connected to the first electrode of the light-emitting element.

62. The display panel according to claim 54, characterized in that, In two adjacent pixel circuit groups arranged along the second direction, the second pole of the third initialization transistor in the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit is shared.

63. The display panel according to claim 54, characterized in that, In two adjacent pixel circuit groups arranged along the second direction, at least four of the third initialization transistors are connected to the same initialization signal line through the same via.

64. A display device, characterized in that, Includes the display panel as described in any one of claims 1-63.

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