Display device and chamfering voltage generation circuit

Abstract

The invention relates to a display device and a chamfering voltage generation circuit, the display device comprises a liquid crystal panel, a gate driver, a source driver and the chamfering voltage generation circuit, the chamfering voltage generation circuit can divide the voltage difference between the gate turn-on voltage VGH end of a PMIC and the gate turn-off voltage VGL end of the PMIC to obtain chamfering voltage, and the chamfering voltage is applied to the PMIC. And the voltage division proportion of the chamfering voltage generation circuit during voltage division is adjustable. According to the embodiment of the invention, the gate driver can generate the scanning signal of which the falling edge is provided with the inclined part according to the chamfering voltage, so that the Feed-Through effect of the near-end thin film transistor close to the gate driver when the near-end thin film transistor is closed is reduced, and the flicker difference of all positions in the liquid crystal panel is further reduced; moreover, the voltage dividing ratio of the chamfering voltage generation circuit to the voltage difference is adjustable, so that the chamfering voltage can be adjusted conveniently and efficiently under the condition that the hardware structure is not changed.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device and a chamfer voltage generating circuit. Background Art

[0002] In the field of display technology, current LCD panels rely on common voltage to adjust pixel grayscale to achieve ideal image display effects. In theory, to achieve a better display state, the common voltage should be precisely at the center of the positive and negative polarity voltages of each grayscale, thereby ensuring that the panel will not have flickering, afterimages, or split screen problems after long-term display.

[0003] In practical applications, there is also a Feed-Through effect, which is mainly caused by the capacitive coupling effect caused by the gate-drain capacitance when the gate driver is turned off. During the operation of the LCD panel, when the gate driver voltage changes, this capacitive coupling will affect the display electrode voltage, thereby causing the positive and negative polarity bias of the liquid crystal pixel electrode to be unbalanced, resulting in flicker problems. In order to compensate for this effect, the common voltage must be adjusted, and the adjustment amount must match the voltage change caused by the Feed-Through effect to achieve the ideal display effect.

[0004] However, there is a difference in the relative position between the thin film transistor (TFT) corresponding to each sub-pixel in the liquid crystal panel and the gate driver used to control the opening and closing of each thin film transistor, which results in different transmission path lengths of the scanning signal sent by the gate driver. When the gate driver sends a shutdown signal, there are obvious differences in the shutdown voltages received by thin film transistors at different positions. Specifically, the signal waveform received by the proximal thin film transistor close to the gate driver is closer to a square. When the thin film transistor is turned off, the voltage difference between its two ends is large, resulting in a large Feed-Through effect. The signal waveform received by the distal thin film transistor is smoother. When the thin film transistor is turned off, the voltage difference between its two ends is small, and the resulting Feed-Through effect is smaller.

[0005] It can be seen that different positions in the LCD panel will produce different degrees of Feed-Through effect, which leads to the fact that a single fixed common voltage cannot meet the display effect requirements of the entire screen, and there are obvious differences in the flickering conditions of various areas in the LCD panel. Summary of the invention

[0006] The present invention provides a display device and a chamfer voltage generating circuit to solve the deficiencies in the related art.

[0007] According to a first aspect of an embodiment of the present invention, there is provided a display device, including:

[0008] A liquid crystal panel, wherein a plurality of sub-pixels and a thin film transistor corresponding to each sub-pixel are arranged in an array, wherein the gate of the thin film transistor controls the conduction state of the thin film transistor according to a scanning signal provided by a gate driver;

[0009] A chamfer voltage generating circuit, used for dividing the voltage difference between the gate-on voltage VGH terminal of the power management integrated circuit PMIC and the gate-off voltage VGL terminal of the PMIC to obtain a chamfer voltage, and providing the chamfer voltage to the gate driver; wherein the voltage division ratio of the chamfer voltage generating circuit for dividing the voltage difference is adjustable;

[0010] A gate driver, configured to generate a scanning signal having a falling edge with an inclined portion according to the chamfered voltage, and transmit the scanning signal to a gate of the thin film transistor corresponding to the sub-pixel;

[0011] A source driver is used to provide a data signal to the sub-pixel through a source of the thin film transistor.

[0012] In a possible implementation manner, the chamfer voltage generating circuit includes a P-MOS transistor, a first resistor, a second resistor, and a third resistor;

[0013] The input end of the chamfer voltage generating circuit is connected to the gate of the P-MOS transistor, and the output end of the chamfer voltage generating circuit is connected to the source of the P-MOS transistor;

[0014] The drain of the P-MOS transistor is connected to the analog ground via a first resistor;

[0015] The source of the P-MOS transistor is connected to the gate-on voltage VGH terminal of the PMIC via a second resistor;

[0016] The source of the P-MOS transistor is connected to the gate-off voltage VGL terminal of the PMIC via a third resistor.

[0017] In a possible implementation manner, the chamfer voltage generating circuit further includes a fourth resistor, and the output end of the chamfer voltage generating circuit is connected to the source of the P-MOS transistor via the fourth resistor.

[0018] In a possible implementation manner, the chamfer voltage generating circuit includes a first resistor and a second resistor;

[0019] The first resistor and the second resistor are connected in series between the gate-on voltage VGH terminal of the PMIC and the gate-off voltage VGL terminal of the PMIC, and the output terminal of the chamfer voltage generating circuit is located between the first resistor and the second resistor;

[0020] Wherein, at least one of the first resistor and the second resistor is a variable resistor element.

[0021] According to a second aspect of an embodiment of the present invention, there is provided a chamfer voltage generating circuit, comprising:

[0022] A first terminal is connected to a gate-on voltage VGH terminal of the PMIC;

[0023] A second terminal is connected to a gate-off voltage VGL terminal of the PMIC;

[0024] The third terminal is used to output the chamfer voltage;

[0025] A chamfering module, the chamfering module is respectively connected to the first end, the second end and the third end, and is used to divide the voltage difference between the VGH end and the VGL end to obtain the chamfering voltage; wherein the voltage division ratio of the chamfering module to divide the voltage difference is adjustable.

[0026] In a possible implementation manner, the chamfer voltage generating circuit further includes: a fourth terminal, the fourth terminal being connected to a regulated voltage output terminal of the PMIC;

[0027] The chamfering module includes a P-MOS transistor, a first resistor, a second resistor and a third resistor;

[0028] The gate of the P-MOS transistor is connected to the fourth terminal, and the source of the P-MOS transistor is connected to the third terminal;

[0029] The drain of the P-MOS transistor is connected to the analog ground via a first resistor;

[0030] The source of the P-MOS transistor is connected to the first end via a second resistor;

[0031] The source of the P-MOS transistor is connected to the second end via a third resistor.

[0032] In a possible implementation manner, the chamfering module further includes a fourth resistor, and the source of the P-MOS transistor and the third end are connected via the fourth resistor.

[0033] In a possible implementation manner, the chamfering module includes a first resistor and a second resistor;

[0034] The first resistor and the second resistor are connected in series between the first end and the second end, and the third end is connected to a connection line between the first resistor and the second resistor;

[0035] Wherein, at least one of the first resistor and the second resistor is a variable resistor element.

[0036] According to a third aspect of the embodiments of the present invention, a display panel is provided, comprising the chamfer voltage generating circuit as described in the second aspect.

[0037] According to a fourth aspect of the embodiments of the present invention, a display device is provided, comprising the display panel as described in the third aspect.

[0038] According to the above embodiments, the display device provided by the present invention includes a liquid crystal panel, a gate driver, a source driver and a chamfer voltage generating circuit, wherein the chamfer voltage generating circuit can divide the voltage difference between the gate-on voltage VGH end of the power management integrated circuit PMIC and the gate-off voltage VGL end of the PMIC to obtain the chamfer voltage. Afterwards, the gate driver can generate a scanning signal with an inclined portion on the falling edge according to the chamfer voltage, thereby reducing the Feed-Through effect of the proximal thin film transistor close to the gate driver when it is turned off, making it closer to the Feed-Through effect of the distal thin film transistor when it is turned off. On this basis, even if a single fixed common voltage is used, the requirements of the entire liquid crystal panel for the display effect can be met, and the problem of obvious differences in flickering in various regions can be solved. At the same time, when the gate-on voltage VGH end and the gate-off voltage VGL end are divided, the voltage division ratio of the voltage difference of the chamfer voltage generating circuit in the embodiment of the present invention is adjustable, so the chamfer voltage can be adjusted conveniently and efficiently without changing the hardware structure. If the chamfer voltage generating circuit is applied to different display devices, the chamfer voltage can be efficiently configured for each display device separately to adapt to the characteristic differences of different display devices, thereby ensuring that each display device can achieve the best display effect.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0041] Figure 1 FIG. 4 is a schematic diagram showing the relationship between a Feed-Through effect and a common voltage according to an embodiment of the present invention.

[0042] Figure 2 The diagram is a schematic diagram of scanning signals of near-end and far-end thin film transistors according to an embodiment of the present invention.

[0043] Figure 3 The diagram is a schematic diagram showing a method of performing chamfering on a scanning signal according to an embodiment of the present invention.

[0044] Figure 4 is a schematic diagram of a chamfer voltage generating circuit according to an embodiment of the present invention.

[0045] FIG. 5( a ) is a schematic diagram of a chamfering module according to an embodiment of the present invention.

[0046] FIG5( b ) is a schematic diagram of a chamfering module using a sliding resistor according to an embodiment of the present invention.

[0047] FIG5( c ) is a schematic diagram of another chamfering module using a sliding resistor according to an embodiment of the present invention.

[0048] Figure 6 FIG. 4 is a schematic diagram of another chamfering module according to an embodiment of the present invention.

[0049] Figure 7 FIG. 4 is a schematic diagram showing the relationship between a chamfer voltage and a chamfer waveform according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0051] In the field of display technology, the core structure of the liquid crystal panel includes multiple sub-pixels arranged in an array. These sub-pixels are the basic units that constitute the image, and each sub-pixel corresponds to a thin film transistor. The gate of the thin film transistor receives a scanning signal from the gate driver (Gate Driver, also known as Gate IC) to accurately control its own conduction state. When the gate of any thin film transistor receives a specific voltage signal, the thin film transistor can be turned on or off according to the signal, thereby determining whether to allow current to pass. On this basis, in conjunction with the data signal provided by the source driver (Source Driver, also known as Source IC), the arrangement of the liquid crystal molecules in the corresponding sub-pixels can be controlled, and the transmittance of the incident light can be changed, thereby controlling the color and brightness of each sub-pixel, and then completing the image display.

[0052] Specifically, when the gate driver is working, it will select each row or column in the liquid crystal panel in turn (depending on the specific design form) and provide a scan signal to the row or column. When the scan signal provided by the gate driver is at a high level, the corresponding thin film transistor is in an on state, that is, the thin film transistor is turned on, allowing the data signal provided by the source driver to be transmitted to the liquid crystal layer through the thin film transistor. When the gate driver provides a low level, the corresponding thin film transistor is in an off state, that is, the thin film transistor is cut off, preventing the data signal from passing through, so that the current state of the liquid crystal molecules remains unchanged. In other words, the gate driver provides a scan signal, which is used to control the conduction state of the thin film transistor corresponding to each sub-pixel, and the source driver provides a data signal, which is transmitted to the corresponding sub-pixel through the turned-on thin film transistor to adjust its display state.

[0053] In order to prevent the liquid crystal material from aging or producing afterimages due to the long-term effect of the electric field in a single direction, the influence of the DC bias is reduced by periodically changing the polarity of the voltage. On this basis, the liquid crystal panel also needs to rely on the common voltage (Vcom) to accurately adjust the voltage difference of each pixel to achieve the ideal image display effect and smooth grayscale transition. In theory, the common voltage Vcom must be precisely located at the center of the positive and negative polarity voltages of each grayscale, that is, the common voltage Vcom is the middle level between the positive and negative polarity voltages. Only in this ideal state can the liquid crystal molecules achieve the best arrangement under the action of the electric field, thereby ensuring that the required brightness and color can be accurately presented when light passes through the liquid crystal layer. When the common voltage Vcom is in the center position, the liquid crystal molecules can achieve a smooth transition between different grayscales under the joint action of the positive and negative polarity voltages, effectively avoiding the problem of excessive or insufficient twisting of the liquid crystal molecules caused by voltage imbalance. It not only helps to improve the contrast and color accuracy of the image, but also ensures that the liquid crystal panel will not have problems such as flickering, afterimages and split screens that seriously affect the visual experience after long-term continuous display.

[0054] However, in actual liquid crystal panel application scenarios, the Feed-Through effect also needs to be considered. The Feed-Through effect mainly originates from the electrical phenomenon caused by the moment the gate driver is turned off. Specifically, when the gate driver is turned off, the gate-drain capacitance (also recorded as Cgd) between the gate and drain of the thin film transistor will produce a capacitive coupling effect. Specifically, during the normal operation of the liquid crystal panel, whenever the level of the scanning signal provided by the gate driver changes, the capacitive coupling formed by the gate-drain capacitance will interfere with the display electrode voltage under each sub-pixel for receiving the data signal through the thin film transistor. This interference directly leads to an imbalance in the positive and negative polarity bias of the liquid crystal pixel electrode, breaking the originally stable voltage balance, which in turn causes the flicker problem.

[0055] The mechanism of the flicker problem is that liquid crystal molecules are extremely sensitive to voltage changes. Even a small voltage fluctuation will cause the torsion angle of the liquid crystal molecules to change, thereby affecting the transmittance of light. When the positive and negative polarity bias is unbalanced, the liquid crystal molecules cannot accurately modulate the light, causing the human eye to perceive unstable changes in screen brightness and color, which is the flicker phenomenon. In order to effectively compensate for the negative effects of the Feed-Through effect, the common voltage Vcom must be adjusted synchronously, and the adjustment amplitude should match the voltage change caused by the Feed-Through effect.

[0056] like Figure 1 As shown, waveform A is used to characterize the waveform of the scanning signal provided by the gate driver, waveform B is used to characterize the ideal waveform of the data signal provided by the source driver, and waveform C is used to characterize the waveform of the voltage actually received by the display electrode.

[0057] Ideally, the voltage of the display electrode should be the same as the waveform of the data signal, and the voltage difference between the positive polarity voltage and the standard common voltage Vcom is the same as the voltage difference between the negative polarity voltage and the standard common voltage Vcom. However, in actual applications, taking the stage of the data signal being positive polarity as an example, when the rising edge of waveform A arrives, the gate of the thin film transistor is turned on, and the data signal provided by the source driver is transmitted to the display electrode, and the display electrode in waveform C receives the data signal; thereafter, when the falling edge of waveform A arrives, the gate of the thin film transistor is turned off. At this time, ideally, the voltage of the current display electrode should be the same as the voltage of waveform B. However, due to the Feed-Through effect, there is a voltage difference between the voltage of the display electrode and the voltage of the data signal shown in waveform B, as shown by mark 11. Similarly, in the stage of the data signal being negative polarity, there is also a voltage difference between the voltage of the display electrode and the voltage of the data signal shown in waveform B, as shown by mark 12. In this case, the original position of the common voltage Vcom is not at the exact center of the positive and negative polarity voltages of the display electrode. Therefore, the common voltage Vcom needs to be adjusted, and the adjustment amplitude should match the voltage change caused by the Feed-Through effect, that is, the common voltage Vcom should be adjusted based on the voltage difference indicated by the mark 11 or the mark 12 .

[0058] However, if we delve deeper into the internal structure and signal transmission path of the LCD panel, we will find another key factor that affects the consistency of the display effect, that is, the relative position difference between the thin film transistors corresponding to each sub-pixel and the gate driver. Due to the large size of the LCD panel, especially in large-size screens (such as long strip screens on cars), this relative position difference is more significant. The scanning signal emitted by the gate driver needs to be transmitted to each thin film transistor through a complex line layout, and the distance between the thin film transistors and the gate driver at different positions is different, which directly leads to significant differences in the transmission path length of the scanning signal.

[0059] Furthermore, when the gate driver sends a scan signal, the difference in the length of the transmission path will cause obvious differences in the voltages received by the thin film transistors at different positions, thereby causing different degrees of Feed-Through effect. Figure 2 A schematic diagram of a scanning signal of a near-end and far-end thin film transistor is shown. Figure 2 , if the leftmost thin film transistor is considered to be the proximal thin film transistor closest to the gate driver, the distance between each thin film transistor and the gate driver increases from left to right. Then for the proximal thin film transistor close to the gate driver, such as the leftmost thin film transistor, since the transmission path between it and the gate driver is shorter, it is less affected by resistance and capacitance, resulting in less signal attenuation and delay, and the waveform of the received scanning signal is closer to a square wave, as shown in waveform A. This square wave will cause a large voltage difference between its two ends at the moment the thin film transistor is turned off. Because the fast falling edge of the square wave causes the thin film transistor to quickly switch from the on state to the off state, a large voltage change is generated in a short time, thereby causing a strong Feed-Through effect. On the contrary, the distal thin film transistor far away from the gate driver, such as Figure 2 In the thin film transistor on the far right, the scanning signal needs to pass through a long transmission path, which is affected by factors such as line resistance and capacitance during the transmission process, causing the scanning signal waveform to be distorted and become flatter, as shown in waveform B. When such a flat waveform reaches the thin film transistor, the voltage difference between the two ends is relatively small at the moment of its closing, so the Feed-Through effect is also smaller.

[0060] It can be seen that since the degree of the Feed-Through effect produced by the thin film transistors at different positions in the liquid crystal panel is different, a single fixed common voltage Vcom obviously cannot meet the diverse requirements of the display effects of various areas of the entire screen. In the near-end area, due to the larger voltage deviation caused by the larger Feed-Through effect, it should be compensated by adjusting the common voltage Vcom to produce a larger voltage difference; while in the far-end area, the smaller Feed-Through effect should be compensated by adjusting the common voltage Vcom to produce a smaller voltage difference. Therefore, when using a unified common voltage Vcom, the flickering conditions in each area will inevitably be different, resulting in obvious differences in the flickering conditions in each area.

[0061] In order to solve the above problems, the present invention provides a display device, wherein the chamfer voltage generating circuit included therein can divide the voltage difference between the gate-on voltage VGH terminal of the power management integrated circuit PMIC and the gate-off voltage VGL terminal of the PMIC, thereby obtaining a chamfer voltage, which can also be referred to as VGN. Afterwards, the gate can generate a scanning signal with an inclined portion on the falling edge according to the chamfer voltage, thereby reducing the Feed-Through effect of the proximal thin film transistor close to the gate driver when it is turned off, making it closer to the Feed-Through effect of the distal thin film transistor when it is turned off. On this basis, even if a single fixed common voltage is used, the requirements of the entire liquid crystal panel for the display effect can be met, and the problem of obvious differences in flickering in various regions can be solved. At the same time, when dividing the gate-on voltage VGH terminal and the gate-off voltage VGL terminal, the voltage division ratio of the chamfer voltage generating circuit in the embodiment of the present invention is adjustable, so the chamfer voltage can be adjusted conveniently and efficiently without changing the hardware structure. The technical solution of the present invention will be described in detail below.

[0062] In one embodiment, a display device includes a liquid crystal panel, a chamfer voltage generating circuit, a gate driver, and a source driver.

[0063] As mentioned above, a plurality of sub-pixels and thin film transistors corresponding to each sub-pixel are arranged in an array in the liquid crystal panel. Each thin film transistor has a gate, a source and a drain. The gate of the thin film transistor can control the conduction state of the thin film transistor to which it belongs according to the scanning signal provided by the gate driver. The gate driver can transmit the scanning signal to the gate of the thin film transistor corresponding to each sub-pixel, and the source driver can provide the data signal to the corresponding sub-pixel through the source of each thin film transistor. When the gate of any thin film transistor receives a high-level scanning signal, the thin film transistor to which it belongs is in the on state, that is, the thin film transistor is turned on, and the sub-pixel corresponding to the thin film transistor can receive the data signal provided by the source driver; when the gate of any thin film transistor receives a low-level scanning signal, the thin film transistor to which it belongs is in the off state, that is, the thin film transistor is turned off, and the sub-pixel corresponding to the thin film transistor cannot receive the data signal provided by the source driver, and the state of the liquid crystal molecules in the sub-pixel remains unchanged.

[0064] It should be noted that, in the display device, the number and position of the source driver, the gate driver and the chamfer voltage generating circuit described below can be adjusted according to actual needs, and the present invention does not limit this.

[0065] The chamfer voltage generating circuit can divide the voltage difference between the gate-on voltage VGH terminal of the power management integrated circuit PMIC and the gate-off voltage VGL terminal of the PMIC to obtain the chamfer voltage, and provide the chamfer voltage to the gate driver.

[0066] The power management integrated circuit PMIC (Power Management Integrated Circuit, referred to as PMIC) is a highly integrated chip used to manage power supply, responsible for the distribution, conversion, monitoring and control of electrical energy, and can provide suitable gate-on voltage VGH and gate-off voltage VGL for the thin-film transistors in the liquid crystal panel. The gate-on voltage VGH refers to the voltage used to turn on the gate of the thin-film transistor in the liquid crystal panel. It usually has a high positive value, and the specific value depends on the design and manufacturing process of the liquid crystal panel. The gate-on voltage VGH terminal is the pin or port on the PMIC that outputs the gate-on voltage VGH. The gate-off voltage VGL is the voltage used to cut off the gate of the thin-film transistor in the liquid crystal panel. Its value is usually a negative value, and the specific value also depends on the design and manufacturing process of the liquid crystal panel. The gate-off voltage VGL terminal is the pin or port on the PMIC that outputs the gate-off voltage VGL.

[0067] On this basis, it can be understood that there should be a certain voltage difference between the gate-on voltage VGH terminal and the gate-off voltage VGL terminal, so by dividing the voltage difference between the gate-on voltage VGH terminal of the PMIC and the gate-off voltage VGL terminal of the PMIC, a new voltage value can be obtained, which can be used as the chamfer voltage. In an embodiment of the present invention, the gate driver can chamfer the falling edge of the scan signal according to a certain stable voltage value, that is, the gate driver can generate a scan signal with an inclined portion on the falling edge according to the chamfer voltage provided by the chamfer generation circuit.

[0068] Figure 3 FIG. 1 shows a schematic diagram of performing corner chamfering on a scanning signal, wherein waveform A is a scanning signal without corner chamfering, and waveform B is a scanning signal after corner chamfering. Figure 3 As shown in FIG. 1 , when the gate of the thin film transistor receives the gate-off voltage VGL, the voltage difference at the falling edge 31 of waveform A is large, and the voltage difference ΔV1 = VGH-VGL. If the corner is chamfered, the gate driver will slowly reduce the gate-on voltage VGH to a certain voltage value Vx before providing the gate-off voltage VGL, and then provide the gate-off voltage VGL. As shown in waveform B, its falling edge 32 has an inclined portion 33, and the voltage difference ΔV2 = Vx-VGL when the thin film transistor is turned off. When Vx < VGH, ΔV2 < ΔV1. It can be understood that since the size of the Feed-Through effect is related to the voltage difference, reducing the voltage difference at the moment when the thin film transistor is turned off can effectively reduce the Feed-Through effect.

[0069] Specifically, since the waveform of the scanning signal received by the proximal thin film transistor is closer to a square wave, that is, the voltage difference of the thin film transistor at the moment of closing is larger, after the gate driver performs angle chamfering on the scanning signal and generates a scanning signal with an inclined portion on the falling edge, if the scanning signal is transmitted to each thin film transistor, it can effectively reduce the voltage difference of the proximal thin film transistor close to the gate driver at the moment of closing, and effectively reduce the Feed-Through effect of the proximal thin film transistor; at the same time, since the voltage difference of the distal thin film transistor at the moment of closing is already in a relatively small state, the impact of the angle chamfering on the distal thin film transistor is relatively small. Based on this, the Feed-Through effect of the proximal thin film transistor can be made closer to the Feed-Through effect of the distal thin film transistor, thereby reducing the flicker difference at various positions in the liquid crystal panel.

[0070] It should also be emphasized that when the chamfer voltage generating circuit in the embodiment of the present invention divides the gate-on voltage VGH and the gate-off voltage VGL, the voltage division ratio used is adjustable, so the chamfer voltage generating circuit can generate different chamfer voltages.

[0071] It is understandable that for multiple display devices with the same or different parameters such as models and specifications, there must be differences between the liquid crystal panels. If the flicker problem of each liquid crystal panel is to be better solved, it is necessary to adjust the chamfer voltage of each display panel in a targeted manner. For the same liquid crystal panel, when multiple gate drivers are provided, since each gate driver is provided at a different position, the gate-on voltage VGH and the gate-off voltage VGH received by different gate drivers may also be different, and the Feed-Through effect of the proximal thin film transistor is also different. In the above two cases, multiple chamfer voltage generating circuits provided by the embodiments of the present invention can be correspondingly provided. Since the chamfer voltage generating circuit can generate different chamfer voltages, the chamfer voltage can be conveniently and efficiently adjusted without changing the hardware to be suitable for different degrees of Feed-Through effect, thereby being able to efficiently handle the flickering conditions of multiple display devices or the flickering conditions between different positions of the same liquid crystal panel, and quickly adjust the display device to the best display effect.

[0072] The structure of the chamfer voltage generating circuit will be described in detail below.

[0073] Figure 4 FIG. 1 is a schematic diagram of a chamfer voltage generating circuit. Figure 4 As shown, the chamfer voltage generating circuit includes:

[0074] A first terminal 41 is connected to a gate-on voltage VGH terminal of the PMIC;

[0075] The second terminal 42 is connected to the gate-off voltage VGL terminal of the PMIC;

[0076] The third terminal 43 is used to output a chamfer voltage;

[0077] A chamfering module 44 is connected to the first terminal, the second terminal and the third terminal respectively, and is used to divide the voltage difference between the VGH terminal and the VGL terminal to obtain the chamfering voltage; wherein the voltage division ratio of the chamfering module to divide the voltage difference is adjustable.

[0078] Among them, the gate-on voltage VGH terminal of the PMIC and the gate-off voltage VGL terminal of the PMIC can be referred to the above records, which will not be repeated here. The first terminal and the second terminal of the chamfer voltage generating circuit are respectively connected to the gate-on voltage VGH terminal of the PMIC and the gate-off voltage VGL terminal of the PMIC, and the third terminal of the chamfer voltage generating circuit is used to output the chamfer voltage VGN to the gate driver. It should be noted that the first terminal, the second terminal, the third terminal and the fourth terminal mentioned in the following embodiments are only used as identifiers to distinguish different pins or ports, and do not imply any specific function or physical position, and are only used to facilitate the description and distinction of each connection point.

[0079] In one embodiment, the chamfering module 44 includes a first resistor 51 and a second resistor 52. As shown in FIG5(a), the first resistor 51 and the second resistor 52 are connected in series between the first end 41 and the second end 42, that is, one end of the first resistor 51 is connected to the gate-on voltage VGH end of the PMIC, and the other end is connected to the second resistor 52; and one end of the second resistor 52 is connected to the gate-off voltage VGL end of the PMIC, and the other end is connected to the first resistor 51. At the same time, the third end 43 for outputting the chamfering voltage VGN is connected to the connecting line between the first resistor 51 and the second resistor 52, that is, the third end 43 is located between the first resistor 51 and the second resistor 52. Among them, at least one of the first resistor 51 and the second resistor 52 is a variable resistance element. Variable resistance element (Variable Resistance Element) refers to an element with variable resistance characteristics, including mechanical variable resistors (such as sliding rheostats) and electronic variable resistors (such as digital potentiometers). When the first resistor 51 is a sliding rheostat, the chamfer voltage generating circuit is shown in FIG. 5( b ); when the second resistor 52 is a sliding rheostat, the chamfer voltage generating circuit is shown in FIG. 5( c ).

[0080] When the gate-on voltage VGH terminal of the PMIC outputs the gate-on voltage VGH and the gate-off voltage VGL terminal of the PMIC outputs the gate-off voltage VGL, in the series resistor circuit composed of the first resistor 51 and the second resistor 52, the current I flows from the gate-on voltage VGH terminal to the gate-off voltage VGL. Based on this, the chamfer voltage VGN is the gate-off voltage VGL plus the voltage drop across the second resistor 52, so that the voltage difference between the gate-on voltage VGH terminal connected to the first terminal 41 and the gate-off voltage VGL terminal connected to the second terminal 42 can be divided by the first resistor 51 and the second resistor 52 to obtain the chamfer voltage VGN, and the chamfer voltage VGN is output from the third terminal 43.

[0081] In one embodiment, the chamfer voltage generating circuit further includes a fourth terminal. Figure 6As shown, the fourth terminal 45 is connected to the regulated voltage output terminal of the PMIC. Meanwhile, the chamfering module 44 includes a P-MOS transistor 60, a first resistor 61, a second resistor 62 and a third resistor 63:

[0082] The gate G of the P-MOS transistor 60 is connected to the fourth terminal 45, and the source S of the P-MOS transistor 60 is connected to the third terminal 43;

[0083] The drain electrode D of the P-MOS transistor 60 is connected to the analog ground GND via a first resistor 61;

[0084] The source S of the P-MOS transistor 60 is connected to the first end 41 via a second resistor 62;

[0085] The source S of the P-MOS transistor 60 is connected to the second end 42 via a third resistor 63 .

[0086] In this embodiment, the PMIC has a gate-on voltage VGH terminal and a gate-off voltage VGL terminal, and also has a regulated voltage output terminal. 2 C) A method of changing the register value by burning, thereby changing the voltage outputted by the regulated voltage output terminal of the PMIC.

[0087] In this embodiment, the voltage division ratio can be adjusted by discharging the P-MOS transistor 60 and adjusting the magnitude of the voltage output by the regulating voltage output terminal of the PMIC. Specifically, when the voltage of the node Vs is greater than the voltage received by the fourth terminal 45, the source S and the drain D of the P-MOS transistor 60 are turned on, that is, the node Vd connected to the node Vs and the drain D is turned on, and at this time, the circuit slowly discharges to the ground through the resistor R4; when the node Vs is discharged to a voltage equal to the voltage of the fourth terminal 45, the source S and the drain D of the P-MOS transistor 60 are turned off, and at this time, the circuit can make the voltage of the node Vs consistent with the voltage of the fourth terminal 45. Because the node Vs is connected to the third terminal 43, that is, the source S of the P-MOS transistor 60 is connected to the third terminal 43, and the third terminal 43 is used to output the chamfer voltage VGN, different chamfer voltages VGN can be generated by changing the voltage received by the fourth terminal 45, that is, changing the voltage output by the regulating voltage output terminal of the PMIC.

[0088] The first resistor 61 and the second resistor 62 are used to adjust and limit the magnitude of the chamfer voltage VGN. Generally speaking, the gate-off voltage VGL+preset value≤chamfer voltage VGN≤gate-on voltage VGL. Figure 7As shown, the chamfer voltages VGN1>VGN2>VGN3, and the three different chamfer voltages correspond to different chamfer waveforms. It can be seen that the larger the value of the chamfer voltage VGN, the larger the slope of the inclined portion of the falling edge of the scanning signal generated by the gate driver according to the chamfer voltage VGN. When the chamfer voltage VGN is equal to the gate turn-on voltage VGL, it is equivalent to not performing chamfering. Of course, when changing the voltage output by the regulating voltage output terminal of the PMIC, it is usually also restricted. The specific value can be set by the technician according to the actual situation, and the present invention does not limit this.

[0089] It should also be noted that the first resistor 61, the second resistor 62, the third resistor 63 and the fourth resistor 64 mentioned in the following embodiment are only used as resistor identifiers to distinguish different resistors, and the resistance specifications of each resistor can be set by technicians according to actual conditions, and the present invention is not limited to this.

[0090] In one embodiment, if Figure 6 The chamfering module shown also includes a fourth resistor 64, through which the source S of the P-MOS transistor 60 is connected to the third terminal 43, that is, one end of the fourth resistor 64 is connected to the source S of the P-MOS transistor 60, which is equivalent to the fourth resistor 64 being connected to the node Vs, and the other end of the fourth resistor 64 is connected to the third terminal 43 for outputting the chamfering voltage VGN. In the chamfering module of this embodiment, when the P-MOS transistor 60 is turned off and the voltage of the node Vs is kept consistent with the voltage of the fourth terminal 45, the voltage of the node Vs will be used as an input voltage to participate in the subsequent voltage divider circuit. At this time, the voltage divider circuit is composed of the fourth resistor 64 and the third resistor 63. The voltage dividing principle of multiple series resistors can refer to the above embodiment, which will not be repeated here. By adding the fourth resistor, high-frequency noise and power supply ripple can be suppressed to a certain extent, and the voltage of the node Vs can be buffered and stabilized to a certain extent, reducing the influence of power supply fluctuations on the chamfering voltage.

[0091] It can be seen from the above embodiments that the embodiments of the present invention provide two different design methods for chamfering modules, so that the chamfering modules can divide the voltage difference between the VGH terminal and the VGL terminal to obtain a chamfering voltage with a reasonable value. More importantly, the above two chamfering modules can obtain chamfering voltages of different sizes by adjusting the voltage division ratio, so that the chamfering voltage can be adjusted more flexibly and conveniently. If the chamfering voltage generating circuit is applied to different display devices, the chamfering voltage can be efficiently configured for each display device separately to adapt to the characteristic differences of different display devices, thereby ensuring that each display device can achieve the best display effect.

[0092] Accordingly, the present invention further provides a display panel, which includes any of the chamfered voltage generating circuits in the above-mentioned embodiments. The embodiments of the above-mentioned chamfered voltage generating circuit are applicable to the display panel provided in this embodiment, and will not be described in detail here. The above-mentioned embodiments and the beneficial effects brought about therewith are also applicable to this embodiment, and the same parts will not be described in detail here. It can be understood that in addition to the chamfered voltage generating circuit, the display panel may also include other structures such as a driving circuit. For other structures, please refer to the display panel in the related art, and no limitation is made here.

[0093] The embodiment of the present invention further provides a display device, including a housing and the display panel in the above embodiment. It should be noted that the display device in this embodiment can be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, etc.

[0094] In the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0095] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the disclosure disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The description and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0096] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A display device, characterized in that: include: A liquid crystal panel, wherein a plurality of sub-pixels and a thin film transistor corresponding to each sub-pixel are arranged in an array, wherein the gate of the thin film transistor controls the conduction state of the thin film transistor according to a scanning signal provided by a gate driver; A chamfer voltage generating circuit, used for dividing the voltage difference between the gate-on voltage VGH terminal of the power management integrated circuit PMIC and the gate-off voltage VGL terminal of the PMIC to obtain a chamfer voltage, and providing the chamfer voltage to the gate driver; wherein the voltage division ratio of the chamfer voltage generating circuit for dividing the voltage difference is adjustable; A gate driver, configured to generate a scanning signal having a falling edge with an inclined portion according to the chamfered voltage, and transmit the scanning signal to a gate of the thin film transistor corresponding to the sub-pixel; A source driver is used to provide a data signal to the sub-pixel through a source of the thin film transistor.

2. The display device according to claim 1, characterized in that The chamfer voltage generating circuit comprises a P-MOS transistor, a first resistor, a second resistor and a third resistor; The input end of the chamfer voltage generating circuit is connected to the gate of the P-MOS transistor, and the output end of the chamfer voltage generating circuit is connected to the source of the P-MOS transistor; The drain of the P-MOS transistor is connected to the analog ground via a first resistor; The source of the P-MOS transistor is connected to the gate-on voltage VGH terminal of the PMIC via a second resistor; The source of the P-MOS transistor is connected to the gate-off voltage VGL terminal of the PMIC via a third resistor.

3. The display device according to claim 2, characterized in that: The chamfer voltage generating circuit further includes a fourth resistor, and the output end of the chamfer voltage generating circuit is connected to the source of the P-MOS transistor through the fourth resistor.

4. The display device according to claim 1, characterized in that The chamfer voltage generating circuit comprises a first resistor and a second resistor; The first resistor and the second resistor are connected in series between the gate-on voltage VGH terminal of the PMIC and the gate-off voltage VGL terminal of the PMIC, and the output terminal of the chamfer voltage generating circuit is located between the first resistor and the second resistor; Wherein, at least one of the first resistor and the second resistor is a variable resistor element.

5. A chamfer voltage generating circuit, characterized in that: include: A first terminal is connected to a gate-on voltage VGH terminal of the PMIC; The second terminal is connected to the gate-off voltage VGL terminal of the PMIC; The third terminal is used to output the chamfer voltage; A chamfering module, the chamfering module is respectively connected to the first end, the second end and the third end, and is used to divide the voltage difference between the VGH end and the VGL end to obtain the chamfering voltage; wherein the voltage division ratio of the chamfering module to divide the voltage difference is adjustable.

6. The chamfer voltage generating circuit according to claim 5, characterized in that: The chamfer voltage generating circuit further includes: a fourth terminal connected to a regulated voltage output terminal of the PMIC; The chamfering module includes a P-MOS transistor, a first resistor, a second resistor and a third resistor; The gate of the P-MOS transistor is connected to the fourth terminal, and the source of the P-MOS transistor is connected to the third terminal; The drain of the P-MOS transistor is connected to the analog ground via a first resistor; The source of the P-MOS transistor is connected to the first end via a second resistor; The source of the P-MOS transistor is connected to the second end via a third resistor.

7. The chamfer voltage generating circuit according to claim 6, characterized in that: The chamfering module further includes a fourth resistor, and the source of the P-MOS transistor is connected to the third end via the fourth resistor.

8. The chamfer voltage generating circuit according to claim 5, characterized in that: The chamfering module includes a first resistor and a second resistor; The first resistor and the second resistor are connected in series between the first end and the second end, and the third end is connected to a connection line between the first resistor and the second resistor; Wherein, at least one of the first resistor and the second resistor is a variable resistor element.

9. A display panel, characterized in that: The invention comprises a chamfer voltage generating circuit as claimed in any one of claims 5 to 8.

10. A display device, characterized in that: It comprises a housing and the display panel as claimed in claim 9.

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