Read-write test method of memory, electronic equipment and storage medium

Abstract

The invention discloses a memory read-write test method, electronic equipment and a storage medium. The method comprises the following steps: establishing communication connection with a to-be-tested memory; obtaining a plurality of test subsequences; setting a corresponding write-in address for each test sub-sequence according to a preset address interval; and writing the corresponding test subsequences into the memory buffer area according to a preset write-in sequence, writing the test subsequences in the memory buffer area into the memory to be tested according to write-in addresses corresponding to the test subsequences, and performing cleaning operation on the memory buffer area to clear data in the memory buffer area. All the test subsequences are written into the memory to be tested until all the test subsequences are written into the memory to be tested; respectively obtaining a plurality of read subsequences from the memory to be tested through the memory cache region and according to the write-in address in sequence according to the write-in sequence; and comparing the read sub-sequence with the test sub-sequence to generate a test result. According to the method and the device, the test accuracy can be ensured while the read-write test can be efficiently performed on the memory.

Description

Technical Field

[0001] The present application relates to the field of memory testing technology, and in particular to a read-write test method for a memory device, an electronic device, and a storage medium. Background Art

[0002] In the development, production and maintenance of contemporary computer systems and electronic equipment, accurate testing of memory read and write performance is crucial. As a key component for data storage and interaction, the read and write performance of memory directly affects the operating efficiency, response speed and stability of the entire system.

[0003] Currently, when performing read and write tests on memory, the mainstream method mainly involves using a main control board with a memory buffer (Cache) to operate the memory under test. There are usually two completely different testing methods: First, open the CPU's memory buffer for read and write tests. In this mode, when the CPU executes read and write instructions, it will first query the memory buffer (Cache). If the required data is cached therein (i.e., the cache hits), the data can be directly and quickly obtained from the memory buffer or written to the memory buffer, greatly improving the read and write speed. However, this method has significant defects. Due to the involvement of the memory buffer, the test process often over-relies on the performance of the memory buffer, making it difficult for the obtained test results to accurately reflect the true read and write characteristics of the memory device under test. A large number of read and write operations are actually completed inside the memory buffer, and only a small number of memory buffer misses will actually trigger access to the memory device under test, which makes it impossible for testers to know the actual read and write capabilities of the memory device under test without the assistance of the memory buffer, thereby lacking a reliable basis for evaluating memory quality, screening compatible memory products, and troubleshooting memory underlying faults.

[0004] Second, turn off the CPU's memory buffer to implement read and write tests. At this point, the CPU directly establishes a read and write channel with the memory device to be tested, and each read and write operation actually acts on the memory device to be tested, ensuring that the test results can truly present the performance status of the memory device itself. However, the disadvantages of this method are equally obvious. Due to the lack of the high-speed caching function of the memory buffer, the CPU must wait for the memory device to be tested to complete the reading, writing and corresponding processing of data, resulting in an extremely slow entire test process. This not only greatly prolongs the test cycle, increases R&D costs and time costs, but also particularly highlights the problem of inefficiency. Moreover, for some system tests with high real-time requirements, too slow a test speed may also result in the inability to accurately capture the dynamic performance changes of the memory when the system is running at high speed. Summary of the invention

[0005] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a read-write test method, electronic device and storage medium for a memory device, which can efficiently perform read-write tests on the memory device while ensuring test accuracy.

[0006] In a first aspect, the present application provides a read / write test method for a memory device, which is applied to a test main control chip, wherein the test control main control chip includes a memory buffer, including: Establishing a communication connection with the memory device to be tested; Acquire a plurality of test subsequences; wherein the length of the test subsequence is less than or equal to the length of the memory buffer; According to a preset address interval, setting a corresponding write address for each of the test subsequences; According to a preset writing order, the corresponding test subsequence is written into the memory buffer, and according to the writing address corresponding to the test sequence, the test subsequence in the memory buffer is written into the memory to be tested, and a flushing operation is performed on the memory buffer until all the test subsequences are written into the memory to be tested; wherein the flushing operation is used to clear the data in the memory buffer; Again, according to the write order, sequentially through the memory cache area and according to the write address, a plurality of read subsequences are obtained from the memory to be tested; The read subsequence is compared with the corresponding test subsequence to generate a test result.

[0007] According to the read-write test method of the memory device of the first embodiment of the present application, at least the following beneficial effects are achieved: first, relying on the test main control chip with a memory buffer, a stable communication connection is established with the memory device to be tested, then, a number of test subsequences are obtained, and the length of the test subsequence is particularly limited to be less than or equal to the length of the memory buffer, so as to avoid the situation where the written data is lost due to overflow caused by excessive data volume. According to the preset address interval, a corresponding write address is set for each test subsequence, and then, according to the preset write order, the test subsequence is first written into the memory buffer, and the memory buffer plays a role in accelerating data transmission, and uses its relatively high-speed read-write characteristics to speed up the flow of data from the main control chip to the memory buffer. Then, according to the set write address, the test subsequence in the memory buffer is written to the memory device to be tested. After each write is completed, a cleaning operation is immediately performed on the memory buffer, that is, the data in the memory buffer is completely cleared. This cycle is repeated until all test subsequences accurately complete the task of writing to the memory device to be tested. Again, according to the previous write order, several read subsequences are obtained from the memory device to be tested through the memory buffer area and the corresponding write address in turn. At this time, due to the previous cleaning operation, there is basically no residual test data in the memory buffer, which prompts the read operation to be directly directed to the memory device to be tested, and forces the read and write operations to interact more directly with the memory device to be tested, so that the write test process no longer relies solely on the memory buffer, but actually involves write operations to different address areas of the memory device to be tested, thereby accurately testing the write performance of the memory device to be tested. During the read test, due to the previous cleaning operation, the test main control chip can only read data from the memory device to be tested, which also ensures the authenticity of the read performance test. This application improves the efficiency of the write test by using the memory buffer while ensuring the accuracy of the test.

[0008] According to some embodiments of the first aspect of the present application, obtaining a plurality of test subsequences includes: Get the test sequence; Cutting the test sequence according to the length of the memory buffer to obtain a plurality of the test subsequences; The writing order for each of the test sub-sequences is generated according to the arrangement order of the test sequence.

[0009] According to some embodiments of the first aspect of the present application, comparing the read subsequence with the corresponding test subsequence to generate a test result includes: Combining a plurality of the read subsequences according to the write order to obtain a read sequence; The read sequence is compared with the test sequence to generate a test result.

[0010] According to some embodiments of the first aspect of the present application, before the step of comparing the read subsequence with the corresponding test subsequence to generate a test result, the step further includes: Adjusting the address interval multiple times, and updating the write address corresponding to each test subsequence according to the adjusted address interval; Erasing the data in the memory to be tested; According to the write order, the test subsequences are written into the memory to be tested in sequence through the memory buffer again and according to the new write address, and a cleaning operation is performed on the memory buffer area after each test subsequence is written into the memory to be tested; Again, according to the write order, sequentially through the memory cache area and according to the new write address, sequentially acquiring a plurality of the read subsequences from the memory to be tested; The comparing the read subsequence with the corresponding test subsequence to generate a test result includes: The read subsequences obtained according to different address intervals are compared with the corresponding test subsequences to generate test results.

[0011] According to some embodiments of the first aspect of the present application, the adjusting the address interval multiple times includes: Obtain the storage capacity of the memory to be tested; Determining the number of adjustments and the increment interval according to the storage capacity; The address interval is adjusted multiple times according to the number of adjustments, and the address interval is increased each time according to the incremental interval.

[0012] According to some embodiments of the first aspect of the present application, comparing the read subsequence with the corresponding test subsequence to generate a test result includes: When the read subsequence does not match the corresponding test subsequence, determining a corresponding abnormal address according to the test subsequence; Obtaining an abnormal address range according to the abnormal address and the length of the corresponding test subsequence; A test result is generated according to the abnormal address range.

[0013] According to some embodiments of the first aspect of the present application, generating a test result according to the abnormal address range includes: Obtain the storage capacity of the memory to be tested; Obtaining an abnormal capacity according to the total length of all the abnormal address ranges; Calculating an abnormality ratio according to the abnormal capacity and the storage capacity; The test result is generated according to the abnormal address range and the abnormal ratio.

[0014] According to some embodiments of the first aspect of the present application, the present invention further includes: Obtaining the writing time of all the test subsequences writing into the memory to be tested through the memory buffer, and the reading time of all the reading subsequences reading from the memory buffer; Obtaining a writing speed according to the writing time and the total length of the test subsequence; Obtaining a reading speed according to the reading time and the total length of the reading subsequence; A processing speed evaluation result is generated according to the write speed and a preset write threshold, the read speed and a preset read threshold.

[0015] In a second aspect, the present application further provides an electronic device, including: at least one memory; at least one processor; at least one program; The program is stored in the memory, and the processor executes at least one of the programs to implement the read and write test method of the memory device described in any embodiment of the second aspect.

[0016] In a third aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer-executable signal, and the computer-executable signal is used to execute the read and write test method of the memory device as described in any one of the first aspects.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A flowchart of a read-write test method for a memory provided in the first embodiment of the present application; Figure 2 For this application Figure 1 Flow chart of step S110; Figure 3 For this application Figure 1 Flow chart of the first embodiment of step S160; Figure 4 For this application Figure 1 Regarding the flowchart before step S160; Figure 5 For this application Figure 4 Flow chart of step S410; Figure 6 For this application Figure 1 Flow chart of the second embodiment of step S160; Figure 7 For this application Figure 6 Flow chart of step S630; Figure 8 A flowchart of a method for reading and writing tests on a memory device provided in the second embodiment of the present application. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0020] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0021] In the description of this application, if there is a description of first or second, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0022] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0023] In the development, production and maintenance of contemporary computer systems and electronic equipment, accurate testing of memory read and write performance is crucial. As a key component for data storage and interaction, the read and write performance of memory directly affects the operating efficiency, response speed and stability of the entire system.

[0024] Currently, when performing read and write tests on memory, the mainstream method mainly involves using a main control board with a memory buffer (Cache) to operate the memory under test. There are usually two completely different testing methods: First, open the CPU's memory buffer for read and write tests. In this mode, when the CPU executes read and write instructions, it will first query the memory buffer (Cache). If the required data is cached therein (i.e., the cache hits), the data can be directly and quickly obtained from the memory buffer or written to the memory buffer, greatly improving the read and write speed. However, this method has significant defects. Due to the involvement of the memory buffer, the test process often over-relies on the performance of the memory buffer, making it difficult for the obtained test results to accurately reflect the true read and write characteristics of the memory device under test. A large number of read and write operations are actually completed inside the memory buffer, and only a small number of memory buffer misses will actually trigger access to the memory device under test, which makes it impossible for testers to know the actual read and write capabilities of the memory device under test without the assistance of the memory buffer, thereby lacking a reliable basis for evaluating memory quality, screening compatible memory products, and troubleshooting memory underlying faults.

[0025] Second, turn off the CPU's memory buffer to implement read and write tests. At this point, the CPU directly establishes a read and write channel with the memory device to be tested, and each read and write operation actually acts on the memory device to be tested, ensuring that the test results can truly present the performance status of the memory device itself. However, the disadvantages of this method are equally obvious. Due to the lack of the high-speed caching function of the memory buffer, the CPU must wait for the memory device to be tested to complete the reading, writing and corresponding processing of data, resulting in an extremely slow entire test process. This not only greatly prolongs the test cycle, increases R&D costs and time costs, but also particularly highlights the problem of inefficiency. Moreover, for some system tests with high real-time requirements, too slow a test speed may also result in the inability to accurately capture the dynamic performance changes of the memory when the system is running at high speed.

[0026] Based on this, the present application provides a read and write test method of a memory device, an electronic device and a storage medium to solve the above-mentioned technical problems. The technical solutions provided by the present application are described in detail one by one below.

[0027] In a first aspect, the present application provides a read / write test method for a memory device, which is applied to test a main control chip, wherein the test control main control chip includes a memory buffer, and the read / write test method includes: Step S110: establishing a communication connection with the memory device to be tested; Step S120: obtaining a plurality of test subsequences; wherein the length of the test subsequence is less than or equal to the length of the memory buffer; Step S130: setting a corresponding write address for each test subsequence according to a preset address interval; Step S140: writing the corresponding test subsequence into the memory buffer in accordance with a preset writing order, writing the test subsequence in the memory buffer into the memory to be tested according to the writing address corresponding to the test sequence, and performing a flushing operation on the memory buffer until all the test subsequences are written into the memory to be tested; wherein the flushing operation is used to clear the data in the memory buffer; Step S150: again in accordance with the writing order, sequentially through the memory cache area and according to the writing address, obtaining a plurality of read subsequences from the memory to be tested; Step S160: Compare the read subsequence with the corresponding test subsequence to generate a test result.

[0028] In step S110 to step S160, first, relying on the test main control chip with a memory buffer, a stable communication connection is established with the memory device to be tested, and then, a number of test subsequences are obtained, and the length of the test subsequence is particularly limited to be less than or equal to the length of the memory buffer, so as to avoid the situation where the written data is lost due to overflow caused by excessive data volume. According to the preset address interval, a corresponding write address is set for each test subsequence, and then, according to the preset write order, the test subsequence is first written into the memory buffer. The memory buffer plays a role in accelerating data transmission, and uses its relatively high-speed read and write characteristics to speed up the flow of data from the main control chip to the memory buffer. Then, according to the set write address, the test subsequence in the memory buffer is written to the memory device to be tested. After each write is completed, a cleaning operation is immediately performed on the memory buffer, that is, the data in the memory buffer is completely cleared. This cycle is repeated until all test subsequences accurately complete the task of writing into the memory device to be tested. Again, according to the previous write order, several read subsequences are obtained from the memory device to be tested through the memory buffer area and the corresponding write address in turn. At this time, due to the previous cleaning operation, there is basically no residual test data in the memory buffer, which prompts the read operation to be directly directed to the memory device to be tested, and forces the read and write operations to interact more directly with the memory device to be tested, so that the write test process no longer relies solely on the memory buffer, but actually involves write operations to different address areas of the memory device to be tested, thereby accurately testing the write performance of the memory device to be tested. During the read test, due to the previous cleaning operation, the test main control chip can only read data from the memory device to be tested, which also ensures the authenticity of the read performance test. This application improves the efficiency of the write test by using the memory buffer while ensuring the accuracy of the test.

[0029] Reference Figure 2 It is understandable that step S110 may include but is not limited to the following steps: Step S210: obtaining a test sequence; Step S220: cutting the test sequence according to the length of the memory buffer to obtain a plurality of test subsequences; Step S230: Generate a writing order for each test subsequence according to the arrangement order of the test sequence.

[0030] In step S210 to step S230, the test sequence is cut according to the length of the memory buffer to obtain a test subsequence, which not only makes full use of the storage space of the memory buffer and avoids the risk of buffer overflow due to excessive data volume, but also assists in data writing with the help of the relatively efficient transmission performance of the memory buffer, thereby optimizing the efficiency of the entire test process. The writing order of each test subsequence is generated according to the arrangement order of the test sequence, which provides a clear logical order for the entire test process. In the write test phase, the test subsequence is written into the memory buffer and the memory to be tested in strict accordance with this order, which can ensure that the data is written in an orderly manner, and trace and troubleshoot when problems occur.

[0031] Reference Figure 3 It is understood that step S160 may include but is not limited to the following steps: Step S310: combining a plurality of read subsequences according to the writing order to obtain a read sequence; Step S320: Compare the read sequence with the test sequence to generate a test result.

[0032] In step S310 to step S320, during the memory reading and writing process, due to the complexity of the data storage and reading mechanism, the read data may be scattered or the order may be different from that when it was written. By combining according to the write order, the complete state of the original data after being read in the memory can be restored to the greatest extent, making it comparable with the original test sequence in format and order. The test results generated by this detailed comparison method can not only reflect whether the memory device to be tested can correctly store and read data, but also further reflect the data reading and writing quality under different write orders, data modes and storage locations.

[0033] It is understandable that before step S160, the following steps may also be included but not limited to: Step S410: adjusting the address interval multiple times, and updating the write address corresponding to each test subsequence according to the adjusted address interval; Step S420: erasing the data in the memory to be tested; Step S430: writing the test subsequences into the memory to be tested in sequence through the memory buffer and according to the new write address in accordance with the write order, and performing a cleaning operation on the memory buffer after each test subsequence is written into the memory to be tested; Step S440: again, according to the writing order, sequentially through the memory cache area and according to the new writing address, sequentially obtaining a plurality of read subsequences from the memory to be tested; Correspondingly, in step S160, the following steps may be included but not limited to: Step S450: Compare the read subsequences obtained according to different address intervals with the corresponding test subsequences to generate a test result.

[0034] In step S410 to step S450, by adjusting the address interval multiple times and updating the write address, various data storage distribution situations can be simulated. In practical applications, data is stored in a variety of ways in memory. Some data may be closely arranged, while some may be sparsely distributed. Rounds of testing can allow the memory to be tested to undergo read and write tests under different "data layouts", thereby comprehensively evaluating the read and write performance of the memory in various possible storage scenarios. Different address intervals will change the positional relationship of the test subsequence in the memory, and this change helps to explore the boundary conditions of the memory performance. For example, when the address interval is very small, the limit performance of the memory when processing continuous data blocks may be tested; and as the address interval increases, the performance of the memory in dealing with scattered data can be observed, including whether there is a local performance bottleneck or performance change law in certain special address intervals, so as to have a deeper understanding of the performance characteristics of the memory.

[0035] It is understandable that the multiple adjustment of the address interval in step S410 may include but is not limited to the following steps: Step S510: obtaining the storage capacity of the memory to be tested; Step S520: Determine the number of adjustments and the increment interval according to the storage capacity; Step S530: adjusting the address interval multiple times according to the adjustment times, and the address interval adjusted each time increases according to an incremental interval.

[0036] In step S510 to step S530, the number of adjustments and the increment interval are determined by obtaining the storage capacity of the memory to be tested. This method enables the test process to be adaptively adjusted according to the actual size of the memory. For a small-capacity memory, it may not require too many adjustments and too large increment intervals to fully test its performance; while for a large-capacity memory, correspondingly increasing the number of adjustments and increment intervals can ensure that the data can cover a wider storage area, thereby achieving accurate testing of memory devices of different capacities. For example, a small-capacity embedded memory may only require a small number of adjustments (such as 3-5 times) and a small increment interval to test the read and write performance of each storage area; while a large-capacity server memory may require more adjustments (such as 10-20 times) and a larger increment interval to fully evaluate its performance under different data distributions. This adaptive adjustment method avoids over-testing or under-testing, and can reduce unnecessary test rounds while ensuring comprehensive testing of memory performance, thereby improving test efficiency. Compared with a fixed adjustment method that does not consider the capacity of the memory, it can arrange test resources more targetedly according to the specific capacity characteristics of the memory, saving test time and cost.

[0037] It is understandable that step S160 may include but is not limited to the following steps: Step S610: when the read subsequence does not match the corresponding test subsequence, determining the corresponding abnormal address according to the test subsequence; Step S620: Obtain an abnormal address range according to the abnormal address and the length of the corresponding test subsequence; Step S630: Generate a test result according to the abnormal address range.

[0038] In steps S610 to S630, when the read subsequence does not match the test subsequence, the corresponding exception address can be determined based on the test subsequence, which makes it possible to accurately locate the location where the read and write errors occur. The exception address range is further obtained based on the exception address and the length of the test subsequence, which enables a more comprehensive assessment of the area affected by the fault.

[0039] It is understandable that step S630 may include but is not limited to the following steps: Step S710: obtaining the storage capacity of the memory to be tested; Step S720: Obtain the abnormal capacity according to the total length of all abnormal address ranges; Step S730: Calculate the abnormality ratio according to the abnormal capacity and the storage capacity; Step S740: Generate a test result according to the abnormal address range and the abnormal ratio.

[0040] In step S710 to step S740, by obtaining the storage capacity of the memory device to be tested and obtaining the abnormal capacity according to the total length of all abnormal address ranges, this process converts the memory read and write errors from simple location information into a quantifiable capacity concept, and further calculates the abnormal ratio according to the abnormal capacity and storage capacity, and presents the read and write performance problems of the memory device in the form of a ratio. This abnormal ratio can provide a unified measurement standard between memory devices of different capacities, which is convenient for horizontal comparison of memory devices. The test results are generated according to the abnormal address range and the abnormal ratio, so that the test results contain both the specific location information of the error and the quantitative evaluation of the overall performance problem. Engineers can locate design defects based on detailed location information and overall ratios; in the production process, quality control personnel can set reasonable quality standards based on the abnormal ratio to determine whether the product is qualified; during use, users can decide whether to continue using the memory device or what measures to take to deal with possible problems based on the test results.

[0041] It is understandable that the memory read and write test method provided in the present application may also include but not limited to the following steps: Step S810: obtaining the writing time of all test subsequences into the memory to be tested through the memory buffer, and the reading time of all read subsequences read through the memory buffer; Step S820: Obtaining the writing speed according to the writing time and the total length of the test subsequence; Step S830: Obtaining the reading speed according to the reading time and the total length of the read subsequence; Step S840: Generate a processing speed evaluation result according to the write speed and a preset write threshold, the read speed and a preset read threshold.

[0042] In step S810 to step S840, the read and write speed of the memory directly affects the response speed and fluency of the system. By obtaining the write time and the read time to calculate the write speed and the read speed respectively, the read and write performance of the memory can be quantitatively evaluated from the speed dimension. The processing speed evaluation result is generated based on the write speed and the preset write threshold, the read speed and the preset read threshold. By setting the corresponding threshold and comparing the measured speed, it can be intuitively determined whether the memory meets the speed requirements of a specific application scenario, thereby providing a strong basis for the selection and adaptation of the memory.

[0043] In a second aspect, the present application also provides an electronic device, comprising: at least one memory, at least one processor and at least one program, the program is stored in the memory, and the processor executes one or more programs to implement the above-mentioned memory read and write test method.

[0044] In this electronic device, first, relying on the test main control chip with a memory buffer, a stable communication connection is established with the memory device to be tested, and then a number of test subsequences are obtained, and the length of the test subsequence is specifically limited to be less than or equal to the length of the memory buffer, so as to avoid the situation where the written data is lost due to overflow caused by excessive data volume. According to the preset address interval, a corresponding write address is set for each test subsequence, and then, according to the preset write order, the test subsequence is first written into the memory buffer. The memory buffer plays a role in accelerating data transmission, and uses its relatively high-speed read and write characteristics to speed up the flow of data from the main control chip to the memory buffer. Then, according to the set write address, the test subsequence in the memory buffer is written to the memory device to be tested. After each write is completed, the memory buffer is immediately cleaned, that is, the data in the memory buffer is completely cleared. This cycle is repeated until all test subsequences have accurately completed the task of writing into the memory device to be tested. Again, according to the previous write order, several read subsequences are obtained from the memory device to be tested through the memory buffer area and the corresponding write address in turn. At this time, due to the previous cleaning operation, there is basically no residual test data in the memory buffer, which prompts the read operation to be directly directed to the memory device to be tested, and forces the read and write operations to interact more directly with the memory device to be tested, so that the write test process no longer relies solely on the memory buffer, but actually involves write operations to different address areas of the memory device to be tested, thereby accurately testing the write performance of the memory device to be tested. During the read test, due to the previous cleaning operation, the test main control chip can only read data from the memory device to be tested, which also ensures the authenticity of the read performance test. This application improves the efficiency of the write test by using the memory buffer while ensuring the accuracy of the test.

[0045] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function; the data storage area may store data related to the read and write test method of the above-mentioned memory device, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processing module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0046] One or more signals are stored in a memory, and when executed by one or more processors, the memory read and write test method in any of the above method embodiments is executed.

[0047] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program is executed by one or more processors, enabling the one or more processors to execute the memory read and write test method in the above method embodiment.

[0048] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0049] Through the description of the above embodiments, it can be understood by those skilled in the art that all or some steps and systems in the methods disclosed above can be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable signals, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally embodies computer readable signals, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0050] It should be understood that in the present application, "at least one item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following items)" or similar expressions refers to any combination of these items, including any combination of single items () or plural items (). For example, at least one of a, b or c () can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0051] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0052] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0053] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0054] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including multiple instructions to enable a computer device (such as a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0055] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A method for reading and writing a memory device, characterized in that: Applied to testing a main control chip, the test control main control chip includes a memory buffer, and the read-write test method includes: Establishing a communication connection with the memory device to be tested; Acquire a plurality of test subsequences; wherein the length of the test subsequence is less than or equal to the length of the memory buffer; According to a preset address interval, setting a corresponding write address for each of the test subsequences; According to a preset writing order, the corresponding test subsequence is written into the memory buffer, and according to the writing address corresponding to the test sequence, the test subsequence in the memory buffer is written into the memory to be tested, and a flushing operation is performed on the memory buffer until all the test subsequences are written into the memory to be tested; wherein the flushing operation is used to clear the data in the memory buffer; Again, according to the write order, sequentially through the memory cache area and according to the write address, a plurality of read subsequences are obtained from the memory to be tested; The read subsequence is compared with the corresponding test subsequence to generate a test result.

2. The read-write test method of a memory device according to claim 1, characterized in that: The obtaining of several test subsequences includes: Get the test sequence; Cutting the test sequence according to the length of the memory buffer to obtain a plurality of the test subsequences; The writing order for each of the test sub-sequences is generated according to the arrangement order of the test sequence.

3. The read-write test method of a memory device according to claim 2, characterized in that: The comparing the read subsequence with the corresponding test subsequence to generate a test result includes: Combining a plurality of the read subsequences according to the write order to obtain a read sequence; The read sequence is compared with the test sequence to generate a test result.

4. The read-write test method of a memory device according to claim 1, characterized in that: Before the step of comparing the read subsequence with the corresponding test subsequence to generate a test result, the method further includes: Adjusting the address interval multiple times, and updating the write address corresponding to each test subsequence according to the adjusted address interval; Erasing the data in the memory to be tested; According to the write order, the test subsequences are written into the memory to be tested in sequence through the memory buffer again and according to the new write address, and a cleaning operation is performed on the memory buffer area after each test subsequence is written into the memory to be tested; Again, according to the write order, sequentially through the memory cache area and according to the new write address, sequentially acquiring a plurality of the read subsequences from the memory to be tested; The comparing the read subsequence with the corresponding test subsequence to generate a test result includes: The read subsequences obtained according to different address intervals are compared with the corresponding test subsequences to generate test results.

5. The read-write test method of a memory device according to claim 4, characterized in that: The step of adjusting the address interval multiple times includes: Obtain the storage capacity of the memory to be tested; Determining the number of adjustments and the increment interval according to the storage capacity; The address interval is adjusted multiple times according to the number of adjustments, and the address interval is increased each time according to the incremental interval.

6. The read-write test method of a memory device according to claim 1, characterized in that: The comparing the read subsequence with the corresponding test subsequence to generate a test result includes: When the read subsequence does not match the corresponding test subsequence, determining a corresponding abnormal address according to the test subsequence; Obtaining an abnormal address range according to the abnormal address and the length of the corresponding test subsequence; A test result is generated according to the abnormal address range.

7. The read-write test method of a memory device according to claim 6, characterized in that: Generating a test result according to the abnormal address range includes: Obtain the storage capacity of the memory to be tested; Obtaining an abnormal capacity according to the total length of all the abnormal address ranges; Calculating an abnormality ratio according to the abnormal capacity and the storage capacity; The test result is generated according to the abnormal address range and the abnormal ratio.

8. The read-write test method of a memory device according to claim 1, characterized in that: Also includes: Obtaining the writing time of all the test subsequences writing into the memory to be tested through the memory buffer, and the reading time of all the reading subsequences reading from the memory buffer; Obtaining a writing speed according to the writing time and the total length of the test subsequence; Obtaining a reading speed according to the reading time and the total length of the reading subsequence; A processing speed evaluation result is generated according to the write speed and a preset write threshold, the read speed and a preset read threshold.

9. An electronic device, characterized in that: include: at least one memory; at least one processor; at least one program; The program is stored in the memory, and the processor executes at least one of the programs to implement the read and write test method of the memory device according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer-executable signal, and the computer-executable signal is used to execute the read and write test method of the memory device according to any one of claims 1 to 8.

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