Control method and device for coupling fault test of memory chip and electronic equipment

Abstract

The invention discloses a memory chip coupling fault test control method and apparatus, and an electronic device. The method comprises the steps of obtaining a distribution structure in a to-be-tested chip; dividing the storage unit into a plurality of to-be-tested areas, and determining a first test sequence among the to-be-tested areas and a second test sequence of each storage unit; obtaining a first test sequence and a second test sequence; writing the first test sequence into the first to-be-tested area, and writing the second test sequence into other to-be-tested areas at a time; after writing of all the to-be-tested areas is completed, according to the first test sequence and the second test sequence, a target test sequence is read from each to-be-tested area; and according to the first test sequence, comparing the target test sequence with the corresponding first test sequence or the second test sequence, and determining a coupling fault type. According to the invention, the efficiency of troubleshooting the coupling fault of the memory chip can be improved, and the quality and reliability of the memory chip are guaranteed.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a control method, device and electronic equipment for memory chip coupling fault testing. Background Art

[0002] In today's digital age, memory chips are widely used in various electronic devices, and their performance and reliability are crucial. However, during the use of memory chips, due to the close layout and electrical characteristics of the memory cells inside the chip, coupling failures are very likely to occur. This failure will cause the signals between the memory cells to interfere with each other, causing errors in data storage and reading, seriously affecting the normal operation of the equipment. Existing memory chip testing methods are difficult to accurately and efficiently determine the type and location of coupling failures, and cannot meet the needs of high-reliability testing of memory chips. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a control method, device and electronic device for memory chip coupling fault testing, which can improve the efficiency of troubleshooting memory chip coupling faults and ensure the quality and reliability of memory chips.

[0004] In a first aspect, the present application provides a control method for memory chip coupling fault testing, comprising: Obtaining the distribution structure of the storage units in the chip to be tested; According to the distribution structure, the storage unit is divided into a plurality of test areas, and a first test sequence between the test areas and a second test sequence of each storage unit are determined; wherein the number of the storage units in each test area is the same; Acquire a first test sequence and a second test sequence to be written into the area to be tested; wherein the length of the first test sequence corresponds to the storage unit of each of the area to be tested, and corresponds to the length of the second test sequence; According to the first test sequence and the second test sequence, the first test sequence is written into the first of the regions to be tested, and the second test sequence is written into the other regions to be tested at one time; After all the test areas have been written, the target test sequence is obtained by reading from each of the test areas according to the first test sequence and the second test sequence; According to the first test order, the target test sequence is compared with the corresponding first test sequence or the second test sequence to determine the coupling fault type.

[0005] According to the control method of memory chip coupling fault test of the first aspect embodiment of the present application, there are at least the following beneficial effects: first, the distribution structure of the storage unit in the chip to be tested is obtained, and based on this, the storage unit is divided into several test areas, and the number of storage units in each test area is ensured to be the same, and the first test sequence between the test areas and the second test sequence of each storage unit are determined. The first test sequence and the second test sequence to be written into the test area are obtained, and the length of the first test sequence corresponds to the storage unit of each test area, and also corresponds to the length of the second test sequence, so as to ensure that the storage unit of each test area can be completely covered, and provide guarantee for comprehensive detection. According to the first test sequence and the second test sequence, the first test sequence is written into the first test area, and the second test sequence is written into other test areas in sequence. After all the test areas are written, the target test sequence is read from each test area again according to the first test sequence and the second test sequence to obtain the target test sequence. Reading in the same order ensures the correspondence between the read data and the written data. According to the first test sequence, the target test sequence is compared with the corresponding first test sequence or second test sequence, and the coupling fault type is determined by comparative analysis. By reasonably dividing the areas to be tested and determining the detailed test sequence, each storage unit can be tested in a targeted manner. After reading the target test sequence and comparing it with the first test sequence or the second test sequence, it can be accurately determined which area to be tested or even which storage unit has a coupling fault, thereby improving the efficiency of troubleshooting coupling faults in memory chips and ensuring the quality and reliability of memory chips.

[0006] According to some embodiments of the first aspect of the present application, obtaining a first test sequence and a second test sequence to be written into the area to be tested includes: Acquire a first test sequence to be written into the area to be tested; Complement the first test sequence to obtain the second test sequence.

[0007] According to some embodiments of the first aspect of the present application, the storage unit is divided into a plurality of areas to be tested according to the distribution structure, including: Determining the region length according to the distribution structure; According to the region length, the region is divided in ascending order of the addresses of the storage units in the distribution structure to form a plurality of the regions to be tested.

[0008] According to some embodiments of the first aspect of the present application, determining a first test order between the regions to be tested and a second test order for each of the storage units includes: Determining the first test order among the areas to be tested according to the address of the first storage unit in each area to be tested; The second test order of each of the storage cells is determined according to the addresses of the storage cells in the same area to be tested.

[0009] According to some embodiments of the first aspect of the present application, comparing the target test sequence with the corresponding first test sequence or the second test sequence respectively to determine the coupling fault type includes: Compare the target test sequence with the corresponding first test sequence or the second test sequence bit by bit, and record abnormal address bits; The coupling fault type is determined according to the distribution of the abnormal address bits.

[0010] According to some embodiments of the first aspect of the present application, determining the coupling fault type according to the distribution of the abnormal address bits includes: When the address adjacent to the abnormal address bit is not the abnormal address bit, determining that the coupling fault type is a single-bit flip fault; When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is less than or equal to a preset ratio threshold, it is determined that the coupling fault type is a multi-bit flip fault; When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is greater than the ratio threshold, it is determined that the coupling fault type is a data shift fault.

[0011] According to some embodiments of the first aspect of the present application, after the step of comparing the target test sequence with the corresponding first test sequence or the second test sequence according to the first test order to determine the coupling fault type, the step further includes: changing the first test sequence and the second test sequence; Performing repeated write and read tests on the chip under test according to the new first test sequence and the second test sequence; Obtaining the current coupling fault type according to the new target test sequence and the new first test sequence or the second test sequence; If the coupling fault type of the current time is inconsistent with the coupling fault type of the previous time, re-changing the first test sequence and the second test sequence, and re-performing the write and read tests on the chip to be tested; If the current coupling fault type is consistent with the previous coupling fault type, the coupling fault type is output.

[0012] In a second aspect, the present application also provides a control device for memory chip coupling fault testing, comprising: A first acquisition unit, used to acquire the distribution structure of the storage units in the chip to be tested; A determination unit, configured to divide the storage unit into a plurality of test areas according to the distribution structure, and determine a first test sequence between the test areas and a second test sequence for each of the storage units; wherein the number of the storage units in each test area is the same; A second acquisition unit, used for acquiring a first test sequence and a second test sequence to be written into each of the regions to be tested; wherein the length of the first test sequence corresponds to the storage unit of each of the regions to be tested, and corresponds to the length of the second test sequence; a writing unit, configured to write the first test sequence into the first of the regions to be tested, and write the second test sequence into the other regions to be tested at one time, according to the first test sequence and the second test sequence; A reading unit, configured to read a target test sequence from each of the test areas respectively according to the first test sequence and the second test sequence after all the test areas have been written; A comparing unit is used to compare the target test sequence with the corresponding first test sequence or the second test sequence according to the first test order to determine the coupling fault type.

[0013] In a third aspect, the present application further provides an electronic device, including: at least one memory; at least one processor; at least one program; The program is stored in the memory, and the processor executes at least one of the programs to implement the control method for memory chip coupling fault testing as described in any one of the embodiments of the first aspect.

[0014] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer-executable signal, and the computer-executable signal is used to execute the control method for memory chip coupling fault testing as described in any embodiment of the first aspect.

[0015] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A flowchart of a control method for memory chip coupling fault testing provided by some embodiments of the present application; Figure 2 For this application Figure 1 Flow chart of step S130; Figure 3 For this application Figure 1 A flowchart of an embodiment of step S120; Figure 4 For this application Figure 1 A flowchart of another embodiment of step S120; Figure 5 For this application Figure 1 Flow chart of step S160; Figure 6 For this application Figure 5 Flow chart of step S520; Figure 7 For this application Figure 5 The flowchart after step S160. DETAILED DESCRIPTION

[0017] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0018] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0019] In the description of this application, if there is a description of first or second, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0020] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0021] In today's digital age, memory chips are widely used in various electronic devices, and their performance and reliability are crucial. However, during the use of memory chips, due to the close layout and electrical characteristics of the memory cells inside the chip, coupling failures are very likely to occur. This failure will cause the signals between the memory cells to interfere with each other, causing errors in data storage and reading, seriously affecting the normal operation of the equipment. Existing memory chip testing methods are difficult to accurately and efficiently determine the type and location of coupling failures, and cannot meet the needs of high-reliability testing of memory chips.

[0022] Based on this, the present application provides a control method, device and electronic device for memory chip coupling fault testing to solve the above-mentioned technical problems. The technical solutions provided by the present application are described in detail one by one below.

[0023] First, refer to Figure 1 , the present application provides a control method for memory chip coupling fault test, including but not limited to the following steps: Step S110: obtaining the distribution structure of the memory cells in the chip to be tested; Step S120: Divide the storage cells into a plurality of test areas according to the distribution structure, and determine a first test sequence between the test areas and a second test sequence for each storage cell; wherein the number of storage cells in each test area is the same; Step S130: obtaining a first test sequence and a second test sequence to be written into the area to be tested; wherein the length of the first test sequence corresponds to the storage unit of each area to be tested, and corresponds to the length of the second test sequence; Step S140: writing the first test sequence into the first area to be tested, and writing the second test sequence into the other areas to be tested at one time according to the first test order and the second test order; Step S150: After all the test areas have been written, the target test sequence is obtained by reading from each test area according to the first test sequence and the second test sequence; Step S160: According to the first test order, the target test sequence is compared with the corresponding first test sequence or second test sequence to determine the coupling fault type.

[0024] In step S110 to step S160, the distribution structure of the storage unit in the chip to be tested is first obtained, and the storage unit is divided into several test areas based on this, and the number of storage units in each test area is ensured to be the same, and the first test sequence between the test areas and the second test sequence of each storage unit are determined. The first test sequence and the second test sequence to be written into the test area are obtained, and the length of the first test sequence corresponds to the storage unit in each test area, and also corresponds to the length of the second test sequence, so as to ensure that the storage unit in each test area can be completely covered, providing guarantee for comprehensive detection. According to the first test sequence and the second test sequence, the first test sequence is written into the first test area, and the second test sequence is written into other test areas in sequence. After all the test areas are written, the target test sequence is read from each test area again according to the first test sequence and the second test sequence to obtain the target test sequence. Reading in the same order ensures the correspondence between the read data and the written data. According to the first test sequence, the target test sequence is compared with the corresponding first test sequence or second test sequence, and the coupling fault type is determined by comparative analysis. By reasonably dividing the areas to be tested and determining the detailed test sequence, each storage unit can be tested in a targeted manner. After reading the target test sequence and comparing it with the first test sequence or the second test sequence, it can be accurately determined which area to be tested or even which storage unit has a coupling fault, thereby improving the efficiency of troubleshooting coupling faults in memory chips and ensuring the quality and reliability of memory chips.

[0025] By using different test sequences (first test sequence and second test sequence) for different areas to be tested, the characteristics of the coupling fault can be better found when the target test sequence is subsequently read and compared with the original test sequence. When the data read from different areas are different, since different test sequences are used for different areas, it is possible to more clearly determine which area has a fault and the type of fault.

[0026] Reference Figure 2 It is understandable that step S130 may include but is not limited to the following steps: Step S210: obtaining a first test sequence to be written into the area to be tested; Step S220: Complement the first test sequence to obtain a second test sequence.

[0027] In step S210 to step S220, the second test sequence is obtained by complementing the first test sequence, so that the storage unit can be tested from both positive and negative angles. For example, if the first test sequence can detect a certain type of coupling fault after being written into the storage unit, then the second test sequence (the complement of the first test sequence) may detect another type of coupling fault different from it after being written. Because the coupling fault between storage cells may have different manifestations under different data modes (original code and complement), various possible coupling fault types can be detected more comprehensively. Coupling faults in memory chips may be caused by various factors, such as different circuit layouts, signal interference methods, etc. A single test sequence may only detect some fault types. By setting the first test sequence and the second test sequence, especially by complementing the first test sequence to obtain the second test sequence, more data storage and reading situations can be simulated.

[0028] Reference Figure 3 It can be understood that, in step S120 of “dividing the storage unit into a plurality of test areas according to the distribution structure”, the following steps may be included but not limited to: Step S310: determining the region length according to the distribution structure; Step S320: dividing the regions according to the region length and in the ascending order of the addresses of the storage units in the distribution structure to form a plurality of regions to be tested.

[0029] First, analyze the distribution structure of the storage cells in the memory chip. This distribution structure contains information such as the arrangement and physical layout of the storage cells in the chip. For example, the storage cells may be arranged in the form of a row and column matrix, or they may be organized differently in different storage modules. According to this distribution information, the region length is determined in combination with the test objectives and requirements. After determining the region length, start dividing it in the ascending order of the address of the storage cell to form several test regions. Dividing the regions in ascending order of the address makes the test process highly logical and systematic. The tester can test each test region in sequence according to the address order, without missing or repeating the test region. At the same time, determining the region length according to the distribution structure of the chip can better match the test region division with the actual physical structure of the chip.

[0030] Reference Figure 4 In step S120 of “determining a first test sequence between the regions to be tested and a second test sequence for each storage unit”, the following steps may be included but not limited to: Step S410: determining a first test sequence among the test areas according to the address of the first storage unit in each test area; Step S420: determining a second test sequence for each memory cell according to the addresses of the memory cells in the same test area.

[0031] In step S410, by checking the address of the first storage unit in each area to be tested, since the areas to be tested have been divided according to the ascending order of the addresses of the storage units, the addresses of the first storage units are also in order. For example, assuming there are three areas to be tested, the address of the first storage unit of the first area to be tested is 0, the address of the first storage unit of the second area to be tested is 100, and the address of the first storage unit of the third area to be tested is 200. According to the order of the addresses from small to large, the first test order can be determined as: first test the first area to be tested, then the second, and finally the third.

[0032] In step S420, in the same area to be tested, the test order is also determined based on the address of the storage unit. Because each storage unit has its own address, these addresses are also incremented in sequence in a region to be tested. For example, in a region to be tested, the address range of the storage unit is from 100 to 109. Then, in order from small to large addresses, the storage unit with address 100 can be tested first, followed by 101, and so on, until the test order of all storage units in the region to be tested is determined.

[0033] Reference Figure 5 It is understandable that step S160 may include but is not limited to the following steps: Step S510: compare the target test sequence with the corresponding first test sequence or second test sequence bit by bit, and record abnormal address bits; Step S520: Determine the coupling fault type according to the distribution of abnormal address bits.

[0034] In step S510 to step S520, when comparing the target test sequence with the corresponding first test sequence or second test sequence, start from the starting bit of the two sequences and compare them bit by bit. For example, if the target test sequence is "1010" and the first test sequence is "1000", then by comparing bit by bit from left to right, it will be found that the third bit is different. After completing the bit-by-bit comparison and recording the abnormal address bits, start to analyze the distribution of these abnormal address bits to determine the type of coupling fault. By comparing and recording the abnormal address bits bit by bit, the specific storage unit where the coupling fault occurs can be accurately found.

[0035] Reference Figure 6 It is understandable that, in step S520, the following steps may be included but not limited to: Step S610: when the address adjacent to the abnormal address bit is not an abnormal address bit, determining that the coupling fault type is a single-bit flip fault; Step S620: when the address adjacent to the abnormal address bit is an abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is less than or equal to a preset ratio threshold, determining that the coupling fault type is a multi-bit flip fault; Step S630: when the address adjacent to the abnormal address bit is an abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is greater than the ratio threshold, it is determined that the coupling fault type is a data shift fault.

[0036] In step S610, in the recorded abnormal address bit information, the adjacent addresses of each abnormal address bit are checked. For example, for the abnormal address bit set {3, 7, 12}, check whether the adjacent addresses of addresses 2, 4, 6, 8, 11, 13, etc. are also in the abnormal address bit set. If the adjacent addresses of each abnormal address bit are not abnormal address bits, it can be determined to be a single-bit flip fault, that is, only the data of a single storage unit is flipped, and there is no simultaneous failure of adjacent storage units.

[0037] In step S620, the adjacent addresses of the abnormal address bit are also checked. When it is found that the adjacent address of the abnormal address bit is also an abnormal address bit, it is necessary to further calculate the overlap ratio of the target test sequence and the first test sequence or the second test sequence. The overlap ratio can be calculated by counting the number of identical bits in the two sequences and then dividing it by the total length of the sequence. For example, the target test sequence is "1010", the first test sequence is "0000", the number of identical bits is 0, the total length is 4, and the overlap ratio is 0. If this overlap ratio is less than or equal to the preset ratio threshold, it is determined to be a multi-bit flip fault. This indicates that multiple adjacent storage unit data have been flipped, and the flipped result is significantly different from the original sequence.

[0038] In step S630, when the adjacent address of the abnormal address bit is an abnormal address bit, and after calculating the overlap ratio, it is found that the overlap ratio is greater than the preset ratio threshold, it is determined to be a data shift fault, which means that the data of the storage unit may have moved in position due to coupling and other reasons, but the overall data similarity is still high. This may be caused by address line errors, abnormal read / write control signals, or timing coupling problems between storage units, suggesting that timing errors occurred during data transmission or storage.

[0039] Reference Figure 7 It is understandable that after step S160, the following steps may also be included but not limited to: Step S710: changing the first test sequence and the second test sequence; Step S720: Repeat writing and reading tests on the chip to be tested according to the new first test sequence and the second test sequence; Step S730: obtaining the current coupling fault type according to the new target test sequence and the new first test sequence or the second test sequence; Step S740: if the current coupling fault type is inconsistent with the previous coupling fault type, re-change the first test sequence and the second test sequence, and re-perform write and read tests on the chip to be tested; Step S750: If the current coupling fault type is consistent with the previous coupling fault type, the coupling fault type is output.

[0040] In step S710 to step S750, after the first round of comparison of the target test sequence with the first and second test sequences is completed and the coupling fault type is determined, the first test sequence and the second test sequence are changed. The change method can be diverse, such as randomly flipping the bits of the original sequence, rearranging the order, or generating a new sequence according to a specific algorithm. For example, if the original first test sequence is "1010", it can be changed to "0110" through a random algorithm. According to the new first test sequence and the second test sequence, the chip to be tested is written and read again. According to the previously determined first test sequence and second test sequence, the new first test sequence is written into the corresponding area to be tested, and the new second test sequence is written into other areas to be tested. After the writing is completed, the new target test sequence is read from each area to be tested. The new target test sequence is compared with the new first test sequence or the second test sequence, and the coupling fault type is determined according to the previous comparison rules, such as bit-by-bit comparison and the coupling fault type is determined according to the abnormal address bit distribution, so as to obtain the current coupling fault type. The current coupling fault type is compared with the previous coupling fault type. If the two are inconsistent, it means that the previously determined coupling fault type may not be accurate, so the first test sequence and the second test sequence are changed again, and then the write and read tests are performed on the chip to be tested again, and the above process is repeated; if the two are consistent, it means that after multiple tests and verifications, the coupling fault type is more reliable, and the coupling fault type is output at this time. By changing the test sequence multiple times and repeating the test, the coupling fault of the memory chip can be detected from different angles. Different test sequences can simulate different data storage and transmission scenarios, thereby more comprehensively covering various possible coupling fault situations.

[0041] In a second aspect, the present application also provides a control device for memory chip coupling fault testing, comprising: A first acquisition unit, used to acquire the distribution structure of the storage units in the chip to be tested; A determination unit, used to divide the storage units into a plurality of test areas according to the distribution structure, and determine a first test sequence between the test areas and a second test sequence for each storage unit; wherein the number of storage units in each test area is the same; A second acquisition unit, used for acquiring a first test sequence and a second test sequence to be written into each area to be tested; wherein the length of the first test sequence corresponds to the storage unit of each area to be tested, and corresponds to the length of the second test sequence; A writing unit, used for writing the first test sequence into the first area to be tested according to the first test sequence and the second test sequence, and writing the second test sequence into the other areas to be tested at one time; A reading unit, configured to read from each area to be tested respectively to obtain a target test sequence according to the first test sequence and the second test sequence after all the areas to be tested have been written; The comparison unit is used to compare the target test sequence with the corresponding first test sequence or second test sequence according to the first test order to determine the coupling fault type.

[0042] The specific implementation of the control device for the memory chip coupling fault test is substantially the same as the specific implementation of the control method for the memory chip coupling fault test described above, and will not be described in detail herein.

[0043] In a third aspect, the present application also provides an electronic device, comprising: at least one memory, at least one processor and at least one program, the program is stored in the memory, and the processor executes one or more programs to implement the above-mentioned control method of memory chip coupling fault test.

[0044] In the electronic device, the distribution structure of the storage unit in the chip to be tested is first obtained, and the storage unit is divided into several test areas based on this, and the number of storage units in each test area is ensured to be the same, and the first test sequence between the test areas and the second test sequence of each storage unit are determined. The first test sequence and the second test sequence to be written into the test area are obtained, and the length of the first test sequence corresponds to the storage unit in each test area, and also corresponds to the length of the second test sequence, so as to ensure that the storage unit in each test area can be completely covered, providing guarantee for comprehensive detection. According to the first test sequence and the second test sequence, the first test sequence is written into the first test area, and the second test sequence is written into other test areas in sequence. After all the test areas are written, the target test sequence is read from each test area again according to the first test sequence and the second test sequence to obtain the target test sequence. Reading in the same order ensures the correspondence between the read data and the written data. According to the first test sequence, the target test sequence is compared with the corresponding first test sequence or second test sequence, and the coupling fault type is determined by comparative analysis. By reasonably dividing the areas to be tested and determining the detailed test sequence, each storage unit can be tested in a targeted manner. After reading the target test sequence and comparing it with the first test sequence or the second test sequence, it can be accurately determined which area to be tested or even which storage unit has a coupling fault, thereby improving the efficiency of troubleshooting coupling faults in memory chips and ensuring the quality and reliability of memory chips.

[0045] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function; the data storage area may store relevant data of the control method of the above-mentioned memory chip coupling fault test, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processing module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0046] One or more signals are stored in a memory, and when executed by one or more processors, the control method for memory chip coupling fault test in any of the above method embodiments is executed.

[0047] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program is executed by one or more processors, enabling the one or more processors to execute the control method for memory chip coupling fault testing in the above method embodiment.

[0048] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0049] Through the description of the above embodiments, it can be understood by those skilled in the art that all or some steps and systems in the methods disclosed above can be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable signals, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally embodies computer readable signals, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0050] It should be understood that in the present application, "at least one item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following items)" or similar expressions refers to any combination of these items, including any combination of single items () or plural items (). For example, at least one of a, b or c () can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0051] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0052] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0053] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0054] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including multiple instructions to enable a computer device (such as a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0055] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A control method for memory chip coupling fault test, characterized in that: include: Obtaining the distribution structure of the storage units in the chip to be tested; According to the distribution structure, the storage unit is divided into a plurality of test areas, and a first test sequence between the test areas and a second test sequence of each storage unit are determined; wherein the number of the storage units in each test area is the same; Acquire a first test sequence and a second test sequence to be written into the area to be tested; wherein the length of the first test sequence corresponds to the storage unit of each of the area to be tested, and corresponds to the length of the second test sequence; According to the first test sequence and the second test sequence, the first test sequence is written into the first of the regions to be tested, and the second test sequence is written into the other regions to be tested at one time; After all the test areas have been written, the target test sequence is obtained by reading from each of the test areas according to the first test sequence and the second test sequence; According to the first test order, the target test sequence is compared with the corresponding first test sequence or the second test sequence to determine the coupling fault type.

2. The control method for memory chip coupling fault test according to claim 1, characterized in that: The acquiring the first test sequence and the second test sequence to be written into the area to be tested comprises: Acquire a first test sequence to be written into the area to be tested; Complement the first test sequence to obtain the second test sequence.

3. The control method for memory chip coupling fault test according to claim 1, characterized in that: According to the distribution structure, the storage unit is divided into a plurality of areas to be tested, including: Determining the region length according to the distribution structure; According to the region length, the region is divided in ascending order of the addresses of the storage units in the distribution structure to form a plurality of the regions to be tested.

4. The control method for memory chip coupling fault test according to claim 3, characterized in that: The determining of a first test sequence between the regions to be tested and a second test sequence for each of the storage units includes: Determining the first test order among the areas to be tested according to the address of the first storage unit in each area to be tested; The second test order of each of the storage cells is determined according to the addresses of the storage cells in the same area to be tested.

5. The control method for memory chip coupling fault test according to claim 1, characterized in that: The comparing the target test sequence with the corresponding first test sequence or the second test sequence respectively to determine the coupling fault type includes: Compare the target test sequence with the corresponding first test sequence or the second test sequence bit by bit, and record abnormal address bits; The coupling fault type is determined according to the distribution of the abnormal address bits.

6. The control method for memory chip coupling fault test according to claim 5, characterized in that: Determining the coupling fault type according to the distribution of the abnormal address bits includes: When the address adjacent to the abnormal address bit is not the abnormal address bit, determining that the coupling fault type is a single-bit flip fault; When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is less than or equal to a preset ratio threshold, it is determined that the coupling fault type is a multi-bit flip fault; When the address adjacent to the abnormal address bit is the abnormal address bit, and the overlap ratio of the target test sequence and the first test sequence or the second test sequence is greater than the ratio threshold, it is determined that the coupling fault type is a data shift fault.

7. The control method for memory chip coupling fault test according to claim 1, characterized in that: After the step of comparing the target test sequence with the corresponding first test sequence or the second test sequence respectively according to the first test order to determine the coupling fault type, the method further includes: changing the first test sequence and the second test sequence; Repeatedly performing write and read tests on the chip under test according to the new first test sequence and the second test sequence; Obtaining the current coupling fault type according to the new target test sequence and the new first test sequence or the second test sequence; If the coupling fault type of the current time is inconsistent with the coupling fault type of the previous time, re-changing the first test sequence and the second test sequence, and re-performing the write and read tests on the chip under test; If the current coupling fault type is consistent with the previous coupling fault type, the coupling fault type is output.

8. A control device for memory chip coupling fault test, characterized in that: include: A first acquisition unit, used to acquire the distribution structure of the storage units in the chip to be tested; A determination unit, configured to divide the storage unit into a plurality of test areas according to the distribution structure, and determine a first test sequence between the test areas and a second test sequence for each of the storage units; wherein the number of the storage units in each test area is the same; A second acquisition unit, used for acquiring a first test sequence and a second test sequence to be written into each of the regions to be tested; wherein the length of the first test sequence corresponds to the storage unit of each of the regions to be tested, and corresponds to the length of the second test sequence; a writing unit, configured to write the first test sequence into the first of the regions to be tested, and write the second test sequence into the other regions to be tested at one time, according to the first test sequence and the second test sequence; A reading unit, configured to read a target test sequence from each of the test areas respectively according to the first test sequence and the second test sequence after all the test areas have been written; A comparing unit is used to compare the target test sequence with the corresponding first test sequence or the second test sequence according to the first test order to determine the coupling fault type.

9. An electronic device, characterized in that: include: at least one memory; at least one processor; at least one program; The programs are stored in the memory, and the processor executes at least one of the programs to implement the control method for memory chip coupling fault testing according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer-executable signal, and the computer-executable signal is used to execute the control method for memory chip coupling fault test according to any one of claims 1 to 7.

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