Formation method of super junction structure, ultra-high density Resurf Schottky diode and preparation method and application of ultra-high density Resurf Schottky diode

Abstract

The invention belongs to the technical field of Schottky diodes, and discloses a forming method of a super junction structure, an ultrahigh-density Resurf Schottky diode, a preparation method and application. According to the forming method of the super junction structure, the mask layer is introduced on the substrate layer, the hole structure is formed in the mask layer, and the P column forming process is split through multiple high-energy ion implantation and rapid annealing treatment in the hole structure, so that the P column forming efficiency is improved; the formed super junction structure is enabled to have a more uniform and smooth PN interface through a multi-time superposition ion implantation mode, and the contradiction among the doping depth-to-width ratio, the junction depth and the lateral diffusion in the existing groove etching-ion implantation technology is effectively solved. The method can be well applied to semiconductor devices with super junction structures, such as an ultrahigh-density Resurf Schottky structure and the like, and has a good application prospect.

Description

Technical Field

[0001] The present invention belongs to the technical field of Schottky diodes, and in particular relates to a method for forming a super junction structure, an ultra-high density Resurf Schottky diode, and a preparation method and application thereof. Background Art

[0002] Schottky diodes are also called metal-semiconductor diodes. When certain metals and semiconductors are in contact, a barrier region is formed at their interface, which produces rectification and detection effects. Schottky diodes can be manufactured using different structural technologies, the most commonly used of which are planar structures and trench structures. The traditional trench Schottky diode (TMBS) adds a trench gate MOSFET structure to the planar Schottky diode, forming a Schottky barrier on the surface between the trenches. When reverse biased, the N-type epitaxial layer between the trenches is laterally depleted, thereby increasing the reverse breakdown voltage. However, the traditional trench Schottky diode (TMBS) has a more complicated process flow, and the corresponding material concentration, trench spacing, and gate oxide thickness are sensitive to parameter control, and the process requirements and corresponding control range are strict.

[0003] The ultra-high density Resurf Schottky structure is based on the structure of the traditional planar Schottky diode. It adopts a super junction structure formed by alternating P columns and N columns with higher doping concentrations to replace the traditional low-doped drift region. The charge balance principle is used to reduce the surface electric field. The withstand voltage value of the traditional low-doped drift region can be achieved even under heavier doping conditions. The heavier doped drift layer will reduce the on-state voltage drop, ultimately achieving the effect of improving the withstand voltage value of the device, and effectively solving the contradiction between the on-state voltage drop and the breakdown voltage in the planar structure and the trench structure.

[0004] At present, trench etching-ion implantation technology is one of the most commonly used methods for preparing ultra-high density Resurf Schottky structures. In this technology, tiny trenches or holes are first made on semiconductor materials (usually silicon wafers), and then doping is performed in the semiconductor material to form P columns. In order to achieve precise control of parameters such as doping aspect ratio, junction depth and lateral diffusion of the P column structure, the etching depth of the trench is generally controlled at around 6 to 8 μm. How to obtain a higher P column (that is, to form a deeper trench structure) is a key and even decisive process for improving the ultra-high density Resurf Schottky structure; however, as the trench deepens, problems such as unexpected doping concentration in the device and serious charge imbalance in the structure may occur, which has great limitations. Summary of the invention

[0005] The first purpose of the present invention is to solve the contradiction between device trench deepening and precise control of element doping concentration in the preparation of the existing ultra-high density Resurf Schottky structure, and to provide a method for forming a super junction structure.

[0006] The second object of the present invention is to provide a method for preparing an ultra-high density Resurf Schottky diode.

[0007] A third object of the present invention is to provide an ultra-high density Resurf Schottky diode.

[0008] A fourth object of the present invention is to provide an application of the ultra-high density Resurf Schottky diode in an integrated circuit.

[0009] Specifically, the method for forming a super junction structure provided by the present invention specifically includes: forming a mask layer with a hole structure on an N-type base layer; performing multiple P-column formation treatments on the N-type base layer on the mask layer to form P columns to obtain the super junction structure; the multiple P-column formation treatments include: alternating multiple high-energy ion implantations and rapid annealing treatments to form P columns on the N-type base layer.

[0010] Furthermore, the material of the mask layer is silicon dioxide.

[0011] Furthermore, the thickness of the mask layer is 2.0-3.0 μm.

[0012] Furthermore, the diameter of the P column is 0.1-3 μm, the depth is 1-10 μm, there are multiple P columns, and the interval between two adjacent P columns is 0.5-5 μm.

[0013] Furthermore, the number of times of the multiple P-pillar forming processes is an integer not less than 2.

[0014] Furthermore, the ions implanted with high-energy ions are selected from one or more of aluminum ions, boron ions and gallium ions.

[0015] Furthermore, the injection energy of the high-energy particle injection is 50-3000 keV, and the ion injection dose is 1×10 12 ~5×10 14 cm -2 .

[0016] Furthermore, the temperature of the rapid annealing treatment is 800-1000° C., and the time is 5-120 seconds.

[0017] Furthermore, the number of multiple P-column formation processes is 3, specifically including: (1) performing a first high-energy ion implantation and a first rapid annealing process on the mask layer to form a P-column on the N-type base layer; (2) performing a second high-energy ion implantation and a second rapid annealing process on the mask layer to form a secondary P-column on the base layer; (3) performing a third high-energy ion implantation and a third rapid annealing process on the mask layer to finally form the P-column on the N-type base layer.

[0018] Furthermore, in the first high-energy ion implantation, the second high-energy ion implantation and the third high-energy ion implantation, the implantation energy shows a decreasing trend and the implantation dose shows an increasing trend.

[0019] Furthermore, the conditions of the first high-energy ion implantation include an implantation energy of 1000-3000 keV and an implantation dose of 1×10 12 ~1×10 13 cm -2 .

[0020] Furthermore, the conditions of the second high-energy ion implantation include an implantation energy of 300-1000 keV and an implantation dose of 5×10 12 ~5×10 13 cm -2 .

[0021] Furthermore, the conditions of the third high energy ion implantation include an implantation energy of 50 to 300 keV and an implantation dose of 1×10 13 ~5×10 14 cm -2 .

[0022] The present invention provides a method for preparing an ultra-high density Resurf Schottky diode, which specifically includes: obtaining a Schottky base layer structure; forming a super junction structure on the Schottky base layer structure by adopting the above-mentioned super junction structure forming method; forming a Schottky barrier layer on the super junction structure; forming a positive electrode metal layer on the Schottky barrier layer; forming a negative electrode metal layer on the side of the Schottky base layer structure away from the super junction structure, to obtain the ultra-high density Resurf Schottky diode.

[0023] Furthermore, the Schottky base layer structure includes N + substrate layer and an N-type surface epitaxial layer, and the N + The substrate layer is disposed on a side of the Schottky base layer structure away from the super junction structure.

[0024] Furthermore, the N + There is also an N-type epitaxial layer between the substrate layer and the N-type surface epitaxial layer. + Buffer layer.

[0025] Furthermore, the N + The material of the substrate layer is phosphorus-doped silicon with a doping concentration of 5×10 19 ~1.0×10 20 cm -3 , thickness is 500~800μm.

[0026] Furthermore, the material of the N-type surface epitaxial layer is phosphorus-doped silicon with a doping concentration of 4.8×10 15 ~7.8×10 16 cm -3 , thickness is 2 to 10 μm.

[0027] Furthermore, the N + The buffer layer is made of phosphorus-doped silicon with a doping concentration of 1.04×10 16 ~3.53×10 17 cm -3 , thickness is 0.5~5μm.

[0028] Furthermore, the material of the Schottky barrier layer is selected from one or more of platinum, titanium and nickel-platinum alloy, and the thickness is 0.05-0.5 μm.

[0029] Furthermore, the material of the positive electrode metal layer is selected from one or more of titanium, nickel, aluminum and silver, and has a thickness of 4 to 8 μm.

[0030] Furthermore, the material of the negative electrode metal layer is selected from one or more of titanium, nickel, silver, gold, tin and copper, and the thickness is 0.5 to 4 μm.

[0031] The ultra-high density Resurf Schottky diode provided by the present invention is prepared by the above-mentioned preparation method.

[0032] The present invention also provides the application of the ultra-high density Resurf Schottky diode in an integrated circuit.

[0033] Beneficial effects:

[0034] The present invention provides a method for forming a super junction structure, in which a process step different from that of the existing trench etching-ion implantation technology is adopted. First, a mask layer is introduced on a substrate layer, and a hole structure is formed on the mask layer by etching, and multiple high-energy ion implantations and rapid annealing are performed on the mask layer of the hole structure, so that the process of forming a P column is split, and the formed super junction structure has a more uniform and smooth PN interface by multiple superimposed ion implantations, which effectively solves the contradiction between the doping aspect ratio, junction depth and lateral diffusion in the existing trench etching-ion implantation technology, and can be well applied to semiconductor devices with super junction structures such as ultra-high density Resurf Schottky structures, and has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the overall process of the method for preparing the ultra-high density Resurf Schottky diode provided in Example 1 of the present invention;

[0036] Figure 2 A schematic diagram of the P column forming process in step S3 of the method for preparing the ultra-high density Resurf Schottky diode provided in Example 1 of the present invention;

[0037] Figure 3 A schematic diagram of the structure of the ultra-high density Resurf Schottky diode provided in Example 1 of the present invention;

[0038] Figure 4 This is a schematic diagram of the structure of the ultra-high density Resurf Schottky diode provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0039] The method for forming a super junction structure provided by the present invention specifically includes: forming a mask layer with a hole structure on an N-type base layer; performing multiple P-column forming processes on the N-type base layer based on the mask layer to form P-columns to obtain the super junction structure.

[0040] In the present invention, the base layer structure is a type of semiconductor material commonly used in existing semiconductor devices. Those skilled in the art can make adaptive selections of the base layer structure and its material according to the super junction structure and the applied semiconductor device.

[0041] In the present invention, specific examples of the material of the mask layer include but are not limited to: silicon dioxide and / or silicon; and the thickness of the mask layer is preferably 2.0 to 3.0 μm, such as 2.0 μm, 2.2 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.9 μm, 3 μm or any value therebetween.

[0042] In the present invention, the diameter of the P column is preferably 0.1-3.0 μm, such as 0.1 μm, 0.2 μm, 0.4 μm, 0.8 μm, 1.2 μm, 1.6 μm, 2 μm, 2.5 μm, 3 μm or any value therebetween; the depth is preferably 1-10 μm, such as 1 μm, 1.8 μm, 2 μm, 2.6 μm, 3 μm, 3.5 μm, 4 μm, 4.9 μm, 5 μm, 8 um, 10 um or any value therebetween; there are multiple P columns, and the spacing between two adjacent P columns is 0.5-5 μm, such as 0.5 μm, 0.8 μm, 1.2 μm, 1.6 μm, 2 μm, 2.5 μm, 3 μm, 4 μm, 5 μm or any value therebetween.

[0043] In the present invention, the multiple P-column formation processes refer to the creative combination and arrangement of conventional technical means such as high-energy ion implantation and rapid thermal annealing as the basis, so as to split the P-column formation process and form a super junction structure with a more uniform and smooth PN interface through multiple superimposed ion implantations.

[0044] In the present invention, the multiple P-column forming processes specifically include: performing multiple high-energy ion implantation and rapid annealing processes alternately on the mask layer having the hole structure to form P-columns on the N-type base layer.

[0045] In the present invention, the shape of the pore structure is adaptively selected according to the desired shape of the P column, and specific examples thereof include but are not limited to: one or more of a circle, a triangle, a quadrilateral, a hexagon and an ellipse.

[0046] In the present invention, the high-energy ion implantation refers to accelerating high-energy ions and then implanting them into semiconductor materials to achieve doping of the semiconductor materials. It is a technology commonly used in the preparation of semiconductor devices.

[0047] In some specific embodiments, specific examples of ions implanted with high energy ions include, but are not limited to, one or more of aluminum ions, boron ions, and gallium ions.

[0048] In some specific embodiments, the conditions for high energy ion implantation include a temperature of preferably 50 to 3000 keV, such as 50 keV, 1000 keV, 1500 keV, 3000 keV or any value therebetween; an ion implantation dose of preferably 1×10 12 ~5×10 14 cm -2 , such as 1×10 12 cm -2 , 1.5×10 12 cm -2 , 2×1013 cm -2 , 8×10 13 cm -2 , 5×10 14 cm -2 or any value in between.

[0049] In the present invention, the rapid annealing process refers to a material processing process in which the material is quickly heated to about 700-1200°C and the annealing is completed within a few seconds to tens of seconds. Compared with conventional annealing processes, the rapid annealing process has a higher annealing temperature and an extremely short annealing time, which is conducive to the formation of a more uniform and smooth PN interface.

[0050] In some specific embodiments, the rapid annealing conditions include a temperature preferably of 800-1000°C, such as 800°C, 830°C, 850°C, 900°C, 1000°C or any value therebetween; and a time preferably of 5-120s, such as 5s, 10s, 25s, 50s, 60s, 120s or any value therebetween.

[0051] In the present invention, the number of the multiple P column forming treatments is specifically an integer not less than 2, such as 2, 3, 4, 5, 6, 7, 8 or other integers greater than these. In some specific embodiments, the number of the multiple P column forming treatments is preferably 2-10.

[0052] In the present invention, the number of multiple P column formation processes is more preferably 3; at this time, the multiple P column formation processes specifically include: (1) performing a first high-energy ion implantation and a first rapid annealing process on the mask layer to form a P column on the N-type base layer; (2) performing a second high-energy ion implantation and a second rapid annealing process on the mask layer to form a secondary P column on the base layer; (3) performing a third high-energy ion implantation and a third rapid annealing process on the mask layer to finally form the P column on the N-type base layer.

[0053] In some specific embodiments, the diameter of the pore structure is preferably 0.1-3 μm, such as 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.67 μm, 0.8 μm, 1 μm, 2 μm, 3 μm or any value therebetween.

[0054] In the present invention, in step (1), the etching process is a technical means commonly used in the preparation of existing semiconductor devices. Those skilled in the art can make adaptive choices according to actual needs, and the present invention does not impose any special limitation on it.

[0055] In the present invention, in steps (1) to (3), the first high-energy ion implantation, the second high-energy ion implantation and the third high-energy ion implantation are technical means conventionally used in the preparation of existing semiconductor devices. Those skilled in the art can make adaptive choices based on actual needs, and the present invention does not impose any special limitations on them.

[0056] In the present invention, in steps (1) to (3), in the first high-energy ion implantation, the second high-energy ion implantation and the third high-energy ion implantation, the implanted ions are P-type doping atoms, which is a technical means conventionally used in the preparation of existing semiconductor devices. Those skilled in the art can make adaptive choices based on actual needs. The present invention does not impose any particular limitation on it. Specific examples include but are not limited to: one or more of aluminum ions, boron ions and gallium ions.

[0057] In the present invention, in the first high-energy ion implantation, the second high-energy ion implantation and the third high-energy ion implantation, preferably the implantation energy is decreasing and the ion implantation dose is increasing, so that a super junction structure with a smooth PN interface can be formed better.

[0058] In some specific embodiments, the conditions of the first high-energy ion implantation include that the implantation energy is preferably 1000-3000 keV, such as 1000 keV, 1500 keV, 2000 keV, 3000 keV or any value therebetween; the implantation dose is preferably 1×10 12 ~1×10 13 cm -2 , such as 1×10 12 cm -2 , 1.5×10 12 cm -2 , 2×10 12 cm -2 , 3×10 12 cm -2 , 4×10 12 cm -2 , 5×10 12 cm -2 , 1×10 13 cm -2 or any value in between.

[0059] In some specific embodiments, the conditions for the second high-energy ion implantation include that the implantation energy is preferably 300-1000 keV, such as 300 keV, 350 keV, 400 keV, 500 keV, 700 keV, 800 keV, 900 keV, 1000 keV or any value therebetween; the implantation dose is preferably 5×10 12 ~5×10 13 cm-2 , such as 5×10 12 cm -2 , 6.3×10 12 cm -2 , 7.8×10 12 cm -2 , 1×10 13 cm -2 , 2.0×10 13 cm -2 , 3×10 13 cm -2 , 4×10 13 cm -2 , 5×10 13 cm -2 or any value in between.

[0060] In some specific embodiments, the conditions of the third high energy ion implantation include an implantation energy of 50 to 300 keV, such as 50 keV, 80 keV, 100 keV, 150 keV, 180 keV, 200 keV, 250 keV, 300 keV or any value therebetween; an implantation dose of 1×10 13 ~5×10 14 cm -2 , such as 1×10 13 cm -2 , 1.5×10 13 cm -2 , 1.8×10 13 cm -2 , 2×10 13 cm -2 , 2.7×10 13 cm -2 , 3.6×10 13 cm -2 , 5×10 13 cm -2 8.0×10 13 cm -2 , 1×10 14 cm -2 , 2×10 14 cm -2 , 5×10 14 cm -2 or any value in between.

[0061] In the present invention, in steps (1) to (3), the first annealing treatment, the second annealing treatment and the third rapid annealing treatment are conventionally used in the preparation of existing semiconductor devices. Those skilled in the art can make adaptive choices according to actual needs, and the present invention does not impose any special limitations on them.

[0062] Based on the above-mentioned method for forming a super junction structure, the present invention also provides a method for preparing an ultra-high density Resurf Schottky diode. In the preparation method, it specifically includes: obtaining a Schottky base layer structure; using the above-mentioned method for forming a super junction structure to form a super junction structure on the Schottky base layer structure; forming a Schottky barrier layer on the super junction structure; forming a positive metal layer on the Schottky barrier layer; forming a negative metal layer on the side of the Schottky base layer structure away from the super junction structure, and obtaining the ultra-high density Resurf Schottky diode.

[0063] In the present invention, the Schottky base layer structure specifically includes N + substrate layer and an N-type surface epitaxial layer, and the N + The substrate layer is disposed on a side of the Schottky base layer structure away from the super junction structure.

[0064] In the present invention, the N + The material of the substrate layer is a type of material commonly used in Schottky diodes. Those skilled in the art may make an adaptive selection according to actual needs, and the present invention does not impose any particular limitation thereon.

[0065] In some specific embodiments, the N + The material of the substrate layer is preferably phosphorus-doped silicon, and the doping concentration is preferably 5×10 19 ~1×10 20 cm -3 , such as 5×10 19 cm -3 , 5.3×10 19 cm -3 , 5.5×10 19 cm -3 , 5.8×10 19 cm -3 , 6×10 19 cm -3 , 6.5×10 19 cm -3 ,7×10 19 cm -3 , 7.5×10 19 cm -3 , 8×10 19 cm -3 , 1×10 20 cm -3 or any value in between.

[0066] In some specific embodiments, the N +The thickness of the substrate layer is preferably 500-800 μm, such as 500 μm, 600 μm, 700 μm, 800 μm or any value therebetween.

[0067] In the present invention, the material of the N-type surface epitaxial layer is a type of material commonly used in Schottky diodes. Those skilled in the art can make adaptive choices according to actual needs, and the present invention does not impose any special limitation on it.

[0068] In some specific embodiments, the material of the N-type surface epitaxial layer is preferably phosphorus-doped silicon, and the doping concentration is preferably 4.8×10 15 ~7.8×10 16 cm -3 ; such as 4.8×10 15 cm -3 , 8×10 15 cm -3 , 1×10 16 cm -3 , 2×10 16 cm -3 , 3×10 16 cm -3 , 5×10 16 cm -3 , 7.8×10 16 cm -3 or any value in between.

[0069] In some specific embodiments, the thickness of the N-type surface epitaxial layer is preferably 2-10 μm, such as 2 μm, 2.5 μm, 3 μm, 4 μm, 6 μm, 8 μm, 10 μm or any value therebetween.

[0070] In the present invention, the Schottky base layer structure preferably also includes N + buffer layer, and the N + The buffer layer is set on N + Between the substrate layer and the N-type surface epitaxial layer. + The material of the buffer layer is a type of material commonly used in Schottky diodes. Those skilled in the art may make an adaptive selection according to actual needs, and the present invention does not impose any particular limitation thereon.

[0071] In some specific embodiments, the N + The material of the buffer layer is preferably phosphorus-doped silicon, and the doping concentration is preferably 1.04×10 16 ~3.53×10 17 cm -3 , such as 1.04×10 16 cm -3 , 2×1016 cm -3 , 3×10 16 cm -3 , 5×10 16 cm -3 , 8×10 16 cm -3 ,9×10 16 cm -3 , 1×10 17 cm -3 , 2×10 17 cm -3 , 3.53×10 17 cm -3 or any value in between.

[0072] In some specific embodiments, the N + The thickness of the buffer layer is preferably 0.5-5 μm, such as 0.5 μm, 0.6 μm, 1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm, 5 μm or any value therebetween.

[0073] In the present invention, the method used for "obtaining a Schottky base layer structure" is a type of technical means conventionally used in the preparation of Schottky diodes. Those skilled in the art can make adaptive choices based on actual needs, and the present invention does not impose any particular limitation on it.

[0074] In the present invention, the material of the Schottky barrier layer is a type of material commonly used in Schottky diodes. Those skilled in the art can make adaptive choices according to actual needs. The present invention does not impose any special limitations on it. Specific examples include but are not limited to: one or more of platinum, titanium and nickel-platinum alloy. The thickness of the barrier layer is preferably 0.05 to 0.5 μm, such as 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.5 μm or any value therebetween.

[0075] In the present invention, the material of the positive electrode metal layer is a type of material commonly used in Schottky diodes. Those skilled in the art can make adaptive choices based on actual needs. The present invention does not impose any special limitations on it. Specific examples include but are not limited to: one or more of titanium, nickel, and silver.

[0076] In some specific embodiments, the thickness of the positive electrode metal layer is preferably 4-8 μm, such as 4 μm, 5 μm, 6 μm, 7 μm, 8 μm or any value therebetween.

[0077] In the present invention, the method of "forming a positive metal layer on the super junction structure" is a type of technical means conventionally used in the preparation of Schottky diodes. Those skilled in the art can make adaptive choices based on actual needs, and the present invention does not impose any special limitation on it.

[0078] In the present invention, the negative electrode metal material is a type of material commonly used in Schottky diodes. Those skilled in the art can make adaptive choices based on actual needs. The present invention does not impose any special limitations on it. Specific examples include but are not limited to: one or more of titanium, nickel, silver, gold, tin and copper.

[0079] In some specific embodiments, the thickness of the negative electrode metal layer is preferably 0.5-4 μm, such as 0.5 μm, 0.6 μm, 1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm or any value therebetween.

[0080] In the present invention, the method of "forming a negative metal layer on the side of the Schottky base layer structure away from the super junction structure" is a type of technical means conventionally used in the preparation of Schottky diodes. Those skilled in the art can make adaptive choices based on actual needs, and the present invention does not impose any special limitation on it.

[0081] Based on the preparation method of the ultra-high density Resurf Schottky diode, the present invention also provides an ultra-high density Resurf Schottky diode. The ultra-high density Resurf Schottky diode has both low conduction voltage drop and high reverse breakdown voltage, excellent performance, and good application prospects.

[0082] Based on the excellent performance of the ultra-high density Resurf Schottky diode, the present invention also provides the application of the ultra-high density Resurf Schottky diode in an integrated circuit.

[0083] Embodiments of the present invention are described in detail below, and the examples of the embodiments are intended to be used to explain the present invention, but should not be construed as limiting the present invention. In the embodiments, if specific techniques or conditions are not specified, the techniques or conditions described in the literature in this area or the product specifications are used. If the manufacturer is not specified for reagents or instruments used, they are all conventional products that can be obtained commercially.

[0084] Example 1

[0085] This embodiment is used to illustrate an ultra-high density Resurf Schottky diode and a method for manufacturing the same. Figure 1 and Figure 2 The preparation method of the ultra-high density Resurf Schottky diode specifically includes:

[0086] S1. (1) Chemical vapor deposition was performed at a temperature of 1150°C and a deposition rate of 5 μm / min in N + The corresponding raw materials are deposited on the substrate layer to form an N-type surface epitaxial layer, thereby obtaining a Schottky base layer structure.

[0087] Among them, N + The substrate layer is phosphorus-doped silicon with a thickness of 600 μm and a phosphorus doping concentration of 5×10 19 cm -3 ; The N-type surface epitaxial layer is phosphorus-doped silicon with a thickness of 4 μm and a phosphorus doping concentration of 1.5×10 16 cm -3 .

[0088] (2) Plasma enhanced chemical vapor deposition was used to deposit a SiO2 mask layer with a thickness of 2.5 μm on the surface of the N-type surface epitaxial layer under the conditions of a radio frequency power of 500 W, a temperature of 400° C. and a deposition rate of 1 μm / min.

[0089] (3) Photoresist is coated, exposed, developed, and dry-etched on the SiO2 mask layer to form a pore structure with a diameter of 0.8 μm, thereby obtaining a mask layer with a pore structure.

[0090] S2, (1) When the implantation energy is 1000 keV and the ion implantation dose is 1×10 12 cm 2 Under the conditions, the Schottky base layer structure within the pore structure is implanted with high-energy boron ions for the first time, and then rapidly thermally annealed to form a primary P column with a depth of 1.8 μm and a diameter of 1.0 μm.

[0091] (2) When the implantation energy is 500 keV and the dose is 5×10 12 cm 2 Under the conditions, a second high-energy boron ion implantation is performed on the Schottky base layer structure within the pore structure, and rapid thermal annealing is performed to form a secondary P column with a depth of 2.0 μm and a diameter of 1.1 μm.

[0092] (3) When the implantation energy is 60 keV and the dose is 1×10 14 cm 2 Under the conditions, the Schottky base layer structure within the hole structure is implanted with high-energy boron ions for the third time, and rapid thermal annealing is performed to finally form a P column with a depth of 2.1μm and a diameter of 1.2μm on the Schottky base layer structure, and the spacing between two adjacent P columns is 2μm, thereby obtaining a super junction structure.

[0093] The temperature of the rapid thermal annealing in steps (1) to (3) of step S2 is 900° C. and the time is 60 seconds.

[0094] S3, coating the SiO2 mask layer with photoresist, exposing, developing and dry etching to form a contact area; at a temperature of 700°C, a pressure of 0.5 Torr and a deposition rate of Under the condition of 300 Å / min, Ti was deposited in the contact area to form a barrier layer with a thickness of 0.05 μm.

[0095] S4, at a temperature of 200°C and a pressure of 1.0×10 -6 Under the conditions of 0.1737 Å and a sputtering rate of 2 μm / min, Al was sputtered on the barrier layer to form a positive electrode metal layer with a thickness of 5 μm.

[0096] S5, at a temperature of 150°C and a pressure of 1.0×10 -6 Torr, on the side of the N+ substrate layer away from the N-type surface epitaxial layer, the thickness is The Ti layer has a thickness of The Ni layer and thickness are The Ag layer, Ti layer, Ni layer and Ag layer together constitute the negative electrode metal layer.

[0097] The structure of the ultra-high density Resurf Schottky diode prepared by the preparation method provided above is as follows: Figure 3 shown.

[0098] Example 2

[0099] This embodiment adopts the method provided in embodiment 1 to prepare the ultra-high density Resurf Schottky diode, except that step S1 specifically includes: using chemical vapor deposition at a temperature of 1150° C. and a deposition rate of 5 μm / min to deposit a super-high density Resurf Schottky diode on N + The corresponding raw materials are deposited on the substrate layer in sequence to form N + Buffer layer and N-type surface epitaxial layer; wherein N + The substrate layer is phosphorus-doped silicon with a thickness of 600 μm and a phosphorus doping concentration of 5×10 19 cm -3 ; N + The buffer layer is phosphorus-doped silicon with a thickness of 2 μm and a phosphorus doping concentration of 7×10 16 cm -3 ; The N-type surface epitaxial layer is phosphorus-doped silicon with a thickness of 2 μm and a phosphorus doping concentration of 1.5×10 16 cm -3 ; Other conditions are the same, and an ultra-high density Resurf Schottky diode is obtained.

[0100] Figure 4The ultra-high density Resurf Schottky diode provided in this embodiment has a N + There is also an N-type epitaxial layer between the substrate layer and the N-type surface epitaxial layer. + Buffer layer.

[0101] Example 3

[0102] This embodiment adopts the method provided in Embodiment 1 to prepare the ultra-high density Resurf Schottky diode, except that in step S2, the implantation energy of the first high energy boron ion implantation, the second high energy boron ion implantation and the third high energy boron ion implantation are all 500 keV and the ion implantation dose is all 5×10 14 cm 2 ; Other conditions are the same, and an ultra-high density Resurf Schottky diode is obtained.

[0103] Example 4

[0104] This embodiment adopts the method provided in Embodiment 1 to prepare the ultra-high density Resurf Schottky diode, except that in step S2(1), the injection energy of the first high energy boron ion implantation is 1500 keV and the dose is 2×10 12 cm 2 In step S2(2), the second high energy boron ion implantation has an implantation energy of 800 keV and a dose of 4×10 13 cm 2 In step S2(3), the third high energy boron ion implantation has an implantation energy of 100 keV and a dose of 2×10 14 cm 2 ; Other conditions are the same, and an ultra-high density Resurf Schottky diode is obtained.

[0105] Example 5

[0106] This embodiment adopts the method provided in Embodiment 1 to prepare the ultra-high density Resurf Schottky diode, except that in step S2(1), the injection energy of the first high energy boron ion implantation is 2000 keV and the dose is 1×10 12 cm 2 In step S2(2), the second high energy boron ion implantation has an implantation energy of 500 keV and a dose of 1×10 13 cm 2 In step S2(3), the third high energy boron ion implantation has an implantation energy of 100 keV and a dose of 1×10 14 cm 2 ; Other conditions are the same, and an ultra-high density Resurf Schottky diode is obtained.

[0107] Test Case

[0108] This test example is used to illustrate the relevant performance of the ultra-high density Resurf Schottky diode prepared by the preparation method provided in the above embodiments and comparative examples. The reverse breakdown voltage and on-state voltage drop of the high-density Resurf Schottky diode are tested using the DTS-2000 test system. The results are shown in Table 1.

[0109] Table 1.

[0110] Group Reverse breakdown voltage (BV, V) Forward voltage drop (VF, V) Example 1 66 0.434 Example 2 68 0.438 Example 3 50 0.440 Example 4 69 0.442 Example 5 69 0.440

[0111] From the test results shown in Table 1, it can be seen that the reverse breakdown voltage of the high-density Resurf Schottky diode prepared by the method provided in Examples 1 to 5 of the present invention is above 50V, and the forward voltage drop is no more than 0.440V. It has both low on-state voltage drop and high reverse breakdown voltage, excellent performance, and good application prospects.

[0112] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention without departing from the principles and intent of the present invention.

Claims

1. A method for forming a super junction structure, characterized in that: The forming method comprises: forming a mask layer having a hole structure on the N-type base layer; Based on the mask layer, the N-type base layer is subjected to multiple P-column forming processes to form P-columns to obtain the super junction structure; The multiple P-column forming processes include: performing multiple high-energy ion implantation and rapid annealing processes alternately to form P-columns on the N-type base layer.

2. The method for forming a super junction structure according to claim 1, characterized in that: The material of the mask layer is silicon dioxide; optionally, the thickness of the mask layer is 2.0 to 3.0 μm; Optionally, the diameter of the P column is 0.1-3 μm, the depth is 1-10 μm, there are multiple P columns, and the distance between two adjacent P columns is 0.5-5 μm.

3. The method for forming a super junction structure according to claim 1, characterized in that: The number of the multiple P-pillar forming processes is an integer not less than 2.

4. The method for forming a super junction structure according to claim 1, characterized in that: The ions implanted by the high-energy ions are selected from one or more of aluminum ions, boron ions and gallium ions; Optionally, the high energy particle implantation has an implantation energy of 50 to 3000 keV and an ion implantation dose of 1×10 12 ~5×10 14 cm -2 ; Optionally, the rapid annealing treatment is performed at a temperature of 800 to 1000° C. and for a time of 5 to 120 seconds.

5. The method for forming a super junction structure according to claim 1, characterized in that: The number of times the multiple P-column formation treatments are performed is 3, specifically including: (1) performing a first high-energy ion implantation and a first rapid annealing treatment on the mask layer to form a primary P-column on the N-type base layer; (2) performing a second high-energy ion implantation and a second rapid annealing treatment on the mask layer to form a secondary P-column on the base layer; (3) performing a third high-energy ion implantation and a third rapid annealing treatment on the mask layer to finally form the P-column on the N-type base layer.

6. The method for forming a super junction structure according to claim 5, characterized in that: In the first high-energy ion implantation, the second high-energy ion implantation and the third high-energy ion implantation, the implantation energy shows a decreasing trend and the ion implantation dose shows an increasing trend; Optionally, the implantation energy of the first high-energy ion implantation is 1000-3000 keV, and the ion implantation dose is 1×10 12 ~1×10 13 cm -2 . Optionally, the second high energy ion implantation has an implantation energy of 300-1000 keV and an ion implantation dose of 5×10 12 ~5×10 13 cm -2 ; Optionally, the implantation energy of the third high energy ion implantation is 50-300 keV, and the ion implantation dose is 1×10 13 ~5×10 14 cm -2 .

7. A method for preparing an ultra-high density Resurf Schottky diode, characterized in that: The preparation method comprises: obtaining a Schottky base layer structure; forming a super junction structure on the Schottky base layer structure by using the super junction structure forming method described in any one of claims 1 to 6; forming a Schottky barrier layer on the super junction structure; forming a positive metal layer on the Schottky barrier layer; forming a negative metal layer on the side of the Schottky base layer structure away from the super junction structure, to obtain the ultra-high density Resurf Schottky diode.

8. The method for preparing the ultra-high density Resurf Schottky diode according to claim 7, characterized in that: The Schottky base layer structure includes N + substrate layer and an N-type surface epitaxial layer, and the N + The substrate layer is arranged on a side of the Schottky base layer structure away from the super junction structure; Optionally, the N + There is also an N-type epitaxial layer between the substrate layer and the N-type surface epitaxial layer. + Buffer layer; Optionally, the N + The material of the substrate layer is phosphorus-doped silicon with a doping concentration of 5×10 19 ~1×10 20 cm -3 , thickness is 500~800μm; Optionally, the material of the N-type surface epitaxial layer is phosphorus-doped silicon with a doping concentration of 4.8×10 15 ~7.8×10 16 cm -3 , thickness is 2 to 10 μm; Optionally, the N + The buffer layer is made of phosphorus-doped silicon with a doping concentration of 1.04×10 16 ~3.53×10 17 cm -3 , thickness is 0.5~5μm; Optionally, the material of the Schottky barrier layer is selected from one or more of platinum, titanium and nickel-platinum alloy, and has a thickness of 0.05 to 0.5 μm; Optionally, the material of the positive electrode metal layer is selected from one or more of titanium, nickel, aluminum and silver, and has a thickness of 4 to 8 μm; Optionally, the material of the negative electrode metal layer is selected from one or more of titanium, nickel, silver, gold, tin and copper, and the thickness is 0.5 to 4 μm.

9. An ultra-high density Resurf Schottky diode, characterized in that: The ultra-high density Resurf Schottky diode is prepared by the preparation method described in claim 7 or 8.

10. Application of the ultra-high density Resurf Schottky diode according to claim 9 in an integrated circuit.

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