Semiconductor device and method for face-up wafer level package using intendent

Abstract

The invention relates to a semiconductor device and a method of making a face-up wafer level package using intense pulsed light irradiation. The semiconductor device has a carrier. The electrical component is arranged on the carrier. An encapsulant is deposited over the electrical component. A conductive layer is formed on the encapsulant. A conductive layer is deposited as a plurality of graphene coated metal balls in a matrix. The conductive layer is sintered by intense pulsed light (IPL) irradiation.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device and method for making a face-up wafer level package using intense pulsed light irradiation. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, power conversion, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are constantly striving to make smaller semiconductor devices to meet the needs of electronic device manufacturers and consumers in a similar manner. As the density of components within semiconductor packages increases, the redistribution layer (RDL) used in semiconductor packages must have smaller spacing between conductors. Smaller spacing increases the vulnerability of the RDL to insulation failure, which may cause short circuits between adjacent conductive traces. A major problem causing short circuits is ion migration from one conductive trace, which may extend through adjacent insulating layers and eventually reach another conductive trace. Therefore, there is a need for semiconductor manufacturing methods and semiconductor devices that are less susceptible to ion migration. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1c Illustration of a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0005] Figure 2a-2q Illustrate a process of forming a semiconductor package having a graphene-based redistribution layer sintered by intense pulsed light irradiation;

[0006] Figure 3a and 3b Illustration of the use of a mask during intense pulsed light irradiation;

[0007] Figure 4a-4e Illustrate a multi-layer RDL embodiment;

[0008] Figure 5a-5c Illustrate a double thickness insulating layer embodiment; and

[0009] Figure 6a and 6b Diagram showing the integration of semiconductor packages into electronic devices. DETAILED DESCRIPTION

[0010] The present invention is described with reference to the figures in the following description in one or more embodiments, wherein like numbers represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purpose of the present invention, it will be understood by those skilled in the art that it is intended to cover alternatives, modifications and equivalents as supported by the following disclosure and the accompanying drawings, as may be included in the spirit and scope of the present invention as defined by the attached claims and their equivalents. The features shown in the figures are not necessarily drawn to scale. The elements assigned with the same reference numerals in the figures have functions similar to each other. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and a plurality of semiconductor devices.

[0011] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors create the relationship between voltage and current necessary to perform the circuit function.

[0012] Back-end manufacturing involves cutting or singulating the finished wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor die, the wafer is scored and broken along the non-functional area of ​​the wafer called the scribe street or scribe line. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor die is formed into a semiconductor package, which includes pins or contact solder joints for interconnection with other system components. Encapsulation or other molding materials are deposited above the semiconductor package to provide physical support and electrical isolation. The finished semiconductor package is then inserted into the electrical system and the functionality of the semiconductor device is made available to other system components. The contact solder joints formed on the semiconductor die are connected to the contact solder joints of the external electrical system through the semiconductor package and another electrical connection type. The electrical connection can be made with a conductive layer, a bump, a stud bump, a conductive paste, or a wire bond.

[0013] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100 in a manner separated by non-active inter-die wafer regions or scribe streets 106. The scribe streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0014] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, the active surface 110 containing analog or digital circuits, which are implemented as active devices, passive devices, conductive layers, and dielectric layers formed on or within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as digital signal processors (DSPs), application specific integrated circuits (ASICs), memories, power devices, or other signal processing circuits. The semiconductor die 104 may also include integrated passive devices (IPDs) such as inductors, capacitors, and resistors for performing RF signal processing.

[0015] Conductive layer 112 is formed on active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating or other suitable metal deposition processes. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 acts as a contact pad electrically connected to the circuit on active surface 110.

[0016] Conductive pillars 114 are formed on contact pads 112. Conductive pillars 114 can be formed of similar materials and using similar methods as taught for contact pads 112. In some embodiments, a photoresist layer is formed on active surface 110, and conductive pillars 114 are formed by depositing or sputtering conductive material into openings in the photoresist layer. In one embodiment, conductive pillars 114 are simply formed as part of conductive layer 112 by making the contact pads higher. In some embodiments, conductive pillars 114 are not formed, and the steps illustrated below occur directly on active surface 110 and contact pads 112 without the vertical offset provided by conductive pillars 114.

[0017] 1c, the semiconductor wafer 100 is singulated into individual semiconductor dies 104 through a dicing street 106 using a saw blade or a laser cutting tool 118. After singulation, the individual semiconductor dies 104 may be inspected and electrically tested for identifying known good dies (KGDs) or known good units (KGUs).

[0018] Figure 2a-2q Illustration of the process of forming a face-up wafer-level package using intense pulsed light irradiation. Figure 2a , the semiconductor die 104 is picked up and placed onto the adhesive carrier tape 120. In addition to or in place of the semiconductor die 104, any other electrical components may be arranged on the carrier tape 120. The semiconductor die 104 is arranged with the back side 108 arranged on the carrier tape 120. In other embodiments, another type of carrier, such as glass, polymer, or silicon, is used instead of the carrier tape 120. In some embodiments, a temporary bonding material, such as a heat or UV release adhesive, is used to adhere the semiconductor die 104 to the carrier tape 120 or an alternative carrier type. Although a single carrier tape 120 suitable for forming two semiconductor packages is shown, hundreds or thousands of units are typically manufactured and processed on a single carrier before being singulated from each other using the same steps described herein performed en masse.

[0019] In FIG. 2 b, an encapsulant or molding compound 124 is deposited over and around the carrier tape 120 and the semiconductor die 104 using slurry printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or another suitable applicator. Encapsulant 124 may be a liquid or granular polymer composite material such as epoxy resin, epoxy acrylate, or another suitable polymer with or without a suitable filler. Encapsulant 124 is non-conductive, provides structural support, and protects the semiconductor device from external elements and contaminants in the environment.

[0020] In some embodiments, the top surface of the conductive pillar 114 is exposed to or coplanar with the top surface of the encapsulant 124 using film assisted molding or another molding technique. Figure 2c As shown in FIG. 1 , a grinder 126 may be used to back grind the top surface of encapsulant 124 to remove a portion of the encapsulant and expose conductive pillars 114. In some embodiments, chemical mechanical planarization (CMP) is used. Figure 2d In either case, the results are shown where the top surface of the conductive pillar 114 is exposed to and coplanar with the surface of the encapsulant 124 .

[0021] exist Figure 2eIn the embodiment, an insulating layer 130 is formed over the package 124 and the semiconductor die 104. The insulating layer 130 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), FR-4, and other materials with similar insulating and structural properties. The insulating layer 130 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation.

[0022] exist Figure 2f 1 , openings 132 are formed through insulating layer 130 in the pattern of a redistribution layer (RDL), including conductive lines shaped to fan in or out of conductive pillars 114. Conductive pillars 114 are exposed within openings 132 to allow subsequent electrical interconnection to semiconductor die 104. Openings 132 are formed by chemical etching, laser ablation, or another suitable process.

[0023] exist Figure 2g , a conductive layer 156 is deposited on the insulating layer 130 by aerosol jet printing of a graphene-based conductive ink. In some embodiments, the conductive layer 156 is printed only within the RDL pattern of the opening 132. As shown, overlapping the opening 132 and completely covering the insulating layer 130 allows the use of other deposition techniques that require less precision. The conductive layer 156 physically and electrically contacts the conductive pillars 114 through the opening 132.

[0024] Figure 2h Detail of one of the graphene coated metal balls 158 of the conductive layer 156 is illustrated. The graphene coated metal ball 158 is formed of a core 160 and a graphene shell or coating 162 formed on and around the core. In one embodiment, the core 160 is Cu, Ag, Ni, a phase change material (PCM), or other suitable metal or similar material. In some embodiments, a mixture of some Cu cores 160 and some Ag cores 160 is used. Figure 2h The details of the graphene shell 162 are illustrated, and the graphene shell 162 is formed as a mesh network around the core 160. The graphene shell 162 is an allotrope of carbon having one or more layers of carbon atoms, and the carbon atoms are arranged in a two-dimensional (2D) honeycomb lattice. The graphene shell 162 can be formed by CVD, wet chemical synthesis or other suitable means. In some embodiments, a plurality of graphene coatings 162 are formed on each core 160.

[0025] For CVD, the core 160 is placed in a chamber heated to 900-1080° C. A gas mixture of CH4 / H2 / Ar is introduced into the chamber to initiate the CVD reaction. When the CVD reaction separates the carbon atoms from the hydrogen atoms, the carbon source decomposes in the high temperature reaction chamber, leaving a graphene shell 162 on the core 160. The release of carbon atoms on the core 160 forms a continuous sheet of graphene shell 162. Additional information related to the formation of the graphene coating 162 is disclosed in U.S. Patent No. 8,535,553, U.S. Patent No. 10,421,123, Korean Patent No. KR101465616, and Korean Patent No. KR101895114, all of which are incorporated herein by reference.

[0026] Figure 2i Further details of the conductive layer 156 formed by a plurality of graphene-coated metal balls 158 are shown. In one embodiment, the conductive layer 156 includes a matrix 164 and a plurality of cores 160 having a graphene coating 162 embedded in the matrix. In one embodiment, the matrix 164 is a thermosetting material, such as an epoxy resin or an adhesive, which has a binder and a filler, and the filler contains aluminum oxide, Al, aluminum zinc oxide or other materials with good conductive properties. The matrix 164 can be a thermally conductive paste, such as silicon or a polymer type, for example, polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET). In other embodiments, the matrix 164 can be an epoxy resin, polyester or acrylic resin. In another embodiment, the matrix 164 is a polymer or composite epoxy resin, which has dispersed graphene, carbon nanotubes, conductive polymers, etc. The conductive layer 156 can be applied as an ink of graphene-coated metal balls 158 floating in the matrix 164.

[0027] Each core 160 as embedded in the matrix 164 is surrounded or covered by a graphene coating or shell 162. In one embodiment, the graphene shell 162 is a graphene slurry or ink formed around a Cu or Ag core. In one embodiment, some cores 162 are formed of Cu and other cores are formed of Ag. The graphene coating 162 of each core 160 contacts the graphene coating of one or more adjacent cores. The cores 160 have sufficient density within the matrix 164 so that most (if not all) of the graphene coatings around the core contact at least one graphene coating around an adjacent core, and typically contact the graphene coatings of multiple adjacent cores.

[0028] Each graphene-coated metal sphere 158 physically contacts an adjacent graphene-coated metal sphere within the matrix 164 to create a conductive path 178 that includes portions of the interconnected graphene shells 162 on adjacent spheres 158. Conductive paths 178 are the primary current carriers for the conductive wiring of the conductive layer 156. Charge flowing through numerous conductive paths like 178 in the spheres 158 acts to carry electrical signals across the substrate 120.

[0029] To ensure that conductive paths 178 are established between all adjacent balls 158, the conductive layer 156 is sintered, such as Figure 2j 15. The sintering is performed using an IPL apparatus 180. The IPL apparatus 180 includes a xenon flash lamp 182 that emits light rays 184. A reflector 186 reflects the light rays 184 to increase the amount of light emitted downward toward the conductive layer 156. An optional ultraviolet filter 188 filters the light rays 184. A platform 189 holds the device being processed.

[0030] IPL uses intense pulses of incoherent light emitted over a range of wavelengths. In one embodiment, the IPL wavelength extends from about 350 nanometers (nm) to 1200 nm. In other embodiments, the lower end of the wavelength spectrum is 400 nm. A xenon flash lamp 182 produces a high output burst of broad spectrum light 184. The light 184 that strikes the matrix 164 with the balls 158 sinters the conductive layer 156 to solidify the material and the electrical connections between the balls. Sintering the conductive layer 156 using IPL irradiation can be completed between a few milliseconds and a few seconds, while conventional conductive layers in the prior art require a thermal heating process that typically takes between 30 and 90 minutes. Compared to UV light, IPL has a higher peak power output and a shorter pulse duration, which enables more energy to be delivered in a shorter time than UV light typically used in the prior art.

[0031] In some embodiments, before IPL irradiation, the panel of the device having the conductive layer 156 is placed in a furnace for pretreatment. The furnace temperature is set between 170°C and 280°C, and the conductive layer 156 is heated between 30 seconds and two minutes. In one embodiment, the conductive layer 156 is heated at 250°C for one minute. The furnace pretreatment removes the organic solvent from the conductive layer 156. In some embodiments, the panel is placed in a furnace for post-treatment after IPL irradiation. The furnace temperature for post-treatment is between 90°C and 120°C for a time length of between five and ten minutes. Post-treatment in the furnace stabilizes the sintered material.

[0032] Forming the conductive layer 156 by sintering through IPL irradiation increases the number of units that can be manufactured per hour (UPH), thereby reducing manufacturing costs. In addition, graphene has ten times the conductivity of copper or silver itself, so the conductive layer 156 has an increased current carrying capacity compared to the prior art. The graphene coating 162 increases the thermal conductivity and hardness of the conductive layer 156. The graphene coating 162 also reduces metal oxidation and ion migration, thereby increasing the mean time between failures.

[0033] exist Figure 2k In the embodiment, the conductive layer 156 is back ground using a grinder 190 or another suitable device to remove the portion of the conductive layer that extends outside the opening 132 and extends onto the top surface of the insulating layer 130. In some embodiments, CMP is used. The remaining portion of the conductive layer 156 is completely within the RDL pattern of the opening 132 and matches the RDL pattern. After back grinding, the individual conductive lines of the conductive layer 156 are physically and electrically separated from each other to allow the conductive layer to function as a fan-out or fan-in interconnect structure. In embodiments where the conductive layer 156 is printed only within the opening 132, back grinding is not required. Figure 2l Conductive layer 156 is shown after back grinding or after IPL if back grinding is not necessary.

[0034] exist Figure 2m Insulating layer 192 is formed over insulating layer 130 and conductive layer 156 as described above for insulating layer 130. Figure 2n As described above for openings 132, openings 194 are formed through insulating layer 192. Openings 194 are formed as vias at ends of conductive traces of conductive layer 156 opposite conductive pillars 114, rather than forming RDL patterns as in the case of openings 132.

[0035] exist Figure 2o In the embodiment of the present invention, the conductive bump material is deposited in the opening 194 above the conductive layer 156 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder and combinations thereof, together with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is optionally bonded to the conductive layer 156 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form a ball or bump 196 by heating the material above its melting point.

[0036] Unlike copper and other common metal conductive lines, the conductive layer 156 formed with graphene coated metal balls 158 has good solder wettability, so that the bump 196 can be formed directly on the conductive layer 156. In other embodiments, the bump 196 is formed above the under-bump metallization (UBM) with a wetting layer, a barrier layer, and an adhesion layer. The bump 196 can also be compression bonded or thermocompressed to the conductive layer 156. The bump 156 represents a type of interconnect structure that can be formed on the conductive layer 156. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps, or other electrical interconnects. The conductive layer 156 provides fan-in or fan-out interconnects from the conductive pillars 114 to the bumps 196.

[0037] exist Figure 2p In the embodiment, the panel is singulated between units using a saw blade or laser cutting tool 198 to separate the panel into individual semiconductor packages 200. The semiconductor packages 200 are picked up and placed from the carrier tape 120 to produce the following: Figure 2q In some embodiments, the carrier tape 120 is singulated together with the package 200 and remains on the package 200 as a protective layer on the back side 108 of the semiconductor die 104 .

[0038] The semiconductor package 200 is a face-up wafer level package having a conductive layer 156 that functions as a redistribution layer sintered by IPL irradiation. The contact pads 112 of the semiconductor die 104 are electrically coupled to the solder bumps 196 through the conductive layer 156. The conductive layer 156 is formed of graphene-coated conductive balls 158. The graphene coating 162 increases electrical and thermal conductivity, hardness, and oxidation stability, and reduces the amount of ion migration that will occur during the life of the semiconductor package 200. Compared to the prior art, IPL irradiation of the conductive layer 156 increases the units that can be manufactured per hour (UPH) by reducing the time required for each unit.

[0039] Continue Figure 2g , Figure 3a and 3bThe illustration uses a mask 210 for IPL irradiation. The mask 210 includes an opening 212 that is aligned with the opening 132 of the insulating layer 130 and is arranged directly above the opening 132. The opening 212 in the mask 210 forms an RDL pattern that matches the RDL pattern of the opening 132 in the insulating layer 130. The opening 212 is the same or substantially the same size and shape as the opening 132. Light rays 184 from the IPL device 180 pass through the opening 212 to hit the portion of the conductive layer 156 within the opening 132. The light rays 184 in other areas hit the mask 210 instead of the conductive layer 156, thereby preventing the conductive layer from hardening outside the opening 132. Undesirable portions of the conductive layer 156 can be removed more easily because the desired portions are not sintered by the IPL irradiation. Figure 3b It is shown that undesirable portions of the conductive layer 156, ie, portions of the conductive layer outside of the opening 132, have been removed. Figure 2m-2q Any of the above or below described embodiments may have IPL irradiation performed with or without the mask 210 .

[0040] Figure 4a-4e An embodiment is illustrated in which the insulating layer 130 is replaced by a pair of insulating layers 220 and 222 . Figure 4a Insulating layers 220 and 222 are shown formed over encapsulation 124 and semiconductor die 104. Each individual insulating layer 220 and 222 is formed in a similar manner and from similar materials as described above for insulating layer 130. Insulating layer 220 is formed first, and insulating layer 222 is then formed on insulating layer 220.

[0041] exist Figure 4b , an opening 224 is formed through the insulating layer 220, and an opening 226 is formed through the insulating layer 222. The openings 224 and 226 are formed by chemical etching, laser ablation, or other suitable processes. In one embodiment, a first etching process forms the opening 226, and then a second etching process forms the opening 224 within the opening 226. The opening 224 forms a through hole to expose the conductive column 114. Each opening 224 has a component package (footprint) size and shape that is substantially the same as the corresponding conductive column 114. The opening 226 is formed in an RDL pattern similar to the opening 132, including a conductive line that fans in or out of the conductive column 114.

[0042] Conductive layer 230 is formed over insulating layers 220 and 222 and extends to Figure 4cThe conductive layer 230 is formed of the graphene-coated metal balls 158, as in the case of the conductive layer 156 above. The conductive layer 230 is subjected to IPL sintering with or without the mask 210, and then any portion of the conductive layer 230 above the top surface of the insulating layer 222 is removed, as shown in FIG. Figure 4d The package 236 is completed by forming the insulating layer 192 and the solder bumps 196, and then singulating, as shown in FIG. Figure 4e as shown in .

[0043] Figure 5a-5c A similar embodiment is shown in which a double thick insulating layer 240 is formed in place of insulating layer 130. Openings 224 and 226 are as shown in FIG. Figure 4b 2, but through a single insulating layer 240 instead of the dual insulating layers 220-222. Conductive layer 230 is formed as described above. Insulating layer 192 and solder bumps 196 are formed, followed by singulation to complete semiconductor package 246, as shown in FIG. Figure 5c as shown in .

[0044] Figure 6a and 6b The above-described semiconductor package, such as semiconductor package 200 , is illustrated as being integrated into a larger electronic device 300 . Figure 6a A partial cross-section of a semiconductor package 200 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300 is illustrated. Bumps 196 are reflowed onto a conductive layer 304 of the PCB 302 to physically attach and electrically connect the semiconductor package 200 to the PCB. In other embodiments, heat pressing or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 200 and the PCB 302. The semiconductor die 104 is electrically coupled to the conductive layer 304 via the bumps 196 and the conductive layer 156.

[0045] Figure 6b An electronic device 300 is illustrated having a chip carrier substrate or PCB 302 with multiple semiconductor packages, including semiconductor package 200, arranged on a surface of PCB 302. Depending on the application, electronic device 300 may have one type of semiconductor package, or multiple types of semiconductor packages.

[0046] The electronic device 300 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 may be a subcomponent of a larger system. For example, the electronic device 300 may be a part of a tablet computer, a mobile phone, a digital camera, a communication system, or other electronic device. Alternatively, the electronic device 300 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are very important for products to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density. The PCB 302 may have a more irregular shape to facilitate a more ergonomic and smaller device housing.

[0047] exist Figure 6b , PCB 302 provides a general substrate for structural support and electrical interconnection of semiconductor packages arranged on the PCB. Conductive signal lines 304 are formed on the surface of PCB 302 or within the layers of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal lines 304 provide electrical communication between each of the semiconductor packages, mounted components and other external system components. Lines 304 also provide power and ground connections to each of the semiconductor packages.

[0048] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first level packaging, where the die is mechanically and electrically arranged directly on the PCB.

[0049] For illustration purposes, several types of first level packages are shown on PCB 302, including a wire bond package 346 and a flip chip 348. Additionally, several types of second level packages are shown arranged on PCB 302, including a ball grid array (BGA) 350, a bump chip carrier (BCC) 352, a land grid array (LGA) 356, a multi-chip module (MCM) or SIP module 358, a quad flat non-leaded package (QFN) 360, a quad flat package 362, and an embedded wafer level ball grid array (eWLB) 364. In one embodiment, eWLB 364 is a fan-out wafer level package (Fo-WLP) or a fan-in wafer level package (Fi-WLP).

[0050] Depending on the system requirements, any combination of semiconductor packages configured with first and second level packaging styles and other electrical components can be connected to the PCB 302. In some embodiments, the electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to malfunction and is less expensive to manufacture resulting in lower costs for consumers.

[0051] While one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will appreciate that modifications and adaptations may be made to the embodiments without departing from the scope of the present invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Provide a carrier; arranging electrical components on the carrier; depositing an encapsulant over the electrical component; forming a conductive layer on the encapsulant, wherein the conductive layer is deposited as a plurality of graphene-coated metal spheres in a matrix; and The conductive layer is sintered by intense pulsed light (IPL) irradiation. 2 . The method of claim 1 , wherein the plurality of graphene-coated metal balls include a plurality of cores formed of copper or silver, and each of the plurality of cores includes a graphene coating.

3. The method according to claim 1, further comprising: forming a first insulating layer on the package; etching an RDL pattern into the first insulating layer; as well as The conductive layer is formed with the RDL pattern.

4. The method according to claim 3, further comprising: forming a second insulating layer on the conductive layer; forming an opening through the second insulating layer to expose the conductive layer; as well as Solder bumps are formed in the openings on the conductive layer.

5. The method according to claim 3, further comprising: forming a second insulating layer between the encapsulant and the first insulating layer; forming a through hole in the second insulating layer; as well as The RDL pattern is formed over the through hole. 6 . The method of claim 3 , further comprising forming a via in the first insulating layer under the RDL pattern.

7. A method for manufacturing a semiconductor device, the method comprising: Supply of electrical components; depositing an encapsulant over the electrical component; forming a conductive layer on the package; as well as The conductive layer is sintered by intense pulsed light (IPL) irradiation.

8. The method of claim 7, further comprising disposing a mask over the encapsulation during sintering.

9. The method of claim 7, wherein the conductive layer comprises a plurality of graphene-coated metal balls.

10. A semiconductor device, comprising: Electrical components; an encapsulant deposited over the electrical component; A conductive layer is formed on the package, wherein the conductive layer includes a plurality of graphene-coated metal balls. The semiconductor device according to claim 10 , further comprising a mask arranged over the encapsulation.

12. The semiconductor device according to claim 10, further comprising: a first insulating layer disposed on the package; as well as An RDL pattern is etched into the first insulating layer, wherein the conductive layer is arranged in the RDL pattern.

13. The semiconductor device according to claim 12, further comprising: a second insulating layer formed on the conductive layer; an opening formed through the second insulating layer to expose the conductive layer; as well as Solder bumps are formed in the openings on the conductive layer.

14. The semiconductor device according to claim 12, further comprising: a second insulating layer formed between the encapsulant and the first insulating layer; as well as A via is formed in the second insulating layer under the RDL pattern. 15 . The semiconductor device of claim 12 , further comprising a via formed in the first insulating layer under the RDL pattern.

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