Integrated circuit element for circuit probe testing and manufacturing method thereof

Abstract

Some embodiments relate to a circuit probe testing method for an integrated circuit structure having a conductive structure. The method includes providing an integrated circuit structure including a substrate, a dielectric structure disposed over the substrate, and a plurality of electrodes disposed over an upper surface of the dielectric structure. The method further includes forming a first dielectric layer over the dielectric structure and the plurality of electrodes, etching the first dielectric layer over each of the plurality of electrodes, forming a conductive layer over the first dielectric layer and the plurality of electrodes, and removing at least a portion of the conductive layer to form a plurality of conductive structures over the plurality of electrodes. Each of the plurality of conductive structures contacts a corresponding subset of the plurality of electrodes.

Description

Technical Field

[0001] The embodiment of the present invention relates to an integrated circuit element for circuit probe testing and a manufacturing method thereof. Background Art

[0002] Continuous advancements in integrated circuit (IC) technology have resulted in continued increases in the functionality and capacity of related IC components. This advancement has increased the importance of accurate and non-destructive IC testing that can be performed at both the wafer level and the individual component level. One form of IC testing is circuit probe (CP) testing, during which various types of functional, voltage, and / or current tests can be performed. Thus, IC manufacturers can employ CP testing to determine whether the IC under test meets customer expectations. Summary of the invention

[0003] An embodiment of the present invention provides a method for manufacturing an integrated circuit element, including: providing an integrated circuit structure including: a substrate; a dielectric structure disposed on the substrate, the dielectric structure including an upper surface; and a plurality of electrodes disposed on the upper surface of the dielectric structure; forming a first dielectric layer on the dielectric structure and the plurality of electrodes; etching the first dielectric layer on each of the plurality of electrodes; forming a conductive layer on the first dielectric layer and the plurality of electrodes; removing at least a portion of the conductive layer to form a plurality of conductive structures on the plurality of electrodes, each of the plurality of conductive structures contacting a corresponding subset of the plurality of electrodes; and performing a circuit probe test on the integrated circuit structure through the plurality of conductive structures.

[0004] An embodiment of the present invention provides a method for manufacturing an integrated circuit element, comprising: providing an integrated circuit structure, comprising: a substrate; a dielectric structure disposed on the substrate, the dielectric structure comprising an upper surface and including a conductive interconnection structure; and a plurality of electrodes disposed on the upper surface of the dielectric structure, wherein at least one of the substrate and the dielectric structure comprises at least one electronic circuit coupled to the plurality of electrodes through the conductive interconnection structure; forming a first protective film on the dielectric structure and the plurality of electrodes; forming a first dielectric layer on the first protective film; etching the first dielectric layer and the first protective film on each of the plurality of electrodes; forming a conductive layer on the first dielectric layer and the plurality of electrodes; removing at least a portion of the conductive layer to form a plurality of conductive structures on the plurality of electrodes, each of the plurality of conductive structures contacting a corresponding subset of the plurality of electrodes; and reducing the thickness of the substrate after forming the first dielectric layer.

[0005] An embodiment of the present invention provides an integrated circuit structure comprising: a substrate; a dielectric structure disposed on the substrate, the dielectric structure comprising an upper surface; a plurality of electrodes disposed on the upper surface of the dielectric structure; and a protective layer disposed on and in contact with the plurality of electrodes and the upper surface of the dielectric structure, wherein a first thickness of the protective layer on a central portion of each of the plurality of electrodes is less than a second thickness of the protective layer on the upper surface of the dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A Cross-sectional views of some embodiments of IC components using conductive structures for CP testing according to the present disclosure are shown.

[0008] Figure 1B Plan views of some embodiments of IC components using conductive structures for CP testing according to the present disclosure are shown.

[0009] Figure 2A-2I Cross-sectional views of some embodiments of semiconductor structures for IC components using conductive structures for CP testing at various stages of fabrication are shown.

[0010] Figure 3 A method of forming an IC component using a conductive structure for CP testing according to some embodiments is shown.

[0011] Figure 4A and Figure 4B The cross-sectional views of some embodiments of semiconductor structures for IC components are shown respectively. Figure 2E and Fig.2I The corresponding specific manufacturing stages employ thinned substrates and conductive structures for CP testing.

[0012] Figure 5A-5G Cross-sectional views of some embodiments of semiconductor structures for IC devices employing thinned substrates and conductive structures for CP testing at various stages of fabrication are shown.

[0013] Figure 6 Some embodiments of semiconductor structures for IC components are shown in cross-sectional views. Figure 2F The corresponding manufacturing stage uses a thinned substrate and a conductive structure for CP testing.

[0014] Figure 7 Methods of forming IC components using thinned substrates and conductive structures for CP testing are shown in accordance with some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides a plurality of different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to limit the present disclosure. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly in contact with each other, or an embodiment in which an additional feature is formed between the first feature and the second feature so that the first and second features are not in direct contact. In addition, the present disclosure may repeat component symbols and / or letters in different embodiments. Such repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations.

[0016] In addition, for ease of description, the present disclosure may use spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. to describe the relationship between one component or feature and another component or features. In addition to the orientation shown in the drawings, spatially relative terms are also intended to cover different orientations of components in use or operation. Components can be oriented in other orientations (rotated 90 degrees or other orientations), and the spatially relative terms used in the present disclosure can also be interpreted accordingly.

[0017] As the trend toward smaller IC features continues, the corresponding size and / or thickness of accessible metal structures, such as electrodes (e.g., electrodes of display panel pixels that may be implemented in a microactuator dielet) tend to decrease in a corresponding manner. While this trend increases the capacity and functionality of related IC technologies, it may also impact the ability to test the resulting ICs, such as by circuit probe (CP) testing that may be performed at the wafer level. For example, by reducing the size and thickness of electrodes, direct hardware probing of the electrodes (e.g., by a probe card) may need to be more precise and less aggressive than is currently possible in order to achieve accurate testing without damaging the electrodes.

[0018] To address these problems, the present disclosure provides some embodiments of IC components including conductive structures for CP testing. In some embodiments, a dielectric layer disposed on a plurality of electrodes is patterned to expose the electrodes. A plurality of conductive structures are disposed on the dielectric layer and the electrodes. Each conductive structure can contact a subset of electrodes. In some embodiments, each conductive structure can be used as a CP bonding pad for receiving a test probe to electrically interact with a subset of electrodes in contact with the conductive structure. Moreover, in some embodiments, a subset of electrodes can be arranged as a two-dimensional electrode array below the corresponding conductive structure.

[0019] Thus, the use of some embodiments of the conductive structure can provide a wider, stronger access point through which the CP test system can make an electrical connection to the electrodes of the IC component. In some embodiments, the conductive structure and associated dielectric layer can be removed after CP testing to facilitate functional access to the electrodes, including additional IC layers or structures, etc.

[0020] Figure 1A 1 shows a cross-sectional view of some embodiments of an IC component 100 using a conductive structure 114 for CP testing according to the present disclosure. As described in more detail below, in some embodiments, Figure 1A The IC element 100 shown in FIG. 1 is in a state where CP testing can be performed on it and may include materials that are not ultimately retained in the functional element. The IC element 100 may include a substrate 102 and a dielectric structure 104 disposed on the substrate 102. In some embodiments, the dielectric structure 104 may include a conductive structure 106 (e.g., a conductive layer 107, a conductive interconnect contact and / or a through hole, etc.) that couples the electronic circuit 103 to at least one corresponding electrode 108 of a plurality of electrodes 108 disposed on an upper surface of the dielectric structure 104.

[0021] In some embodiments, electronic circuit 103 may be a panel display micro-driver for a sub-pixel associated with a corresponding electrode 108. For example, the voltage potential of electrode 108 may cause the sub-pixel to exhibit a particular brightness. To provide the sub-pixels of IC device 100, one or more additional layers and / or structures (e.g., a liquid crystal (LC) layer, a color filter, a common electrode, etc.) may be formed on electrode 108.

[0022] Each electronic circuit 103 has Figure 1A 103 are depicted as general functional blocks because the electronic circuit 103 can take a variety of different forms (e.g., one or more transistors such as metal oxide semiconductor field effect transistors (MOSFETs), thin film transistors (TFTs), one or more capacitors and / or other components in various configurations).

[0023] In some embodiments, first protective film 110 may be disposed over each electrode 108 and over a portion of the upper surface of dielectric structure 104 between electrodes 108. In some embodiments, first protective film 110 may provide some degree of protection for underlying portions of IC element 100 during subsequent IC processing operations.

[0024] In some examples, each electrode 108 may be very small (e.g., less than 10 μm in width), making direct probing difficult. Therefore, in some embodiments, to facilitate CP testing, a first dielectric layer 112 may be formed over the first protective film 110. Thereafter, a portion of the first dielectric layer 112 and a portion of the first protective film 110 located over the electrode 108 may be removed. Subsequently, a plurality of conductive structures 114 may be formed over the electrode 108 and the first dielectric layer 112 to serve as CP landing pads. In some embodiments, each conductive structure 114 may contact and substantially cover a subset of the plurality of electrodes 108 to facilitate testing of each associated electronic circuit 103 coupled to the subset of electrodes 108. Each conductive structure 114 may be formed over the first dielectric layer 112 to provide a CP landing pad. Figure 1A 108 is depicted as having a sufficient length to contact three electrodes 108 located below the conductive structure 114. Additionally, in some embodiments, each conductive structure 114 includes a landing portion 116 and a plurality of conductive pillars 118. In some embodiments, each conductive pillar 118 extends downward through the first dielectric layer 112 to contact a corresponding one of the subset of electrodes 108 associated with the conductive structure 114. Additionally, in some embodiments, the width of each conductive pillar 118 may be less than or equal to the width of the corresponding one of the subset of electrodes 108.

[0025] Figure 1B FIG. 1 shows a plan view of some embodiments of an IC component 100 that uses a conductive structure 114 for CP testing according to the present disclosure. Figure 1B As shown, in some embodiments, each conductive structure 114 is substantially rectangular (eg, square) in shape and has sufficient size to cover three electrodes 108 in two lateral dimensions. Figure 1A and Figure 1B , each conductive structure 114 can contact nine electrodes 108. In addition, each conductive structure 114 can be much larger in plan view than each associated electrode 108 to which it is coupled, thereby advantageously providing a larger and more stable landing surface for the CP probe than the electrode 108 itself, while also providing a protective layer for the electrode 108 during CP testing. For example, in some embodiments (e.g., where the minimum length and width of the conductive structure 114 required for compatibility with the CP probe is approximately 40 micrometers (μm)), as shown in FIG. Figure 1B As shown, a three row and three column arrangement of electrodes 108 for a single conductive structure 114 may be considered a minimum size, while other larger arrangements (e.g., three by four, four by three, four by four, four by five, five by four, five by five, etc.) are also acceptable in this embodiment.

[0026] Although in Figure 1A and Figure 1BIn the embodiment of FIG. 1 , each conductive structure 114 contacts nine electrodes 108, but in other embodiments, each conductive structure 114 may be sized to contact any number of two or more electrodes 108. Additionally, the conductive structures 114 may have shapes other than square or rectangular in plan view.

[0027] Figure 2A-2I Some embodiments of semiconductor structures for IC components using conductive structures for CP testing at various stages of manufacturing are shown in cross-sectional views. Figure 2A-2I Described as a series of actions, it should be understood that these actions are not restrictive, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0028] Figure 2A A semiconductor structure is shown that can represent a partially constructed IC component 200 that can be used as a base structure on which processes such as Figure 2B-Figure 2I Additional processing actions as shown. In some embodiments, as described above, IC component 200 includes substrate 102 (e.g., a silicon substrate) and dielectric structure 104 (e.g., one or more layers of dielectric material, such as silicon dioxide (SiO2)) disposed on substrate 102. A plurality of electrodes 108 are disposed on an upper surface of dielectric structure 104. Electrodes 108 may include metal (e.g., aluminum, gold, titanium, ruthenium, iridium, rhodium, molybdenum, copper, or some other metal, or alloys thereof) and / or another conductive material. In some embodiments, each electrode 108 may be coupled to a corresponding electronic (e.g., micro-actuator) circuit 103 via an associated conductive structure 106, which may include one or more conductive layers 107 and associated interconnecting contacts, through-holes, etc.

[0029] In some embodiments, the first protective film 110 may be disposed over the electrode 108 and the exposed portion of the dielectric structure 104. In some embodiments, the first protective film 110 may include tantalum, a tantalum compound, or another material that can protect the IC device 200 from mechanical and / or electrical damage. In addition, in some embodiments, the first protective film 110 can be formed on the electrode 108 and the dielectric structure 104 by atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. In some embodiments, when the IC device 100 is transferred from one location to another during the manufacturing process, the first protective film 110 can provide a certain degree of protection for the electrode 108 and other portions of the IC device 100. Additionally or alternatively, in some embodiments, the first protective film 110 can act as a barrier to protect portions of the underlying structure from subsequent IC processing operations. Furthermore, in some embodiments, such as Figure 2A The IC component 200 is shown in a state where additional processing operations may be performed thereon, such as forming additional functional layers above the electrode 108 and the dielectric structure 104. Figure 2B-Figure 2I As shown, subsequent operations described below are performed to provide a conductive structure that facilitates CP testing of the electronic circuit 103 through the electrode 108.

[0030] Figure 2B A first dielectric layer 112 (eg, SiO 2) is shown formed (eg, deposited) over the electrode 108 and the exposed portion of the dielectric structure 104. x In some embodiments, the first dielectric layer 112 may be used as a layer on which the conductive structure 114 will be formed.

[0031] Figure 2C The patterning (e.g., etching using photolithography or other processes) of a portion 202 of the first dielectric layer 112 and the first protective film 110 covering at least some of each electrode 108 is shown. In some embodiments, in a plan view, a central portion of each electrode 108 may be exposed while leaving a peripheral portion of the electrode 108 covered by the first dielectric layer 112 and / or the first protective film 110. In some embodiments, the removed portion 202 or size of the first dielectric layer 112 may be designed to facilitate the formation of vias for subsequent redistribution layers of IC components.

[0032] Figure 2D The formation (e.g., deposition) of a conductive layer 204 including a conductive material (e.g., a metal such as aluminum, gold, tin, copper, and / or alloys thereof, or another conductive material) is shown. In some embodiments, the conductive layer 204 includes conductive pillars 118, each of which extends downward to contact a corresponding electrode 108. In some embodiments, the thickness of the conductive layer 204 can be sized similarly to a redistribution layer with associated vias of an IC component.

[0033] Figure 2E The conductive layer 204 is shown patterned (e.g., etched) to create a plurality of conductive structures 114. In some embodiments, each conductive structure 114 includes a landing portion 116 and a plurality of conductive posts 118 coupled thereto. Furthermore, in some embodiments, each conductive structure 114 contacts each of a subset (e.g., two or more) of the plurality of electrodes 108 through an associated conductive post 118, as described in more detail above.

[0034] In some embodiments, Figure 2EA state of the IC element 100 is depicted in which a CP test may be performed on each of the associated electronic circuits 103 coupled to a subset of the electrodes 108 via the plurality of conductive structures 114. In other embodiments, the IC element 100 may be further processed to enhance the CP test operation. For example, Figure 2F The second dielectric layer 212 is shown formed (eg, deposited) over the plurality of conductive structures 114 and the first dielectric layer 112. In some embodiments, the second dielectric layer 212 may include SiO x or another dielectric material.

[0035] Figure 2G Patterning (e.g., etching) of the second dielectric layer 212 is shown to remove a portion of the second dielectric layer 212 over each of the plurality of conductive structures 114, thereby exposing the conductive structures 114. In some embodiments, a peripheral portion of each conductive structure 114 remains covered by the second dielectric layer 212, while an upper surface of the second dielectric layer 212 is located at a higher level than an upper surface of the conductive structure 114. In some embodiments, the patterned second dielectric layer 212 can be used to protect the edges of the conductive structures 114 and prevent a probe from electrically shorting two adjacent conductive structures 114 during CP testing. Thus, Figure 2G The final IC component 100A shown may represent in addition to Figure 2E Additional embodiments beyond those shown facilitate CP testing.

[0036] Figure 2H The removal of the plurality of conductive structures 114, the first dielectric layer 112, and the second dielectric layer 212 (if present) is shown (eg, using a dry and / or wet etching process). In some embodiments, the removal exposes Figure 2C The remaining portion of the first protective film 110 and the plurality of electrodes 108 after the patterning operation is shown. In some embodiments, the first protective film 110 can protect the underlying dielectric structure 104. Figure 2H In addition, in some embodiments, Figure 2H The removal operation may be performed after the CP test of the electronic circuit 103 is completed.

[0037] In some embodiments, Figure 2H The removal operation may leave residues of one or more contaminants on the upper surface 214 of the plurality of electrodes 108, which may cause problems in subsequent contact between additional layers of IC components subsequently formed thereon and the electrodes 108. For example, in some embodiments, such contaminants may include dislodged barrier material (e.g., tantalum and / or other barrier materials). In some embodiments, the contaminants may include Figure 2HThe contaminants may include dry etch byproducts (e.g., carbon, fluoride, and / or other materials) remaining after the removal operation of the conductive structure 114. Moreover, in some embodiments, the contaminants may include conductive material (e.g., aluminum or another metal) that may have leaked onto the upper surface 214 of the electrode 108 through seams in a barrier metal (e.g., tantalum nitride (TaN)) used as a liner for the conductive pillars 118 of the conductive structure 114. However, other contaminants may also be present. Therefore, in some embodiments, Figure 2H The removal operation may be followed by a cleaning operation (eg, application and rinsing of one or more solvents) at least directed to the upper surface 214 of the electrode 108. In some embodiments, the cleaning process may produce a depression in the upper surface 214 of the electrode 108 of about 100 angstroms or less.

[0038] Fig.2I The second protective film 110A is shown formed (e.g., deposited) over the first protective film 110 and the plurality of electrodes 108. In some embodiments, the second protective film 110A may include tantalum, a tantalum compound, or another material. In some embodiments, the second protective film 110A may protect the resulting IC device 200 from mechanical and / or electrical damage to the IC device, such as when the IC device 200 is placed in a manner that allows the IC device 200 to be electrically conductive. Fig.2I The resulting structure is physically transferred to another party (e.g., a customer).

[0039] In some embodiments, forming a second protective film 110A over the first protective film 110 and the electrode 108 may result in a first thickness 216 of the second protective film 110A over the electrode 108 and a second thickness 218 of the combined protective film 110B (including the first protective film 110 and the second protective film 110A) between the electrodes 108 and possibly over the peripheral portion of each electrode 108. In some embodiments, the first thickness 216 may be in a first range of 100 angstroms to 400 angstroms, 250 angstroms to 300 angstroms, or another range of values. In some embodiments, the second thickness 218 may be in a second range of 150 angstroms to 600 angstroms, 200 angstroms to 500 angstroms, or another range of values. In some embodiments, the difference between the first thickness 216 and the second thickness 218 may be in a range of 50 angstroms to 300 angstroms, 100 angstroms to 200 angstroms, or another range of values. In some embodiments, as described above, using various thicknesses for the first protection film 110 and the second protection film 110A can facilitate acceptable protection of the dielectric structure 104 and the electrode 108 during different processing stages of the IC device, such as in preparation for CP testing (e.g., Figure 2E and Figure 2G ), and subsequently transmitted to another party (e.g., as Fig.2I shown).

[0040] Figure 3A method 300 for forming an IC component that uses a conductive structure for CP testing according to some embodiments is shown. Although the method and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that the present disclosure is not limited to the order or actions shown. Therefore, in some embodiments, these actions can be performed in an order different from the order shown, and / or can be performed simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0041] In some embodiments, actions 302 to 316 may correspond to, for example, FIG. 2A to FIG. 2I At action 302, for example, an IC may be provided, the IC having a substrate (eg, Figure 2A A substrate 102, a dielectric structure (eg, Figure 2A The dielectric structure 104) and a plurality of electrodes (eg, Figure 2A In some embodiments, the IC structure may further include a first protective film (eg, Figure 2A The first protective film 110). Figure 2A A cross-sectional view corresponding to some embodiments of act 302 is shown.

[0042] At act 304, a dielectric layer (eg, Figure 2B a first dielectric layer 112). Figure 2B A cross-sectional view corresponding to some embodiments of act 304 is shown.

[0043] At act 306, at least a portion of the first dielectric layer over the electrode (eg, Figure 2C part 202). Figure 2C A cross-sectional view corresponding to some embodiments of act 306 is shown.

[0044] At act 308, a conductive layer (eg, Figure 2D conductive layer 204). Figure 2D A cross-sectional view corresponding to some embodiments of act 308 is shown.

[0045] At act 310, at least a portion of the conductive layer may be removed or patterned (eg, etched) to form a plurality of conductive structures (eg, Figure 2E Conductive structure 114). Figure 2E A cross-sectional view corresponding to some embodiments of act 310 is shown.

[0046] Furthermore, in some embodiments, an additional dielectric layer (eg, Figure 2F The second dielectric layer 212 of Figure 2F In addition, in some embodiments, a portion of the second dielectric layer above the conductive structure 114 may be removed or patterned (eg, etched), as shown in FIG. Figure 2G Described in.

[0047] At act 312, the conductive structure may be provided by a plurality of conductive structures (e.g., Figure 2E or Figure 2G In some embodiments, the CP test may include a yield test that determines which dies of the wafer are electrically and / or functionally sufficient for use.

[0048] At act 314 , the plurality of conductive structures, the first dielectric layer, and the second dielectric layer (if present) are removed to expose the plurality of electrodes and the first protective film (if present). Figure 2H A cross-sectional view of some embodiments corresponding to act 314 is shown. In some embodiments, some contaminants or residues resulting from the removal operation or previous operations performed on the IC structure may remain on the electrode. Therefore, in some embodiments, a cleaning process (e.g., using one or more solvents) may be performed on the electrode to remove such contaminants or residues.

[0049] At act 316, a protective film (eg, Fig.2I The second protective film 110A). Fig.2I A cross-sectional view corresponding to some embodiments of act 316 is shown.

[0050] Figure 4A and Figure 4B The cross-sectional views of some embodiments of semiconductor structures for IC components are shown respectively. Figure 2E and Fig.2I The corresponding specific manufacturing stage uses a thinned (or "thinned") substrate 102A and a conductive structure 114 for CP testing. More specifically, in some embodiments, Figure 4A The IC component 400 includes Figure 2ESimilar to the structure of IC component 100, IC component 400 includes multiple conductive structures 114 coupled to multiple electrodes 108, which are configured to facilitate CP testing of multiple electronic circuits 103, as described above. In addition, in some embodiments, IC component 401 includes Fig.2I The IC element 200 has a similar structure, wherein the second protection film 110A is disposed on the plurality of electrodes 108 and the first protection film 110 .

[0051] However, in Figure 4A and Figure 4B In the embodiment, the thinned substrate 102A replaces Figure 2E and Fig.2I A substrate 102 is provided, wherein a carrier structure 406 is attached to the lower surface of the thinned substrate 102A by means of an adhesive layer 404. In some embodiments, the thinned substrate 102A may have a thickness 410 (e.g., 3 μm-10 μm) that is less than the corresponding thickness of the dielectric structure 104. As used herein, the carrier structure 406 is a wafer-sized structure that includes silicon, glass, quartz, or other material and is attached or adhered to the lower surface of the thinned silicon wafer to provide stability to the substrate and prevent substrate breakage during the IC manufacturing process. Therefore, in some embodiments, the use of the carrier structure 406 can facilitate the use of the conductive structure 114 to perform CP testing of IC components using the thinned substrate 102A.

[0052] Figure 5A-5G Cross-sectional views of some embodiments of semiconductor structures for IC devices employing a thinned substrate 102A and a conductive structure 114 for CP testing at various stages of fabrication are shown.

[0053] Figure 5A A semiconductor structure is shown which may represent a partially constructed IC component which may be used as a base structure such as Figure 5B-5G , additional processing actions may be performed on the base structure. In some embodiments, as described above, the IC component includes a substrate 102 and a dielectric structure 104 disposed thereon. A plurality of electrodes 108 are disposed on the upper surface of the dielectric structure 104. The electrodes 108 may include metal and / or another conductive material. In some embodiments, each electrode 108 may be coupled to a corresponding electronic circuit 103 through an associated conductive structure 106 within the dielectric structure 104 and including one or more conductive layers and associated interconnecting contacts, through-holes, etc.

[0054] In some embodiments, the first protective film 110 may be disposed on the exposed portion of the electrode 108 and the dielectric structure 104, as shown in the above combination. Figure 2AFurthermore, in some embodiments, the first dielectric layer 112 is formed (eg, deposited) on the first protective film 110. Therefore, in some embodiments, Figure 5A The IC components include Figure 2B The IC structure shown in . In addition, Figure 5A The IC device includes a first carrier structure 406A coupled to the upper surface of the first dielectric layer 112 to provide support for the IC device during subsequent IC operations, such as performing a backside thinning operation on the substrate 102 .

[0055] Figure 5B Shows Figure 5A The IC element is flipped (eg, physically inverted 180 degrees) so that the substrate 102 faces upward and the first carrier structure 406A faces downward. Thereafter, Figure 5C A portion of the substrate 102 is shown removed by a thinning operation (e.g., grinding and / or other processes that remove material from the substrate 102). In some embodiments, the thickness of the thinned substrate 102A (e.g., 3 μm-10 μm) can be less than the thickness of the dielectric structure 104 disposed over the thinned substrate 102A. In some embodiments, the thinned substrate 102A can be advantageous for use in micro-actuators for panel displays and other advanced technology devices.

[0056] Figure 5D The second carrier structure 406B is shown coupled (eg, adhered) to the thinned substrate 102A via the adhesive layer 404. Thus, at this stage, the first carrier structure 406A and the second carrier structure 406B are attached to the substrate 102A. Figure 5D opposite side of the IC structure.

[0057] Figure 5E Another flip (eg, another physical inversion) of the IC component is shown such that the second carrier structure 406B faces downward and the first carrier structure 406A faces upward.

[0058] Fig. 5F Removal of the first carrier structure 406A is shown, thereby exposing the first dielectric layer 112 so that additional processing can be performed to facilitate the addition of the conductive structure 114 .

[0059] Figure 5G Shows Fig. 5F Further preparation of the IC structure, such as Figures 2C to 2G As shown in and described above in conjunction with the same, the conductive structure 114 and the associated portion of the second dielectric layer 212 are provided to facilitate CP testing of the electronic circuit 103. In some embodiments, the second dielectric layer 212 may be omitted, thereby obtaining a thinned substrate 102A, an adhesive layer 404, and a second carrier structure 406B. Figure 2EIn some embodiments, the second carrier structure 406B provides strength and stability for the IC structure when performing CP testing.

[0060] Figure 6 Some embodiments of semiconductor structures for IC components are shown in cross-sectional views. Figure 2F The thinned substrate and the conductive structure for CP testing are used at the corresponding manufacturing stage. In some embodiments, the substrate 102 is not thinned until the first dielectric layer 112 is added. Figure 5C As shown, Figure 6 4 shows that before adding the first carrier structure 406A and subsequently thinning the substrate 102, the conductive structure 114 and the second dielectric layer 212 are added, as shown in FIG. Figure 2F As shown and described above. Therefore, Figure 6 Indicates that the FIG. 5A to FIG. 5F Prior to the thinning operation of the substrate 102 shown, a further number of operations are performed, such as Figure 2C to Figure 2F shown.

[0061] Figure 7 A method 700 for forming an IC device using a thinned substrate and a conductive structure for CP testing according to some embodiments is shown. In some embodiments, actions 702 to 720 may correspond to, for example, those previously described in Figures 2A to 2G , FIG. 5A to FIG. 5G as well as Figure 6 The structure shown in .

[0062] At act 702, for example, an IC structure may be provided, the IC structure having a substrate (eg, Figure 2A A substrate 102, a dielectric structure (eg, Figure 2A The dielectric structure 104) and a plurality of electrodes (eg, Figure 2A In some embodiments, the IC structure may further include a first protective film (eg, Figure 2A The first protective film 110).

[0063] Additionally, in some embodiments, at act 704, the IC structure may be partially prepared for CP testing. Figure 5A As shown, before coupling the first carrier structure 406A, a first dielectric layer 112 may be formed on the plurality of electrodes 108 and the first protection film 110. In other embodiments, as Figure 6 As shown, the conductive structure 114 and the second dielectric layer 212 may also be formed before coupling with the first carrier structure 406A.

[0064] At act 706 , the first carrier structure 406A can be coupled to the integrated circuit structure opposite the substrate 102 . Figure 5A and Figure 6 Cross-sectional views corresponding to some embodiments of act 702 , act 704 , and act 706 are shown.

[0065] At act 708, the thickness of the substrate may be reduced to form a thinned substrate (eg, Figure 5C The thinned substrate 102A). Figure 5B and Figure 5C A cross-sectional view corresponding to some embodiments of act 708 is shown.

[0066] At act 710, a second carrier structure (eg, Figure 5D A second carrier structure 406B) is coupled to the IC structure opposite the first carrier structure. Figure 5D A cross-sectional view corresponding to some embodiments of act 710 is shown.

[0067] At act 712, the first carrier structure is removed from the IC structure. Figure 5E and Fig. 5F A cross-sectional view corresponding to some embodiments of act 712 is shown.

[0068] At act 714, preparation of the IC structure for CP testing is completed to provide a plurality of conductive structures (eg, Figure 5G In some embodiments, as shown in FIG. Figure 5A As shown, the first dielectric layer 112 is added before the first carrier structure 406A. The further preparation of the IC structure may include FIG. 2C to FIG. 2E (or alternatively, Figure 2C to Figure 2G ). In some embodiments, as Figure 6 As shown, the second dielectric layer 212 is added before the first carrier structure 406A. The further preparation of the IC structure may include Figure 2G The operation shown. Figure 5G A cross-sectional view corresponding to some embodiments of act 714 is shown.

[0069] At act 716, the IC structure (e.g., Figure 5G In some embodiments, the CP test may include a yield test that determines which dies of the wafer are electrically and / or functionally sufficient for use.

[0070] At act 718, the integrated circuit structure may be processed to remove the plurality of conductive structures and expose the plurality of electrodes. In some embodiments, the plurality of conductive structures, the first dielectric layer, and the second dielectric layer (if present) are removed to expose the plurality of electrodes and the first protective film (if present). Figure 2H A cross-sectional view of some embodiments corresponding to action 718 is shown. In some embodiments, contaminants or residues resulting from the removal operation or previous operations performed on the IC structure may remain on the electrode. Therefore, in some embodiments, a cleaning process may be performed on the electrode to remove the contaminants or residues, as described more fully above.

[0071] At act 720, a protective film (eg, Fig.2I The second protective film 110A). Fig.2I A cross-sectional view corresponding to some embodiments of act 720 is shown.

[0072] Some embodiments relate to a method of manufacturing an integrated circuit element. The method includes providing an integrated circuit structure, the integrated circuit structure including a substrate, a dielectric structure disposed on the substrate and having an upper surface, and a plurality of electrodes disposed on the upper surface of the dielectric structure. The method also includes forming a first dielectric layer on the dielectric structure and the plurality of electrodes, etching the first dielectric layer on each of the plurality of electrodes, forming a conductive layer on the first dielectric layer and the plurality of electrodes, removing at least a portion of the conductive layer to form a plurality of conductive structures on the plurality of electrodes. Each of the plurality of conductive structures contacts a corresponding subset of the plurality of electrodes. The method further includes performing circuit probe testing on the integrated circuit structure through the plurality of conductive structures.

[0073] In some embodiments, each of the plurality of conductive structures comprises: a landing portion disposed on the first dielectric layer; and a plurality of conductive posts extending downward from the landing portion through the first dielectric layer, each of the plurality of conductive posts contacting an associated one of the corresponding subsets of the plurality of electrodes. In some embodiments, the width of each of the plurality of conductive posts is less than or equal to the width of the associated one of the corresponding subsets of the plurality of electrodes. In some embodiments, the corresponding subsets of the plurality of electrodes are arranged in a plan view as a two-dimensional electrode array, the two-dimensional electrode array comprising nine electrodes and having a minimum of three rows of electrodes and three columns of electrodes. In some embodiments, the integrated circuit structure further comprises at least one electronic circuit residing in at least one of the substrate and the dielectric structure, the at least one electronic circuit coupled to the plurality of electrodes; and performing the circuit probe test comprises testing the at least one electronic circuit. Performing the circuit probe test comprises testing the at least one electronic circuit. In some embodiments, the method further comprises: forming a second dielectric layer over the plurality of conductive structures and the first dielectric layer; and etching the second dielectric layer over at least a portion of each of the plurality of electrodes. In some embodiments, the upper surface of the second dielectric layer is higher than the upper surface of each of the plurality of conductive structures. In some embodiments, the method further includes: before forming the first dielectric layer, forming a first protective film over the dielectric structure and the plurality of electrodes, wherein etching the first dielectric layer further includes etching at least a portion of the first protective film over the plurality of electrodes. In some embodiments, the method further includes: after removing at least a portion of the conductive layer to form the plurality of conductive structures over the plurality of electrodes, removing the first dielectric layer and the plurality of conductive structures to expose the plurality of electrodes and the first protective film. In some embodiments, the method further includes: forming a second protective film over the plurality of electrodes and the first protective film to produce a combined protective film having a first thickness over the plurality of electrodes and a second thickness over the upper surface of the dielectric structure, wherein the second thickness is greater than the first thickness.

[0074] Some embodiments relate to another method for manufacturing an integrated circuit element. The method includes providing an integrated circuit structure, the integrated circuit structure including a substrate, a dielectric structure disposed on the substrate and having an upper surface, and a plurality of electrodes disposed on the upper surface of the dielectric structure. The dielectric structure includes a conductive interconnect structure, and at least one of the substrate and the dielectric structure includes at least one electronic circuit coupled to the plurality of electrodes through the conductive interconnect structure. The method also includes forming a first protective film on the dielectric structure and the plurality of electrodes, forming a first dielectric layer on the first protective film, etching the first dielectric layer and the first protective film on each of the plurality of electrodes, forming a conductive layer on the first dielectric layer and the plurality of electrodes, and removing at least a portion of the conductive layer to form a plurality of conductive structures on the plurality of electrodes. Each of the plurality of conductive structures contacts a corresponding subset of the plurality of electrodes. The method also includes reducing the thickness of the substrate after forming the first dielectric layer.

[0075] In some embodiments, the method further includes: removing the first dielectric layer and the plurality of conductive structures to expose the plurality of electrodes and the first protective film; and forming a second protective film over the plurality of electrodes and the first protective film to produce a combined protective film having a first thickness over the plurality of electrodes and a second thickness over the upper surface of the dielectric structure, wherein the second thickness is greater than the first thickness. In some embodiments, the method further includes: forming a second dielectric layer over the first dielectric layer and the plurality of conductive structures; and etching the second dielectric layer over at least a portion of each of the plurality of electrodes. In some embodiments, the method further includes: removing the first dielectric layer, the second dielectric layer, and the plurality of conductive structures to expose the plurality of electrodes and the first protective film; and forming a second protective film over the plurality of electrodes and the first protective film to produce a combined protective film having a first thickness over the plurality of electrodes and a second thickness over the upper surface of the dielectric structure, wherein the second thickness is greater than the first thickness. In some embodiments, reducing the thickness of the substrate comprises: after forming the second dielectric layer, coupling a first carrier structure to the integrated circuit structure opposite to the substrate; thinning the substrate; coupling a second carrier structure to the thinned substrate; and removing the first carrier structure before etching the second dielectric layer. In some embodiments, reducing the thickness of the substrate comprises: after forming the first dielectric layer, coupling a first carrier structure to the integrated circuit structure opposite to the substrate; thinning the substrate; coupling a second carrier structure to the thinned substrate; and removing the first carrier structure before etching the first dielectric layer and the first protective film.

[0076] Some embodiments relate to an integrated circuit component. The integrated circuit component includes a substrate, a dielectric structure disposed on the substrate and including an upper surface, a plurality of electrodes disposed on the upper surface of the dielectric structure, and a protective layer disposed on and in contact with the plurality of electrodes and the upper surface of the dielectric structure. A first thickness of the protective layer on a central portion of each of the plurality of electrodes is less than a second thickness of the protective layer on the upper surface of the dielectric structure.

[0077] In some embodiments, a third thickness of the protective layer over a peripheral portion of each of the plurality of electrodes is substantially equal to the second thickness. In some embodiments, the first thickness of the protective layer is in a first range of 100 angstroms to 400 angstroms; and the second thickness of the protective layer is in a second range of 150 to 600 angstroms. In some embodiments, the difference between the first thickness and the second thickness is in a range of 50 angstroms to 300 angstroms.

[0078] It should be understood that in this written description and in the following claims, the terms "first", "second", "third", etc. are merely general identifiers used for ease of description to distinguish different components of a figure or series of figures. By themselves, these terms do not imply any temporal order or structural proximity of these components, and are not intended to describe corresponding components in different illustrated embodiments and / or non-illustrated embodiments. For example, a "first dielectric layer" described in conjunction with a first figure does not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and does not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0079] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing an integrated circuit element, comprising: An integrated circuit structure is provided, comprising: substrate; A dielectric structure is disposed on the substrate, the dielectric structure comprising an upper surface; and A plurality of electrodes are disposed on the upper surface of the dielectric structure; forming a first dielectric layer over the dielectric structure and the plurality of electrodes; etching the first dielectric layer over each of the plurality of electrodes; forming a conductive layer on the first dielectric layer and the plurality of electrodes; removing at least a portion of the conductive layer to form a plurality of conductive structures over the plurality of electrodes, each of the plurality of conductive structures contacting a corresponding subset of the plurality of electrodes; and The integrated circuit structure is subjected to circuit probe testing through the plurality of conductive structures.

2. The method for manufacturing an integrated circuit element according to claim 1, characterized in that: Each of the plurality of conductive structures comprises: A landing portion is disposed on the first dielectric layer; and A plurality of conductive posts extend downwardly from the landing portion through the first dielectric layer, each of the plurality of conductive posts contacting an associated one of the corresponding subset of the plurality of electrodes.

3. The method for manufacturing an integrated circuit element according to claim 1, characterized in that: The corresponding subset of the plurality of electrodes is arranged in a plan view as a two-dimensional electrode array comprising nine electrodes and having a minimum of three rows of electrodes and three columns of electrodes.

4. The method for manufacturing an integrated circuit element according to claim 1, wherein: The integrated circuit structure further includes at least one electronic circuit residing in at least one of the substrate and the dielectric structure, the at least one electronic circuit coupled to the plurality of electrodes; as well as Performing the circuit probe test includes testing the at least one electronic circuit.

5. The method for manufacturing an integrated circuit element according to claim 1, wherein: Also includes: forming a second dielectric layer over the plurality of conductive structures and the first dielectric layer; as well as The second dielectric layer is etched over at least a portion of each of the plurality of electrodes.

6. A method for manufacturing an integrated circuit element, comprising: An integrated circuit structure is provided, comprising: substrate; A dielectric structure is disposed on the substrate, the dielectric structure comprising an upper surface and including a conductive interconnect structure; and a plurality of electrodes disposed over the upper surface of the dielectric structure, wherein at least one of the substrate and the dielectric structure includes at least one electronic circuit coupled to the plurality of electrodes through the conductive interconnect structure; forming a first protective film on the dielectric structure and the plurality of electrodes; forming a first dielectric layer on the first protective film; etching the first dielectric layer and the first protective film on each of the plurality of electrodes; forming a conductive layer on the first dielectric layer and the plurality of electrodes; removing at least a portion of the conductive layer to form a plurality of conductive structures over the plurality of electrodes, each of the plurality of conductive structures contacting a corresponding subset of the plurality of electrodes; and After forming the first dielectric layer, the thickness of the substrate is reduced.

7. The method for manufacturing an integrated circuit element according to claim 6, characterized in that: Also includes: removing the first dielectric layer and the plurality of conductive structures to expose the plurality of electrodes and the first protective film; as well as A second protective film is formed over the plurality of electrodes and the first protective film to produce a combined protective film having a first thickness over the plurality of electrodes and a second thickness over the upper surface of the dielectric structure, wherein the second thickness is greater than the first thickness.

8. The method for manufacturing an integrated circuit element according to claim 6, characterized in that: Reducing the thickness of the substrate includes: After forming the first dielectric layer, coupling a first carrier structure to the integrated circuit structure opposite to the substrate; thinning the substrate; coupling a second carrier structure to the thinned substrate; and Before etching the first dielectric layer and the first protection film, the first carrier structure is removed.

9. An integrated circuit structure comprising: substrate; A dielectric structure is disposed on the substrate, the dielectric structure comprising an upper surface; A plurality of electrodes are disposed on the upper surface of the dielectric structure; as well as A protective layer is disposed over and in contact with the plurality of electrodes and the upper surface of the dielectric structure, wherein a first thickness of the protective layer over a central portion of each of the plurality of electrodes is less than a second thickness of the protective layer over the upper surface of the dielectric structure.

10. The integrated circuit structure according to claim 9, characterized in that: A third thickness of the protective layer over a peripheral portion of each of the plurality of electrodes is substantially equal to the second thickness.

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