Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device is provided. The method includes providing an interlayer dielectric layer having a trench on a substrate in a first substrate processing apparatus in a vacuum state; forming a first metal barrier layer in the trench while the substrate is in the first substrate processing apparatus; unloading the substrate from the first substrate processing apparatus and exposing the substrate to a non-vacuum environment; providing a substrate in a second substrate processing apparatus in a vacuum state; forming a second metal barrier layer in the trench in a second substrate processing apparatus; and forming a metal pattern to fill the trench.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0116373 and No. 10-2024-0011510 filed on September 1, 2023 and January 25, 2024, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a method of manufacturing a semiconductor device, and in particular, to a method of manufacturing a semiconductor device using a plurality of substrate processing apparatuses configured to increase the efficiency of a manufacturing process and improve space utilization efficiency. Background Art

[0004] Semiconductor devices can be manufactured through several processes. The semiconductor manufacturing process may include the operation of forming fine metal patterns on a substrate. The metal pattern can be used to conduct electrical signals, and as the integration density and complexity of the substrate increase, it is very important to form the metal pattern finely and densely.

[0005] The metal pattern can be formed by forming a groove in the interlayer dielectric layer and filling the groove with a metal layer. However, if the metal layer is directly formed in the groove, the metal element may diffuse into the substrate due to the concentration difference, and this may cause the semiconductor device to deteriorate in quality or fail. Therefore, a barrier layer may be formed in the groove to prevent the diffusion of the metal element, and a metal pattern may be formed on the barrier layer in the groove. Summary of the invention

[0006] One or more example embodiments provide a semiconductor manufacturing method of removing an oxide layer formed on a substrate when the substrate is transferred in a non-vacuum environment.

[0007] One or more example embodiments provide a semiconductor manufacturing method of removing an oxide layer from a substrate using a sputtering process.

[0008] One or more example embodiments provide a semiconductor manufacturing method of removing an oxide layer from a substrate through a chemical reaction process using a reactive gas or plasma.

[0009] One or more example embodiments provide a semiconductor manufacturing method using a plurality of substrate processing apparatuses to improve space utilization efficiency.

[0010] One or more example embodiments provide a semiconductor manufacturing method using a plurality of substrate processing apparatuses to diversify process chamber types and improve manufacturing process efficiency.

[0011] According to one aspect of an example embodiment, a method for manufacturing a semiconductor device includes: providing an interlayer dielectric layer having a groove on a substrate in a first substrate processing device in a vacuum state; forming a first metal barrier layer in the groove while the substrate is in the first substrate processing device; unloading the substrate from the first substrate processing device and exposing the substrate to a non-vacuum environment; providing the substrate in a second substrate processing device in a vacuum state; forming a second metal barrier layer in the groove in the second substrate processing device; and forming a metal pattern to fill the groove.

[0012] According to one aspect of an example embodiment, a method for manufacturing a semiconductor device includes: providing an interlayer dielectric layer having a groove on a substrate in a first substrate processing device in a vacuum state; forming a deposition inhibition layer in the groove while the substrate is in the first substrate processing device; unloading the substrate from the first substrate processing device to expose the substrate to a non-vacuum state; providing the substrate in a second substrate processing device in a vacuum state; forming a first metal barrier layer in the groove in the second substrate processing device; and forming a metal pattern to fill the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features will become more apparent from the following description of example embodiments in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a perspective view showing a substrate processing system according to an example embodiment;

[0015] Figure 2 is a perspective view showing a substrate processing system according to an example embodiment;

[0016] Figure 3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an example embodiment;

[0017] Figure 4 is a perspective view showing a substrate and an interlayer dielectric layer according to an example embodiment;

[0018] Figure 5 is a cross-sectional view showing a substrate and an interlayer dielectric layer according to example embodiments;

[0019] Figure 6 is a cross-sectional view showing a substrate and an interlayer dielectric layer having a first metal barrier layer formed thereon according to an example embodiment;

[0020] Figure 7 is a cross-sectional view showing a substrate and an interlayer dielectric layer having a first metal barrier layer and a second metal barrier layer formed thereon according to an example embodiment;

[0021] Figure 8is a cross-sectional view showing a substrate and an interlayer dielectric layer having a first metal barrier layer, a second metal barrier layer, and a seed layer formed thereon according to example embodiments;

[0022] Fig. 9 is a cross-sectional view showing a substrate and an interlayer dielectric layer on which a metal pattern is formed on a seed layer according to example embodiments;

[0023] Fig.10 is a cross-sectional view illustrating an atomic layer deposition (ALD) process performed on a substrate and an interlayer dielectric layer according to example embodiments;

[0024] Fig.11 is a cross-sectional view illustrating an atomic layer deposition (ALD) process performed on a substrate and an interlayer dielectric layer according to example embodiments;

[0025] Fig.12 is a cross-sectional view illustrating a physical vapor deposition (PVD) process performed on a substrate and an interlayer dielectric layer according to example embodiments;

[0026] Fig.13 is a cross-sectional view illustrating a physical vapor deposition (PVD) process performed on a substrate and an interlayer dielectric layer according to example embodiments;

[0027] Fig.14 is a cross-sectional view showing a substrate and an interlayer dielectric layer having a first metal barrier layer, a second metal barrier layer, a liner layer, and a seed layer formed thereon according to example embodiments;

[0028] Fig.15 is a cross-sectional view illustrating a chemical vapor deposition (CVD) process performed on a substrate and an interlayer dielectric layer according to example embodiments;

[0029] Fig.16 is a cross-sectional view illustrating a chemical reaction process performed on a substrate and an interlayer dielectric layer according to example embodiments;

[0030] Fig.17 is a flowchart illustrating a method of manufacturing a semiconductor device according to an example embodiment;

[0031] Fig.18 is a cross-sectional view showing a substrate and an interlayer dielectric layer having a deposition inhibiting layer and a first metal barrier layer formed thereon according to example embodiments;

[0032] Fig.19 is a cross-sectional view illustrating a sputtering process performed to remove an oxide layer from a substrate and an interlayer dielectric layer according to example embodiments;

[0033] Fig. 20is a cross-sectional view illustrating a substrate and an interlayer dielectric layer having a first metal barrier layer and a second metal barrier layer formed thereon according to example embodiments; and

[0034] Fig.21 is a cross-sectional view illustrating a substrate and an interlayer dielectric layer having a metal pattern formed on a second metal barrier layer according to example embodiments. DETAILED DESCRIPTION

[0035] Example embodiments will be described in detail with reference to the accompanying drawings. Similar reference numerals in the accompanying drawings represent similar elements, and their description will therefore be omitted. It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to the other element or layer, or there may be an intermediate element or layer. On the contrary, when an element is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and may be implemented in various other forms. Each example embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment that is also provided herein or is not provided herein but consistent with the present disclosure.

[0036] In the present application, reference numerals D1, D2, and D3 will be used to represent a first direction, a second direction, and a third direction, respectively, which are not parallel to each other.

[0037] Figure 1 is a perspective view showing a substrate processing system SY according to an example embodiment, and Figure 2 is a perspective view illustrating a substrate processing system SY according to example embodiments.

[0038] Reference Figure 1 and Figure 2, the substrate processing system SY may include a plurality of substrate processing devices SA. The substrate W may be a silicon wafer, but the example embodiment is not limited thereto. In the example embodiment, two or more substrate processing devices SA may be provided. For example, the substrate processing system SY may include a first substrate processing device SA1, a second substrate processing device SA2, a third substrate processing device SA3, and a fourth substrate processing device. However, the number of substrate processing devices SA included in the substrate processing system SY may be variously changed. Each of the substrate processing devices SA may include a central chamber CC, a load lock chamber LC, and a plurality of processing chambers PC. However, the structure of the substrate processing device SA is not limited to this example, and may also include other elements for the substrate processing process. The first substrate processing device SA1 may include a (1-1)th processing chamber PC1-1, a (1-2)th processing chamber PC1-2, a (1-3)th processing chamber PC1-3, a first central chamber CC1, and a first load lock chamber LC1. Similarly, the second substrate processing device SA2 may include a (2-1)th processing chamber PC2-1, a (2-2)th processing chamber PC2-2, a (2-3)th processing chamber PC2-3, a second central chamber CC2, and a second load lock chamber LC2. Each of the third substrate processing device SA3 and the fourth substrate processing device may include a processing chamber PC, a central chamber CC, and a load lock chamber LC in a similar manner. When the substrate W is transferred between different chambers or between different substrate processing devices SA, the elements formed on the substrate W may be transferred together with the substrate W. In the following description, if the substrate W is transferred, it can be understood that the elements formed on the substrate W are transferred together with the substrate W. The processing chamber PC may be used to perform processes different from each other. One substrate processing device SA may include a plurality of processing chambers PC that perform processes different from each other. However, the example embodiments are not limited thereto, and one substrate processing device SA may include a plurality of processing chambers PC that perform the same process. For example, the first substrate processing device SA1 may include two or more processing chambers PC that are used to perform processes different from each other. Figure 6 The trench TR is formed Figure 6 The first metal barrier layer MB1 of the substrate W and the interlayer dielectric layer ILD is formed on the substrate W and the interlayer dielectric layer ILD. Fig. 9 The process chamber PC can be used to form the metal wire MM in the trench TR. The metal wire MM will be described in more detail below. In the following description, if it is not explicitly described that the substrate W is transferred from one substrate processing device SA to another substrate processing device SA, it can be understood that the related processes are performed in the same substrate processing device SA. In the case where several processes are performed on the substrate W in one substrate processing device SA, it can be understood that these processes are performed in process chambers PC different from each other. In the following, reference will be made to Figure 1 and Figure 2 The Process Chamber PC is Described in More Detail Various processes performed using the process chamber PC will be described in more detail below.

[0039] The central chamber CC can be used to transfer the substrate W from processing chamber PC to processing chamber PC and from one processing chamber PC to another processing chamber PC. For example, the first central chamber CC1 can be used to move the substrate W from the (1-1)th processing chamber PC1-1 to the (1-3)th processing chamber PC1-3 without breaking the vacuum state.

[0040] The load lock chamber LC can be used to load the substrate W from the outside to the central chamber CC. The processing chamber PC and the central chamber CC can be configured to maintain a high vacuum state. The load lock chamber LC can be used to transfer the substrate W to the substrate processing device SA without breaking the high vacuum state of the processing chamber PC and the central chamber CC. In the case where the substrate W is set in the load lock chamber LC, a pump can be used to change the internal space of the load lock chamber LC to a low vacuum state. The substrate W can be transferred from the load lock chamber LC in a low vacuum state to the central chamber CC and the processing chamber PC in a high vacuum state. It may take a long time to convert the internal space of the processing chamber PC and the central chamber CC from an atmospheric pressure state to a high vacuum state. When the load lock chamber LC is used to load and unload the substrate W, the time and energy required to maintain the processing chamber PC and the central chamber CC in a high vacuum state can be reduced.

[0041] Figure 3 is a flowchart illustrating a method Sa of manufacturing a semiconductor device according to an example embodiment, Figure 4 is a perspective view showing a substrate W and an interlayer dielectric layer ILD according to example embodiments, Figure 5 is a cross-sectional view showing a substrate W and an interlayer dielectric layer ILD according to example embodiments, Figure 6 is a cross-sectional view illustrating a substrate W and an interlayer dielectric layer ILD having a first metal barrier layer MB1 formed thereon according to example embodiments, Figure 7 is a cross-sectional view illustrating a substrate W and an interlayer dielectric layer ILD having a first metal barrier layer MB1 and a second metal barrier layer MB2 formed thereon according to example embodiments, Figure 8 is a cross-sectional view illustrating a substrate W and an interlayer dielectric layer ILD on which a first metal barrier layer MB1, a second metal barrier layer MB2, and a seed layer SL are formed according to example embodiments, and Fig. 9 is a cross-sectional view illustrating a substrate W and an interlayer dielectric layer ILD on which a metal pattern MC is formed on a seed layer SL according to example embodiments.

[0042] Reference Figure 3, the manufacturing method Sa may include providing an interlayer dielectric layer ILD having a trench TR on a substrate W (in operation Sa1) and forming a metal line MM in the trench TR (in operation Sa2). The formation of the metal line MM (in operation Sa2) may include forming a first metal barrier layer MB1 in the trench TR using a first substrate processing device SA1 (in operation Sa21), unloading the substrate W from the first substrate processing device SA1 and exposing the substrate W to a non-vacuum environment (in operation Sa22), transferring the substrate W to a second substrate processing device SA2 (in operation Sa23), forming a second metal barrier layer MB2 in the trench TR using the second substrate processing device SA2 (in operation Sa24), and forming a metal pattern MC to fill the trench TR (in operation Sa25). In the following description, an element formed on the substrate W and the interlayer dielectric layer ILD may indicate an element formed in the trench TR. The formation of the first metal barrier layer MB1 may be performed in the first substrate processing device SA1. The (1-1)th processing chamber PC1-1 may be used to form a first metal barrier layer MB1. The first metal barrier layer MB1 may be formed on the interlayer dielectric layer ILD. The first metal barrier layer MB1 may be formed in the trench TR. The formation of the second metal barrier layer MB2 may be performed in the second substrate processing device SA2. The second metal barrier layer MB2 may be formed on the first metal barrier layer MB1.

[0043] Reference Figure 4 and Figure 5 , a substrate W and an interlayer dielectric layer ILD having a trench TR may be provided. The substrate W and the interlayer dielectric layer ILD may have thicknesses different from those shown. The substrate W may be formed of or include silicon (Si). However, example embodiments are not limited thereto. The interlayer dielectric layer ILD may be formed on the substrate W. The interlayer dielectric layer ILD may be formed of or include silicon oxide. The trench TR may be formed by performing an etching process on the interlayer dielectric layer ILD. The metal line MM may be formed in the trench TR (for example, see Fig. 9 ). The interlayer dielectric layer ILD may include at least one of a silicon oxide layer or a silicon oxynitride layer. In an example embodiment, another semiconductor device may be provided between the substrate W and the interlayer dielectric layer ILD. For example, a circuit layer may be formed between the substrate W and the interlayer dielectric layer ILD. The circuit layer may indicate a layer or region in which an integrated circuit (e.g., a transistor) is formed. However, the structure of the circuit layer is not limited to this example. The circuit layer may include transistors, memory devices, and resistors. The transistor may be a single or combined FinFET, nanowire transistor, or nanosheet transistor. The memory device may include a random access memory (RAM) device, a read-only memory (ROM) device, and a FLASH memory device. The metal line MM may be electrically connected to the circuit layer or the substrate W.

[0044] The conductive pattern EP may be placed in the interlayer dielectric layer ILD. The conductive pattern EP may have conductive properties. The conductive pattern EP may be formed of or include at least one of copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). However, example embodiments are not limited thereto. The conductive pattern EP may include a plurality of interconnects that are spaced apart from each other vertically or horizontally. The conductive pattern EP may include a via plug and a contact plug that are used to connect a plurality of vertically stacked interconnects. The interconnects may be metal lines. The contact plugs may electrically connect the interconnects to the substrate W. The conductive pattern EP may be disposed below the trench TR. The metal line MM may be electrically connected to the circuit layer or the substrate W through the conductive pattern EP. The metal line MM may be electrically connected to the substrate W through the conductive pattern EP and the circuit layer.

[0045] Reference Figure 6 , a first metal barrier layer MB1 may be formed in the trench TR. Figure 7 , the second metal barrier layer MB2 may be formed on the first metal barrier layer MB1. Figure 8 , the seed layer SL may be formed on the second metal barrier layer MB2. For example, the first metal barrier layer MB1, the second metal barrier layer MB2, and the seed layer SL may be consistent with the shape of the trench TR, and may extend to the outside of the trench along the upper surface of the interlayer dielectric layer ILD. The seed layer SL will be described in more detail below. The arrangement of the seed layer SL is not limited to this example, and the seed layer SL may be formed on the first metal barrier layer MB1 but not on the second metal barrier layer MB2. The first metal barrier layer MB1 and the second metal barrier layer MB2 may have an amorphous structure. An amorphous structure may refer to a property of a material in which there is no regularity in the arrangement of atoms over a long distance. In the case where the first metal barrier layer MB1 and the second metal barrier layer MB2 have an amorphous structure, the materials on the first metal barrier layer MB1 and the second metal barrier layer MB2 may be prevented from diffusing through grain boundaries. Each of the first metal barrier layer MB1 and the second metal barrier layer MB2 may be formed of or include at least one of tantalum nitride (TaN), tantalum nitride-tantalum alloy (TaN / Ta), or ruthenium-doped tantalum nitride (Ru-doped TaN). However, the materials of the first metal barrier layer MB1 and the second metal barrier layer MB2 are not limited to these examples. The first metal barrier layer MB1 may also include another material that prevents a material formed on the first metal barrier layer MB1 from diffusing into the interlayer dielectric layer ILD. The second metal barrier layer MB2 may also include another material that prevents a material formed on the second metal barrier layer MB2 from diffusing into the interlayer dielectric layer ILD. For example, the first metal barrier layer MB1 and the second metal barrier layer MB2 may include different compositions.

[0046] The first metal barrier layer MB1 and the second metal barrier layer MB2 may be formed by different processes. For example, the first metal barrier layer MB1 may be formed by an atomic layer deposition (ALD) method. The second metal barrier layer MB2 may be formed by a physical vapor deposition (PVD) method. Fig.10 , Fig.11 , Fig.12 and Fig.13 The ALD and PVD methods are described in more detail. The first metal barrier layer MB1 and the second metal barrier layer MB2 may be formed in different substrate processing devices SA. Different processes may be performed in different substrate processing devices SA. The first metal barrier layer MB1 may be formed in the first substrate processing device SA1. The second metal barrier layer MB2 may be formed in the second substrate processing device SA2. The first metal barrier layer MB1 may be formed by the PVD method. The second metal barrier layer MB2 may be formed by the ALD method. However, the formation of the first metal barrier layer MB1 and the second metal barrier layer MB2 is not limited to this example.

[0047] Reference Fig. 9 , a metal pattern MC may be formed to fill the trench TR. In an example embodiment, the metal pattern MC may be formed by forming a metal layer on the seed layer SL and performing a planarization process on the metal layer. The planarization process may be a chemical mechanical planarization process. The planarization process may be performed to expose the interlayer dielectric layer ILD. In this case, each of the first metal barrier layer MB1, the second metal barrier layer MB2, the seed layer SL, and the metal pattern MC may be confined within the trench TR, and thus, a metal line MM may be formed in the trench TR. The metal line MM may include a metal pattern MC, a seed layer SL, and a first metal barrier layer MB1, a second metal barrier layer MB2 formed in the trench TR. However, the structure of the metal line MM is not limited to this example. The metal pattern MC may be formed on the seed layer SL. However, the position of the metal pattern MC is not limited to this example. The metal pattern MC may be formed on the first metal barrier layer MB1 or the second metal barrier layer MB2, but not on the seed layer SL. The metal pattern MC may be formed on one metal barrier layer. The metal pattern MC may be formed on the liner layer LL, which will be referred to Fig.15 In the following description, a metal pattern MC may be formed by finally performing a deposition process to form a metal line MM. The metal pattern MC may be formed on any combination of the metal barrier layer, the liner layer LL, and the seed layer SL. The metal pattern MC may be formed of or include at least one of copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), or titanium (Ti).

[0048] Fig.10 and Fig.11is a cross-sectional view illustrating an atomic layer deposition (ALD) process performed on a substrate W and an interlayer dielectric layer ILD according to example embodiments.

[0049] Reference Fig.10 and Fig.11 , an ALD method may be performed to form a first metal barrier layer MB1 on a substrate W, an interlayer dielectric layer ILD, and a conductive pattern EP. In the (1-1)th processing chamber PC1-1, a first metal barrier layer MB1 may be formed in a trench TR. A precursor MBa may be injected into the (1-1)th processing chamber PC1-1. The precursor MBa may be deposited on the interlayer dielectric layer ILD and the conductive pattern EP. The precursor MBa may be chemically adsorbed on the top surface of the interlayer dielectric layer ILD and the top surface of the conductive pattern EP. If the precursor MBa and the interlayer dielectric layer ILD and the precursor MBa and the conductive pattern EP sufficiently react with each other on the top surface of the interlayer dielectric layer ILD and the top surface of the conductive pattern EP through a self-saturation reaction, the deposition of the precursor MBa may be controlled to stop. The precursor MBa that is not adsorbed on the interlayer dielectric layer ILD and the conductive pattern EP may be removed, and then, the reactant MBb may be injected into the (1-1)th processing chamber PC1-1. The chemical reaction between the reactant MBb and the precursor MBa may form a product MBc. The product MBc may aggregate to form a thin film. The residue MBd left after the reaction between the reactant MBb and the precursor MBa may be discharged from the (1-1) processing chamber PC1-1 to the outside. In the following description, the same as in the reference Fig.10 and Fig.11 The ALD method is performed in a similar manner to the ALD method described above.

[0050] Fig.12 and Fig.13 is a cross-sectional view showing a physical vapor deposition (PVD) process performed on a substrate W and an interlayer dielectric layer ILD according to an example embodiment. Fig.12 and Fig.13 The illustrated PVD process may be performed in different substrate processing apparatuses SA.

[0051] Reference Fig.12, a PVD process may be performed on a structure including a substrate W, an interlayer dielectric layer ILD, and a conductive pattern EP. For example, a PVD process may be performed on a substrate W and an interlayer dielectric layer ILD (and a conductive pattern EP) in the (2-1)th processing chamber PC2-1. An inert gas P1 may be injected into the (2-1)th processing chamber PC2-1 in which the substrate W is placed. The inert gas P1 may be in a plasma state. When the inert gas P1 collides with the target plate TP, target plate particles P3 may be ejected from the target plate TP. The inert gas P1 may bounce off after colliding with the target plate TP. However, after the inert gas P1 collides with the target plate TP, it may adhere to the target plate TP without bouncing off. The target plate particles P3 may be deposited on the interlayer dielectric layer ILD. The ejection of the target plate particles P3 that occurs due to the collision between the inert gas P1 and the target plate TP may be referred to as a "sputtering process". The sputtered target plate particles P3 may be deposited on the first metal barrier layer MB1.

[0052] Fig.13 1 shows a PVD process performed on a substrate W and an interlayer dielectric layer ILD covered with an oxide layer OL. For example, in the PVD process described below, when the substrate W is transferred between substrate processing apparatuses SA, it can be understood that the substrate W and the interlayer dielectric layer ILD are exposed to a non-vacuum environment. In an example embodiment, when the substrate W is transferred from one substrate processing apparatus SA to another substrate processing apparatus SA, the substrate W and the interlayer dielectric layer ILD may be exposed to air. As described above, Fig.12 and Fig.13 The PVD process shown may be performed in different substrate processing apparatuses SA. In the case where the substrate W is exposed to a non-vacuum environment, an oxide layer OL may be formed on the interlayer dielectric layer ILD. When the substrate W is transferred from the first substrate processing apparatus SA1 to the second substrate processing apparatus SA2, the substrate W and the interlayer dielectric layer ILD may be exposed to a non-vacuum environment. Fig.12 The first substrate processing apparatus SA1 of the PVD process shown in FIG. Fig.13 When the second substrate processing device SA2 of the PVD process is performed, the substrate W and the interlayer dielectric layer ILD may be exposed to the air. Therefore, an oxide layer OL may be formed on the first metal barrier layer MB1. If the target plate particles P3 collide with the oxide layer OL, the oxide layer particles OLP may fall off from the oxide layer OL due to the high energy of the sputtered target plate particles P3. Therefore, the oxide layer OL may be removed by the target plate particles P3. The oxide layer OL of the metal line MM may be removed by a sputtering method of the PVD process. In the following description, the PVD process and the sputtering process may be described in the same manner as in the reference. Fig.12 and Fig.13 The above method is performed in a similar manner.

[0053] Fig.14is a cross-sectional view illustrating a substrate W and an interlayer dielectric layer ILD on which a first metal barrier layer MB1, a second metal barrier layer MB2, a liner layer LL, and a seed layer SL are formed according to example embodiments, and Fig.15 is a cross-sectional view illustrating a chemical vapor deposition (CVD) process performed on a substrate W and an interlayer dielectric layer ILD according to example embodiments.

[0054] When the metal pattern MC is formed in the trench TR using an electroplating process, the seed layer SL can help conduct electrons. A metal layer can be grown on the seed layer SL. The metal pattern MC can be formed on the seed layer SL. The metal pattern MC can be formed of or include at least one of copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), or titanium (Ti). Electrons can be conducted through the metal pattern MC on the seed layer SL. If there is no electron conduction in the electroplating process, an electrochemical reaction may not occur, and in this case, the metal pattern MC may not be formed. In the case where there is a problem in the electrochemical reaction, the metal pattern MC may be formed to have poor step coverage characteristics, and this may cause the manufactured semiconductor device to malfunction. Since the seed layer SL can be used as a nucleus in the nucleation effect, the seed layer SL can be used to grow the crystal structure of the metal pattern MC in the electroplating process. The properties of the metal pattern MC may depend on the thickness, crystal structure, and grain size of the seed layer SL. The seed layer SL may be formed of or include at least one of copper (Cu), titanium (Ti), ruthenium (Ru), molybdenum (Mo), tungsten (W), or a copper alloy (Cu alloy). The seed layer SL may be formed by a PVD method. However, the method of forming the seed layer SL is not limited to this example.

[0055] Reference Fig.14 , the liner layer LL may be used to form the seed layer SL to a uniform thickness. The liner layer LL may be configured to provide an environment that allows the seed layer SL to be uniformly formed. The seed layer SL may be uniformly formed by the liner layer LL. The liner layer LL may be formed of or include cobalt (Co), ruthenium (Ru), or a ruthenium-cobalt alloy (Ru-Co alloy). The liner layer LL may be formed by a chemical vapor deposition (CVD) method. Reference Fig.15 , a CVD method may be performed using the reaction gas P5. In the (2-2)th process chamber PC2-2, a liner layer may be formed in the trench TR. The reaction gas P5 may be injected into the (2-2)th process chamber PC2-2. The reaction gas P5 may form a laminar flow FL. A boundary layer BL may be formed below the laminar flow FL, wherein the reaction gas P5 is relatively close to the interlayer dielectric layer ILD or the metal line MM (for example, see Fig. 9) is zero. The reaction gas P5 may react with the interlayer dielectric layer ILD or the metal wire MM. If the concentration of the reaction gas P5 in the boundary layer BL decreases, the reaction gas P5 may diffuse from the laminar flow FL into the boundary layer BL. The interlayer dielectric layer ILD or the metal wire MM may react with the reaction gas P5 of the boundary layer BL to form a thin film. In order to make the reaction gas P5 react with the interlayer dielectric layer ILD or the metal wire MM, the (2-2)th processing chamber PC2-2 may be heated or the (2-2)th processing chamber PC2-2 may be used to generate plasma. However, the method of forming the liner layer LL is not limited to this example. The CVD process may be a process of forming a new thin film by a reaction between the reaction gas P5 and the interlayer dielectric layer ILD or the metal wire MM without forming a laminar flow FL and a boundary layer BL of the reaction gas P5. In the following description, the CVD method may be described in the same manner as in reference. Fig.15 The CVD method described above is performed in a similar manner. The liner layer LL may be formed by a PVD or ALD method.

[0056] One of the first metal barrier layer MB1 and the second metal barrier layer MB2 may not be formed in the trench TR. In an example embodiment, the first substrate processing device SA1 may be used to form only the first metal barrier layer MB1 in the trench TR. In the first substrate processing device SA1, the first metal barrier layer MB1 may be formed by a PVD method. However, the method of forming the first metal barrier layer MB1 is not limited to this example. When the substrate W is transferred from the first substrate processing device SA1 to the second substrate processing device SA2, an oxide layer OL may be formed on the substrate W and the interlayer dielectric layer ILD. The oxide layer OL of the metal line MM formed when the substrate W is exposed to air or a non-vacuum environment may be removed by a sputtering process performed in the second substrate processing device SA2. In the second substrate processing device SA2, a seed layer SL may be formed on the first metal barrier layer MB1. Before the substrate W is exposed to the non-vacuum environment, in the first substrate processing device SA1, a liner layer LL may be formed on the first metal barrier layer MB1.

[0057] Fig.16 is a cross-sectional view illustrating a chemical reaction process performed on a substrate W and an interlayer dielectric layer ILD according to example embodiments.

[0058] In the first substrate processing device SA1, the first metal barrier layer MB1 may be formed using an ALD method. However, the method of forming the first metal barrier layer MB1 is not limited to this example. For example, the first metal barrier layer MB1 may be formed by CVD and PVD methods. The first metal barrier layer MB1 may be formed in the (1-1)th processing chamber PC1-1. The substrate W may be unloaded from the first substrate processing device SA1 and may be exposed to a non-vacuum environment. Therefore, an oxide layer OL may be formed on the first metal barrier layer MB1. The substrate W may be loaded in the second substrate processing device SA2. The substrate W may be loaded in the (2-1)th processing chamber PC2-1. Fig.16 A pre-cleaning process performed on a substrate W and an interlayer dielectric layer ILD in the (2-1)th processing chamber PC2-1 is shown. The oxide layer OL and / or contaminant materials on the interlayer dielectric layer ILD can be removed by the pre-cleaning process. For the pre-cleaning process, a reaction gas P5 can be injected into the (2-1)th processing chamber PC2-1. The oxide layer OL can be removed by a reaction between the reaction gas P5 and the oxygen atoms of the oxide layer OL. The partial pressure of the reaction gas P5 can be increased to increase the reactivity between the reaction gas P5 and the oxide layer OL. The internal temperature of the (2-1)th processing chamber PC2-1 can be increased to increase the reactivity between the reaction gas P5 and the oxide layer OL. The reaction gas P5 may include hydrogen (H2) radicals. However, the type of reaction gas P5 is not limited to this example. The reaction gas P5 may include various other materials that can react with the oxide layer OL.

[0059] Hereinafter, various processes that can be performed in the second substrate processing device SA2 after removing the oxide layer OL will be described. These processes are not limited to the examples to be described below, and also include other processes. After the pre-cleaning process, the second substrate processing device SA2 can be used to form a seed layer SL. Before forming the seed layer SL, the second substrate processing device SA2 can be used to form a liner layer LL on the first metal barrier layer MB1. The liner layer LL can be formed by a CVD method. However, in an example embodiment, the formation of the seed layer SL can be performed in another substrate processing device SA. For example, after performing the pre-cleaning process in the second substrate processing device SA2, the substrate W can be transferred from the second substrate processing device SA2 to the third substrate processing device SA3 in a vacuum state. In the third substrate processing device SA3, the second metal barrier layer MB2 can be formed in the trench TR. The formation of the second metal barrier layer MB2 can be performed by a PVD method (for example, see Fig.12 The oxide layer OL of the metal wire MM formed when the substrate W is transferred from the second substrate processing apparatus SA2 to the third substrate processing apparatus SA3 may be removed by a sputtering process (eg, see Fig.13 ).

[0060] Before forming the seed layer SL in the third substrate-processing apparatus SA3 , a liner layer LL for forming the seed layer SL to a uniform thickness may be formed in the trench TR in the third substrate-processing apparatus SA3 .

[0061] Before forming the seed layer SL in the trench TR, the second metal barrier layer MB2 may be formed in the second substrate processing device SA2 without forming the liner layer LL. That is, after forming the first metal barrier layer MB1 in the first substrate processing device SA1, a pre-cleaning process may be performed in the second substrate processing device SA2. After the pre-cleaning process, the second metal barrier layer MB2 may be formed in the second substrate processing device SA2. The second metal barrier layer MB2 may be formed by a method different from the first metal barrier layer MB1. For example, the second metal barrier layer MB2 may be formed by a PVD or CVD method. After forming the second metal barrier layer MB2 in the second substrate processing device SA2, the seed layer SL may be formed on the second metal barrier layer MB2. After forming the second metal barrier layer MB2 in the second substrate processing device SA2, the liner layer LL may be formed on the second metal barrier layer MB2, and the seed layer SL may be formed thereon. The first metal barrier layer MB1 may be formed by a PVD method. However, the method of forming the first metal barrier layer MB1 is not limited to this example. The first metal barrier layer MB1 may be formed using a CVD method.

[0062] After forming the first metal barrier layer MB1 in the trench TR in the first substrate processing apparatus SA1, the substrate W may be transferred to the second substrate processing apparatus SA2. A pre-cleaning process may be performed in the second substrate processing apparatus SA2. After the pre-cleaning process, a seed layer SL may be formed on the liner layer LL in the second substrate processing apparatus SA2. Before the substrate W is transferred to the second substrate processing apparatus SA2, a liner layer LL may be formed on the first metal barrier layer MB1 in the first substrate processing apparatus SA1.

[0063] Fig.17 is a flowchart illustrating a method Sb of manufacturing a semiconductor device according to an example embodiment, Fig.18 is a cross-sectional view illustrating a substrate W and an interlayer dielectric layer ILD having a deposition inhibiting layer IH and a first metal barrier layer MB1 formed thereon according to example embodiments, Fig.19 is a cross-sectional view illustrating a sputtering process performed to remove the oxide layer OL from the substrate W and the interlayer dielectric layer ILD according to example embodiments, Fig. 20 is a cross-sectional view illustrating a substrate W and an interlayer dielectric layer ILD having a first metal barrier layer MB1 and a second metal barrier layer MB2 formed thereon according to example embodiments, and Fig.21is a cross-sectional view illustrating a substrate W and an interlayer dielectric layer ILD on which a metal pattern MC is formed on a second metal barrier layer MB2 according to example embodiments.

[0064] Reference Fig.17 , the manufacturing method Sb may include providing an interlayer dielectric layer ILD having a trench TR on a substrate W (in operation Sb1) and forming a metal line MM in the trench TR (in operation Sb2). The formation of the metal line MM (in operation Sb2) may include forming a deposition inhibition layer IH in a first substrate processing device SA1 (in operation Sb21), unloading the substrate W from the first substrate processing device SA1 to break the vacuum state of the first substrate processing device SA1 (in operation Sb22), transferring the substrate W in a second substrate processing device SA2 (in operation Sb23), forming a first metal barrier layer MB1 using the second substrate processing device SA2 (in operation Sb24), and forming a metal pattern MC to fill the trench TR (in operation Sb25). The pretreatment process may include removing contamination materials or oxide layers OL on the substrate W and the interlayer dielectric layer ILD. The pretreatment process may include forming a deposition inhibition layer IH in the trench TR. The pretreatment process may promote nucleation of a layer formed on the interlayer dielectric layer ILD and may enhance uniformity of layer thickness. The pretreatment process may increase the density of the layer disposed on the substrate W.

[0065] Reference Fig.18 , an interlayer dielectric layer ILD on which a deposition inhibition layer IH and a first metal barrier layer MB1 are formed may be provided. The first substrate processing device SA1 may be used to form a deposition inhibition layer IH in the trench TR. The substrate W may be unloaded from the first substrate processing device SA1 and may be exposed to a non-vacuum environment. The substrate W may be loaded in the second substrate processing device SA2. The second substrate processing device SA2 may be used to form a first metal barrier layer MB1. The deposition inhibition layer IH may prevent other materials from being deposited on the interlayer dielectric layer ILD. The deposition inhibition layer IH may inhibit the first metal barrier layer MB1 and the second metal barrier layer MB2 from being formed on the top surface of the interlayer dielectric layer ILD. The deposition inhibition layer IH may inhibit the first metal barrier layer MB1 and the second metal barrier layer MB2 from being formed on the bottom surface of the trench TR. The deposition inhibition layer IH may include a polymer material. The deposition inhibition layer IH may include carbon (C). The first metal barrier layer MB1 may be formed using an ALD method. However, the method of forming the first metal barrier layer MB1 is not limited to this example. The first metal barrier layer MB1 may be formed using a PVD or CVD method. The first metal barrier layer MB1 may be formed using a plasma enhanced atomic layer deposition (PEALD) method or a thermal ALD method. The first metal barrier layer MB1 may be formed using plasma.

[0066] Reference Fig.19 , the oxide layer OL formed on the substrate W and the interlayer dielectric layer ILD can be removed by plasma particles P9. Plasma can be an ionized gas containing free electrons, ions, free radicals and neutral particles. The plasma particles P9 can be one of the free electrons, ions, free radicals and neutral particles. Due to the high reactivity of the free radicals, the free radicals can chemically react with the substrate W. The free radicals can react with the layers formed on the substrate W and the interlayer dielectric layer ILD. The ions can have electrical properties. The ions can be sputtered onto the substrate W by accelerating them with an electric field. When the substrate W is transferred from the first substrate processing device SA1 to the second substrate processing device SA2, a first oxide layer OL1 can be formed on the substrate W and the interlayer dielectric layer ILD. Refer to Fig.19 , a substrate W and an interlayer dielectric layer ILD on which a first oxide layer OL1 is formed may be provided. A portion of the first oxide layer OL1 may be formed on the deposition inhibiting layer IH. The first oxide layer OL1 may be removed by physical and chemical reactions of the plasma particles P9. The first oxide layer OL1 may be removed by sputtering of ions. The first oxide layer OL1 may be removed by a chemical reaction between free radicals and the first oxide layer OL1. When the plasma particles P9 collide with the first oxide layer OL1, an oxide layer compound P7 may be formed. Since the oxide layer compound P7 is formed by the first oxide layer OL1, the first oxide layer OL1 may be removed. The deposition inhibiting layer IH may be removed together with the first oxide layer OL1 by the plasma particles P9.

[0067] Reference Fig. 20 , a substrate W and an interlayer dielectric layer ILD on which a second metal barrier layer MB2 is formed on the first metal barrier layer MB1 may be provided. Due to the deposition inhibiting layer IH, the oxide layer OL and the first and second metal barrier layers MB1 and MB2 may be prevented or inhibited from being formed in a specific area of ​​the trench TR. By using the deposition inhibiting layer IH, any other material may be prevented from being formed under the metal pattern MC.

[0068] Reference Fig.21 , the metal line MM may be formed in the trench TR. The metal pattern MC may be formed on the first metal barrier layer MB1 and the second metal barrier layer MB2. However, the location of the metal pattern MC is not limited to this example. For example, the metal pattern MC may be formed on a combination of the first metal barrier layer MB1, the second metal barrier layer MB2, the liner layer LL, and the seed layer SL. Only one metal barrier layer may be formed under the metal pattern MC. The bottom surface of the metal pattern MC may be directly connected to the interlayer dielectric layer ILD.

[0069] Hereinafter, various processes that can be performed after forming the deposition inhibition layer IH in the first substrate processing device SA1 and forming the first metal barrier layer MB1 in the second substrate processing device SA2 will be described. These processes are not limited to the examples to be described below, and also include other processes. The substrate W can be transferred from the second substrate processing device SA2 to the third substrate processing device SA3 in a vacuum state. When the substrate W is transferred from the second substrate processing device SA2 to the third substrate processing device SA3, the substrate W can be exposed to a non-vacuum environment, and thus a second oxide layer of the metal line MM can be formed. The third substrate processing device SA3 can be used to form a seed layer SL in the trench TR. The seed layer SL can be formed by a PVD method. When a sputtering process using the PVD method is performed, the second oxide layer can be removed.

[0070] After the substrate W is transferred to the third substrate processing device SA3, before the seed layer SL is formed, a second metal barrier layer MB2 may be formed in the trench TR. The second metal barrier layer MB2 may be formed by a PVD method. When the second metal barrier layer MB2 is formed, the second oxide layer may be removed by a sputtering process. After the second metal barrier layer MB2 is formed, a liner layer LL may be formed on the second metal barrier layer MB2. However, the removal of the second oxide layer is not limited to this example.

[0071] After the substrate W is transferred to the third substrate processing device SA3, a liner layer LL may be formed in the trench TR without forming the second metal barrier layer MB2. The liner layer LL may be formed by a CVD method. In the third substrate processing device SA3, the oxide layer OL may be removed by a chemical reaction between the reaction gas P5 and the oxide layer OL. The liner layer LL may be formed by a plasma enhanced chemical vapor deposition (PECVD) method. The PECVD method may be performed using plasma particles P9. In the third substrate processing device SA3, before forming the liner layer LL, the second oxide layer may be removed by a reaction between the plasma particles P9 and the second oxide layer. In the third substrate processing device SA3, the second oxide layer may be removed by a physical and chemical reaction using plasma. In the third substrate processing device SA3, the second oxide layer may be removed by a sputtering process and a chemical reaction process using plasma.

[0072] After the substrate W is transferred to the third substrate processing device SA3, a post-processing process may be performed on the substrate W and the interlayer dielectric layer ILD in the third substrate processing device SA3. The post-processing process may include removing the deposition inhibition layer IH using a sputtering process or a chemical reaction process using plasma, and removing the second oxide layer or contamination material from the substrate W and the interlayer dielectric layer ILD. The second oxide layer or contamination material on the substrate W and the interlayer dielectric layer ILD may be removed by a sputtering process or a chemical reaction process using plasma. The process of removing the deposition inhibition layer IH and the second oxide layer using plasma may include at least one of a chemical reaction process or a sputtering process. The deposition inhibition layer IH and the second oxide layer may be removed again by a post-processing process. After the post-processing process in the third substrate processing device SA3, the third substrate processing device SA3 may be used to form a seed layer SL in the trench TR. However, before forming the seed layer SL, in the third substrate processing device SA3, a liner layer LL may be formed on the interlayer dielectric layer ILD where the post-processing process is performed. In this regard, the liner layer LL may be formed on the first metal barrier layer MB1. The liner layer LL may be formed using a CVD method.

[0073] After the substrate W is transferred to the third substrate processing apparatus SA3, a pre-cleaning process may be performed on the substrate W and the interlayer dielectric layer ILD in the third substrate processing apparatus SA3. In an example embodiment, the pre-cleaning process may be performed in the (3-1)th processing chamber PC3-1 (e.g., see Figure 2 ). The reaction gas P5 may be injected into the (3-1)th processing chamber PC3-1. The reaction gas P5 may be injected into the third substrate processing device SA3. In the third substrate processing device SA3, the second oxide layer may chemically react with the reaction gas P5, and thus, the second oxide layer may be removed. After removing the second oxide layer, a pre-cleaning process may be performed in the third substrate processing device SA3. The substrate W may be transferred from the third substrate processing device SA3 to the fourth substrate processing device. When the substrate W is transferred from the third substrate processing device SA3 to the fourth substrate processing device, the substrate W may be exposed to a non-vacuum environment. When the substrate W is transferred from the third substrate processing device SA3 to the fourth substrate processing device, a third oxide layer of the metal wire MM may be formed due to the non-vacuum environment.

[0074] The fourth substrate processing device can be used to form a second metal barrier layer MB2 in the trench TR. The second metal barrier layer MB2 can be formed by a PVD method. In the fourth substrate processing device, the third oxide layer can be removed by a sputtering process. However, the method of removing the third oxide layer using the fourth substrate processing device is not limited to this example. The fourth substrate processing device can be used to form a liner layer LL in the trench TR. The liner layer LL can be formed by a CVD method. In the fourth substrate processing device, the third oxide layer can react with the reaction gas P5 and can be removed. The liner layer LL can be formed using a CVD method. The liner layer LL can be formed by a PECVD method using plasma. The third oxide layer can be removed by physical and chemical reactions of plasma. After removing the third oxide layer in the fourth substrate processing device, a seed layer SL can be formed in the trench TR.

[0075] In the method of manufacturing a semiconductor device according to an example embodiment, one substrate processing system may include a plurality of substrate processing devices. That is, the substrate processing system may be divided into a plurality of substrate processing devices. In an example embodiment, two or more substrate processing devices may be provided. Since the substrate processing system includes a plurality of substrate processing devices, space utilization efficiency may be improved. The substrate processing device may be placed in a small area. The substrate processing device may occupy a space smaller than the space required for simultaneously arranging a plurality of substrate processing devices.

[0076] In the method of manufacturing a semiconductor device according to example embodiments, the efficiency of a semiconductor manufacturing process can be improved. In the case where the substrate processing devices are all connected and cannot be separated, when one of the processing chambers fails, the entire substrate processing system cannot be used. In contrast, according to example embodiments, since the substrate processing system includes a plurality of separate substrate processing devices, even if one of the processing chambers fails, the remaining processing chambers can be utilized, and this can improve the efficiency of the manufacturing process.

[0077] In the method for manufacturing a semiconductor device according to an example embodiment, since substrate processing devices different from each other are provided, the substrate processing devices can be easily managed. In the case where the substrate processing devices are all connected and cannot be separated, even when only one of the processing chambers needs to be replaced, the entire substrate processing device may need to be replaced. For example, a normally operating processing chamber needs to be replaced with a new processing chamber. On the contrary, in the case where the substrate processing system includes a plurality of substrate processing devices, when one of the substrate processing devices needs to be replaced or repaired, the remaining substrate processing devices can be used uninterruptedly for replacement or repair. In addition, in this case, the substrate processing devices may not be managed by one manufacturer, and they may be managed separately by different manufacturers.

[0078] In the method of manufacturing a semiconductor device according to an example embodiment, various methods may be used to remove an oxide layer formed when a substrate is transferred between substrate processing devices. When a PVD process is performed, the oxide layer may be removed by a sputtering process. The oxide layer may be removed from the substrate by causing target plate particles or an inert gas to collide with the oxide layer. When an ALD process is performed, the oxide layer may be removed. The ALD process may be performed using plasma. The oxide layer may be removed by physical and chemical reactions with the oxide layer using plasma. The oxide layer may be removed by chemical reactions between plasma particles and the oxide layer. The oxide layer may be removed by physical reactions between the oxide layer and ions of plasma particles. Ions may remove the oxide layer by collision with the oxide layer. Ions may be used to remove the oxide layer by a sputtering process. When a CVD process is performed, the oxide layer may be removed. The oxide layer may be removed by chemical reactions between a reactive gas used in a CVD process and the oxide layer. In the case where plasma is used in a CVD process, the oxide layer may physically and chemically react with the plasma and be removed. The oxide layer may be removed by sputtering and chemical reactions with the plasma. The oxide layer may be removed by a pre-cleaning process. In the pre-cleaning process, the oxide layer may be removed by reactions between reactive gases and the oxide layer. The oxide layer may be removed by a post-treatment process. Since the deposition inhibition layer is removed in the post-treatment process, the oxide layer may also be removed. In the post-treatment process, the oxide layer may be removed by a sputtering process and a chemical reaction process.

[0079] In the method of manufacturing a semiconductor device according to example embodiments, an oxide layer of a metal wire formed when a substrate is transferred in a non-vacuum environment may be removed.

[0080] In the method of manufacturing a semiconductor device according to example embodiments, an oxide layer of the metal wire may be removed using a sputtering process.

[0081] In a method of manufacturing a semiconductor device according to example embodiments, an oxide layer of a metal wire may be removed through a chemical reaction process using a reaction gas or plasma.

[0082] In a method of manufacturing a semiconductor device according to example embodiments, a plurality of substrate processing apparatuses may be used to improve space utilization efficiency.

[0083] In a method of manufacturing a semiconductor device according to example embodiments, a plurality of substrate processing apparatuses may be used to diversify types of process chambers and improve efficiency of a manufacturing process.

[0084] One or more substrate processing devices consistent with example embodiments may include one or more processors and one or more memories. For example, each of the one or more memories may be a non-transitory computer-readable medium.

[0085] While aspects of the example embodiments have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: In a first substrate processing apparatus under a vacuum state, providing an interlayer dielectric layer having a groove on a substrate; In the first substrate processing apparatus, forming a first metal barrier layer in the trench; unloading the substrate from the first substrate processing device and exposing the substrate to a non-vacuum environment; providing the substrate in a second substrate processing apparatus in a vacuum state; In the second substrate processing apparatus, forming a second metal barrier layer in the trench; as well as A metal pattern is formed to fill the trench.

2. The method according to claim 1, further comprising: In the second substrate processing apparatus, a liner layer is formed on the second metal barrier layer. Wherein, the liner layer includes cobalt Co, ruthenium Ru or ruthenium cobalt Ru-Co alloy.

3. The method according to claim 2, further comprising: forming a seed layer on the liner layer, Wherein, each of the first metal barrier layer and the second metal barrier layer comprises one of tantalum nitride TaN, tantalum nitride-tantalum TaN / Ta alloy and ruthenium Ru doped tantalum nitride TaN.

4. The method according to claim 1, wherein: Also includes: In the second substrate processing apparatus, a seed layer is formed on the second metal barrier layer. Wherein, the seed layer includes at least one of copper Cu, titanium Ti, ruthenium Ru, molybdenum Mo, tungsten W and copper Cu alloy.

5. The method according to claim 1, wherein: The method further comprises: before providing the substrate in the second substrate processing device, providing a substrate having the first metal barrier layer in a third substrate processing apparatus under a vacuum state; In the third substrate processing apparatus, performing a pre-cleaning process on the substrate; and The substrate is unloaded from the third substrate processing apparatus and exposed to a non-vacuum environment.

6. The method according to claim 5, further comprising: After forming the second metal barrier layer on the substrate, a seed layer is formed on the second metal barrier layer.

7. The method according to claim 6, further comprising: Before forming the seed layer on the substrate in the second substrate processing apparatus, a liner layer is formed on the substrate.

8. The method according to claim 1, further comprising: Before forming the second metal barrier layer on the substrate, a pre-cleaning process is performed on the substrate in the second substrate processing apparatus.

9. The method according to claim 8, further comprising: In the second substrate processing apparatus, a seed layer is formed on the second metal barrier layer.

10. The method according to claim 9, further comprising: Before forming the seed layer on the substrate, forming a liner layer on the second metal barrier layer, Wherein, the liner layer includes cobalt Co, ruthenium Ru or ruthenium cobalt Ru-Co alloy.

11. The method according to claim 1, further comprising: Before forming the first metal barrier layer on the substrate in the first substrate processing apparatus, providing the substrate in a third substrate processing apparatus under a vacuum state; In the third substrate processing apparatus, forming a deposition inhibiting layer on the substrate; as well as The substrate is unloaded from the third substrate processing apparatus and exposed to a non-vacuum environment.

12. The method according to claim 11, further comprising: After forming the second metal barrier layer in the second substrate processing apparatus, a liner layer is formed on the substrate.

13. A method for manufacturing a semiconductor device, comprising: In a first substrate processing apparatus under a vacuum state, providing an interlayer dielectric layer having a groove on a substrate; In the first substrate processing apparatus, forming a deposition inhibiting layer in the groove; unloading the substrate from the first substrate processing device to expose the substrate to a non-vacuum state; providing the substrate in a second substrate processing apparatus in a vacuum state; In the second substrate processing apparatus, forming a first metal barrier layer in the trench; as well as A metal pattern is formed to fill the trench.

14. The method according to claim 13, wherein: Also includes: unloading the substrate from the second substrate processing device and exposing the substrate to a non-vacuum environment; providing the substrate in a third substrate processing apparatus in a vacuum state; as well as In the third substrate processing apparatus, a second metal barrier layer is formed on the first metal barrier layer. Wherein, different methods are used to form the second metal barrier layer and the first metal barrier layer.

15. The method according to claim 14, further comprising: In the third substrate processing apparatus, a seed layer is formed on the second metal barrier layer. Wherein, the seed crystal layer includes one of copper Cu, titanium Ti, ruthenium Ru, molybdenum Mo, tungsten W and copper Cu alloy.

16. The method according to claim 13, further comprising: unloading the substrate from the second substrate processing device and exposing the substrate to a non-vacuum environment; providing the substrate in a third substrate processing apparatus in a vacuum state; as well as A seed layer is formed on the substrate.

17. The method according to claim 16, further comprising: Before forming the seed layer on the substrate, forming a liner layer on the first metal barrier layer, Wherein, the liner layer includes cobalt Co, ruthenium Ru or ruthenium cobalt Ru-Co alloy.

18. The method according to claim 13, further comprising: moving the substrate from the second substrate processing apparatus to a third substrate processing apparatus in a vacuum state; as well as A post-processing process is performed in the third substrate processing apparatus.

19. The method according to claim 13, further comprising: moving the substrate from the second substrate processing apparatus to a third substrate processing apparatus in a vacuum state; as well as In the third substrate processing apparatus, a pre-cleaning process is performed on the substrate.

20. The method according to claim 19, further comprising: unloading the substrate from the third substrate processing apparatus and exposing the substrate to a non-vacuum environment; providing the substrate in a fourth substrate processing apparatus in a vacuum state; as well as In the fourth substrate processing apparatus, a liner layer is formed on the first metal barrier layer.

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