Bus voltage reduction method, circuit and system using single-stage PFC architecture

Abstract

The present invention relates to the technical field of fast charging conversion circuits, and specifically to a method, circuit, and system for reducing bus voltage using a single-stage PFC architecture. The steps of the bus voltage reduction method include: detecting the output voltage of the C1 / C2 port in the circuit, and determining whether the output voltages are all less than a preset threshold value of 16V; when it is detected that the output voltages are all less than the preset threshold value of 16V or no device is connected in standby mode, the output IO is set to a low level through the MCU instruction to trigger the voltage reduction mechanism of the circuit, thereby reducing the bus voltage from 31V to 22V and then to 17V. By introducing components such as MCU and optocoupler, the present invention designs a method and circuit that can intelligently adjust the bus voltage according to load demand, thereby solving the problem of low efficiency of the single-stage PFC architecture in PD fast charging products.

Description

Technical Field

[0001] The present invention relates to the technical field of fast charging conversion circuits, and in particular to a method, circuit and system for reducing bus voltage using a single-stage PFC architecture. Background Art

[0002] In modern electronic devices, AC-DC conversion circuits are often used to convert mains electricity into a DC voltage suitable for use in electronic devices. Traditional AC-DC conversion circuits typically use a multi-stage PFC architecture, which achieves efficient power transmission by gradually improving and stabilizing the power factor in multiple stages. However, this multi-stage architecture not only increases circuit complexity and cost, but also has a negative impact on the overall efficiency of the system. In a single-stage PFC architecture, the lack of a secondary detection and regulation mechanism makes it difficult to accurately control the bus voltage under different load conditions. This is especially true in PD fast-charging products, where the bus voltage needs to be flexibly adjusted according to different PD voltage charging conditions to improve AC-DC conversion efficiency.

[0003] At present, existing technical solutions usually adjust the secondary reference voltage through secondary detection to achieve different AC-DC bus voltage outputs. In a single-stage PFC circuit, due to the lack of a secondary detection mechanism, this dynamic voltage adjustment cannot be achieved. This is a major technical challenge for PD fast charging products that require multiple output voltages. For example, when the product needs to operate in 15V mode, the efficiency cannot be optimized through the existing single-stage PFC architecture, resulting in low conversion efficiency of the product under high load conditions. It also increases the operating temperature and affects the stability and life of the equipment. In addition, the existing technical solutions have high power consumption in no-load or standby states, making it difficult to meet the requirements of the energy efficiency regulations Level VI energy efficiency standards. Summary of the Invention

[0004] The present invention provides a bus voltage reduction method, circuit and system using a single-stage PFC architecture to solve the technical problem of how to achieve intelligent regulation of the bus voltage in a single-stage PFC architecture, especially in PD fast charging products, how to optimize the output of the bus voltage according to different PD voltage charging conditions, thereby ensuring high efficiency while reducing the operating temperature and no-load power consumption.

[0005] The technical solution of the present invention to solve the above technical problems is as follows:

[0006] In one aspect, a method for reducing bus voltage using a single-stage PFC architecture is provided, wherein the steps of the method for reducing bus voltage include:

[0007] Detect the output voltage of C1 / C2 ports in the circuit and determine whether the output voltage is less than the preset threshold value of 16V;

[0008] When it is detected that the output voltage is less than the preset threshold of 16V or no device is connected in standby mode, the MCU command sets the output IO to a low level to trigger the circuit's voltage reduction mechanism, reducing the bus voltage from 31V to 22V and then to 17V;

[0009] When it is detected that any end of the output voltage is greater than or equal to the preset threshold value of 16V, the output IO is set to a high level of 3V through the MCU instruction to maintain the bus voltage rising to 22V and then to 31V;

[0010] By adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit, the voltage switching transition process is controlled to smoothly switch between different operating modes and reduce the impact of voltage mutations on circuit components;

[0011] During the entire voltage switching and maintenance process, the output state of the bus voltage is successively evaluated and adjusted through the feedback mechanism to achieve the best AC-DC conversion efficiency.

[0012] In another aspect, a bus voltage reduction circuit using a single-stage PFC architecture is provided. The bus voltage reduction circuit includes:

[0013] The MCU is used to output PWM signals and high / low level commands, and controls the rise and fall of the bus voltage according to the output voltage status of the detected C1 / C2 ports;

[0014] An optocoupler connected to the MCU, and MOS transistors Q7 and Q8 connected to the optocoupler. The optocoupler is used to isolate the signal path between the MCU and MOS transistors Q7 and Q8, and forward level signals according to the received MCU instructions.

[0015] MOS transistor Q7 receives the signal from the optocoupler. When the optocoupler transmits a high level, MOS transistor Q7 is turned on, and the voltage regulator LDO charges capacitor C9 through diode D10. When the optocoupler transmits a low level, MOS transistor Q7 is turned on and off, and capacitor C9 is discharged to ground through resistors R39 and R35. The charge and discharge state of capacitor C9 is controlled by adjusting the PWM duty cycle to ensure the driving state of MOS transistor Q7.

[0016] MOS transistor Q8 receives a signal from the optocoupler. When the optocoupler transmits a high level, MOS transistor Q8 is turned on, and the voltage regulator LDO charges capacitor C15 through resistor R12, voltage regulator ZD2, and fast recovery diode D14. When the optocoupler transmits a low level, MOS transistor Q8 is turned off, and capacitor C11 is discharged to ground through fast recovery diode D13 and resistor R35. The charge and discharge state of capacitor C11 is controlled by adjusting the PWM duty cycle and the parameters of resistor R12, capacitor C11, and fast recovery diode D13 to ensure that MOS transistor Q8 is not turned on when the voltage of capacitor C11 is less than the threshold voltage of 5.1V of voltage regulator ZD2.

[0017] The rise and fall process of bus voltage includes:

[0018] When the output voltage of C1 / C2 port is less than 16V or there is no device in standby mode, the MCU outputs a low level of 0V, and the bus voltage drops from 31V to 17V, first to 22V and then to 17V.

[0019] When the output voltage of any port C1 / C2 is greater than 16V, the MCU outputs a high level of 3V, and the bus voltage remains at 31V or increases from 17V to 31V. The boost process first increases to 22V and then to 31V.

[0020] On the other hand, a bus voltage reduction system adopting a single-stage PFC architecture is provided, including the bus voltage reduction circuit adopting the single-stage PFC architecture as described above. The system also includes a power adapter connected to the bus voltage reduction circuit, a load device, a temperature monitoring module and a transient voltage protection module. The bus voltage reduction system automatically adjusts the bus voltage according to the needs of the load device and maintains high efficiency and low power consumption characteristics in any operating mode.

[0021] The beneficial effects of the present invention are:

[0022] By introducing components such as MCU and optocouplers, the present invention designs a method and circuit that can intelligently adjust the bus voltage according to load demand, solving the problem of low efficiency of the single-stage PFC architecture in PD fast charging products. The bus voltage reduction method using a single-stage PFC architecture of the present invention can achieve dynamic switching of the bus voltage between 31V and 17V, ensuring that the bus voltage drops to 17V under low load or standby state, thereby significantly reducing standby power consumption and meeting the requirements of the energy efficiency regulation Level VI standard. Under high load conditions, the bus voltage can quickly return to 31V, ensuring high efficiency and stability of power transmission.

[0023] Furthermore, the PWM signals and high / low level commands output by the MCU control the charging and discharging processes of the MOS tubes and capacitors, achieving a smooth transition in voltage switching. Specifically, during the voltage switching process, the precise adjustment of the PWM signal duty cycle and the resistance values of the circuit resistors effectively reduces the impact of sudden voltage changes on circuit components.

[0024] In addition, the present invention further improves the safety performance and service life of the circuit by introducing a transient voltage suppression circuit and a temperature monitoring element. Under different PD voltage charging conditions, the circuit can adaptively adjust the control strategy, optimize the AC-DC conversion efficiency, and ensure the efficient operation of the product in various application scenarios. This not only improves the energy efficiency of PD fast charging products, but also significantly enhances the safety and stability of the products. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a flow chart of a bus voltage reduction method using a single-stage PFC architecture in one embodiment of the present invention;

[0026] Figure 2 A diagram showing the relationship between temperature and PWM duty cycle in one embodiment of the present invention;

[0027] Figure 3 A diagram showing the relationship between noise interference and voltage detection accuracy in one embodiment of the present invention;

[0028] Figure 4 Graph showing conversion efficiency under different load conditions in one embodiment of the present invention;

[0029] Figure 5 A diagram showing the relationship between standby power consumption and bus voltage in one embodiment of the present invention;

[0030] Figure 6 is a relationship diagram of transient voltage protection performance in one embodiment of the present invention;

[0031] Figure 7 The bus voltage reduction circuit principle of a single-stage PFC architecture in one embodiment of the present invention is shown as follows: Figure 1 ;

[0032] Figure 8 The bus voltage reduction circuit principle of a single-stage PFC architecture in one embodiment of the present invention is shown as follows: Figure 2 ;

[0033] Figure 9 A diagram showing the relationship between PWM duty cycle and charge and discharge time in one embodiment of the present invention;

[0034] Figure 10 This is the circuit diagram of the USB interface C1 pin;

[0035] Figure 11 This is the circuit diagram of the USB interface C2 pin. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0037] In order to facilitate understanding of the technical solution of the present invention, some features are briefly explained first:

[0038] C1 / C2: Two pins used for Power Delivery Handshake in the Type-C USB interface.

[0039] PFC: Power Factor Correction, power factor correction.

[0040] PD: Power Delivery.

[0041] MCU: Microcontroller Unit, microcontroller.

[0042] The present invention provides the following preferred embodiments:

[0043] Example 1

[0044] In order to solve the problem that the single-stage PFC architecture cannot achieve different AC-DC bus voltage outputs in PD fast charging products, this embodiment proposes a bus voltage reduction method using a single-stage PFC architecture to ensure efficient AC-DC conversion under different PD voltage charging conditions and meet the energy efficiency requirements of Energy Efficiency Regulation VI. Figure 1 As shown, the steps of the bus voltage reduction method include:

[0045] S100 , detecting the output voltage of ports C1 / C2 in the circuit to determine whether the output voltages are both less than a preset threshold value of 16V.

[0046] S200: When it is detected that the output voltage is less than the preset threshold value of 16V or no device is connected in standby mode, the output IO is set to a low level through the MCU instruction to trigger the voltage reduction mechanism of the circuit to reduce the bus voltage from 31V to 22V and then to 17V.

[0047] S300: When it is detected that any end of the output voltage is greater than or equal to the preset threshold value 16V, the output IO is set to a high level of 3V through the MCU instruction to maintain the bus voltage rising to 22V and then to 31V.

[0048] S400, controlling the voltage switching transition process by adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit, so as to smoothly switch between different working modes and reduce the impact of voltage mutation on circuit components.

[0049] S500, during the entire voltage switching and maintenance process, the output state of the bus voltage is successively evaluated and adjusted through a feedback mechanism to achieve optimal AC-DC conversion efficiency.

[0050] Specifically, the bus voltage reduction circuit in this embodiment includes an MCU, an optocoupler, two small-signal MOS transistors (Q7 and Q8), fast recovery diodes (D10, D13, D14), an LDO voltage regulator, and related resistors and capacitors. The specific models and connection relationships of these components are as follows:

[0051] MCU (MCU-1): An STM32F103 microcontroller with multiple I / O ports for outputting PWM signals and high / low level commands. MCU-1 controls the rise and fall of the bus voltage by monitoring the output voltage status of ports C1 and C2.

[0052] Optocoupler: A TLP250 optocoupler is used. Its input is connected to the IO port of MCU-1, and its output is connected to MOS transistors Q7 and Q8. The optocoupler isolates the signal path between the MCU and the MOS transistors and forwards level signals based on the received MCU instructions.

[0053] MOS transistor Q7: The small-signal MOS transistor Q7 (such as the IRF9530) receives signals from the optocoupler. When the optocoupler transmits a high voltage of 3V, MOS transistor Q7 turns on. The voltage regulator LDO charges capacitor C9 through fast recovery diode D10, keeping MOS transistor Q7 in the high-voltage on state. When the optocoupler transmits a low voltage of 0V, MOS transistor Q7 turns off. Capacitor C9 discharges to ground through resistors R39 and R35, keeping MOS transistor Q7 in the low-voltage off state. By adjusting the duty cycle of the PWM signal output by the MCU, the on and off states of Q7 can be precisely controlled, thereby regulating the bus voltage.

[0054] MOS transistor Q8: The small-signal MOS transistor Q8 (such as the IRF530) receives signals from the optocoupler. When the optocoupler transmits a high voltage level of 3V, MOS transistor Q8 turns on. The voltage regulator LDO charges capacitor C15 through resistor R12, Zener diode ZD2, and fast recovery diode D14, keeping MOS transistor Q8 in the high-voltage on state. When the optocoupler transmits a low voltage level of 0V, MOS transistor Q8 turns off. Capacitor C11 discharges to ground through fast recovery diode D13 and resistor R35, keeping MOS transistor Q8 in the low-voltage off state. By adjusting the duty cycle of the PWM signal output by the MCU and the parameters of R12, C11, and D13, the on and off states of Q8 can be precisely controlled, thereby regulating the bus voltage.

[0055] Fast recovery diodes (D10, D13, D14): Fast recovery diodes, such as the 1N4148, are used to form the charge and discharge loop. The fast recovery characteristics of these diodes help reduce energy loss during voltage switching and improve circuit efficiency.

[0056] A TLV7031 LDO regulator is used to provide a stable low-voltage source for the optocoupler, MOSFET, and associated resistors and capacitors. The LDO's output voltage is 10V, ensuring stable operation in all circuit modes.

[0057] Resistors (R12, R35, R39) and capacitors (C9, C11, C15): These resistors and capacitors form different feedback paths, controlling the on and off states of the MOS transistors. The parameters of R12, C11, and D13 need to be optimized based on the specific application scenario to achieve precise control of the bus voltage.

[0058] Furthermore, when the output voltages of ports C1 and C2 are both less than 16V or when no device is in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler turns off, and both MOS transistors Q7 and Q8 are turned off. At this point, the bus voltage drops from 31V to 22V and then to 17V through the feedback mechanism. During this process, the voltage regulator LDO discharges capacitor C9 through resistors R39 and R35, keeping MOS transistor Q7 in the off state. Simultaneously, the voltage regulator LDO discharges capacitor C11 through fast recovery diode D13 and resistor R35, keeping Q8 in the off state. The discharge process of capacitors C9 and C11 ensures a smooth drop in the bus voltage, reducing the impact of sudden voltage changes on circuit components.

[0059] Furthermore, when the output voltage of either port C1 or C2 is detected to be greater than or equal to 16V, the IO port of MCU-1 outputs a high level of 3V, the optocoupler is fully turned on, and both MOS transistors Q7 and Q8 are turned on. At this point, the bus voltage rises from 17V to 22V and then to 31V through the feedback mechanism. During this process, the LDO regulator charges capacitor C9 via fast recovery diode D10, keeping Q7 on. Simultaneously, the LDO regulator charges capacitor C15 via resistor R12, Zener diode ZD2, and fast recovery diode D14, keeping MOS transistor Q8 on. The charging process of capacitors C9 and C15 ensures a smooth rise in the bus voltage, improving AC-DC conversion efficiency.

[0060] Furthermore, MCU-1 controls the on-time of MOS transistors Q7 and Q8 by adjusting the duty cycle of the PWM signal, thereby achieving precise regulation of the bus voltage. When the bus voltage needs to drop from 31V to 17V, MCU-1 outputs a low-duty-cycle PWM signal, keeping MOS transistors Q7 and Q8 in the off-state for a longer period of time at a low level. When the bus voltage needs to rise from 17V to 31V, MCU-1 outputs a high-duty-cycle PWM signal, keeping MOS transistors Q7 and Q8 in the on-state for a longer period of time at a high level. This precise regulation of the PWM signal enables smooth switching between different operating modes, ensuring circuit stability and efficiency.

[0061] Furthermore, the feedback resistor (R11 in parallel with R36 and R27) and capacitors C9, C11, and C15 together form a feedback path, which is used to sequentially evaluate and adjust the bus voltage output state. When the bus voltage needs to drop to 17V, the feedback resistor's resistance is minimum, resulting in a Vout output voltage of 17V. When the bus voltage needs to rise to 31V, the feedback resistor's resistance is large, resulting in a Vout output voltage of 31V. This feedback mechanism monitors bus voltage changes in real time and makes adjustments accordingly, ensuring optimal AC-DC conversion efficiency in different operating modes.

[0062] Furthermore, the value of resistor R12 needs to be optimized based on the specific application scenario. In this embodiment, the value of R12 is 10kΩ to ensure that when MOS transistor Q8 is turned on, the voltage regulator LDO charges C15 through R12, ZD2, and D14 at an appropriate speed, neither too fast to cause a voltage surge nor too slow to affect the response speed of voltage regulation. The value of capacitor C11 is selected to be 100nF to ensure that when MOS transistor Q8 is turned off, C11 discharges to ground through D13 and R35 at an appropriate speed, maintaining a smooth voltage transition. The selection of D13 and D14 should take into account their fast recovery characteristics to ensure that energy loss is reduced during the voltage switching process.

[0063] The benefit of this embodiment is that, through sophisticated circuit design and feedback mechanism, a single-stage PFC architecture is implemented for efficient voltage regulation in PD fast-charging products, ensuring the stability and energy efficiency of the product in different operating modes. In particular, under no-load or light-load conditions, the bus voltage can be reduced to 17V, significantly reducing no-load power consumption and meeting the energy efficiency requirements of Energy Efficiency Regulation VI. When the load is heavy, the bus voltage can be increased to 31V, improving the AC-DC conversion efficiency, reducing the operating temperature of the product, and ensuring the service life of the product.

[0064] Through this embodiment, the invention not only solves the problem that the single-stage PFC architecture cannot achieve different AC-DC bus voltage outputs in PD fast charging products, but also further improves the performance of the circuit through fine regulation and feedback mechanisms.

[0065] Example 2

[0066] In order to solve the problem of efficiency degradation caused by excessive temperature during the bus voltage boosting process of a single-stage PFC architecture in PD fast charging products, this embodiment further optimizes the method of monitoring the circuit temperature through an ambient temperature detector and dynamically adjusting the PWM signal duty cycle to ensure that the circuit conversion efficiency is optimized under high temperature conditions.

[0067] In this embodiment, MCU-1 connects to an ambient temperature detector via an AD interface to monitor circuit temperature changes in real time. When the output voltage of ports C1 / C2 is detected to be greater than or equal to 16V, MCU-1's IO port outputs a high level of 3V, fully conducting the optocoupler, MOSFETs Q7 and Q8, and the bus voltage gradually increases from 17V to 22V and then to 31V. The output signal of the ambient temperature detector is proportional to the circuit temperature, varying by 10mV per degree Celsius. MCU-1 calculates the current ambient temperature by reading the voltage value of the AD interface and dynamically adjusts the duty cycle of the PWM signal based on the temperature.

[0068] Furthermore, when the ambient temperature detector detects that the circuit temperature is high, MCU-1 will appropriately reduce the duty cycle of the PWM signal, such as Figure 2 As shown, this reduces the MOS transistor's on-time and the bus voltage's ramp-up rate, thereby reducing circuit power consumption and heat generation. This dynamic adjustment strategy allows the circuit to maintain a low operating temperature even under high-temperature conditions, preventing performance degradation and component damage caused by overheating. It's important to understand that temperature monitoring and duty cycle adjustment are implemented through an algorithm that calculates based on preset temperature thresholds and the PWM signal frequency to ensure accurate and timely duty cycle adjustments.

[0069] Furthermore, when the ambient temperature sensor detects a low circuit temperature, MCU-1 appropriately increases the duty cycle of the PWM signal, accelerating the bus voltage ramp-up and improving the circuit's response speed and energy efficiency. This adjustment strategy not only optimizes circuit performance across varying temperature conditions but also ensures efficient operation under no-load or light-load conditions. As can be seen, the coordinated operation of the temperature sensor and MCU-1 allows the circuit to maintain stable conversion efficiency under a wide range of environmental conditions.

[0070] The benefit of this embodiment is that by incorporating an ambient temperature sensor and dynamically adjusting the PWM signal's duty cycle based on the temperature, the circuit's performance is optimized under high-temperature conditions, improving conversion efficiency and stability while reducing power consumption and heat generation. Furthermore, this approach ensures fast response and high energy efficiency at low temperatures, making it suitable for a variety of operating environments.

[0071] Example 3

[0072] In order to solve the problem that the single-stage PFC architecture is easily affected by noise when detecting the output voltage of C1 / C2 port in PD fast charging products, such as Figure 3 As shown, this embodiment further optimizes the detection accuracy, adopts a dual-channel differential amplifier to improve the detection accuracy, and prevents erroneous operation caused by noise interference.

[0073] In this embodiment, the output voltage of ports C1 / C2 is amplified and processed by a dual-channel differential amplifier. The amplified signal is then transmitted to the AD interface of MCU-1 for precise detection. The effective gain of the dual-channel differential amplifier can be adjusted according to actual needs to improve the sensitivity and accuracy of output voltage detection. When MCU-1 detects that the output voltage of either port C1 / C2 is greater than or equal to 16V, the IO port of MCU-1 outputs a high level of 3V, the optocoupler is fully turned on, and MOS transistors Q7 and Q8 are also turned on. The bus voltage is gradually increased from 17V to 22V, and then to 31V.

[0074] Furthermore, to ensure detection accuracy, the low-noise, high-precision LM358 dual-channel differential amplifier is used. The two channels of the LM358 are connected to the output voltages of ports C1 and C2, respectively. Using differential amplification technology, the two voltage signals are compared and amplified, effectively suppressing noise interference. MCU-1 reads the amplified voltage signals via the AD interface to accurately determine the output voltage status of ports C1 and C2. If the output voltages of ports C1 and C2 are both less than 16V or are in standby mode, the MCU-1 IO port outputs a low level of 0V, the optocoupler turns off, MOSFETs Q7 and Q8 are turned off, and the bus voltage is reduced to 17V through a feedback mechanism.

[0075] Furthermore, to prevent malfunctions caused by noise interference, MCU-1 can filter the amplified voltage signal after receiving it. The filtering algorithm can employ a digital filter, such as a low-pass filter, to further improve detection accuracy. It should be understood that the combination of a dual-channel differential amplifier and a filtering algorithm not only improves detection accuracy but also enhances circuit stability, particularly in complex electromagnetic environments.

[0076] This embodiment benefits from using a dual-channel differential amplifier to improve output voltage detection accuracy, effectively preventing malfunctions caused by noise interference and ensuring circuit reliability and stability. Furthermore, high-precision voltage detection facilitates more precise voltage regulation, improving AC-DC conversion efficiency and meeting the energy efficiency requirements of Regulation VI.

[0077] Example 4

[0078] In order to solve the power loss problem of the single-stage PFC architecture when the bus voltage is switched in PD fast charging products, this embodiment further optimizes the charging and discharging time of capacitors C9 and C11, and adopts a time adjustment algorithm to reduce the power loss during the voltage switching process.

[0079] In this embodiment, MCU-1 uses a time adjustment algorithm to calculate the charge and discharge times of capacitors C9 and C11 during bus voltage switching to optimize the voltage switching process. When the output voltages of ports C1 and C2 are both less than 16V or when no device is in standby mode, MCU-1's IO port outputs a low level of 0V, the optocoupler turns off, and MOS transistors Q7 and Q8 are both turned off. At this point, the bus voltage gradually decreases from 31V to 22V, and then to 17V. The expression for the time adjustment algorithm is:

[0080] , where T min is the minimum charge and discharge time of the capacitor, f is the PWM signal frequency, V th is the voltage threshold, V in is the input voltage, and V out is the output voltage.

[0081] MCU-1 further calculates the current capacitor charge and discharge time by reading the output voltage of ports C1 / C2. When the output voltage of either port C1 / C2 is detected to be greater than or equal to 16V, MCU-1's IO port outputs a high level of 3V, fully turning on the optocoupler, and subsequently MOSFETs Q7 and Q8. At this point, the bus voltage gradually increases from 17V to 22V, and then to 31V. Using a time adjustment algorithm, MCU-1 can precisely control the charge and discharge times of capacitors C9 and C11, ensuring smooth and low-loss switching.

[0082] Furthermore, the timing adjustment algorithm takes into account not only the voltage difference but also the PWM signal frequency. By adjusting the PWM signal frequency, MCU-1 can further optimize the capacitor's charge and discharge time, reducing heat and power loss during the charge and discharge process. It's important to understand that this algorithm not only improves voltage switching efficiency but also extends the capacitor's lifespan and enhances the stability of the entire circuit.

[0083] The benefit of this embodiment is that by introducing a time adjustment algorithm to optimize the capacitor's charge and discharge times, it significantly reduces power loss during voltage switching, improving the circuit's energy efficiency and stability. Furthermore, this algorithm effectively reduces heat generated during the charge and discharge process, extending the circuit's service life and making it suitable for high-frequency switching applications.

[0084] Example 5

[0085] In order to solve the problem of conversion efficiency fluctuation in the single-stage PFC architecture during the voltage switching transition process in PD fast charging products, this embodiment further optimizes the method of stabilizing the conversion efficiency by adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit, and adopts a duty cycle optimization algorithm to achieve the goal.

[0086] In this embodiment, MCU-1 detects the output voltage of C1 / C2 port in real time through AD interface and dynamically adjusts the duty cycle of PWM signal and related resistance value according to the detection result. The duty cycle optimization algorithm is expressed as:

[0087] , where D opt represents the optimal PWM duty cycle, V load is the load voltage, V offset is the voltage offset, V input is the input voltage, V output is the output voltage, and K is the comparator gain factor. MCU-1 uses this algorithm to calculate the optimal PWM duty cycle, thereby stabilizing the conversion efficiency during the voltage switching process.

[0088] Furthermore, when MCU-1 detects that the output voltage of port C1 / C2 is less than 16V or that no device is in standby mode, the IO port outputs a low level of 0V, the optocoupler turns off, and both MOS transistors Q7 and Q8 are turned off. The bus voltage gradually decreases from 31V to 22V and then to 17V. MCU-1 reads the output voltage of port C1 / C2 through the AD interface and calculates the optimal PWM duty cycle based on a duty cycle optimization algorithm, thereby maintaining stable conversion efficiency during the voltage switching process.

[0089] Furthermore, in order to further improve the conversion efficiency, MCU-1 can also adjust the load voltage V load and voltage offset V offset Dynamically adjust the resistance value in the circuit. This can be achieved using a digital potentiometer, such as the AD5206. The digital potentiometer is connected to MCU-1 via the SPI interface, allowing MCU-1 to adjust the resistance value as needed to optimize circuit performance. It's important to understand that this dynamic adjustment strategy not only improves the circuit's conversion efficiency but also enhances its adaptability under varying load conditions.

[0090] The benefit of this embodiment is that by introducing a duty cycle optimization algorithm and dynamically adjusting the resistance value, the stability of the conversion efficiency during the voltage switching process is significantly improved, the efficiency fluctuation is reduced, and the overall performance of the circuit is improved. In addition, this optimization method also enables the circuit to maintain high conversion efficiency under different load conditions, such as Figure 4 shown.

[0091] Example 6

[0092] In order to solve the problem of excessive power consumption in the standby state of the single-stage PFC architecture in PD fast charging products, this embodiment further optimizes the deep sleep mechanism when entering the standby state, maintains the bus voltage at 17V, and meets the requirements of energy efficiency standard VI by reducing the standby power consumption. Figure 5 As shown, a transient voltage suppression circuit is added to the control circuit to protect circuit components from damage caused by voltage transients.

[0093] In this embodiment, MCU-1 automatically activates the deep sleep mechanism when it detects that the output voltage of ports C1 / C2 is less than 16V or when no device is in standby mode. In deep sleep mode, MCU-1's IO ports output a low level of 0V, the optocoupler turns off, and both MOS transistors Q7 and Q8 are turned off. At this point, the bus voltage is reduced to 17V through a feedback mechanism, reducing power consumption in standby mode. After entering deep sleep, MCU-1 shuts down most internal functional modules to further reduce power consumption.

[0094] Furthermore, in order to protect circuit components from damage during voltage transients, this embodiment incorporates a transient voltage suppression (TVS) circuit into the control circuit. The TVS circuit uses a fast-response transient voltage suppressor, such as the SM110CA model. When a circuit voltage transient occurs, the TVS suppressor responds quickly, clamping the voltage within a safe range to prevent damage to circuit components due to overvoltage. Figure 6 As shown in the figure, MCU-1 monitors the output voltage and circuit temperature of C1 / C2 ports and can activate the TVS circuit when necessary to ensure safe operation of the circuit.

[0095] Furthermore, MCU-1 switches from deep sleep mode to normal operation mode when it detects that the output voltage of either port C1 or C2 is greater than or equal to 16V. During this switching process, MCU-1 reads the voltage clamping status of the TVS circuit through the AD interface to ensure a smooth increase in bus voltage. It is important to understand that the combination of this deep sleep mechanism and the TVS circuit not only significantly reduces standby power consumption but also protects circuit components from damage caused by voltage transients, thereby improving circuit reliability and safety.

[0096] The benefit of this embodiment is that by introducing a deep sleep mechanism and a transient voltage suppression circuit, the power consumption in the standby state is significantly reduced, meeting the requirements of energy efficiency standard VI. In addition, the addition of the TVS circuit effectively protects circuit components from damage by transient voltages.

[0097] Example 7

[0098] In order to solve the problem of low conversion efficiency of the single-stage PFC architecture under different PD voltage charging conditions in PD fast charging products, this embodiment further optimizes the method of dynamically adjusting the PWM signal and related resistance values through an adaptive control algorithm, realizes the optimization of the adaptive response under different load conditions, and improves the AC-DC conversion efficiency.

[0099] In this embodiment, MCU-1 monitors circuit performance parameters, including load voltage, current, and temperature, in real time via an AD interface. Based on these parameters, MCU-1 dynamically adjusts the PWM signal duty cycle and associated resistance values using an adaptive control algorithm to optimize conversion efficiency under varying PD charging voltages. By monitoring circuit performance parameters under varying load conditions, the adaptive control algorithm adjusts the control strategy to ensure high conversion efficiency across all operating states.

[0100] Furthermore, when the output voltage of ports C1 / C2 is detected to be less than 16V or when no device is in standby mode, MCU-1's IO port outputs a low level of 0V, the optocoupler turns off, MOS transistors Q7 and Q8 are both turned off, and the bus voltage drops to 17V through a feedback mechanism. When MCU-1 enters standby mode, it shuts down most internal functional modules to reduce power consumption. If the output voltage of either port C1 / C2 is detected to be greater than or equal to 16V, MCU-1 switches from standby mode to normal operation, at which point the adaptive control algorithm takes effect.

[0101] Furthermore, the adaptive control algorithm calculates the optimal PWM signal duty cycle and resistance value by analyzing the load voltage, current, and temperature. MCU-1 connects to a digital potentiometer via the SPI interface to dynamically adjust the resistance value, thereby optimizing circuit performance. For example, when the load increases, MCU-1 increases the PWM signal duty cycle, increasing the speed at which the bus voltage rises. When the load decreases, MCU-1 decreases the PWM signal duty cycle, slowing the speed at which the bus voltage rises to minimize power loss. It is important to understand that this adaptive control strategy enables the circuit to dynamically adjust parameters based on actual operating conditions, ensuring high conversion efficiency under varying load conditions.

[0102] The benefit of this embodiment is that, by introducing an adaptive control algorithm and a digital potentiometer, it optimizes the adaptive response to varying PD voltage charging conditions, significantly improving AC-DC conversion efficiency. Furthermore, this dynamic adjustment method not only improves the circuit's adaptability and flexibility, but also ensures its stability under various operating conditions.

[0103] Example 8

[0104] In order to solve the problem of accurate control of the MOS tube driving state during the bus voltage rise and fall process in the single-stage PFC architecture of PD fast charging products, this embodiment proposes a bus voltage reduction circuit using a single-stage PFC architecture, such as Figures 7 to 9 As shown, the coordinated work of the optocoupler and MOS tubes Q7 and Q8 ensures that the rise and fall of the bus voltage is accurate and smooth.

[0105] In this embodiment, MCU-1 is responsible for outputting PWM signals and high / low level commands, controlling the rise and fall of the bus voltage based on the detected output voltage status of ports C1 / C2. An optocoupler connects MCU-1 and MOS transistors Q7 and Q8, isolating the signal path and ensuring the reliability and security of signal transmission. When MCU-1 detects that the output voltage of ports C1 / C2 is less than 16V or that no device is in standby mode, the MCU-1 IO port outputs a low level of 0V, the optocoupler turns off, and MOS transistors Q7 and Q8 are both turned off. At this point, the bus voltage gradually decreases from 31V to 17V, first to 22V and then to 17V.

[0106] Furthermore, MOS transistor Q7 receives the signal from the optocoupler. When the optocoupler transmits a high level, MOS transistor Q7 is turned on, and the voltage regulator LDO charges capacitor C9 through diode D10. When the optocoupler transmits a low level, MOS transistor Q7 is turned off, and capacitor C9 is discharged to the ground through resistors R39 and R35. Figure 9 As shown, the charge and discharge state of capacitor C9 is precisely controlled by the duty cycle of the PWM signal, ensuring that the driving state of MOS transistor Q7 is always optimal. It should be understood that this design improves the reliability and stability of the circuit through the isolation effect of the optocoupler and the precise control of the MOS transistor.

[0107] Furthermore, MOS transistor Q8 receives the signal from the optocoupler. When the optocoupler transmits a high level, MOS transistor Q8 is turned on, and the voltage regulator LDO charges capacitor C15 through resistor R12, voltage regulator ZD2 and fast recovery diode D14. When the optocoupler transmits a low level, MOS transistor Q8 is turned off, and capacitor C11 is discharged to ground through fast recovery diode D13 and resistor R35. Figure 9 As shown, the charge and discharge states of capacitor C11 are controlled not only by the duty cycle of the PWM signal but also by adjusting the parameters of resistor R12, capacitor C11, and fast recovery diode D13 to ensure that MOS transistor Q8 does not conduct when the voltage of capacitor C11 is less than the threshold voltage of 5.1V of Zener diode ZD2. It can be understood that this multi-parameter adjustment strategy enables the circuit to maintain high conversion efficiency and stable output voltage under various operating conditions.

[0108] The benefit of this embodiment is that the coordinated operation of the optocoupler and MOS transistor enables precise control of the bus voltage rise and fall process, improving the reliability and stability of the circuit. In addition, by optimizing the multi-parameters of the capacitor charge and discharge state, the circuit ensures efficient conversion and low power consumption in different operating modes, making it suitable for high-performance PD fast charging applications.

[0109] Embodiment 9

[0110] In order to solve the problems of system function integrity and reliability in the bus voltage regulation process of the single-stage PFC architecture in PD fast charging products, this embodiment proposes a bus voltage reduction system using a single-stage PFC architecture. By integrating the power adapter, load device, temperature monitoring module and transient voltage protection module, it ensures the high efficiency and low power consumption characteristics of the system in any working mode.

[0111] In this embodiment, the bus voltage reduction circuit serves as the core of the system. MCU-1 detects the output voltage of ports C1 / C2 in real time via an AD interface and controls the bus voltage rise and fall process based on the detection results. An optocoupler connects MCU-1 and MOS transistors Q7 and Q8 to isolate the signal path and ensure the reliability and security of signal transmission. When the output voltage of ports C1 / C2 is detected to be less than 16V or when no device is in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler turns off, MOS transistors Q7 and Q8 are both turned off, and the bus voltage gradually decreases from 31V to 17V, first to 22V and then to 17V.

[0112] Furthermore, the system includes a power adapter connected to the bus voltage step-down circuit to provide a stable input voltage. The power adapter utilizes a switching power supply design, maintaining a stable 24V output voltage to ensure proper operation of the system under various input voltage conditions. Load devices are connected to the system via the C1 / C2 ports. The MCU-1 detects the load device's needs and dynamically adjusts the PWM signal's duty cycle and bus voltage to meet voltage requirements under varying load conditions. It's important to understand that this dynamic adjustment strategy enables the system to maintain efficient energy conversion under varying load conditions.

[0113] Furthermore, the system integrates a temperature monitoring module, which uses a temperature sensor to monitor circuit temperature in real time and feeds this data back to the MCU-1. The MCU-1 adjusts the duty cycle of the PWM signal based on this temperature data to optimize conversion efficiency under high-temperature conditions. Furthermore, the system incorporates a transient voltage protection module, which uses a transient voltage suppressor (TVS) to protect circuit components from voltage transients. The transient voltage protection module uses a fast-response TVS suppressor, such as the SM110CA model. When a circuit voltage transient occurs, the TVS suppressor responds quickly, clamping the voltage within a safe range and preventing damage to circuit components due to overvoltage. As can be seen, the addition of the temperature monitoring module and transient voltage protection module further enhances system safety.

[0114] The benefit of this embodiment lies in the integration of a power adapter, load device, temperature monitoring module, and transient voltage protection module to create a complete bus voltage reduction system, achieving efficient energy conversion and stable voltage output under varying load conditions. Furthermore, the system's multi-module collaboration improves overall reliability and safety, making it suitable for a variety of complex charging scenarios.

[0115] Example 10

[0116] In order to solve the high efficiency and low standby power consumption problems of the power adapter in the single-stage PFC architecture of PD fast charging products, this embodiment further optimizes the design of the power adapter. By adopting a bus voltage reduction system, efficient energy conversion, low standby power consumption and compliance with the requirements of Energy Efficiency Regulation VI are achieved.

[0117] In this embodiment, the power adapter integrates a bus voltage reduction system. MCU-1 detects the output voltage of ports C1 / C2 in real time via the AD interface and controls the rise and fall of the bus voltage based on the detection results. An optocoupler connects MCU-1 and MOS transistors Q7 and Q8 to isolate the signal path and ensure the reliability and security of signal transmission. When the output voltage of ports C1 / C2 is detected to be less than 16V or when no device is in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler turns off, MOS transistors Q7 and MOS transistors Q8 are both turned off, and the bus voltage gradually decreases from 31V to 17V, first to 22V and then to 17V.

[0118] Furthermore, the power adapter utilizes a multi-stage filtering design to ensure the purity and stability of the output voltage. The primary filter utilizes an LC filter, while the secondary filter utilizes an RC filter. This multi-stage filter design effectively removes high-frequency noise and electromagnetic interference from the input voltage. This design not only improves the output quality of the power adapter but also extends the lifespan of the load device. It is important to understand that this multi-stage filter design enables the power adapter to maintain stable performance in complex electromagnetic environments.

[0119] Furthermore, the power adapter also integrates a variety of safety protection mechanisms, including over-temperature protection, overvoltage protection and short-circuit protection. Over-temperature protection is achieved through a temperature sensor integrated inside the power adapter. When it is detected that the temperature exceeds the preset threshold, the MCU-1 will automatically reduce the duty cycle of the PWM signal to reduce power consumption and heat. Overvoltage protection is achieved through the voltage regulator LDO and the fast recovery diode D14. When the output voltage exceeds the set value, the voltage regulator LDO will automatically adjust the output to keep the voltage within a safe range. Short-circuit protection is achieved through the current detection module. When it is detected that the load current exceeds the safety threshold, the MCU-1 will automatically cut off the output to prevent damage to the load equipment and the power adapter. It can be understood that the addition of these protection mechanisms significantly improves the safety and reliability of the power adapter.

[0120] The benefit of this embodiment is that, by integrating a high-performance bus voltage reduction system, it achieves efficient energy conversion and low standby power consumption in the power adapter, complying with the requirements of Energy Efficiency Regulation VI. Furthermore, the multi-stage filtering design and the inclusion of multiple safety protection mechanisms further enhance the output quality and safety of the power adapter.

[0121] The above embodiments further illustrate the objectives, technical solutions and beneficial effects of the present invention. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the present invention should be included in the scope of protection of the present invention.

Claims

1. A bus voltage reduction method using a single-stage PFC architecture, applied to a bus voltage reduction circuit, the bus voltage reduction circuit comprising an MCU for outputting PWM signals and high / low level commands, an optocoupler connected to the MCU, and MOS transistors Q7 and Q8 connected to the optocoupler. When the optocoupler transmits a high level, the MOS transistor Q7 is turned on, and the voltage regulator LDO charges the capacitor C9 through the diode D10. When the optocoupler transmits a low level, the MOS transistor Q8 is turned off, and the capacitor C11 is discharged to ground through the fast recovery diode D13 and the resistor R35. The method is characterized in that: The steps of the bus voltage reduction method include: Detect the output voltage of the C1 / C2 port in the circuit to determine whether the output voltage is less than a preset threshold of 16V. The C1 / C2 port represents the two pins used for power handshake in the Type-C USB interface. When it is detected that the output voltage is less than the preset threshold value of 16V or no device is connected in standby mode, the output IO is set to a low level through the MCU instruction to trigger the voltage reduction mechanism of the circuit, reducing the bus voltage from 31V to 22V and then to 17V; When it is detected that any end of the output voltage is greater than or equal to the preset threshold value of 16V, the output IO is set to a high level of 3V through the MCU instruction to maintain the bus voltage rising to 22V and then to 31V; By adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit, the voltage switching transition process is controlled to smoothly switch between different operating modes and reduce the impact of voltage mutations on circuit components; During the entire voltage switching and maintenance process, the output state of the bus voltage is evaluated and adjusted successively through the feedback mechanism; The output IO is set to a low level through the MCU instruction. During the process, a time adjustment algorithm is used to optimize the charging and discharging time of the capacitors C9 and C11. The expression of the time adjustment algorithm is: , where T min is the minimum charge and discharge time of the capacitor, f is the PWM signal frequency, V th is the voltage threshold, V in is the input voltage, and V out is the output voltage; The transition process of controlling the voltage switching by adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit adopts a duty cycle optimization algorithm, and the expression of the duty cycle optimization algorithm is: , where D opt represents the optimal PWM duty cycle, V load is the load voltage, V offset is the voltage offset, V input is the input voltage, V output is the output voltage, and K is the comparator gain factor.

2. The bus voltage reduction method using a single-stage PFC architecture according to claim 1, characterized in that: In the process of maintaining the bus voltage rising to 22V and then rising to 31V, the temperature of the circuit is monitored by an ambient temperature detector, and the duty cycle of the PWM signal is dynamically adjusted according to the temperature change.

3. The bus voltage reduction method using a single-stage PFC architecture according to claim 1, characterized in that: In the step of detecting the output voltage of the C1 / C2 port in the circuit, a dual-channel differential amplifier is used to improve detection accuracy.

4. The bus voltage reduction method using a single-stage PFC architecture according to claim 1, characterized in that: The method further comprises the following steps: When entering the standby state, the deep sleep mechanism is automatically activated to maintain the bus voltage at 17V; A transient voltage suppression circuit is added to the control circuit to protect circuit components when the voltage rises or drops instantly.

5. The bus voltage reduction method using a single-stage PFC architecture according to claim 1, characterized in that: An adaptive control algorithm is used to dynamically adjust the PWM signal and related resistance values based on the current operating state of the circuit to adaptively respond to different PD voltage charging conditions. The adaptive control algorithm includes adjusting the control strategy by monitoring the performance parameters of the circuit under different load conditions.

6. A bus voltage reduction circuit using a single-stage PFC architecture, used to implement the bus voltage reduction method using a single-stage PFC architecture as claimed in any one of claims 1 to 5, characterized in that: The bus voltage reduction circuit includes: The MCU is used to output PWM signals and high / low level commands, and controls the rise and fall of the bus voltage according to the output voltage status of the detected C1 / C2 ports; An optocoupler connected to the MCU, and MOS transistors Q7 and Q8 connected to the optocoupler, the optocoupler being used to isolate the signal path between the MCU and the MOS transistors Q7 and Q8, and forwarding level signals according to received MCU instructions; The MOS transistor Q7 receives the signal transmitted from the optocoupler. When the optocoupler transmits a high level, the MOS transistor Q7 is turned on, and the voltage regulator LDO charges the capacitor C9 through the diode D10. When the optocoupler transmits a low level, the MOS transistor Q7 is turned on and off, and the capacitor C9 is discharged to the ground through the resistors R39 and R35. The charging and discharging state of the capacitor C9 is controlled by adjusting the PWM duty cycle to ensure the driving state of the MOS transistor Q7. The MOS transistor Q8 receives a signal transmitted from the optocoupler. When the optocoupler transmits a high level, the MOS transistor Q8 is turned on, and the voltage regulator LDO charges the capacitor C15 through the resistor R12, the voltage regulator ZD2, and the fast recovery diode D14. When the optocoupler transmits a low level, the MOS transistor Q8 is turned off, and the capacitor C11 is discharged to ground through the fast recovery diode D13 and the resistor R35. The charge and discharge state of the capacitor C11 is controlled by adjusting the PWM duty cycle and the parameters of the resistor R12, the capacitor C11, and the fast recovery diode D13 to ensure that the MOS transistor Q8 is not turned on when the voltage of the capacitor C11 is less than the threshold voltage of the voltage regulator ZD2, 5.1V. The bus voltage rise and fall process includes: When the output voltage of C1 / C2 port is less than 16V or there is no device in standby mode, the MCU outputs a low level of 0V, and the bus voltage drops from 31V to 17V, first to 22V and then to 17V. When the output voltage of any port C1 / C2 is greater than 16V, the MCU outputs a high level of 3V, and the bus voltage remains at 31V or increases from 17V to 31V. The boost process first increases to 22V and then to 31V.

7. A bus voltage reduction system using a single-stage PFC architecture, comprising the bus voltage reduction circuit using a single-stage PFC architecture according to claim 6, characterized in that: The system also includes a power adapter, a load device, a temperature monitoring module and a transient voltage protection module connected to the bus voltage reduction circuit. The bus voltage reduction system automatically adjusts the bus voltage according to the needs of the load device.

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