Oscillator frequency based on mobility and PTAT temperature compensation

Abstract

The invention relates to oscillator frequency based on mobility and PTAT temperature compensation. In an example, a system (100) includes a first transistor (102) having a first terminal coupled to a current mirror (126), and a control terminal coupled to a first current source (116) and a resistor (120). The system (100) includes a second transistor (104) having a first terminal coupled to the current mirror (126), a second terminal coupled to the second terminal of the first transistor (102), and a control terminal coupled to the resistor (120) and a second current source (118). The system (100) includes a third transistor (106) having a first terminal coupled to the voltage terminal (122), a second terminal coupled to the control terminal of the second transistor (104), and a control terminal coupled to the first terminal of the second transistor (104). The system (100) includes a fourth transistor (108) having a control terminal coupled to the current mirror (126), a first terminal and a second terminal coupled to each other and to the second terminal of the first transistor (102).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Indian Provisional Patent Application No. 202341058650 filed on September 1, 2023, titled “IMPROVED ACCURACY OF OSCILLATORFREQUENCY BASED ON MOBILITY AND PTAT TEMPERATURE COMPENSATION”, which is hereby incorporated herein by reference in its entirety. Background Art

[0003] An oscillator is an electronic circuit that produces a periodic signal (such as a sine wave, square wave, or triangle wave) at a given frequency. Linear or harmonic oscillators produce sine waves or near-sine waves. Relaxation oscillators produce non-sinusoidal output signals, such as square waves, triangle waves, or sawtooth waves. The frequency of many relaxation oscillators is proportional to the resistance and capacitance in the electronic circuit. Summary of the invention

[0004] According to at least one example described, a system includes a first transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to a current mirror, and the control terminal being coupled to a first current source and a resistor. The system also includes a second transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror, the second terminal being coupled to the second terminal of the first transistor, and the control terminal being coupled to the resistor and the second current source. The system includes a third transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to a voltage terminal, the second terminal being coupled to the control terminal of the second transistor, and the control terminal being coupled to the first terminal of the second transistor. The system includes a fourth transistor having a control terminal and a first terminal and a second terminal, the control terminal being coupled to the current mirror, the first terminal and the second terminal being coupled to each other, and being coupled to the second terminal of the first transistor and the second terminal of the second transistor.

[0005] According to at least one example described, a system includes a first transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to a current mirror, and the control terminal being coupled to a first current source and a resistor. The system also includes a second transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror, the second terminal being coupled to the second terminal of the first transistor, and the control terminal being coupled to the resistor and the second current source. The system includes a third transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to a voltage terminal, the second terminal being coupled to the control terminal of the second transistor, and the control terminal being coupled to the first terminal of the second transistor. The system includes a fourth transistor having a control terminal and a first terminal and a second terminal, the control terminal being coupled to the current mirror, the first terminal and the second terminal being coupled to each other, and being coupled to the second terminal of the first transistor and the second terminal of the second transistor. The system also includes a comparator having a comparator output and a first comparator input and a second comparator input, wherein the control terminal of the fourth transistor is coupled to the first comparator input.

[0006] According to at least one example described, a system includes a first transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to a current mirror, and the control terminal being coupled to a first current source and a resistor, the first current source being configured to provide a proportional to absolute temperature (PTAT) current. The system also includes a second transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror, the second terminal being coupled to the second terminal of the first transistor, and the control terminal being coupled to the resistor and the second current source. The system includes a third transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to a voltage terminal, the second terminal being coupled to a control terminal of the second transistor, and the control terminal being coupled to the first terminal of the second transistor. The system also includes a fourth transistor having a control terminal and a first terminal and a second terminal, the control terminal being coupled to the current mirror, the first terminal and the second terminal being coupled to each other, and being coupled to the second terminal of the first transistor and the second terminal of the second transistor, the fourth transistor being configured to receive a first current from the current mirror at its control terminal. The system includes a comparator having a comparator output and first and second comparator inputs, wherein a control terminal of the fourth transistor is coupled to the first comparator input, and wherein the comparator is configured to compare a voltage at the control terminal of the fourth transistor to a reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is the core of a relaxation oscillator having a frequency that depends on electron mobility according to various examples.

[0008] Figure 2 is a relaxation oscillator according to various examples.

[0009] Figure 3 are graphs of waveforms of relaxation oscillators according to various examples.

[0010] Figure 4 Circuits of a relaxation oscillator with a frequency that depends on electron mobility with universal temperature compensation according to various examples.

[0011] Figure 5 Methods for providing an oscillating output signal according to various examples.

[0012] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar (in function and / or structure) features. DETAILED DESCRIPTION

[0013] A relaxation oscillator is a nonlinear oscillator that produces a non-sinusoidal output signal, such as a triangular wave or a square wave. A relaxation oscillator typically uses a switching device (such as a transistor or a comparator) that repeatedly charges and discharges a capacitor or inductor through a resistor. The frequency of the oscillator depends on the time constant of the circuit. The time constant characterizes the response of the circuit to a step input. In a resistor-capacitor (RC) based oscillator, the time constant and frequency of the oscillator are proportional to the values ​​of R and C.

[0014] In some semiconductor manufacturing processes, the value of a resistor may vary from the designed value by 10-15%. The value of a capacitor may vary from the designed value by 10%. The combined changes in resistance and capacitance may cause the frequency of the oscillator to vary by about 25%. In order to improve the frequency of the oscillator in response to these changes, fine-tuning bits may be useful. However, fine-tuning bits use additional area on the chip, fine-tuning circuitry, memory cells, and other components. Fine-tuning bits also increase test time and test costs.

[0015] In the examples herein, a relaxation oscillator architecture is described in which the frequency of the oscillator depends on electron mobility (μ) rather than R and C. Electron mobility is a single parameter rather than two parameters (such as R and C) and is easier to control for a given manufacturing process. The examples herein also describe circuits that can compensate for various temperature coefficients of the manufacturing process. The examples herein show a relaxation oscillator that produces a square wave, but other examples can produce other types of oscillating output signals.

[0016] Figure 1The core 100 of a relaxation oscillator according to various examples herein, whose frequency depends on electron mobility. In an example, a circuit provides a current to a transistor configured as a capacitor (e.g., a metal oxide semiconductor (MOS) capacitor). Temperature changes are offset by using a proportional to absolute temperature (PTAT) bias current in the core 100. In other examples described below, a divider in the oscillator circuit produces a linear temperature coefficient, which can be compensated by changing the reference voltage of the oscillator proportionally to the temperature.

[0017] Core 100 includes transistors 102, 104, 106, 108, 110, 112, and 114. Core 100 also includes current sources 116 and 118 and resistor 120. Core 100 includes voltage terminals 122 and 124. Core 100 includes current mirror 126. Also shown in core 100 are a number of currents, such as currents 128, 130, 132, 134, and 136.

[0018] In core 100, transistors 102, 104, 106, 108, 110, 112, and 114 are field effect transistors (FETs). In one example, the transistors may be metal oxide semiconductor FETs (MOSFETs). In other examples, other types of transistors may be useful. In this example, transistors 102, 104, 106, and 108 are n-channel FETs, and transistors 110, 112, and 114 are p-channel FETs. For transistors described herein, a gate terminal may be referred to as a control terminal. A source terminal and a drain terminal of a transistor may be referred to as a first terminal or a second terminal (or vice versa) in this article.

[0019] Transistor 102 has a gate, a source, and a drain. The gate (e.g., a control terminal) is coupled to a first terminal of current source 116 and a first terminal of resistor 120. The drain (e.g., a first terminal) of transistor 102 is coupled to transistor 110 in current mirror 126. The source (e.g., a second terminal) of transistor 102 is coupled to voltage terminal 124, current source 118, the source of transistor 104, and the source and drain of transistor 108. Voltage terminal 124 can provide a voltage VSS, which can be any suitable value, including ground.

[0020] Transistor 104 has a gate (e.g., a control terminal) coupled to a second terminal of resistor 120, a first terminal of current source 118, and a source of transistor 106. A drain (e.g., a first terminal) of transistor 104 is coupled to a gate of transistor 106 and transistor 112 in current mirror 126. A source (e.g., a second terminal) of transistor 104 is coupled to voltage terminal 124, a second terminal of current source 118, a source of transistor 102, and a source and drain of transistor 108.

[0021] In this example, transistor 106 is configured as a source follower. Transistor 106 has a gate (e.g., a control terminal) coupled to the drain of transistor 104 and transistor 112 in current mirror 126. The drain (e.g., a first terminal) of transistor 106 is coupled to voltage terminal 122. The source (e.g., a second terminal) of transistor 106 is coupled to a first terminal of current source 118.

[0022] Transistor 108 has a gate (e.g., a control terminal) coupled to the drain of transistor 114 in current mirror 126. Transistor 108 has a drain (e.g., a first terminal) and a source (e.g., a second terminal) coupled to each other and to voltage terminal 124. Transistor 108 is configured as a MOS capacitor. One terminal of the MOS capacitor is the gate of transistor 108, and the other terminal is the source and drain of transistor 108. The capacitance of the MOS capacitor depends on the voltage at the gate terminal. In one example, the source and drain of transistor 108 can be coupled to ground.

[0023] Transistors 110, 112, and 114 form a current mirror 126. Transistor 110 has a gate (e.g., a control terminal) coupled to a gate of transistor 112 and a drain (e.g., a first terminal) of transistor 110. Transistor 110 has a source (e.g., a second terminal) coupled to voltage terminal 122. Transistor 112 has a gate (e.g., a control terminal) coupled to the gates of transistors 110 and 114. Transistor 112 has a drain (e.g., a first terminal) coupled to a gate of transistor 106 and a drain of transistor 104. Transistor 112 has a source (e.g., a second terminal) coupled to voltage terminal 122. Transistor 114 has a gate (e.g., a control terminal) coupled to a gate of transistor 112. Transistor 114 has a drain (e.g., a first terminal) coupled to a gate of transistor 108. Transistor 114 has a source (e.g., a second terminal) coupled to voltage terminal 122.

[0024] First current source 116 has a first terminal coupled to the gate of transistor 102 and resistor 120. First current source 116 has a second terminal coupled to voltage terminal 122. Second current source has a first terminal coupled to the source of transistor 106 and a second terminal coupled to voltage terminal 124. Resistor 120 has a first terminal coupled to the gate of transistor 102 and a second terminal coupled to the gate of transistor 104.

[0025] In this example, the voltage terminal provides a voltage V DD , and the voltage terminal 124 provides a voltage V SS In one example, V SSThe first current source 116 provides a PTAT current (I PTAT ) current 134. Second current 118 provides current 136. Current 136 can be greater than current 134, such as at least twice as much as current 134 in one example. In one example, transistors 110, 112, and 114 are approximately the same size. In one example, the width-to-length ratio of transistor 104 is approximately four times the width-to-length ratio of transistor 102.

[0026] In an example operation, the current mirror provides currents 128, 130, and 132. These currents are similar in magnitude and may have a value I1. Current sources 116 and 118 provide bias currents that bias transistors 102 and 104, and current source 118 provides a bias current for transistor 106. Current 132 is provided to transistor 108, i.e., a MOS capacitor. The voltage at the gate of transistor 108 is provided to a comparator ( Figure 1 ), and the switch ( Figure 1 (not shown) charges and discharges the MOS capacitor to provide an oscillating output signal. Figure 2 Describe switches and comparators and their operation.

[0027] Core 100 is capable of generating an oscillating signal having a frequency based on electron mobility (μ) based on the following equations. In these equations, transistor 102 is referred to as MN1, transistor 104 is referred to as MN2, transistor 110 is referred to as MP1, and transistor 112 is referred to as MP2. Figure 1 , the current through transistor MP2 (transistor 112) is current 130. This current is defined in equation (1):

[0028]

[0029] In equation (1), μ is the electron mobility of the process, c OX is the oxide capacitance of the process, W MN1 is the width of transistor 102 (MN1), L MN1 is the length of transistor 02, V gs2 is the gate-to-source voltage of transistor 104 (MN2), and V th is the threshold voltage of transistor 104. As described above, in this example, the W / L ratio of transistor 104 is four times the W / L ratio of transistor 102, so 4W MN1 =W MN2 , and L MN1 =L MN2 .

[0030] Equation (2) is the current through MP1 (transistor 110):

[0031]

[0032] As shown in equation (2), the voltage value in brackets now includes I PTAT The current (current 134) is multiplied by resistance R, which is the resistance of resistor 120. Current mirror 126 provides that currents 128 and 130 are equal, and therefore I MP1 =I MP2 The difference between the gate-to-source voltage of transistor 102 and transistor 104 is I PTAT R. Because I MP1 =I MP2 , so equation (2) can be rewritten as equation (3):

[0033]

[0034] As described above, transistor 108 is configured as a MOS capacitor. The capacitance value of the MOS capacitor may be referred to herein as C1. The capacitance value C1 is given by equation (4):

[0035] C1=C OX (W C1 *L C1 ) (4)

[0036] In equation (4), c OX is the oxide capacitance of the process, W C1 is the width of the MOS capacitor (transistor 108), and L C1 is the length of the MOS capacitor. The voltage increment (eg, voltage change) ΔV across the MOS capacitor caused by the current 132 flowing into the MOS capacitor C1 Given by equation (5):

[0037]

[0038] Among them I MP1 is the value of current 132, C1 is the capacitance value from equation (4), and t is the time. Substituting I in equation (5) MP1 and C1, we get equation (6):

[0039]

[0040] Where R1 is the value of resistor 120. Rewriting equation (6) to solve for frequency f (eg, 1 / t) yields equation (7):

[0041]

[0042] In equation (7), the frequency f depends on the electron mobility μ and the bias current I PTAT, both of which vary with temperature. The temperature variation can be accounted for by using a temperature proportional bias current (I PTAT ) to offset, as shown in the following equation. First, the electron mobility μ of the example manufacturing process described in this article is about 2.2. Therefore, the electron mobility μ and its relationship with temperature are shown in equation (8):

[0043] μ=μ o *T -2.2 (8)

[0044] where μ o is the standard electron mobility and T is the temperature. PTAT The current is shown in equation (9):

[0045]

[0046] Where ΔV BE is proportional to the temperature T. In addition, according to equation (9), (ΔV BE ) 2 With temperature T 2 According to equation (6), if the electron mobility μ is proportional to T -2.2 Proportional, and I PTAT 2 With T 2 Proportional (via ΔV BE ), then V C1 With T -0.2 is proportional to the bias current I. Therefore, temperature compensation is achieved. PTAT The temperature changes of are approximately offset. Equation (6) can be rewritten as equation (10):

[0047]

[0048] Equation (7) can be rewritten as equation (11):

[0049]

[0050] If the temperature coefficient of the manufacturing process is about 2 (e.g., about 2.2 in one example), then the above process provides temperature compensation. However, other processes may have different temperature coefficients. If the temperature coefficient of the process is different from 2, then alternative circuits may be used to provide temperature compensation. Figure 4 An alternative circuit to compensate for various temperature coefficients is described.

[0051] Figure 22 is a relaxation oscillator 200 according to various examples herein. The relaxation oscillator 200 includes many of the components of the core 100 described above, and includes additional components, such as comparators and switches, to produce an oscillating output. The oscillating output in this example is a square wave, which can be programmed to have various duty cycles. Other types of oscillating outputs can be produced in other examples.

[0052] Relaxation oscillator 200 includes transistors 102, 104, 106, 108, 110, and 112. Relaxation oscillator 200 also includes current sources 116 and 118 and resistor 120. Relaxation oscillator 200 includes voltage terminals 122 and 124. Also shown in relaxation oscillator 200 are a number of currents, such as currents 128, 130, 134, and 136.

[0053] The relaxation oscillator 200 also includes transistors 202, 204, 206, and 208. In this example, transistors 202 and 204 are p-channel FETs, and transistors 206 and 208 are n-channel FETs. The relaxation oscillator 200 includes switches 210 and 212. The relaxation oscillator 200 includes a current mirror 214. The relaxation oscillator 200 includes a comparator 216 having a first comparator input 218A, a second comparator input 218B, and a comparator output 220. The relaxation oscillator 200 includes an inverter 222 having an inverter input 224 and an inverter output 226. The relaxation oscillator 200 also includes switches 228 and 230, voltage terminals 232 and 234 (e.g., voltage reference terminals), and currents 236, 238, and 240.

[0054] The components of the relaxation oscillator 200 found in the core 100 are as described above with respect to Figure 1 These components include transistors 102, 104, 106, 108, 110, and 112, current sources 116 and 118, resistor 120, voltage terminals 122 and 124, and currents 128, 130, 134, and 136. Additional components of relaxation oscillator 200 are described below.

[0055] Transistor 202 has a control terminal (e.g., a gate) coupled to the control terminals of transistors 112 and 204, a first terminal (e.g., a drain) coupled to the first terminal of switch 210, and a second terminal (e.g., a source) coupled to voltage terminal 122. Transistor 204 has a control terminal (e.g., a gate) coupled to the control terminal of transistor 202, a first terminal (e.g., a drain) coupled to the first terminal of transistor 208, and a second terminal (e.g., a source) coupled to voltage terminal 122. Transistors 110, 112, 202, and 204 form a current mirror 214. In one example, transistors 110 and 112 are approximately the same size. In one example, transistor 204 can be approximately four times larger than transistor 202.

[0056] Transistor 206 has a control terminal (e.g., a gate) coupled to a control terminal of transistor 208. Transistor 206 has a first terminal (e.g., a drain) coupled to a first terminal of switch 212. Transistor 206 has a second terminal (e.g., a source) coupled to voltage terminal 124 and a second terminal of transistor 208.

[0057] Transistor 208 has a control terminal (e.g., a gate) coupled to its first terminal (e.g., a drain) and a control terminal of transistor 206. Transistor 208 has a first terminal coupled to its control terminal and a first terminal of transistor 204. Transistor 208 has a second terminal (e.g., a source) coupled to voltage terminal 124 and a second terminal of transistor 206. In one example, transistors 206 and 208 are configured as a current mirror.

[0058] Switch 210 has a first terminal coupled to the drain of transistor 202 and a second terminal coupled to the gate of transistor 108. Switch 212 has a first terminal coupled to the drain of transistor 206 and a second terminal coupled to the gate of transistor 108. The gate of transistor 108 is also coupled to comparator 216 (e.g., a second comparator input 218B of comparator 216).

[0059] Comparator 216 has a first comparator input 218A, a second comparator input 218B, and a comparator output 220. First comparator input 218A is coupled to switches 228 and 230. Second comparator input 218B is coupled to the gate of transistor 108 and switches 210 and 212. Comparator output 220 is coupled to inverter input 224.

[0060] Inverter 222 has an inverter input 224 and an inverter output 226. Comparator 216 generates an OUT signal at comparator output 220. The OUT signal is received by inverter 222 at inverter input 224. Inverter 222 generates an OUT_BAR signal at inverter output 226. The OUT and OUT_BAR signals are inverted from each other. As described below, the OUT and OUT_BAR signals are used to switch switches 210, 212, 228, and 230.

[0061] The switch 228 has a first terminal coupled to the first comparator input 218A and a second terminal coupled to a voltage terminal 232. The voltage terminal 232 provides a voltage V REF_HIGH The switch 230 has a first terminal coupled to the first comparator input 218A and a second terminal coupled to a voltage terminal 234. The voltage terminal 234 provides a voltage V REF_LOW Voltage V REF_HIGH and V REF_LOW The duty cycle of the relaxation oscillator 200 is provided as follows.

[0062] In operation, when the voltage at the gate of transistor 108 reaches V REF_HIGH or V REF_LOW When OUT_BAR is on, comparator 216 switches the charging and discharging currents provided to transistor 108. First, the OUT_BAR signal closes switches 210 and 228. The OUT signal opens switches 212 and 320. If switch 210 is closed, current mirror 214 provides current 236 to the gate of transistor 108. In one example, the magnitude of current 236 can be similar to currents 128 and 130. Transistor 108 is a MOS capacitor, so current 236 charges the capacitor. If switch 228 is closed, the voltage value V REF_HIGH Provided to the first comparator input 218A via switch 228. Because V REF_HIGH is a higher value than the charge at the gate of transistor 108 at this time (when transistor 108 is charging), so comparator output 220 provides V at its output REF_HIGH . V REF_HIGH is a static high voltage value, while the voltage value at the second comparator input 218B is a lower but rising value.

[0063] After the current 236 charges the voltage value at the gate of the transistor 108, the voltage value provided to the second comparator input 218B becomes greater than V REF_HIGH , causing comparator output 220 to switch. If comparator output 220 switches, the switches controlled by OUT are closed (switches 212 and 230), and the switches controlled by OUT_BAR are opened (switches 210 and 228). With switch 230 closed and switch 228 open, voltage VREF_LOW is provided to the first comparator input 218A. With switch 212 closed and switch 210 open, transistor 108 stops charging and begins discharging. Current 238 through switch 212 discharges the voltage at the gate of transistor 108. Current 240 flows through transistor 208 to voltage terminal 124, and the current mirror of transistors 206 and 208 also pulls current 238 from the gate of transistor 108 to voltage terminal 124 through switch 212. Thus, current 238 discharges the MOS capacitor of transistor 108.

[0064] During the discharge period, the voltage at the gate of transistor 108 decreases. This voltage is provided to the second comparator input 218B and eventually drops below V REF_LOW The value of V REF_LOW is provided to the first comparator input 218A. If the voltage at the gate of transistor 108 drops below V REF_LOW , then comparator output 220 switches. If comparator output 220 switches, switches 212 and 230 are opened, and switches 210 and 228 are closed. With switch 210 closed, the voltage at the gate of transistor 108 begins to charge again via current 236. With switch 228 closed, voltage V REF_HIGH is provided to the first comparator input 218A. Thus, the charge and discharge cycle repeats and is REF_HIGH and V REF_LOW Switching occurs at the set voltage value.

[0065] Voltage V REF_HIGH and V REF_LOW can be set to any suitable value to provide high and low values ​​for the oscillating output signal of the relaxation oscillator 200. The oscillating output signal is provided at the comparator output 220. The voltage at the gate of transistor 108 charges until it reaches V REF_HIGH , and discharges until it reaches V REF_LOW . The ratio of the sizes of transistors 202 and 204 can be selected to provide a given duty cycle for the oscillating output signal. Current 236 charges transistor 108 and current 240 discharges transistor 108. Therefore, if current 240 is four times greater than current 236, transistor 108 will discharge four times as fast as it charges to provide an 80% duty cycle. In another example, if transistors 202 and 204 are equal in size, then currents 236 and 240 are approximately equal in size. In this example, transistor 108 charges at approximately the same rate as it discharges, providing a 50% duty cycle. Figure 3 Describe example voltage waveforms.

[0066] Figure 33 is a graph 300 of a waveform of a relaxation oscillator according to various examples herein. In one example, the relaxation oscillator can be the relaxation oscillator 200. The graph 300 includes two waveforms, waveform 302 and waveform 304. In the graph 300, the x-axis is time in milliseconds and the y-axis is voltage in volts.

[0067] Waveform 302 is the voltage at the gate of transistor 108, referred to herein as V C1 This is the voltage provided to the second comparator input 218B. V C1 is the voltage that is charged and discharged via switches 210 and 212 as described above. In this example, V C1 Charge to about 3.0V, and discharge to about 1.0V. V REF_HIGH is set to 3.0V, and V REF_LOW is set to 1.0 V. Waveform 302 shows that V C1 Charging is slower than discharging. As mentioned above, the relative lengths of the charge and discharge cycles provide the duty cycle of the oscillating output signal. In this example, a longer charge time creates a higher duty cycle. Figure 3 The example in has a duty cycle of about 80%, so the charging time is four times the discharging time. The charging and discharging times can be set by the relative current values ​​of currents 236 and 240. Figure 2 , since transistor 204 is approximately four times larger than transistor 202, current 240 is approximately four times larger than current 236. Therefore, the duty cycle is 4:1, or 80%.

[0068] In one example, waveform 304 is the voltage V at output 220 of comparator 216. OUT (e.g., OUT signal). Comparator 216 generates an OUT signal that extends between approximately 5.0V and 0.0V. In this example, the OUT signal has an 80% duty cycle. As shown in waveform 304, when V C1 When charging, V OUT is high, and when V C1 When discharging, V OUT is low. When V C1 When charging, the comparator 216 generates a high output signal of 5.0V. C1 When charging is in progress, the signal at the first comparator input 218A is higher than the signal at the second comparator input 218B. C1 When discharging, the comparator 216 generates a low output signal of 0.0V. C1 When discharging, the signal at the first comparator input 218A is lower than the signal at the second comparator input 218B. Therefore, the V C1The charging and discharging cycles produce an oscillating output signal shown as waveform 304.

[0069] Figure 4 A circuit 400 for a relaxation oscillator having a frequency dependent on electron mobility with universal temperature compensation according to various examples herein. In an example, the circuit 400 provides a current to a MOS capacitor. The circuit 400 can compensate for process electron mobility μ that varies with any temperature coefficient. A divider in the oscillator circuit produces a linear temperature coefficient that can be compensated by changing the reference voltage of the oscillator.

[0070] Circuit 400 includes many of the components of core 100 described above, and includes components that compensate for a general temperature coefficient X (rather than the temperature coefficient of about 2 or 2.2 in core 100). Circuit 400 includes transistors 102, 104, 106, 108, 110, and 112. Circuit 400 includes resistor 120 and voltage terminals 122 and 124. Circuit 400 also includes transistors 402, 404, 406, 408, and 410. Circuit 400 includes current sources 412 and 414 and divider 416. Circuit 400 also includes a plurality of currents 418, 420, 422, 424, and 426.

[0071] In this example, transistors 102, 104, 106, and 108 are n-channel FETs, and transistors 110, 112, 402, 404, and 406 are p-channel FETs. In this example, transistors 408 and 410 are bipolar junction transistors (BJTs). The components of the relaxation oscillator 200 found in the core 100 are as described above with respect to Figure 1 These components include transistors 102, 104, 106, 108, 110, and 112, resistor 120, and voltage terminals 122 and 124. Additional components of circuit 400 are described below.

[0072] Circuit 400 includes transistor 402. Transistor 402 has a control terminal (e.g., gate) coupled to the gate of transistor 112. Transistor 402 has a first terminal (e.g., drain) coupled to a first terminal (e.g., collector) of transistor 408. Transistor 402 has a second terminal (e.g., source) coupled to voltage terminal 122.

[0073] Transistor 404 has a control terminal (e.g., a gate) coupled to the gate of transistor 406 and a first terminal (e.g., a drain) of transistor 404. The first terminal of transistor 404 is also coupled to a first terminal (e.g., a collector) of transistor 410. Transistor 404 has a second terminal (e.g., a source) coupled to voltage terminal 122.

[0074] Transistor 406 has a control terminal (eg, gate) coupled to the gate of transistor 404. Transistor 406 has a first terminal (eg, drain) coupled to the gate of transistor 108. Transistor 406 has a second terminal (eg, source) coupled to voltage terminal 122.

[0075] Transistor 408 has a base (eg, a control terminal) coupled to its first terminal (eg, a collector) and to an input of divider 416. Transistor 408 has a first terminal coupled to a first terminal of transistor 402. Transistor 408 has a second terminal (eg, an emitter) coupled to voltage terminal 124.

[0076] Transistor 410 has a base (eg, a control terminal) coupled to the output of divider 416. Transistor 410 has a first terminal (eg, a collector) coupled to a first terminal of transistor 404. Transistor 410 has a second terminal (eg, an emitter) coupled to voltage terminal 124.

[0077] Current source 412 has a first terminal coupled to voltage terminal 122 and has a second terminal coupled to the gate of transistor 102 and resistor 120. Current source 414 has a first terminal coupled to the gate of transistor 104, resistor 120, and the source of transistor 106. Divider 416 has an input coupled to the base of transistor 408 and an output coupled to the base of transistor 410.

[0078] Current 418 is the current (I1) through transistor 102. Current 420 is the current (I OSCO ). Current 422 is the current (I OSC ). Current 424 is the current (I C2 Current 426 is the current supplied to the gate of transistor 108 (I C1 ), which charges the MOS capacitor of transistor 108.

[0079] In one example, the aspect ratios of transistors 110 , 112 , 402 , 404 , and 406 are approximately equal. In one example, the aspect ratio of transistor 104 is four times the aspect ratio of transistor 102 .

[0080] In one example operation, current source 412 generates I ZTC (zero temperature coefficient) current. In this example, I ZTC is the bandgap reference current, as shown in equation (12):

[0081]

[0082] Where V BGis a bandgap voltage reference. In one example, current source 414 generates a current approximately twice that of current source 412. Therefore, the current from current source 414 is as shown in equation (13):

[0083]

[0084] exist Figure 4 In the example, the current 420 is labeled as I OSCO Current 420 is generated by the current mirror of transistors 110 and 112. Current 422 is I OSC , and as shown in equation (14):

[0085] I OSC =I OSCO *T X (14)

[0086] Where X is the temperature index for a given manufacturing process. By using current sources 412 and 414, current 422 (I OSC ) is also shown in equation (15):

[0087]

[0088] Where μ is the electron mobility, X is the process temperature index, C OX is the oxide capacitance of the process, W n1 is the width of transistor 102, L n1 is the length of transistor 102, and I ZTC *R=V BG (from equation (12) above). Therefore, I OSC By V BG / R current is defined, not by Figure 1 The I PTAT Current definition.

[0089] exist Figure 4 In the example, the base-to-emitter voltage (V BE1 ) is defined by equation (16):

[0090] V BE1 =X*V t *ln((I OSCO *T) / I S ) (16)

[0091] Where X is the known temperature index of the process, V t is the thermal voltage of transistor 408, and I s is the saturation current of transistor 408. Because divider 416 divides by X, the base-to-emitter voltage (V BE2) is V BE1 Divide by X, as shown in equation (17):

[0092] V BE2 =V t *ln((I OSCO *T) / I S ) (17)

[0093] Where V t is the thermal voltage of transistor 410, and I s is the saturation current of transistor 410. In one example, transistors 408 and 410 are the same size, and their thermal voltages and saturation currents may also be similar. Therefore, divider 416 divides V BE2 In the case of a known temperature index X, divider 416 can be designed or programmed to divide by the appropriate value of X. Because divider 416 is divided from V BE2 The temperature index X is removed from V BE2 The current (for example, the current 424I C2 ) no longer has a temperature index X. As shown in equation (15) above, current 422 includes T X Component. Current 424 (I C2 ) is no T X The current 422 of the component is shown in equation (18):

[0094]

[0095] Therefore, the temperature index X of the process can be compensated by the circuit 400 .

[0096] The current mirror of transistors 404 and 406 provides a current I to the gate of transistor 108. C2 (current 424), such as Figure 4 The current 426 (I C1 ). The voltage at the gate of transistor 108 changes by ΔV C1 (T) is given by equation (19):

[0097]

[0098] Where W C1 is the width of transistor 108, and L C1 is the length of transistor 108 .

[0099] Figure 5 is a method 500 for providing an oscillating output signal according to various examples herein. The steps of method 500 may be performed in any suitable order. In some examples, the above Figure 2The described hardware components may perform method 500. In some examples, any suitable hardware, software, or digital logic may perform method 500.

[0100] The method 500 begins at 510 where a capacitor is charged with a first current. As an example, the current 236 charges the transistor 108 configured as a MOS capacitor.

[0101] The method 500 continues at 520 where the voltage at the capacitor is provided to a first input of a comparator. In one example, the voltage at the gate of the transistor 108 is provided to a second input 218B of the comparator 216 .

[0102] Method 500 continues at 530 where the comparator compares the voltage at the capacitor to a first reference voltage. The voltage from the MOS capacitor is compared to the voltage at the first input 218A of the comparator 216. At this point, the voltage V REF_HIGH is provided to the first input 218A.

[0103] The method 500 continues at 540 where the comparator switches its output in response to the voltage at the capacitor exceeding the first reference voltage. As the MOS capacitor charges, the voltage at the second input 218B of the comparator 216 increases until it exceeds the voltage V REF_HIGH At this point, the output of the capacitor switches, and the OUT and OUT_BAR signals also switch. In one example, switches 210 and 228 are open, and switches 212 and 230 are closed.

[0104] The method 500 continues at 550 where the capacitor is discharged with a second current. In one example, the second current is the current 238 that flows through the closed switch 212 toward the transistor 206 and then to the voltage terminal 124.

[0105] The method 500 continues at 560 where the voltage at the gate of the transistor 108 is again provided to the second input 218B of the comparator 216 .

[0106] Method 500 continues at 570, where the comparator compares the voltage at the gate of transistor 108 to a second reference voltage. At this point, voltage V REF_LOW is provided to a first input 218A of the comparator 216 .

[0107] The method 500 continues at 580, where the comparator switches its output in response to the voltage at the capacitor falling below the second reference voltage. As the MOS capacitor discharges, the voltage at the second input 218B of the comparator 216 decreases until it falls below the voltage V REF_LOW Thereafter, the output of comparator 216 switches again.

[0108] Although not shown herein, the processor (or controller) may be configured to read and execute computer-readable instructions to perform the examples described herein. For example, the processor may be configured to call and execute instructions stored in a memory. In some examples, the processor may be implemented as a general or custom processor or controller capable of executing instructions stored in a memory. In some examples, the processor may be implemented as an application specific integrated circuit (ASIC). In some examples, the processor may include one or more of a field programmable gate array (FPGA), a central processing unit (CPU), a graphics processor unit (GPU), a digital signal processor (DSP). In some examples, the processor may include a finite state machine (FSM). Other implementations are also possible.

[0109] In some examples, the memory can be integrated with the processor. The memory can be a non-transitory computer-readable medium configured to store various software programs and / or multiple sets of instructions. The memory can be configured to store instructions for implementing the various methods and processes provided according to the various examples of the present description. The memory can be implemented in any manner known in the art.

[0110] In the examples described herein, a relaxation oscillator architecture is described in which the frequency of the oscillator depends on electron mobility (μ) rather than R and C. Electron mobility is a single parameter rather than two parameters (such as R and C) and is easier to control for a given manufacturing process. The examples herein also describe circuits that can compensate for any temperature coefficient of the manufacturing process. The mobility-based oscillator implementation as described herein improves the accuracy of the oscillator. Temperature compensation is integrated inside the circuit to offset changes in electron mobility across temperature. In the examples herein, no external temperature sensor is used for temperature compensation. In addition, since the trimming bits of the oscillator are eliminated, the examples herein provide a reduction in test time, test cost, and circuit area of ​​the oscillator circuit.

[0111] In this description, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B through a direct connection; or (b) in a second example, if the intervening component C does not change the functional relationship between device A and device B, device A is coupled to device B through an intervening component C, so that device B is controlled by device A via the control signal generated by device A.

[0112] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform that function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0113] A circuit or device described herein as including certain components may instead be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be coupled to at least some of the passive elements and / or sources during or after manufacturing (e.g., by an end user and / or a third party) to form the described structure.

[0114] Although certain components may be described herein as components of a particular process technology, these components may be replaced with components of other process technologies. The circuits described herein are reconfigurable to include replacement components, thereby providing functionality that is at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0115] The use of the phrase "ground" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of the present description. In this description, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / -10% of the parameter. Modifications in the described examples are possible, and other examples are possible within the scope of the claims.

[0116] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between device elements, circuit elements, integrated circuits, devices, or semiconductor components, or a terminal thereof. In addition, a voltage rail, or more simply a "rail", may also be referred to as a voltage terminal, and may generally mean a common node or a group of coupled nodes in a circuit that are at the same potential.

Claims

1. A system comprising: a first transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror and the control terminal being coupled to a first current source and a resistor; a second transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror, the second terminal being coupled to the second terminal of the first transistor, and the control terminal being coupled to the resistor and a second current source; a third transistor having a control terminal and a first terminal coupled to a voltage terminal and a second terminal coupled to the control terminal of the second transistor and the control terminal coupled to the first terminal of the second transistor; as well as A fourth transistor has a control terminal coupled to the current mirror and a first terminal and a second terminal coupled to each other and to the second terminal of the first transistor and the second terminal of the second transistor. 2 . The system of claim 1 , wherein the first current source is coupled to the voltage terminal. 3 . The system of claim 1 , wherein the fourth transistor is configured as a metal oxide semiconductor capacitor (MOS capacitor).

4. The system according to claim 1, further comprising: A first switch and a second switch are coupled to the control terminal of the fourth transistor. 5 . The system of claim 4 , wherein the first switch is coupled between the control terminal of the fourth transistor and the current mirror, and the second switch is coupled between the control terminal of the fourth transistor and a second current mirror.

6. The system according to claim 1, further comprising: a fifth transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror, the control terminal being coupled to the first terminal, and the second terminal being coupled to the second terminal of the first transistor and the second terminal of the second transistor; a sixth transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the second current mirror and the second terminal being coupled to the second terminal of the first transistor and the second terminal of the second transistor; as well as A divider is coupled to the control terminal of the fifth transistor and the control terminal of the sixth transistor.

7. The system of claim 6, wherein the fifth transistor and the sixth transistor are bipolar junction transistors.

8. The system of claim 1, wherein the second transistor is larger than the first transistor.

9. The system of claim 1, wherein the second current source is larger than the first current source.

10. A system comprising: a first transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror and the control terminal being coupled to a first current source and a resistor; a second transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror, the second terminal being coupled to the second terminal of the first transistor, and the control terminal being coupled to the resistor and a second current source; a third transistor having a control terminal and a first terminal coupled to a voltage terminal and a second terminal coupled to the control terminal of the second transistor and the control terminal coupled to the first terminal of the second transistor; a fourth transistor having a control terminal coupled to the current mirror and a first terminal and a second terminal coupled to each other and to the second terminal of the first transistor and the second terminal of the second transistor; as well as A comparator having a comparator output and first and second comparator inputs, wherein the control terminal of the fourth transistor is coupled to the first comparator input.

11. The system according to claim 10, further comprising: A first switch and a second switch are coupled to the control terminal of the fourth transistor.

12. The system according to claim 11, further comprising: A third switch and a fourth switch are coupled to the second comparator input, wherein the third switch is coupled to the first voltage reference terminal and the fourth switch is coupled to the second voltage reference terminal.

13. The system of claim 12, further comprising: an inverter coupled to the comparator output.

14. The system of claim 10, further comprising: a fifth transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror, the control terminal being coupled to the first terminal, and the second terminal being coupled to the second terminal of the first transistor and the second terminal of the second transistor; a sixth transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the second current mirror and the second terminal being coupled to the second terminal of the first transistor and the second terminal of the second transistor; as well as A divider is coupled to the control terminal of the fifth transistor and the control terminal of the sixth transistor.

15. A system comprising: a first transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror and the control terminal being coupled to a first current source and a resistor, the first current source being configured to provide a proportional to absolute temperature current, i.e., a PTAT current; a second transistor having a control terminal and a first terminal and a second terminal, the first terminal being coupled to the current mirror, the second terminal being coupled to the second terminal of the first transistor, and the control terminal being coupled to the resistor and a second current source; a third transistor having a control terminal and a first terminal coupled to a voltage terminal and a second terminal coupled to the control terminal of the second transistor and the control terminal coupled to the first terminal of the second transistor; a fourth transistor having a control terminal coupled to the current mirror and a first terminal and a second terminal, the first terminal and the second terminal being coupled to each other and to the second terminal of the first transistor and the second terminal of the second transistor, the fourth transistor being configured to receive the first current from the current mirror at its control terminal; as well as A comparator having a comparator output and a first comparator input and a second comparator input, wherein the control terminal of the fourth transistor is coupled to the first comparator input, and wherein the comparator is configured to compare a voltage at the control terminal of the fourth transistor with a reference voltage.

16. The system of claim 15, wherein the fourth transistor is further configured to provide an oscillating output signal at a control terminal thereof.

17. The system of claim 16, further comprising: A first switch and a second switch are coupled to the control terminal of the fourth transistor.

18. The system of claim 17, further comprising: an inverter coupled to the comparator output.

19. The system of claim 18, wherein the comparator is configured to provide a first output signal and the inverter is configured to provide a second output signal, wherein the first output signal is configured to control the first switch and the second output signal is configured to control the second switch.

20. The system of claim 16, wherein the frequency of the oscillating output signal depends on electron mobility.

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