Mixer second order input intercept temperature compensation

Abstract

The invention relates to mixer second order input intercept temperature compensation. The invention relates to compensation for temperature variation of a mixer. Embodiments herein may include a mixer, a calibration circuit coupled to the mixer, a replica mixer circuit coupled to the calibration circuit, and a temperature compensation circuit coupled to the calibration circuit. The replica mixer circuit may generate or be used to generate a reference voltage that varies with a common mode voltage and / or a threshold voltage of the replica mixer. A reference voltage may be applied to a resistor ladder of the calibration circuit to adjust the bias voltage and compensate for temperature variations. Further, the temperature compensation circuit may generate a temperature coefficient, which may be applied to the current flowing through the calibration circuit to facilitate compensation for the temperature change.

Description

Background Art

[0001] The present disclosure relates generally to mixers of transceivers, and more particularly to compensating for temperature variations at the mixers.

[0002] The mixer of the transceiver may include multiple transistors (e.g., acting as switches). Each of the multiple transistors may be coupled to an impedance. For example, each transistor may receive a positive in-phase component or a negative in-phase component or a positive quadrature component or a negative quadrature component of a local oscillation signal. However, due to the actual (e.g., manufacturing and / or process) differences between transistors, the switch threshold voltage of the transistor may be mismatched, resulting in a second-order nonlinearity in the mixer. Although a calibration circuit (e.g., including a resistor ladder coupled to the transistor) may be used to calibrate the compensation value of the mismatched transistor, the threshold voltage of the transistor and the bias voltage may vary with temperature. In addition, the mixer may experience a rapid drop in performance across temperature. Therefore, it may be desirable to reduce the second-order intercept point (IIP2) variation caused by the operation of the mixer across temperature. Summary of the invention

[0003] The following describes a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented only to provide the reader with a concise summary of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may encompass a number of aspects that may not be described below.

[0004] In one embodiment, an electronic device includes one or more antennas and a mixer coupled to the one or more antennas. The mixer includes: a plurality of transistors; a calibration circuit coupled to the plurality of transistors; a replica mixer circuit coupled to the calibration circuit, the replica mixer circuit including a first transistor and a first voltage buffer; and a temperature compensation circuit coupled to the calibration circuit.

[0005] In another embodiment, the receiver includes a low noise amplifier and a mixer coupled to the low noise amplifier. The mixer includes a plurality of transistors and a calibration circuit coupled to the plurality of transistors, the calibration circuit being configured to calibrate a common mode voltage, a threshold voltage, or both of at least one of the plurality of transistors. In addition, the mixer includes a replica mixer circuit coupled to the calibration circuit, the replica mixer circuit being configured to generate a reference voltage to be applied to the calibration circuit. In addition, the mixer includes a temperature compensation circuit coupled to the calibration circuit, the temperature compensation circuit being configured to generate a temperature coefficient to be applied to the calibration circuit.

[0006] In yet another embodiment, the mixer includes a plurality of transistors and a calibration circuit coupled to the plurality of transistors, the calibration circuit being configured to calibrate a common mode voltage, a threshold voltage, or both of at least one of the plurality of transistors. The mixer also includes a replica mixer circuit coupled to the calibration circuit, the replica mixer circuit being configured to generate a reference voltage to be applied to the calibration circuit, the reference voltage varying with temperature.

[0007] With respect to various aspects of the present disclosure, there may be various improvements to the above-mentioned features. Other features may also be incorporated in these various aspects. These improvements and additional features may exist individually or in any combination. For example, the various features discussed below with respect to one or more embodiments in the illustrated embodiments may be incorporated into any of the above-mentioned aspects of the present disclosure individually or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of the embodiments of the present disclosure, without limiting the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be better understood upon reading the following detailed description and referring to the drawings described below, in which like reference numerals refer to like parts.

[0009] Figure 1 is a block diagram of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 2 According to the embodiments of the present disclosure Figure 1 Functional diagram of electronic equipment;

[0011] Figure 3 According to the embodiments of the present disclosure Figure 1 A schematic diagram of a receiver of an electronic device;

[0012] Figure 4 is a circuit diagram of a mixer having a calibration circuit, a replica mixer, and a temperature compensation circuit according to an embodiment of the present disclosure;

[0013] Figure 5 is a flow chart of a process for determining an analog-to-digital converter (ADC) power value based on a first set of ADC power samples and a second set of ADC power samples to compensate for second-order intermodulation products according to an embodiment of the present disclosure; and

[0014] Figure 6 is a flow chart of a process for determining an ADC power value to compensate for second order intermodulation products based on iterating through a plurality of sets of ADC power samples according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] When introducing the elements of various embodiments of the present disclosure, the articles "one", "an" and "the" are intended to mean one or more elements present in the element. The terms "including", "comprising" and "having" are intended to be inclusive, and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that the reference to "one embodiment" or "embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the features. In addition, specific features, structures or characteristics can be combined in any appropriate manner in one or more embodiments. The use of the terms "roughly", "approximately", "approximately", "close to" and / or "substantially" should be understood to mean including close to a target (e.g., design, value and amount), such as within the limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.). In addition, it should be understood that any exact value, number, measurement value, etc. provided herein can be conceived to include approximate values ​​of these exact values, numbers, measurement values, etc. (e.g., within the limits of suitable or conceivable error). Additionally, the term "set" may include one or more. That is, a set may include a single set of one member, but a set may also include sets of multiple members.

[0016] The present disclosure relates to a mixer of a transceiver of an electronic device, and more specifically to compensating for temperature variations of the mixer. In a transceiver, a mixer implements transmission and reception in a radio frequency (RF) signal by converting the frequency of an incoming signal to different frequencies to facilitate various signal processing operations. However, the switching threshold voltage of one or more transistors of the mixer may be mismatched due to variations between the one or more transistors. Therefore, second-order nonlinearity may be generated in the mixer, thereby affecting the performance of the mixer. In addition, as a solution, a calibration circuit may be used to calibrate compensation values ​​for one or more transistors of the mismatch. However, due to temperature variations causing threshold voltages and bias voltages to change, this solution may be insufficient. Therefore, it may be desirable to generate a reference voltage that tracks or changes with the common-mode voltage and / or threshold voltage of one or more transistors of the mixer.

[0017] Embodiments herein may include a replica mixer circuit and a temperature compensation circuit. The replica mixer circuit may generate or facilitate the generation of a reference voltage that tracks a common-mode voltage and / or a threshold voltage (e.g., varies with, varies directly with) of a replica mixer (e.g., a replica of a transistor of a mixer). The reference voltage may then be applied to a resistor ladder to adjust the threshold voltage and / or bias voltage to compensate for temperature variations. In particular, the gate of the replica mixer may be coupled to the output of a first voltage buffer in a feedback loop so that the source voltage of the replica mixer is equal to the common-mode voltage output by the mixer, and the gate voltage or gate-source voltage of the replica mixer is equal to the sum of the common-mode voltage, the threshold voltage of the replica mixer, and the overdrive voltage or offset voltage. The gate of the replica mixer may be coupled to an input terminal (e.g., a negative terminal) of a second voltage buffer that outputs a reference voltage.

[0018] The temperature compensation circuit can generate a temperature coefficient that can be applied to the current (I out ) to facilitate compensating for temperature changes. The temperature compensation circuit may include a transistor having a gate and a drain coupled to the gate of the transistor of the calibration circuit at a node, and the temperature compensation circuit includes three current sources (bias current source (I b ), pull-up current source (I up ) and the pull-down current source (I dn )). It should be noted that the current in the calibration circuit can be expressed as the sum of the bias current source and the pull-up current source minus the pull-down current source (I b +I up -I dn The pull-up current source and the pull-down current source can be set to be proportional to absolute temperature (PTAT) current sources (I ptat ) and the inversely proportional to absolute temperature (NTAT) current source (I ntat ) or a constant current source (I const ). This allows the temperature compensation circuit to track the temperature and thus compensate for temperature changes.

[0019] Figure 1 is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. The electronic device 10 may include, among other things, one or more processors 12 (collectively referred to herein as a single processor for convenience, which may be implemented in any suitable form of processing circuitry), a memory 14, a non-volatile storage device 16, a display 18, input structures 22, an input / output (I / O) interface 24, a network interface 26, and a power supply 29. Figure 1The various functional blocks shown may include hardware elements (including circuits), software elements (including machine executable instructions), or a combination of hardware and software elements (which may be referred to as logical components). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., through or via another component, a communication bus, a network) to transmit and / or receive signals between each other. It should be noted that Figure 1 This is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10 .

[0020] By way of example, electronic device 10 may include any suitable computing device, including a desktop or laptop computer, a portable electronic or handheld electronic device (such as a wireless electronic device or a smart phone), a tablet computer, a wearable electronic device, and other similar devices. In additional or alternative embodiments, electronic device 10 may include an access point, such as a base station, a router (e.g., a wireless or Wi-Fi router), a hub, a switch, etc. It should be noted that Figure 1 The processor 12 and other related items in the embodiment may be embodied in whole or in part as software, hardware, or both. Figure 1 Other related items in the electronic device 10 may be single independent processing modules, or may be fully or partially integrated into any of the other elements in the electronic device 10. The processor 12 may be implemented using a combination of a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, a gated logic, a discrete hardware component, a dedicated hardware finite state machine, or any other suitable entity that can perform calculations or other manipulations of information. The processor 12 may include one or more application processors, one or more baseband processors, or both, and perform various functions described herein.

[0021] exist Figure 1In the electronic device 10, the processor 12 may be operably coupled to the memory 14 and the non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article including one or more tangible computer-readable media. The tangible computer-readable medium may include the memory 14 and / or the non-volatile storage device 16, individually or collectively, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard drive, and optical disk. In addition, the program (e.g., operating system) encoded on such a computer program product may also include instructions that can be executed by the processor 12 to enable the electronic device 10 to provide various functions.

[0022] In certain embodiments, display 18 may facilitate a user viewing images generated on electronic device 10. In some embodiments, display 18 may include a touch screen that may facilitate a user interacting with a user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light emitting diode (LED) displays, organic light emitting diode (OLED) displays, active matrix organic light emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0023] The input structures 22 of the electronic device 10 may enable a user to interact with the electronic device 10 (e.g., press a button to increase or decrease the volume level). As with the network interface 26, the I / O interface 24 may enable the electronic device 10 to interact with a variety of other electronic devices. In some embodiments, the I / O interface 24 may include an I / O port for a hardwired connection to charge and / or manipulate content using a standard connector and protocol (such as a Lightning connector, a universal serial bus (USB), or other similar connectors and protocols). The network interface 26 may include, for example, one or more interfaces for a personal area network (PAN), such as an ultra-wideband (UWB) or Network; Local Area Network (LAN) or Wireless Local Area Network (WLAN), such as one of the IEEE 802.11x family of protocols (e.g., ) networks; and / or wide area networks (WANs), such as any standards associated with the 3rd Generation Partnership Project (3GPP), including, for example, 3rd Generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), 4th Generation (4G) cellular networks, Long Term Evolution (LET), and / or 4G cellular networks. (LTE) cellular network, Long Term Evolution Licensed Assisted Access (LTE-LAA) cellular network, 5th Generation (5G) cellular network and / or New Radio (NR) cellular network, 6th Generation (6G) or beyond 6G cellular network, satellite network, non-terrestrial network, etc. Specifically, the network interface 26 may include, for example, one or more interfaces for using a cellular communication standard of the 5G specification including a millimeter wave (mmWave) frequency range (e.g., 24.25 gigahertz (GHz) to 300 GHz) that defines and / or implements a frequency range for wireless communication. The network interface 26 of the electronic device 10 may allow communication through the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0024] The network interface 26 may also include, for example, one or more interfaces for: a broadband fixed wireless access network (eg, ), mobile broadband wireless network (mobile ), asynchronous digital subscriber line (e.g., ADSL, VDSL), digital video terrestrial broadcasting Network and its extension DVB handheld devices Networks, ultra-wideband (UWB) networks, alternating current (AC) power lines, etc.

[0025] As shown, the network interface 26 may include a transceiver 30. In some embodiments, all or part of the transceiver 30 may be disposed within the processor 12. The transceiver 30 may support sending and receiving various wireless signals via one or more antennas, and thus may include a transmitter and a receiver. The power supply 29 of the electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0026] Figure 2 According to the embodiments of the present disclosure Figure 1 1 is a functional diagram of an electronic device 10. As shown, the processor 12, memory 14, transceiver 30, transmitter 52, receiver 54 and / or antenna 55 (shown as 55A-55N, collectively referred to as antenna 55) can be directly or indirectly communicatively coupled to each other (e.g., through or via another component, a communication bus, a network) to transmit and / or receive signals between each other.

[0027] The electronic device 10 may include a transmitter 52 and / or a receiver 54, both of which enable, for example, a network (e.g., including a base station or access point) or a direct connection to transmit and receive signals between the electronic device 10 and an external device. As shown, the transmitter 52 and the receiver 54 may be combined into a transceiver 30. The electronic device 10 may also have one or more antennas 55A to 55N electrically coupled to the transceiver 30. Antennas 55A-55N may be configured in an omnidirectional or directional configuration, such as a single beam, a dual beam, or a multi-beam arrangement. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in the antennas 55A-55N of an antenna group or module may be communicatively coupled to a corresponding transceiver 30, and each may emit a radio frequency signal that may be constructively and / or destructively combined to form a beam. The electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas suitable for various communication standards. In some embodiments, transmitter 52 and receiver 54 may send and receive information via other wired or wired systems or components.

[0028] As shown, the various components of the electronic device 10 can be coupled together via a bus system 56. The bus system 56 may include, for example, a data bus and, in addition to the data bus, a power bus, a control signal bus, and a status signal bus. The components of the electronic device 10 may be coupled together or use some other mechanism to receive or provide input to each other.

[0029] Figure 3 8 is a schematic diagram of a receiver 54 (e.g., receiving circuit) that may be part of a transceiver 30 according to an embodiment of the present disclosure. As shown, the receiver 54 may receive received data 80 from one or more antennas 55 in the form of an analog signal. A low noise amplifier (LNA) 81 may amplify the received analog signal to a suitable level for processing by the receiver 54. A mixer 82 may combine the amplified signal with a local oscillator signal 83 from a local oscillator 84 to generate an intermediate or baseband frequency signal, which may include a high frequency component and a low frequency component. A filter 85 (e.g., a filter circuit and / or software) may remove undesirable noise from the signal, such as cross-channel interference. The filter 85 may also remove additional signals at frequencies other than the desired signal received by the one or more antennas 55. The filter 85 may include one or more any suitable filters for removing undesirable noise or signals from the received signal, such as a bandpass filter, a bandstop filter, a low pass filter, a high pass filter, and / or a decimation filter. The filter 85 may filter the high frequency component and pass the low frequency component. The low frequency component may include noise such as nonlinear beat noise which may be referred to as a beat component.

[0030] The demodulator 86 may remove the RF envelope from the filtered signal and / or extract the demodulated signal from the filtered signal for processing. The analog-to-digital converter (ADC) 88 may receive the demodulated analog signal and convert the signal into a digital signal of the incoming data 90 for further processing by the electronic device 10. Additionally, the receiver 54 may include any suitable additional components not shown, or may not include some of the illustrated components, so that the receiver 54 may receive the received data 80 via one or more antennas 55. For example, the receiver 54 may include an additional mixer and / or a digital down converter (e.g., for converting the input signal from an intermediate frequency to a baseband frequency).

[0031] Figure 4 A system including a calibration circuit 100, a replica mixer circuit 102, and a temperature compensation circuit 104 according to an embodiment of the present disclosure Figure 3 82. As illustrated, the mixer 82 may include one or more transistors 106A, 106B, 106C, 106D (collectively referred to herein as transistor 106 for convenience). Each of the transistors 106 may be coupled to impedances 108A, 108B, 108C, and 108D (collectively referred to herein as impedance 108 for convenience). In addition, each of the transistors 106 may receive a positive in-phase component or a negative in-phase component or a positive orthogonal component or a negative orthogonal component of a local oscillator signal. In particular, the local oscillator 84 may generate a plurality of local oscillator signals 83, each of which is phase-shifted relative to each other to generate an in-phase component and a quadrature component. The local oscillator signal 83 may be phase-shifted at 0 volts (by turning off the local oscillator signal 83) and a power supply voltage 119 (V DD ) (by turning on the local oscillator signal 83). The power supply voltage 119 can be a voltage supplied by a power supply such as the power supply 29. Based at least on the local oscillator signal 83, the mixer 82 is operable to upconvert or downconvert the frequency of the input RF signal to facilitate subsequent processing.

[0032] For example, transistor 106A may correspond to the positive in-phase component of the local oscillator signal, transistor 106B may correspond to the negative in-phase component of the local oscillator signal, transistor 106C may correspond to the positive quadrature component, and transistor 106D may correspond to the negative quadrature component. Combining the positive in-phase component and the negative in-phase component and the positive quadrature component and the negative quadrature component may produce a set of signals spanning a 360-degree phase range, which may enable mixer 82 to extract a desired frequency component from the input signal.

[0033] The threshold voltage of transistor 106 may include a voltage level at which transistor 106 switches. When transistors 106 are activated at different or unequal voltage levels, a threshold mismatch may occur. The threshold mismatch may cause second-order nonlinearity in mixer 82. However, calibration circuit 100 (e.g., including resistor ladder 116 coupled to transistor 118) may determine a bias voltage 120 to be applied to calibrate the threshold mismatch and reduce the second-order nonlinearity. Calibration circuit 100 may be coupled to mixer 82, and compensation for the threshold mismatch may be achieved by adjusting circuit parameters to achieve improved linearity.

[0034] In view of the above, Figure 4 An example of a positive in-phase component 110 generated by transistor 106A and a negative in-phase component 112 generated by transistor 106B is shown. Figure 4 As shown in , a threshold mismatch may exist between the positive in-phase component 110 and the negative in-phase component 112. As an example, the first transistor 106A may have a threshold voltage of 100 millivolts, and the second transistor 106B may have a threshold voltage of 110 millivolts. Therefore, the calibration circuit 100 may determine that the bias voltage 120 is 10 millivolts (e.g., the difference between the threshold voltages of the first transistor 106A and the second transistor 106B), and adjust the bias voltage 120 applied to the mixer 82 to reduce or minimize the threshold mismatch between the transistors 106 (e.g., 106A, 106B). It should be noted that the positive in-phase component 110 and the negative in-phase component 112 are used as examples only, and the same techniques may be applied to Figure 4 The positive orthogonal components and / or negative orthogonal components shown in .

[0035] However, the threshold mismatch and bias voltage 120 may fluctuate under varying temperatures. For example, the threshold mismatch may increase at low temperatures and decrease at high temperatures. In addition, the on-resistance (R on ) may determine the out-of-band blocker gain at its input, which may result in different powers of second-order intermodulation (IM2) products and, therefore, corresponding low-frequency components passing through filter 85. Temperature variations may also result in variations in the on-resistance of transistor 106. Post-calibration of the variation in the second-order input intercept point (IIP2) of mixer 82 may vary with the on-resistance of transistor 106, where local oscillator signal 83 has a duty cycle of alpha (α). As an example, equation 1 is shown below, where μ n is the electron mobility and C ox is the oxide capacitance per unit area:

[0036]

[0037] In order to reduce or minimize the effects of temperature changes on mixer 82, it may be desirable to enable the bias voltage to track common-mode voltage 122 (V CM ) and / or threshold voltage (V TH ) (e.g., varies with, varies directly with). Thus, the disclosed embodiments include a replica mixer circuit 102 and a temperature compensation circuit 104 implemented to reduce IIP2 variations of the mixer 82. That is, the replica mixer circuit 102 may generate or enable generation of a reference voltage 124 (V REF ), which can track the common-mode voltage 122 (V CM ) and / or threshold voltage (V TH ). The reference voltage 124 may then be applied to the resistor ladder 116 to adjust the threshold voltage and / or the bias voltage 120 to compensate for temperature variations. Additionally, the temperature compensation circuit 104 may generate a temperature coefficient that may be applied to the current 126 (I out ) to enable determination of the percentage of mismatch variation across temperature and compensation for the temperature variation. It should be understood that while the replica mixer 123 shown replicates one transistor (e.g., 106A), in additional or alternative embodiments, the mixer 82 may include multiple replica mixers 123 to replicate multiple transistors (including 106B, 106C, and / or 106D). Additional details regarding the replica mixer circuit 102 and the temperature compensation circuit 104 will be discussed below.

[0038] The gate of the replica mixer 123 may be coupled to the output of a first voltage buffer 128 (e.g., an operational amplifier, a voltage follower) in a feedback loop. In addition, the drain of the replica mixer 123 may be coupled to the power supply voltage 119, and the source of the replica mixer 123 may be coupled to the input (I0) of the current source 132 and the inverting input terminal (e.g., a negative terminal) of the first voltage buffer 128 at a node 130. The output of the current source 132 may be grounded 134. The first voltage buffer 128 may include a non-inverting input terminal (e.g., a positive terminal) coupled to a common-mode voltage source and an inverting input terminal. The output voltage of the first voltage buffer 128 may be equal to (or approximately equal to) the input voltage of the first voltage buffer 128. Therefore, the output voltage of the first voltage buffer 128 may be equal to the received common-mode voltage (e.g., the input voltage). The common-mode voltage 122 may then be provided as a source voltage for the replica mixer 123. Turning on the replica mixer 123 may include providing a gate (or gate-source) voltage 136 (V G) to drive the replica mixer 123 into the saturation region. The gate voltage 136 may be equal to the common mode voltage 122 of the replica mixer 123, the threshold voltage, and the overdrive voltage or offset voltage (V OD ). As an example, Equation 2 is shown below:

[0039] V G =V CM +V TH +V OD (Equation 2)

[0040] The gate of the replica mixer 123 may be coupled to an inverting input terminal (e.g., a negative terminal) of a second voltage buffer 138 (e.g., an operational amplifier, a voltage follower). The second voltage buffer 138 may also include a non-inverting input terminal (e.g., a positive terminal) coupled to its output via a transistor 140. The gate voltage 136 may be output by the replica mixer 123 and input to the second voltage buffer 138 via the inverting input terminal. The output voltage of the second voltage buffer 138 may be coupled to the gate of the transistor 140. The output voltage may be equal to (or approximately equal to) the input voltage of the second voltage buffer 138. Therefore, the second voltage buffer 138 may receive the gate voltage 136 from the replica mixer 123, and may provide (e.g., output) a reference voltage 124 to the transistor 140. The transistor 140 may have a source coupled to the power supply voltage 119 and a drain coupled to the calibration circuit 100 at a node 142. The reference voltage 124 may have a one-to-one relationship (e.g., proportional) to the gate voltage 136. In addition, the reference voltage 124 may also be equal to the common mode voltage 122, the threshold voltage, and the overdrive voltage or offset voltage (V OD ). As an example, Equation 3 is shown below:

[0041] V REF =V CM +V TH +V OD (Equation 3)

[0042] As observed in Equation 3, the reference voltage 124 can track the common mode voltage 122 and the threshold voltage of the replica mixer 123. That is, changes in the common mode voltage 122 and / or the threshold voltage can correspond to changes in the reference voltage 124. In addition, as described above, the bias voltage 120 can be applied to the mixer 82 to reduce or minimize the threshold mismatch. The bias voltage 120 can be related to the reference voltage 124, as shown in the following Equation 4:

[0043] V B =V REF -I out *R (Equation 4)

[0044] Compensation for temperature variations can be improved by enabling the bias voltage 120 to track the common mode voltage 122 and / or the voltage threshold. Thus, enabling the reference voltage 124 to track the common mode voltage and / or the voltage threshold can enable the bias voltage 120 to be more accurately adjusted by the relationship shown in Equation 4 above. The reference voltage 124 can then be applied to the resistor ladder to adjust the bias voltage 120 and compensate for temperature variations. In this way, threshold mismatch can be minimized.

[0045] As described above, the threshold mismatch may change at various temperatures. Therefore, it may be desirable to determine the amount or percentage of the threshold mismatch at different or various temperatures. As described above, the disclosed embodiments may include a temperature compensation circuit 104 that may generate a temperature coefficient that may be applied to the current 126 (I out ), so that the mismatch variation percentage across temperature can be determined and facilitate compensation for the temperature variation. The mismatch variation percentage can enable determination, adjustment, and / or generation of the current 126 in the calibration circuit 100. The voltage increment (e.g., difference) of the bias voltage 120 from the resistor ladder 116 due to the variation (e.g., temperature variation) can be represented as shown in the following equation 5:

[0046] ΔV b =I out *ΔR (Equation 5)

[0047] The disclosed embodiments may also enable the voltage increment to be determined by selecting the current 126 (I out ) to compensate for the mismatch variation (e.g., by temperature compensation circuit 104, mixer 82, processor 12, etc.). As an example, the threshold mismatch may be positive bias voltage 146 (V bp ) and negative bias voltage 148(V bn ). The positive bias voltage 146 and the negative bias voltage 148 may be selected so that the difference (e.g., the threshold mismatch) is 10 millivolts. For example, the mismatch variation percentage may be determined to be equal to 10% at low temperatures and equal to -10% at high temperatures. Thus, the current 126 may be selected so that the mismatch variation percentage is no greater than 10% at low temperatures and no less than -10% at high temperatures. Additional details regarding the temperature compensation circuit 104 will be discussed below.

[0048] The gate of transistor 118 of calibration circuit 102 may be coupled to the gate and drain of transistor 150 of temperature compensation circuit 104 via node 152. The source of transistor 150 may be grounded 154. Temperature compensation circuit 104 may include bias current source 144 (I b ), pull-up current source 156 (Iup ) and the pull-down current source 158 (I down ). The input of bias current source 144 and the input of pull-up current source 156 may be coupled to supply voltage 119. The output of pull-up current source 156, the input of pull-down current source 158, the output of bias current source 144, the drain of transistor 150, and the gate of transistor 150 may be coupled together via node 160. The output of pull-down current source 158 may be connected to ground 164. Current 126 in calibration circuit 100 may be expressed as shown in Equation 6 below:

[0049] I out =I b +I up -I dn (Equation 6)

[0050] In Equation 6, the pull-up current source 156 and the pull-down current source 158 can be set to be proportional to absolute temperature (PTAT) current sources (I ptat ), and the inversely proportional to absolute temperature (NTAT) current source (I ntat ), or a constant current source (I const The pull-up current source 156 and the pull-down current source 158 may be selected to be equal at room temperature (and to carry (k*I b )), so that the current 126 can be determined by the bias current source 144. Therefore, due to the subtraction, three types of output currents (e.g., PTAT current source, NTAT current source, and constant current source) can be achieved using two types of currents of PTAT current source, NTAT current source, and / or constant current source. In addition, the bias current source 144 (or the bias current source 144 and the pull-up current source 156, or the bias current source 144 and the pull-down current source 158) can be a PTAT current source, an NTAT current source, or a constant current source, but the mismatch variation percentage can be pre-designed. Additional details about this specific implementation will be described below.

[0051] In the first case, such as when the mismatch variation percentage increases with increasing temperature, it may be desirable to apply a PTAT current source to the resistor ladder 116. For example, if the mismatch variation percentage becomes 10% higher at high temperatures and becomes -10% at low temperatures, the current 126 may be equal to the PTAT current source, so that a higher voltage increment may be generated at a higher temperature. Therefore, the bias current source 144 may be a selected constant value, the pull-up current source 156 may be set to be proportional to the PTAT current source, and the pull-down current source 158 may be set to a constant current source. Because the bias current source 144 and the pull-down current source 158 are constant, the current 126 in the calibration circuit 100 and applied to the resistor ladder 116 may be equal to the PTAT current source. As an example, Equation 7 is shown below, where T0 is the initial temperature, ΔT is the change in temperature (the difference between the current temperature and the initial temperature), and k is a coefficient (e.g., factor) used to adjust or calibrate the current measurement result:

[0052]

[0053] In the second case, such as when the mismatch variation percentage decreases with increasing temperature, it may be desirable to apply an NTAT current source to the resistor ladder 116. Thus, the bias current source 144 may be a selected constant value, the pull-up current source 156 may be set to a constant current source, and the pull-down current source 158 may be set to be proportional to the PTAT current source. Because the bias current source 144 and the pull-up current source 156 are constant, the current 126 passing through the calibration circuit 100 and applied to the resistor ladder 116 may be equal to the NTAT current source. As an example, Equation 8 is shown below:

[0054]

[0055] In this manner, the pull-up current source 156 and the pull-down current source 158 may be selected so that the current 126 through the calibration circuit 100 may track the mismatch variation percentage. That is, the current 126 may vary at different temperatures, and thus the selection of the pull-up current source 156 and / or the pull-down current source 158 may enable compensation for the current 126 through the calibration circuit 100. Thus, the temperature compensation circuit 104 may be configured based on the known mismatch variation percentage, so that when the mixer 82 experiences a mismatch, the temperature compensation circuit 104 may output a corresponding compensation current.

[0056] As described herein, using calibration circuit 100 to calibrate compensation values ​​for mismatched transistors can compensate for temperature changes, but such calibration may include determining the analog-to-digital (ADC) output power of a second-order nonlinear tone to select a compensation value (e.g., a calibration code). However, the second-order nonlinear tone may have a power less than or equal to the noise floor, resulting in inaccurate measurement of the tone. One method of detecting the ADC output power is to repeatedly measure the ADC output power and use the average value to improve the signal-to-noise ratio (SNR). Averaging N times improves the SNR by 10*log10(N); however, a prerequisite is to phase align each sample, which may be difficult.

[0057] Thus, the disclosed embodiments may include performing a single-point fast Fourier transform (FFT) (or complex down-conversion with DC averaging) on ​​a plurality of samples to obtain a transform for each of the plurality of samples, phase aligning a set of phases associated with each transform, and averaging each transform to generate an analog-to-digital converter (ADC) power value. In addition, the disclosed embodiments may include generating a compensation value based on the analog-to-digital converter power value, and applying the compensation value to a calibration circuit 100 of the mixer 82 to compensate for second-order intermodulation products.

[0058] In view of the above, Figure 5 1 is a flow chart of a process 200 for determining an (ADC) power value based on a first set of ADC power samples and a second set of ADC power samples to compensate for second-order intermodulation products according to an embodiment of the present disclosure. Any suitable device (e.g., a controller) that can control components of the electronic device 10 (such as the processor 12 or the transceiver 30) can perform the process 200. In some embodiments, the process 200 can be implemented by using the processor 12 or the transceiver 30 to execute instructions stored in a tangible, non-transitory computer-readable medium such as the memory 14 or the storage device 16. For example, the process 200 can be performed at least in part by one or more software components such as an operating system of the electronic device 10, one or more software applications of the electronic device 10, etc. Although the process 200 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps can be performed in an order different from the order shown, and that certain described steps can be skipped or not performed at all.

[0059] The single-point FFT can be determined by using Equation 9 shown below, where IM2 fft is the FFT of the second-order intermodulation product, f0 is the beat frequency, s(n) is the time domain input signal at time index n, T s is the temperature, n is the number of iterations, and k is the index of the frequency component being calculated (as k increases, the frequency of the corresponding component also increases):

[0060]

[0061] The beat frequency of the second order intermodulation product may be received at mixer 82. In some embodiments, the beat frequency may be predefined in mixer 82. Thus, the beat frequency may be known to processor 12. At process block 202, processor 12 determines a subharmonic of the ADC clock. That is, the beat frequency (f0) may be selected by processor 12 as a subharmonic of the ADC clock, where f0=f s / M and M is the number of phases (e.g., phasors, number of ADC power sample sets), which yields Equation 10 shown below:

[0062]

[0063] At process block 204, processor 12 receives a first set of ADC power samples. The first set of ADC power samples may include any suitable number of ADC power samples. For example, the sample size may be equal to 512 samples. Using this sampling scheme, an improved signal-to-noise ratio (SNR) may be achieved. At process block 206, processor 12 performs a first transform on the first set of ADC power samples associated with the first phase set. That is, processor 12 may use the first set of samples to perform Equation 10 and determine IM2 fft In addition, the processor 12 may determine the first phase set associated with the first sample set by executing equation 11 shown below:

[0064]

[0065] At process block 208, processor 12 receives a second set of ADC power samples. At process block 210, processor 12 performs a second transform on the second set of ADC power samples associated with the second phase set. As described above, processor 12 may use the second set of samples to perform Equation 10 and determine IM2 fft In addition, the processor 12 may determine the second phase set associated with the second sample set by executing equation 11 shown above.

[0066] At process block 212, processor 12 rotates the second transform so that the second phase set is aligned with the first phase set (to align with the previous sample). That is, the second transform may be rotated (eg, phase shifted, phase aligned) by equation 12 shown below:

[0067]

[0068] Furthermore, in the case where k is in {1, 2, ..., M}, the minimum index can be found by Equation 13 shown below:

[0069]

[0070] At process block 214, the processor 12 averages (e.g., phase-aligned averages) the second transform with the first transform to generate an ADC power value. That is, the second transform and the first transform values ​​are added and then divided by 2 (for the number of samples) to obtain an average. It should be noted that although process 200 is described using a first set of ADC power samples and a second set of ADC power samples, any suitable number of ADC power samples may be collected and averaged to generate an ADC power value. In this way, the accuracy of the generation of the ADC power value may be improved. Additional details on providing the ADC power value will be provided below. A compensation value may then be generated based on the ADC power value and applied to the calibration circuit 100 of the mixer 82 to compensate for second-order intermodulation products.

[0071] Figure 6 250 is a flow chart of a process for determining an ADC power value to compensate for second-order intermodulation products based on iterating through a plurality of ADC power sample sets according to an embodiment of the present disclosure. Any suitable device (e.g., a controller) that can control components of the electronic device 10 (such as the processor 12 or the transceiver 30) can perform the process 250. In some embodiments, the process 250 can be implemented by using the processor 12 or the transceiver 30 to execute instructions stored in a tangible, non-transitory computer-readable medium such as the memory 14 or the storage device 16. For example, the process 250 can be performed at least in part by one or more software components such as an operating system of the electronic device 10, one or more software applications of the electronic device 10, etc. Although the process 250 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps can be performed in an order different from the order shown, and that certain described steps can be skipped or not performed at all.

[0072] At process block 252, processor 12 determines whether the counting process has been completed, which corresponds to the completion of phase alignment for a specified number (e.g., a predefined number, count) of ADC power samples (e.g., a set of ADC power samples). If processor 12 determines that the counting process is not complete (e.g., at least one of the sets of ADC power samples is not aligned), process 250 may proceed to process block 254. At process block 254, processor 12 receives the set of ADC power samples. As described above, processor 12 performs a single-point FFT on the set of ADC power samples to determine IM2 fft At process block 256, processor 12 determines a phase (eg, an initial phase) associated with the set of ADC power samples. That is, processor 12 may determine the phase (eg, an initial phase) associated with the set of ADC power samples using IM2 fft Equation 11 shown above is executed to determine the phase.

[0073] At process block 258, the processor 12 determines whether the determined phase ends the list of the plurality of phasors. If the processor 12 determines that there are remaining phasors (e.g., additional phasors that are not yet phase aligned), the process 250 may proceed to process block 260. At process block 260, the processor 12 compares the phase increment (e.g., phase difference) between the subharmonic of the ADC clock and each of the plurality of determined phasors. At process block 262, the processor 12 determines the closest phasor. That is, the processor 12 determines which phasor of the plurality of phasors has the smallest phase increment and is therefore closest in value to the subharmonic of the ADC clock. The process 250 may then proceed to process block 258 to determine the closest phasor for each of the plurality of phasors. The process 250 may continuously iterate through process block 258, process block 260, and process block 262 until the processor 12 determines that the phasor has ended.

[0074] Thus, in view of the above, and referring back to process block 258, if at process block 258 the processor 12 determines that no more phasors remain (e.g., the list of the plurality of phasors has ended), the process may proceed to process block 264. At process block 264, the processor 12 rotates the set of ADC power samples having the phasor closest to the subharmonic of the ADC clock to phase align the set of ADC power samples. As described herein, the ADC power samples may be rotated based on equation 12 shown above.

[0075] The process 250 may then proceed to process block 252. At process block 252, the processor 12 determines whether the counting process is complete. If the processor 12 determines that the completion of the phase alignment for the specified number of ADC power samples has been performed, the process 250 may proceed to process block 266. At process block 266, the processor 12 may average the phase-aligned ADC power samples. That is, the processor 12 may add each ADC power sample in the phase-aligned ADC power samples and then divide the added value by the total number of phase-aligned ADC power samples. At process block 268, the processor 12 provides an average ADC power value (e.g., average IM2 intermodulation). The processor 12 may then generate a compensation value based on the average ADC power value and apply the compensation value to the calibration circuit 100 of the mixer 20. It may be difficult to measure the ADC power value in the tone power that is equal to or below the noise floor. Therefore, the disclosed embodiments enable IIP2 calibration to be performed by determining the ADC power value with improved accuracy. Determining the ADC power value with improved accuracy may also enable the processor 12 to drive a minimum search.

[0076] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may allow for various modifications and alternative forms. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but are intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure.

[0077] The technology presented and claimed herein is cited and applied to specific examples of a physical and practical nature that significantly improves the art and is therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended at the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is intended that such elements should be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements should not be interpreted in accordance with 35 U.S.C. 112(f).

[0078] It is understood that the use of personally identifiable information should be subject to privacy policies and practices that are generally recognized to meet or exceed industry or government requirements for maintaining user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of the authorized use should be clearly stated to users.

[0079] In one embodiment, an electronic device may include: a receiver including a mixer and an analog-to-digital converter (ADC), the mixer including a calibration circuit; and one or more processors coupled to the receiver, the one or more processors configured to: receive a first set of ADC power samples from the ADC; perform a first transform on the first set of ADC power samples associated with a first phase set; receive a second set of ADC power samples from the ADC; perform a second transform on the second set of ADC power samples; and apply compensation values ​​based on the first transform and the second transform to the calibration circuit of the mixer to compensate for second-order intermodulation products.

[0080] The one or more processors may be configured to receive a subharmonic of the ADC clock.

[0081] The one or more processors may be configured to receive a closest phasor between the first set of phases and the second set of phases.

[0082] The one or more processors may be configured to rotate the second transform based on a phasor that is closest to a subharmonic of the ADC clock.

[0083] The first transform and the second transform may include a Fast Fourier Transform (FFT).

[0084] The one or more processors may be configured to receive a beat frequency of the second order intermodulation product at the mixer.

[0085] The one or more processors may be configured to receive a subharmonic of the ADC clock corresponding to the beat frequency.

[0086] The one or more processors may be configured to rotate the second transform to align the second set of phases with the first set of phases.

[0087] In an alternative or additional embodiment, a method may include: receiving, via processing circuitry, a set of analog-to-digital converter (ADC) power samples at a mixer; receiving, via processing circuitry, a set of phases associated with the set of ADC power samples; receiving, via processing circuitry, a closest phasor of the set of phases based on a subharmonic of the ADC clock; generating, via processing circuitry, a compensation value based on the set of ADC power samples and the closest phasor; and applying, via processing circuitry, the compensation value to a calibration circuit of the mixer.

[0088] The method may include generating, via the processing circuit, the compensation value including averaging, via the processing circuit, the set of ADC power samples.

[0089] The method may include receiving, via processing circuitry, a beat frequency of second order intermodulation products at a mixer.

[0090] The method may include receiving, via the processing circuit, a subharmonic of the ADC clock, the subharmonic of the ADC clock corresponding to a beat frequency.

[0091] The closest phasor may include a phasor in the set of phasors associated with the phase set that is closest to a subharmonic of the ADC clock.

[0092] The method may include determining, via processing circuitry, a misaligned phasor in a set of phasors associated with the phase set.

[0093] The method may include determining, via the processing circuitry, whether a set of ADC power samples are phase aligned.

[0094] The method may include receiving, via the processing circuit, an additional set of ADC power samples at the mixer based on at least one of the sets of ADC power samples being misaligned.

[0095] In yet another alternative or additional embodiment, one or more non-transitory tangible computer-readable media store instructions configured to cause a processor to: receive a beat frequency of a second-order intermodulation product; receive a subharmonic of an analog-to-digital converter (ADC) clock corresponding to the beat frequency; receive a first set of ADC power samples; perform a first transform on the first set of ADC power samples; receive a first set of phases associated with the first set of ADC power samples; receive a second set of ADC power samples; perform a second transform on the second set of ADC power samples; receive a second set of phases associated with the second set of ADC power samples; rotate the second transform to align the second set of phases with the first set of phases; and generate an ADC power value based on the first transform and the rotated second transform.

[0096] The instructions may be configured to cause the processor to generate an ADC power value by averaging the first transform and the rotated second transform.

[0097] The instructions may be configured to cause the processor to generate a compensation value based on the ADC power value.

[0098] The instructions may be configured to cause the processor to apply the compensation value to a calibration circuit of the mixer to compensate for second order intermodulation products.

Claims

1. An electronic device, comprising: one or more antennas; as well as a mixer coupled to the one or more antennas, the mixer comprising: Multiple transistors; a calibration circuit coupled to the plurality of transistors; a replica mixer circuit coupled to the calibration circuit, the replica mixer circuit comprising a first transistor and a first voltage buffer; and A temperature compensation circuit is coupled to the calibration circuit. 2 . The electronic device of claim 1 , wherein the replica mixer circuit comprises a second voltage buffer, the first transistor being coupled to the second voltage buffer and the first voltage buffer in a feedback loop.

3. The electronic device of claim 2, wherein a gate of the first transistor is coupled to an output of the first voltage buffer, a drain of the first transistor is coupled to a power supply, and a source of the first transistor is coupled to a current source and the first voltage buffer. 4 . The electronic device of claim 2 , wherein a gate of the second transistor is coupled to the second voltage buffer, a drain of the second transistor is coupled to the calibration circuit, and a source of the second transistor is coupled to a power supply. 5 . The electronic device according to claim 1 , wherein the temperature compensation circuit comprises a bias current source, a pull-up current source, and a pull-down current source. 6 . The electronic device of claim 5 , wherein the bias current source and the pull-up current source are coupled to a power source. 7 . The electronic device of claim 5 , wherein the pull-up current source, the pull-down current source, the bias current source, the drain of the first transistor, and the gate of the first transistor are coupled together.

8. A receiver, comprising: Low noise amplifier; as well as A mixer, the mixer being coupled to the low noise amplifier, the mixer comprising: Multiple transistors; a calibration circuit coupled to the plurality of transistors, the calibration circuit configured to calibrate a common mode voltage, a threshold voltage, or both of at least one transistor of the plurality of transistors; a replica mixer circuit coupled to the calibration circuit, the replica mixer circuit configured to generate a reference voltage to be applied to the calibration circuit; and a temperature compensation circuit coupled to the calibration circuit, The temperature compensation circuit is configured to generate a temperature coefficient to be applied to the calibration circuit.

9. The receiver of claim 8, wherein the replica mixer circuit comprises a first transistor, a first voltage buffer, and a second voltage buffer, the first transistor being coupled to the first voltage buffer and to the second voltage buffer in a feedback loop. 10 . The receiver of claim 9 , wherein the first voltage buffer is configured to receive the common mode voltage from a common mode voltage source and provide the common mode voltage to the first transistor.

11. The receiver of claim 9, wherein the first transistor is configured to receive a gate-source voltage comprising a sum of the common mode voltage, the threshold voltage, and an overdrive voltage. 12 . The mixer of claim 11 , wherein the second voltage buffer is configured to receive the gate-source voltage from the first transistor and provide the reference voltage to a second transistor coupled to the calibration circuit.

13. The mixer of claim 12, wherein the reference voltage is proportional to the gate-source voltage.

14. The mixer according to claim 11, wherein the temperature compensation circuit comprises a pull-up current source and a pull-down current source, wherein the pull-up current source and the pull-down current source are each configured It is proportional to a proportional to absolute temperature (PTAT) current source or proportional to an inverse proportional to absolute temperature (NTAT) current source.

15. The mixer of claim 14, wherein the pull-up current source is configured to be proportional to the PTAT current source and the pull-down current source is configured to be proportional to a constant current source, and wherein the temperature compensation circuit is configured to apply the pull-up current source to a resistor ladder of the calibration circuit.

16. The mixer of claim 14, wherein the pull-up current source is configured to be proportional to a constant current source and the pull-down current source is configured to be proportional to the PTAT current source, and wherein the temperature compensation circuit is configured to apply the pull-down current source to a resistor ladder of the calibration circuit.

17. A mixer, comprising: Multiple transistors; a calibration circuit coupled to the plurality of transistors, the calibration circuit configured to calibrate a common mode voltage, a threshold voltage, or both of at least one transistor of the plurality of transistors; as well as A replica mixer circuit is coupled to the calibration circuit, the replica mixer circuit being configured to generate a reference voltage to be applied to the calibration circuit, the reference voltage varying with temperature.

18. The mixer of claim 17, wherein the reference voltage varies with the common mode voltage, the threshold voltage, or both.

19. The mixer of claim 17, wherein the calibration circuit is configured to generate a bias voltage based on the reference voltage and apply the bias voltage to the mixer.

20. The mixer of claim 17, comprising a temperature compensation circuit coupled to the calibration circuit, the temperature compensation circuit configured to generate a temperature coefficient to apply to a current in the calibration circuit based on a mismatch variation percentage.

21. An electronic device, comprising: a receiver comprising a mixer and an analog-to-digital converter (ADC), the mixer comprising a calibration circuit; as well as one or more processors, the one or more processors coupled to the receiver, the one or more processors configured to: receiving a first set of ADC power samples from the ADC; performing a first transform on the first set of ADC power samples associated with a first set of phases; receiving a second set of ADC power samples from the ADC; performing a second transform on the second set of ADC power samples associated with a second set of phases; as well as A compensation value based on the first transform and the second transform is applied to the calibration circuit of the mixer to compensate for second order intermodulation products.

22. The electronic device of claim 21, wherein the one or more processors are configured to receive a subharmonic of the ADC clock.

23. The electronic device of claim 22, wherein the one or more processors are configured to receive a closest phasor between the first set of phases and the second set of phases.

24. The electronic device of claim 23, wherein the one or more processors are configured to rotate the second transform based on a phasor closest to the subharmonic of the ADC clock.

25. The electronic device of claim 21, wherein the first transform and the second transform comprise Fast Fourier Transforms (FFTs).

26. The electronic device of claim 21, wherein the one or more processors are configured to receive a beat frequency of the second-order intermodulation product at the mixer.

27. The electronic device of claim 26, wherein the one or more processors are configured to receive a subharmonic of an ADC clock corresponding to the beat frequency.

28. The electronic device of claim 21, wherein the one or more processors are configured to rotate the second transform to align the second set of phases with the first set of phases.

29. A method comprising: receiving, via processing circuitry, a set of analog-to-digital converter (ADC) power samples at a mixer; receiving, via the processing circuit, a set of phases associated with the set of ADC power samples; receiving, via the processing circuit, a closest phasor based on a subharmonic of an ADC clock and the set of phases; as well as generating, via the processing circuit, a compensation value based on the set of ADC power samples and the closest phasor; as well as The compensation value is applied to a calibration circuit of the mixer via the processing circuit.

30. The method of claim 29, wherein generating, via the processing circuit, the compensation value comprises averaging, via the processing circuit, the set of ADC power samples.

31. The method of claim 29, comprising receiving, via the processing circuit, a beat frequency of a second order intermodulation product at the mixer.

32. The method of claim 31 , comprising receiving, via the processing circuit, a subharmonic of the ADC clock, the subharmonic of the ADC clock corresponding to the beat frequency.

33. The method of claim 29, wherein the closest phasor comprises a phasor in a set of phasors associated with the phase set that is closest to the subharmonic of the ADC clock.

34. The method of claim 29, comprising determining, via the processing circuit, misaligned phasors in a set of phasors associated with the set of phases.

35. The method of claim 29, comprising determining, via the processing circuit, whether a set of ADC power samples are phase aligned.

36. The method of claim 35, comprising receiving, via the processing circuit, an additional set of ADC power samples at the mixer based on at least one of the sets of ADC power samples being misaligned.

37. One or more non-transitory tangible computer readable media storing instructions configured to cause a processor to: Receive the beat frequency of the second-order intermodulation product; receiving a subharmonic of an analog-to-digital converter (ADC) clock corresponding to the beat frequency; receiving a first set of ADC power samples; performing a first transform on the first set of ADC power samples; receiving a first set of phases associated with the first set of ADC power samples; receiving a second set of ADC power samples; performing a second transform on the second set of ADC power samples; receiving a second set of phases associated with the second set of ADC power samples; rotating the second transform to align the second set of phases with the first set of phases; as well as An ADC power value is generated based on the first transform and the rotated second transform.

38. The one or more non-transitory tangible computer readable media of claim 37, wherein the instructions are configured to cause the processor to generate the ADC power value by averaging the first transform and the rotated second transform.

39. The one or more non-transitory tangible computer readable media of claim 37, wherein the instructions are configured to cause the processor to generate a compensation value based on the ADC power value.

40. The one or more non-transitory tangible computer readable media of claim 39, wherein the instructions are configured to cause the processor to apply the compensation value to a calibration circuit of a mixer to compensate for the second-order intermodulation products.

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