Semiconductor device, amplifier and bias circuit
By designing a series-coupled first transistor and second transistor in a semiconductor device, and controlling a specific enable period and delay period, the problem of easy damage to the input and output circuit of the semiconductor chip is solved, and effective protection against voltage surge and overshoot is achieved.
Patent Information
- Application Number
- CN202410759009.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-04
- Filing Date
- 2024-06-13
- Publication Date
- 2025-03-04
AI Technical Summary
The input and output circuit of the semiconductor chip is easily damaged by voltage surge or current surge due to the thinner oxide layer thickness.
A semiconductor device is designed, including a first transistor and a second transistor coupled in series, and through a specific enable and delay period control, it is ensured that the transistor avoids voltage surge or overshoot caused by charge accumulation when on.
Effectively prevent semiconductor devices from being damaged by voltage surge or overshoot, ensuring the stability and reliability of the chip.
Smart Images
Figure CN119561505A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to semiconductor circuit technology, and more particularly to a semiconductor device, an amplifier, and a bias circuit capable of preventing surge or overshoot. Background Art
[0002] With the advancement of semiconductor process technology, the channel length and gate oxide thickness of transistors are also decreasing. Therefore, chips made using advanced processes have advantages such as low power consumption, high component density, and high instruction cycle. However, thinner oxide thickness means lower voltage withstand capability, so transistors in the chip's input and output (I / O) circuits are often damaged by voltage surges or current surges. Summary of the invention
[0003] The present disclosure provides a semiconductor device, which includes a first transistor and a second transistor. The first transistor is used to be turned on in a first enable period. The second transistor is used to be turned on in a second enable period. The first transistor is coupled in series with the second transistor. The first enable period includes a first delay period, a second enable period, and a second delay period arranged in sequence.
[0004] The present disclosure provides an amplifier, which includes a first semiconductor device and a second semiconductor device. The second semiconductor device is coupled to the first semiconductor device. The first semiconductor device and the second semiconductor device each include a first transistor, a second transistor and a third transistor. The first transistor is used to turn on in a first enable period. The second transistor is used to turn on in a second enable period. The third transistor is coupled between the first transistor and the second transistor. The first transistor is used to receive an input signal, and the second transistor is used to generate an output signal. The first enable period includes a first delay period, a second enable period and a second delay period arranged in sequence. The third transistor is turned on at least in the second enable period.
[0005] The present disclosure provides a bias circuit, which includes a semiconductor device, a first voltage generating circuit, a second voltage generating circuit and a third voltage generating circuit. The semiconductor device includes a first transistor, a second transistor and a third transistor. The third transistor is coupled between the first transistor and the second transistor. The first voltage generating circuit is used to output a first switching signal to control the first transistor to be turned on in a first enable period. The second voltage generating circuit is used to output a second switching signal to control the second transistor to be turned on in a second enable period. The third voltage generating circuit is used to output a third switching signal to control the third transistor to be turned on at least in the second enable period. The third voltage generating circuit forms a negative feedback with the third transistor. The first enable period includes a first delay period, a second enable period and a second delay period arranged in sequence.
[0006] One of the advantages of the semiconductor device, amplifier, and bias circuit described above is that they can prevent surges or overshoots. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.
[0008] Figure 2 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device according to an embodiment of the present disclosure.
[0009] Figure 3A is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.
[0010] Figure 3B A schematic diagram of a semiconductor device according to another embodiment of the present disclosure is illustrated.
[0011] Figure 4 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device according to an embodiment of the present disclosure.
[0012] Figure 5 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device according to an embodiment of the present disclosure.
[0013] Figure 6 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device according to an embodiment of the present disclosure.
[0014] Figure 7 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.
[0015] Figure 8 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device according to an embodiment of the present disclosure.
[0016] Fig. 9 is a schematic diagram of an amplifier according to one embodiment of the present disclosure.
[0017] Fig.10 is a schematic diagram of a bias circuit according to one embodiment of the present disclosure. DETAILED DESCRIPTION
[0018] The embodiments of the present disclosure will be described below in conjunction with the relevant drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.
[0019] Figure 1is a schematic diagram of a semiconductor device 10 according to an embodiment of the present disclosure. The semiconductor device 10 includes a first transistor M1 and a second transistor M2. The first transistor M1 and the second transistor M2 are sequentially coupled in series between a power supply terminal VSS and a power supply terminal VDD, wherein the voltage of the power supply terminal VDD is higher than the voltage of the power supply terminal VSS. The first transistor M1 is controlled by a first switching signal VG1, and the second transistor M2 is controlled by a second switching signal VG2. In some embodiments, the first transistor M1 and the second transistor M2 can be implemented by N-type metal-oxide-semiconductor field-effect transistors (NMOSFET, referred to as N-type transistors). In some embodiments where the semiconductor device 10 is used as an input-output (I / O) circuit, the semiconductor device 10 is a bias circuit.
[0020] Also refer to Figure 1 and Figure 2 ,in Figure 2 is a schematic diagram of signal waveforms of a semiconductor device 10 according to an embodiment of the present disclosure. Figure 2 The diagram shows the timing relationship between the following multiple signals and multiple voltages: the first switch signal VG1, the second switch signal VG2, the drain voltage VD1 of the first transistor M1, the drain-gate voltage VDG1 of the first transistor M1, and the gate-source voltage VGS2 of the second transistor M2. The semiconductor device 10 can alternately operate in the receiving mode Rx and the transmitting mode Tx. Before switching from the receiving mode Rx to the transmitting mode Tx, the semiconductor device 10 does not output a signal, so the first switch signal VG1 and the second switch signal VG2 have a low voltage (e.g., a ground voltage) to turn off the first transistor M1 and the second transistor M2.
[0021] When entering the transmission mode Tx, the first switch signal VG1 switches to the first voltage V1 to turn on the first transistor M1, so that the drain of the first transistor M1 is in a low impedance state. The first switch signal VG1 will be maintained at the first voltage V1 during the first enable period TE1. In addition, when the first switch signal VG1 switches to the first voltage V1 and after the first delay period TD1, the second switch signal VG2 switches to the second voltage V2 to turn on the second transistor M2. Since the drain of the first transistor M1 is already in a low impedance state when the second transistor M2 is turned on, the drain of the first transistor M1 will not generate a voltage surge or overshoot caused by charge accumulation.
[0022] When the second switch signal VG2 switches to the second voltage V2 and the second enable period TE2 passes, the semiconductor device 10 ends the transmission mode Tx and enters the reception mode Rx, and the second switch signal VG2 switches to a low voltage to turn off the second transistor M2. When the second switch signal VG2 switches to a low voltage and the second delay period TD2 passes, the first switch signal VG1 switches to a low voltage to turn off the first transistor M1. Since the second transistor M2 is turned off in advance when the first transistor M1 is turned off, the drain of the first transistor M1 does not generate a voltage surge or overshoot caused by charge accumulation.
[0023] The first delay period TD1 and the second delay period TD2 may be the same or different. In some embodiments, the first delay period TD1 and the second delay period TD2 are each between 50 and 200 nanoseconds (ns), but the present disclosure is not limited to this time range. In some embodiments, the first delay period TD1 is longer to wait for the linear regulator LDO that supplies power to the first power supply terminal VDD to enter a stable state, and the second delay period TD2 is shorter to stop the output of the semiconductor device 10 as soon as possible.
[0024] In summary, to prevent the semiconductor device 10 from being damaged by voltage surge or overshoot, the first transistor M1 is used to be turned on in the first enable period TE1, and the second transistor M2 is used to be turned on in the second enable period TE2, wherein the first enable period TE1 includes a first delay period TD1, a second enable period TE2, and a second delay period TD2 arranged in sequence. In addition, in some embodiments, the first voltage V1 is lower than the breakdown voltage of the first transistor M1 and higher than the critical voltage of the first transistor M1, so the absolute value of the drain-gate voltage VDG1 of the first transistor M1 is kept lower than the absolute value of the breakdown voltage of the first transistor M1.
[0025] Figure 3A is a schematic diagram of a semiconductor device 30 according to an embodiment of the present disclosure. The semiconductor device 30 includes a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1, the third transistor M3, and the second transistor M2 are sequentially coupled in series between a power supply terminal VSS and a power supply terminal VDD, that is, the third transistor M3 is coupled between the first transistor M1 and the second transistor M2. In some embodiments, the first transistor M1, the second transistor M2, and the third transistor M3 can be implemented by N-type transistors. The first transistor M1, the second transistor M2, and the third transistor M3 are controlled by a first switching signal VG1, a second switching signal VG2, and a third switching signal VG3, respectively. Figure 1 Similar to the semiconductor device 10, in some embodiments, Figure 3A The semiconductor device 30 is a bias circuit.
[0026] Also refer to Figure 3A and Figure 4 ,in Figure 4 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device 30 according to an embodiment of the present disclosure. Figure 4 The diagram illustrates the timing relationship between the following multiple signals and multiple voltages: a first switching signal VG1, a second switching signal VG2, a third switching signal VG3, a drain voltage VD1 of the first transistor M1, a drain-gate voltage VDG1 of the first transistor M1, a gate-source voltage VGS2 of the second transistor M2, a drain voltage VD3 of the third transistor M3, a drain-gate voltage VDG3 of the third transistor M3, and a gate-source voltage VGS3 of the third transistor M3. Figure 4 The waveforms of the first switching signals VG1 and VG2 are combined with the above Figure 2 The contents described are similar and will not be repeated here for the sake of brevity.
[0027] Before switching from the receiving mode Rx to the transmitting mode Tx, the third switch signal VG3 has a low voltage to turn off the third transistor M3. When entering the transmitting mode Tx, the third switch signal VG3 switches to the third voltage V3 to turn on the third transistor M3, so that the drain of the first transistor M1 and the drain of the third transistor M3 are in a low impedance state. When the third switch signal VG3 switches to the third voltage V3 and passes through the first delay period TD1, the third switch signal VG3 switches to the fourth voltage V4 and maintains the fourth voltage V4 in the second enable period TE2. In this way, even if the second transistor M2 is turned on early due to the offset of the element characteristics, since the drain of the first transistor M1 and the drain of the third transistor M3 are already in a low impedance state in advance, the drain of the first transistor M1 and the drain of the third transistor M3 will not generate a voltage surge or overshoot.
[0028] When the third switch signal VG3 switches to the fourth voltage V4 and passes through the second enable period TE2, the third switch signal VG3 switches to the third voltage V3. The third switch signal VG3 will be maintained at the third voltage V3 in the second delay period TD2, and then switched to a low voltage to turn off the third transistor M3. In this way, even if the second transistor M2 is delayed in turning off due to the deviation of the element characteristics, since the drain of the first transistor M1 and the drain of the third transistor M3 are still in a low impedance state, the drain of the first transistor M1 and the drain of the third transistor M3 will not generate a voltage surge or overshoot.
[0029] In the present embodiment, the fourth voltage V4 is higher than the third voltage V3 and higher than the breakdown voltage of the third transistor M3, so the on-resistance of the third transistor M3 in the second enable period TE2 is less than the on-resistance of the third transistor M3 in the first delay period TD1 and the second delay period TD2. In addition, the third voltage V3 is lower than the breakdown voltage of the third transistor M3 and higher than the critical voltage of the third transistor M3. Therefore, in the first delay period TD1 and the second delay period TD2, the voltage of the third switch signal VG3 (i.e., the third voltage V3) is between the critical voltage of the third transistor M3 and the breakdown voltage of the third transistor M3. In the second enable period TE2, the breakdown voltage of the third transistor M3 is between the critical voltage of the third transistor M3 and the voltage of the third switch signal VG3 (i.e., the fourth voltage V4). Therefore, the absolute value of the drain-gate voltage VDG3 of the third transistor M3 is maintained lower than the absolute value of the breakdown voltage of the third transistor M3.
[0030] Figure 5 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device 30 according to an embodiment of the present disclosure. Figure 5 Examples and Figure 4 The embodiments of are similar, so only the differences between the two are described below. Figure 5 In the embodiment of the present invention, when entering the transmission mode Tx, the third switch signal VG3 is directly switched from the low voltage to the fourth voltage V4, and is maintained at the fourth voltage V4 in the first enable period TE1. Therefore, the third transistor M3 remains turned on in the first enable period TE1. Then, when the first enable period TE1 ends, the third switch signal VG3 is directly switched from the fourth voltage V4 to the low voltage.
[0031] Figure 6 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device 30 according to an embodiment of the present disclosure. Figure 6 Examples and Figure 4 The embodiments of are similar, so only the differences between the two are described below. Figure 6 In the embodiment of the present invention, the second switch signal VG2 has a low voltage in the first delay period TD1 and the second delay period TD2, and has a fourth voltage V4 in the second enable period TE2. Therefore, the third transistor M3 is turned on in the second enable period TE2, and is turned off in the first delay period TD1 and the second delay period TD2.
[0032] As can be seen from the above, the third switch signal VG3 can have a simpler waveform or a shorter pulse width. As long as the third transistor M3 is turned on at least in the second enable period TE2, the advantage of preventing surge or overshoot can be achieved.
[0033] In addition, although the above Figure 3AIn the description, a third transistor M3 is provided between the first transistor M1 and the second transistor M2, but the present disclosure is not limited thereto. The semiconductor device 30 may be provided with a plurality of transistors connected in series between the first transistor M1 and the second transistor M2. Figure 3B , which illustrates a schematic diagram of a semiconductor device 30' according to another embodiment of the present disclosure. Figure 3B As shown, the semiconductor device 30' is provided with a third transistor M3 and a fourth transistor M4 between the first transistor M1 and the second transistor M2. The third transistor M3 and the fourth transistor M4 are coupled in series between the first transistor M1 and the second transistor M2, and the third transistor M3 and the fourth transistor M4 are controlled by a third switch signal VG3 and a fourth switch signal VG4, respectively. In one embodiment, the signal waveform of the fourth switch signal VG4 is similar to Figure 4 , Figure 5 or Figure 6 The third switching signal VG3 has a signal waveform, so the third transistor M3 and the fourth transistor M4 have the same or similar operation, and for the sake of brevity, they are not repeated here. Similarly, two or more transistors connected in series can be set between the first transistor M1 and the second transistor M2, and multiple transistors connected in series (for example Figure 3B The third transistor M3 and the fourth transistor M4 in the embodiment can be controlled by similar switch signals, and the above Figure 3A , Figures 4 to 6 Described functions and operations.
[0034] In some embodiments, the second transistor M2 is implemented by an input / output device Metal Oxide Semiconductor (IO MOS) or a laterally diffused Metal Oxide Semiconductor (LDMOS). Therefore, the breakdown voltage of the second transistor M2 is greater than the breakdown voltage of the first transistor M1, and greater than the breakdown voltage of the third transistor M3 (which is also greater than Figure 3B The breakdown voltage of the fourth transistor M4 in FIG.
[0035] Figure 7 is a schematic diagram of a semiconductor device 70 according to an embodiment of the present disclosure. Figure 7 The semiconductor device 70 and Figure 3AThe semiconductor device 70 is similar to the semiconductor device 30, so only the differences between the two are described below. The semiconductor device 70 includes a first transistor M1', a second transistor M2' and a third transistor M3', wherein the first transistor M1', the third transistor M3' and the second transistor M2' are sequentially coupled in series between the power supply terminal VDD and the power supply terminal VSS. In some embodiments, the first transistor M1', the second transistor M2' and the third transistor M3' can be implemented by a P-type metal oxide semiconductor field effect transistor (P-type Metal-Oxide-Semiconductor Field-Effect Transistor, PMOSFET, referred to as P-type transistor). Figure 7 and Figure 8 In the embodiment of the present invention, the drain voltage VD1 of the first transistor M1' is the source voltage VS3 of the third transistor M3', and the drain voltage VD3 of the third transistor M3' is the source voltage VS2 of the second transistor M2'.
[0036] Also refer to Figure 7 and Figure 8 ,in Figure 8 FIG. 7 is a schematic diagram of signal waveforms of a semiconductor device 70 according to an embodiment of the present disclosure. Figure 8 The signal timing is combined with the above Figure 4 The contents are similar, but the signal waveforms are opposite. When entering the transmission mode Tx, the first switch signal VG1 will drop to the fifth voltage V5 to turn on the first transistor M1'. And the first switch signal VG1 will be maintained at the fifth voltage V5 in the first enable period TE1, and the absolute value of the gate-source voltage VGS1 (not shown in the figure) of the first transistor M1' in the first enable period TE1 is higher than the critical voltage V TH1 (not shown in the figure), that is, |VGS1|=|VG1-VS1|=|V5-VDD|>|V TH1 |, and the absolute value of the drain-gate voltage VDG1 of the first transistor M1' is lower than the breakdown voltage V BD1 (not shown in the figure), that is, |VDG1|<|V BD1 |, such as Figure 8 As shown, |VDD-V5|<|V BD1 | and |V8-VGS3-V5|<|V BD1|. The second switch signal VG2 has a high voltage (e.g., the voltage of the power supply terminal VDD) in the first delay period TD1 and the second delay period TD2 to turn off the second transistor M2', and is reduced to the sixth voltage V6 in the second enable period TE2 to turn on the second transistor M2'. The third switch signal VG3 will have a seventh voltage V7 in the first delay period TD1 and the second delay period TD2 to turn on the third transistor M3', and the absolute value of the gate-source voltage VGS3 (not shown in the figure) of the third transistor M3' in the first delay period TD1 and the second delay period TD2 is higher than the critical voltage V TH3 (not shown in the figure), that is, |VGS3|=|VG3-VS3|=|V7-VDD|<|V TH3 |, and the absolute value of the drain-gate voltage VDG3 of the third transistor M3' is lower than the breakdown voltage V BD3 (not shown in the figure), that is, |VDG3|<|V BD3 |, such as Figure 8 As shown, |VDD-V7|<|V BD3 |.
[0037] Fig. 9 is a schematic diagram of an amplifier 90 according to an embodiment of the present disclosure. The amplifier 90 includes a first semiconductor device 91 and a second semiconductor device 92. The first semiconductor device 91 and the second semiconductor device 92 can each be composed of Figure 3A The semiconductor device 30 or Figure 3B The first semiconductor device 91 and the second semiconductor device 92 each have a first transistor M1, a second transistor M2 and a third transistor M3, wherein the third transistor M3 is coupled between the first transistor M1 and the second transistor M2 (for convenience of explanation, Fig. 9 The third transistor M3 is only schematically illustrated for each semiconductor device. In actual applications, a plurality of transistors connected in series may be provided between the first transistor M1 and the second transistor M2, such as Figure 3B The first semiconductor device 91 and the second semiconductor device 92 are coupled to each other to receive the same first switching signal VG1, second switching signal VG2 and third switching signal VG3.
[0038] The gate of the first transistor M1 of the first semiconductor device 91 is used to receive the first differential input signal Vin (e.g., the inverted differential input signal), and the drain of the second transistor M2 of the first semiconductor device 91 is used to generate the first differential output signal Von (e.g., the inverted differential output signal). The gate of the first transistor M1 of the second semiconductor device 92 is used to receive the second differential input signal Vip (e.g., the non-inverted differential input signal), and the drain of the second transistor M2 of the second semiconductor device 92 is used to generate the second differential output signal Vop (e.g., the non-inverted differential output signal).
[0039] In operation, the first semiconductor device 91 and the second semiconductor device 92 are adapted to the aforementioned Figures 4 to 6 Therefore, for each of the first semiconductor device 91 and the second semiconductor device 92, the first transistor M1 is used to be turned on in the first enable period TE1, the second transistor M2 is used to be turned on in the second enable period TE2, and the third transistor M3 is used to be turned on at least in the second enable period TE2, wherein the first enable period TE1 includes a first delay period TD1, a second enable period TE2, and a second delay period TD2 arranged in sequence.
[0040] Fig.10 1 is a schematic diagram of a bias circuit 100 according to an embodiment of the present disclosure. The bias circuit 100 includes a first voltage generating circuit 101, a second voltage generating circuit 102, a third voltage generating circuit 103, and a semiconductor device 104. The semiconductor device 104 may be composed of Figure 3A The semiconductor device 30 or Figure 3B The semiconductor device 30' is implemented, that is, the semiconductor device 104 includes a first transistor M1, a second transistor M2 and a third transistor M3 (or further includes another transistor connected in series with the third transistor M3, refer to Figure 3B The fourth transistor M4 is also provided, and the first transistor M1, the third transistor M3 and the second transistor M2 are connected in series in sequence between the power supply terminal VSS' and the power supply terminal VDD'.
[0041] In some embodiments, bias circuit 100 is coupled to Fig. 9 The amplifier 90 is configured to provide a first switching signal VG1, a second switching signal VG2 and a third switching signal VG3 to the bias circuit 100. Fig. 9 In one embodiment, the first reference voltage Vref1 and the second reference voltage Vref2 are controlled by an external operation circuit (not shown) so that the first switch signal VG1, the second switch signal VG2 and the third switch signal VG3 generated by the bias circuit 100 have the aforementioned Figures 4 to 6 The signal waveform of any one of the embodiments of the embodiments.
[0042] The first voltage generating circuit 101 includes a first amplifier OP1, a current source CS, and a fifth transistor M5. The inverting input terminal of the first amplifier OP1 is coupled to the current source CS and the drain of the fifth transistor M5 to form a negative feedback. The non-inverting input terminal of the first amplifier OP1 is used to receive a first reference voltage Vref1. The output terminal of the first amplifier OP1 is used to output a first switching signal VG1 to the gate of the first transistor M1 of the semiconductor device 104 and the gate of the fifth transistor M5 to control the first transistor M1 of the semiconductor device 104 to be turned on during the first enable period TE1.
[0043] The second voltage generating circuit 102 includes a second amplifier OP2. The inverting input terminal and the output terminal of the second amplifier OP2 are coupled to each other to form a negative feedback, and the output terminal of the second amplifier OP2 is used to generate a second switching signal VG2. In addition, the non-inverting input terminal of the second amplifier OP2 is used to receive a second reference voltage Vref2. The output terminal of the second amplifier OP2 is used to output the second switching signal VG2 to the gate of the second transistor M2 of the semiconductor device 104 to control the second transistor M2 of the semiconductor device 104 to turn on in the second enable period TE2.
[0044] The third voltage generating circuit 103 includes a third amplifier OP3. The inverting input terminal of the third amplifier OP3 and the source of the third transistor M3 corresponding thereto are coupled to each other to form negative feedback, and the output terminal of the third amplifier OP3 is used to output a third switching signal VG3 to the third transistor M3 corresponding thereto. In addition, the non-inverting input terminal of the third amplifier OP3 is used to receive a third reference voltage Vref3. The output terminal of the third amplifier OP3 is used to output the third switching signal VG3 to the gate of the third transistor M3 of the semiconductor device 104 to control the third transistor M3 of the semiconductor device 104 to be turned on at least in the second enable period TE2. In one embodiment, Fig.10 The third switch signal VG3 generated by the third voltage generating circuit 103 can be output to the third transistor M3 and also to the fourth transistor M4 (eg, Figure 3B Or in another embodiment, the bias circuit 100 may further include a fourth voltage generating circuit (not shown in the figure) for generating a fourth switching signal VG4, which is output to Figure 3B The fourth transistor M4 is shown, wherein the architecture of the fourth voltage generating circuit (not shown in the figure) is similar to the third voltage generating circuit 103 .
[0045] Certain words are used in the specification and the scope of the patent application to refer to specific components. However, a person with general knowledge in the relevant technical field should understand that the same component may be referred to by different nouns. The specification and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The "including" mentioned in the specification and the scope of the patent application is an open-ended term and should therefore be interpreted as "including but not limited to". In addition, "coupling" in this article includes any direct and indirect means of connection. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element by a signal connection method such as electrical connection or wireless transmission, optical transmission, or can be indirectly electrically connected or signal-connected to the second element by other elements or connection means.
[0046] In addition, unless otherwise specified in the specification, any singular form of the term also includes the plural form.
[0047] The above are only preferred embodiments of the present disclosure. Various modifications and equivalent changes may be made to the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.
[0048]
Explanation of symbols
[0049] 10, 30, 30', 70: Semiconductor devices
[0050] 90: Amplifier
[0051] 91: First semiconductor device
[0052] 92: Second semiconductor device
[0053] 100: Bias circuit
[0054] 101: First voltage generating circuit
[0055] 102: Second voltage generating circuit
[0056] 103: Third voltage generating circuit
[0057] 104: Semiconductor devices
[0058] CS: Current Source
[0059] M1, M1': first transistor
[0060] M2, M2': second transistor
[0061] M3, M3': The third transistor
[0062] M4: The fourth transistor
[0063] M5: The fifth transistor
[0064] OP1: First Amplifier
[0065] OP2: Second amplifier
[0066] OP3: Third Amplifier
[0067] Tx: Transmit mode
[0068] Rx: receiving mode
[0069] TD1: First delay period
[0070] TD2: Second delay period
[0071] TE1: First enabling period
[0072] TE2: Second enabling period
[0073] V1: first voltage
[0074] V2: Second voltage
[0075] V3: The third voltage
[0076] V4: fourth voltage
[0077] V5: Fifth voltage
[0078] V6: Sixth voltage
[0079] V7: Seventh voltage
[0080] V8: Eighth Voltage
[0081] Vin: First differential input signal
[0082] Vip: Second differential input signal
[0083] Von: First differential output signal
[0084] Vop: Second differential output signal
[0085] VG1: First switch signal
[0086] VG2: Second switching signal
[0087] VG3: The third switching signal
[0088] VG4: Fourth switch signal
[0089] VD1, VD3: drain voltage
[0090] VS2, VS3: Source voltage
[0091] VDG1, VDG3: drain-gate voltage
[0092] VGS2, VGS3: Gate-source voltage
[0093] VDD, VDD', VSS, VSS': power supply terminals
[0094] Vref1: first reference voltage
[0095] Vref2: Second reference voltage
[0096] Vref3: The third reference voltage
Claims
1. A semiconductor device comprising: A first transistor, configured to be turned on during a first enabling period; as well as a second transistor, configured to be turned on during a second enable period, wherein the first transistor is coupled in series with the second transistor, The first enabling period includes a first delay period, a second enabling period and a second delay period which are arranged in sequence.
2. The semiconductor device according to claim 1, further comprising: a third transistor, wherein the third transistor is coupled between the first transistor and the second transistor, The third transistor is turned on at least in the second enabling period.
3. The semiconductor device according to claim 2, wherein the third transistor is turned on in the first enable period, The third transistor has an on-resistance, and the on-resistance in the second enable period is smaller than the on-resistance in the first delay period, and smaller than the on-resistance in the second delay period.
4. The semiconductor device according to claim 3, wherein the third transistor is controlled by a switch signal and has a threshold voltage and a breakdown voltage, In the first delay period and the second delay period, the voltage of the switch signal is between the critical voltage and the breakdown voltage, In the second enabling period, the breakdown voltage is between the critical voltage and the voltage of the switch signal. The semiconductor device according to claim 2 , wherein the third transistor remains turned on during the first enable period. 6 . The semiconductor device according to claim 2 , wherein the third transistor is turned on in the second enable period, and is turned off in the first delay period and the second delay period. 7 . The semiconductor device according to claim 2 , wherein a breakdown voltage of the second transistor is greater than a breakdown voltage of the first transistor, and greater than a breakdown voltage of the third transistor.
8. The semiconductor device according to claim 2, 3, 4, 5, 6 or 7, further comprising a fourth transistor, the third transistor and the fourth transistor being coupled in series between the first transistor and the second transistor.
9. An amplifier, comprising: a first semiconductor device; as well as a second semiconductor device coupled to the first semiconductor device, The first semiconductor device and the second semiconductor device each include: A first transistor, configured to be turned on during a first enabling period; a second transistor, configured to be turned on during a second enable period; and a third transistor, wherein the third transistor is coupled between the first transistor and the second transistor, The first transistor is used to receive an input signal, and the second transistor is used to generate an output signal. The first enabling period includes a first delay period, a second enabling period and a second delay period which are arranged in sequence, and the third transistor is turned on at least in the second enabling period.
10. A bias circuit comprising: A semiconductor device comprising a first transistor, a second transistor and a third transistor, wherein the third transistor is coupled between the first transistor and the second transistor; A first voltage generating circuit, configured to output a first switching signal to control the first transistor to be turned on during a first enabling period; A second voltage generating circuit, configured to output a second switching signal to control the second transistor to be turned on during a second enabling period; as well as a third voltage generating circuit, configured to output a third switching signal to control the third transistor to be turned on at least during the second enabling period, wherein the third voltage generating circuit and the third transistor form a negative feedback, The first enabling period includes a first delay period, a second enabling period and a second delay period which are arranged in sequence.