Semiconductor device, amplifier and bias circuit
By designing and controlling the on-time periods of the first, second and third transistors in the semiconductor device, the problem of easy damage to the input and output circuit of the semiconductor chip is solved, and effective protection against voltage surge and overshoot is achieved.
Patent Information
- Application Number
- CN202410759035.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-04
- Filing Date
- 2024-06-13
- Publication Date
- 2025-03-04
AI Technical Summary
The input and output circuit of the semiconductor chip is easily damaged by voltage surge or current surge due to the thinner oxide layer thickness.
A semiconductor device is designed, including first, second and third transistors, by precisely controlling the switching signal, the transistor is turned on for a specific period of time, ensuring that the drain and gate voltages are within a safe range, and avoiding voltage surge or overshoot.
Effectively prevent semiconductor devices from being damaged by voltage surge or overshoot, ensuring the stability and reliability of the circuit.
Smart Images
Figure CN119561506A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to semiconductor circuit technology, and more particularly to semiconductor devices, amplifiers, and bias circuits that can prevent surges or overshoots. Background Art
[0002] With the advancement of semiconductor process technology, the channel length and gate oxide thickness of transistors are also decreasing. Therefore, chips made using advanced processes have advantages such as low power consumption, high component density, and high instruction cycle. However, thinner oxide thickness means lower voltage withstand capability, so transistors in the chip's input and output (I / O) circuits are often damaged by voltage surges or current surges. Summary of the invention
[0003] The present disclosure provides a semiconductor device, which includes a first transistor, a second transistor and a third transistor. The first transistor is controlled by a first switch signal and is used to be turned on in a first enable period. The second transistor is controlled by a second switch signal and is used to be turned on at least in a second enable period. The first enable period includes a first delay period, a second enable period and a second delay period arranged in sequence. The third transistor is controlled by a third switch signal and is used to be turned on at least in a third enable period. The second transistor is coupled between the first transistor and the third transistor. The second enable period includes a third delay period, a third enable period and a fourth delay period arranged in sequence.
[0004] The present disclosure provides an amplifier, which includes a first semiconductor device and a second semiconductor device. The second semiconductor device is coupled to the first semiconductor device. The first semiconductor device and the second semiconductor device each include a first transistor, a second transistor and a third transistor. The first transistor is controlled by a first switch signal and is used to be turned on in a first enable period. The second transistor is controlled by a second switch signal and is used to be turned on at least in a second enable period. The first enable period includes a first delay period, a second enable period and a second delay period arranged in sequence. The third transistor is controlled by a third switch signal and is used to be turned on at least in a third enable period. The second transistor is coupled between the first transistor and the third transistor. The second enable period includes a third delay period, a third enable period and a fourth delay period arranged in sequence. The first transistor is used to receive an input signal, and the third transistor is used to generate an output signal.
[0005] The present disclosure provides a bias circuit, which includes a semiconductor device, a first voltage generating circuit, a second voltage generating circuit and a third voltage generating circuit. The semiconductor device includes a first transistor, a second transistor and a third transistor. The second transistor is coupled between the first transistor and the third transistor. The first voltage generating circuit is used to output a first switching signal to control the first transistor to be turned on in a first enable period. The second voltage generating circuit is used to output a second switching signal to control the second transistor to be turned on at least in a second enable period. The first enable period includes a first delay period, a second enable period and a second delay period arranged in sequence. Each second voltage generating circuit forms a negative feedback with a corresponding one of the second transistors. The third voltage generating circuit is used to output a third switching signal to control the third transistor to be turned on at least in a third enable period. The second enable period includes a third delay period, a third enable period and a fourth delay period arranged in sequence.
[0006] One of the advantages of the semiconductor device, amplifier, and bias circuit described above is that they can prevent surges or overshoots. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1A FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.
[0008] Figure 1B FIG. 4 is a schematic diagram of a semiconductor device according to another embodiment of the present disclosure.
[0009] Figure 2 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device according to an embodiment of the present disclosure.
[0010] Figure 3 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device according to an embodiment of the present disclosure.
[0011] Figure 4 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure.
[0012] Figure 5 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device according to an embodiment of the present disclosure.
[0013] Figure 6 FIG. 4 is a schematic diagram of an amplifier according to an embodiment of the present disclosure.
[0014] Figure 7 FIG. 4 is a schematic diagram of a bias circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0015] The following will illustrate the embodiments of the present disclosure with reference to the related drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.
[0016] Figure 1A Schematic diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1, the second transistor M2, and the third transistor M3 are sequentially coupled in series between a power supply terminal VSS and a power supply terminal VDD, wherein the voltage of the power supply terminal VDD is higher than the voltage of the power supply terminal VSS. The first transistor M1, the second transistor M2, and the third transistor M3 are controlled by a first switch signal VG1, a second switch signal VG2, and a third switch signal VG3, respectively. In some embodiments, the first transistor M1, the second transistor M2, and the third transistor M3 can be implemented by an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) (referred to as an N-type transistor). In some embodiments where the semiconductor device 100 is used as an input-output (I / O) circuit, the semiconductor device 100 is a bias circuit.
[0017] Please also refer to Figure 1A and Figure 2 ,in Figure 2 FIG. 1 is a schematic diagram of signal waveforms of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 2 The timing relationship between the following multiple signals and multiple voltages is shown: the first switch signal VG1, the second switch signal VG2, the third switch signal VG3, the drain voltage VD1 of the first transistor M1, the drain-gate voltage VDG1 of the first transistor M1, the drain voltage VD2 of the second transistor M2, the drain-gate voltage VDG2 of the second transistor M2, the gate-source voltage VGS2 of the second transistor M2, and the gate-source voltage VGS3 of the third transistor M3. The semiconductor device 100 can alternately operate in the receiving mode Rx and the transmitting mode Tx. Before switching from the receiving mode Rx to the transmitting mode Tx, the semiconductor device 100 does not output a signal, so the first switch signal VG1, the second switch signal VG2, and the third switch signal VG3 have a low voltage (e.g., a ground voltage) to turn off the first transistor M1, the second transistor M2, and the third transistor M3.
[0018] When entering the emission mode Tx, the first switch signal VG1 switches to the first voltage V1 to turn on the first transistor M1, and the second switch signal VG2 switches to the second voltage V2 to turn on the second transistor M2. Therefore, the drain of the first transistor M1 and the drain of the second transistor M2 are in a low impedance state. The first switch signal VG1 is maintained at the first voltage V1 in the first enable period TE1, wherein the first enable period TE1 includes the first delay period TD1, the second enable period TE2 and the second delay period TD2 arranged in sequence. The second switch signal VG2 is maintained at the second voltage V2 in the first delay period TD1. When entering the emission mode Tx and passing the first delay period TD1, the third switch signal VG3 switches to the third voltage V3 to turn on the third transistor M3. The third switch signal VG3 is maintained at the third voltage V3 in the second enable period TE2, wherein the second enable period TE2 includes the third delay period TD3, the third enable period TE3 and the fourth delay period TD4 arranged in sequence.
[0019] Thus, even if the third transistor M3 is turned on early due to the deviation of the device characteristics, since the drain of the first transistor M1 and the drain of the second transistor M2 are already in a low impedance state, the drain of the first transistor M1 and the drain of the second transistor M2 will not generate a voltage surge or overshoot.
[0020] After the first delay period TD1 ends, the second switch signal VG2 continues to maintain at the second voltage V2 in the third delay period TD3. Then, the second switch signal VG2 switches to the fourth voltage V4 and maintains at the fourth voltage V4 in the third enable period TE3, wherein the fourth voltage V4 is higher than the second voltage V2 and higher than the breakdown voltage of the second transistor M2. After the third enable period TE3 ends, the second switch signal VG2 switches to the second voltage V2 and maintains at the second voltage V2 in the following fourth delay period TD4 and second delay period TD2.
[0021] On the other hand, when the fourth delay period TD4 ends, the third switch signal VG3 is switched from the third voltage V3 to a low voltage to turn off the third transistor M3. In this way, even if the third transistor M3 is turned off with delay due to the deviation of the element characteristics, since the drain of the first transistor M1 and the drain of the second transistor M2 are still in a low impedance state, the drain of the first transistor M1 and the drain of the second transistor M2 will not generate a voltage surge or overshoot.
[0022] The first delay period TD1 and the second delay period TD2 may be the same or different. The third delay period TD3 and the fourth delay period TD4 may be the same or different. In some embodiments, the first delay period TD1, the second delay period TD2, the third delay period TD3 and the fourth delay period TD4 are each between 50 and 200 nanoseconds (ns), but the present disclosure is not limited thereto. In some embodiments, the sum of the first delay period TD1 and the third delay period TD3 is longer to wait for the linear regulator LDO that supplies power to the first power supply terminal VDD to enter a stable state, and the sum of the second delay period TD2 and the fourth delay period TD4 is shorter to stop the output of the semiconductor device 100 as soon as possible.
[0023] In summary, to prevent the semiconductor device 100 from being damaged by voltage surge or overshoot, the first transistor M1 is used to be turned on in the first enable period TE1, the second transistor M2 is used to be turned on at least in the second enable period TE2, and the third transistor M3 is used to be turned on at least in the third enable period TE3. The first enable period TE1 includes a first delay period TD1, a second enable period TE2, and a second delay period TD2 arranged in sequence. The second enable period TE2 includes a third delay period TD3, a third enable period TE3, and a fourth delay period TD4 arranged in sequence.
[0024] It is worth mentioning that since the fourth voltage V4 is higher than the second voltage V2, the on-resistance of the second transistor M2 in the third enabling period TE3 is smaller than the on-resistance of the second transistor M2 in the first delay period TD1, the second delay period TD2, the third delay period TD3 and the fourth delay period TD4.
[0025] In some embodiments, the first voltage V1 is lower than the breakdown voltage of the first transistor M1 and higher than the threshold voltage of the first transistor M1 , so the absolute value of the drain-gate voltage VDG1 of the first transistor M1 remains lower than the absolute value of the breakdown voltage of the first transistor M1 .
[0026] In other embodiments, the second voltage V2 is lower than the breakdown voltage of the second transistor M2 and higher than the critical voltage of the second transistor M2. In the first delay period TD1, the second delay period TD2, the third delay period TD3, and the fourth delay period TD4, the voltage of the second switch signal VG2 (i.e., the second voltage V2) is between the critical voltage of the second transistor M2 and the breakdown voltage of the second transistor M2. In the third enable period TE3, the breakdown voltage of the second transistor M2 is between the critical voltage of the second transistor M2 and the voltage of the second switch signal VG2 (i.e., the fourth voltage V4). Therefore, the absolute value of the drain-gate voltage VDG2 of the second transistor M2 is maintained lower than the absolute value of the breakdown voltage of the second transistor M2.
[0027] Figure 3 FIG. 1 is a schematic diagram of signal waveforms of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3 An embodiment similar to Figure 2 Therefore, only the differences between the two are described below. Figure 3 In the embodiment of the present invention, the second switch signal VG2 has a low voltage in the first delay period TD1 and the second delay period TD2, and is maintained at the fourth voltage V4 in the second enable period TE2. The third switch signal VG3 has a low voltage in the first delay period TD1, the second delay period TD2, the third delay period TD3, and the fourth delay period TD4, and has the third voltage V3 in the third enable period TE3.
[0028] As can be seen from the above, the second switch signal VG2 and the third switch signal VG3 can have simpler waveforms or shorter pulse widths. As long as the second transistor M2 is turned on at least in the second enable period TE2 and the third transistor M3 is turned on at least in the third enable period TE3, the advantage of preventing surge or overshoot can be achieved.
[0029] In addition, although the above Figure 1A The description is given by assuming that a second transistor M2 is disposed between the first transistor M1 and the third transistor M3 , but the present disclosure is not limited thereto.
[0030] In another embodiment, a plurality of transistors connected in series may be disposed between the first transistor M1 and the third transistor M3. Figure 1B , which shows a schematic diagram of a semiconductor device 100' according to another embodiment of the present disclosure. Figure 1B In the embodiment shown, the semiconductor device 100' is provided with a second transistor M2 and a fourth transistor M4 between the third transistor M3 and the first transistor M1. The second transistor M2 and the fourth transistor M4 are coupled in series between the third transistor M3 and the first transistor M1, and the second transistor M2 and the fourth transistor M4 are controlled by the second switch signal VG2 and the fourth switch signal VG4, respectively. In one embodiment, the signal waveform of the fourth switch signal VG4 is similar to Figure 2 or Figure 3 The signal waveform of the second switch signal VG2 is the same as that of the second transistor M2 and the fourth transistor M4, and therefore, for the sake of brevity, they are not repeated here. Similarly, two or more transistors connected in series may be arranged between the third transistor M3 and the first transistor M1, and multiple transistors connected in series (e.g. Figure 1B The second transistor M2 and the fourth transistor M4 in the embodiment can be controlled by similar switch signals, and the aforementioned Figure 1A , Figure 2 and Figure 3 In some embodiments, the third transistor M3 is implemented by an input / output device metal oxide semiconductor (IO MOS) or a laterally diffused metal oxide semiconductor (LDMOS). Therefore, the breakdown voltage of the third transistor M3 is greater than the breakdown voltage of the first transistor M1 and greater than the breakdown voltage of the second transistor M2.
[0031] Figure 4 FIG. 4 is a schematic diagram of a semiconductor device 400 according to an embodiment of the present disclosure. Figure 4 The semiconductor device 400 is similar to Figure 1A The semiconductor device 100 is a semiconductor device 400, so only the differences between the two are described below. The semiconductor device 400 includes a first transistor M1', a second transistor M2' and a third transistor M3', wherein the first transistor M1', the second transistor M2' and the third transistor M3' are sequentially coupled in series between the power supply terminal VDD and the power supply terminal VSS. In some embodiments, the first transistor M1', the second transistor M2' and the third transistor M3' can be implemented by P-type transistors.
[0032] Please also refer to Figure 4 and Figure 5 ,in Figure 5 FIG. 4 is a schematic diagram of signal waveforms of a semiconductor device 400 according to an embodiment of the present disclosure. Figure 5 The signal timing is similar to the above coordination Figure 2The content described above, but the signal waveform is opposite. When entering the transmission mode Tx, the first switch signal VG1 will drop to the fifth voltage V5 to turn on the first transistor M1'. The first switch signal VG1 will be maintained at the fifth voltage V5 in the first enable period TE1, so that the absolute value of the gate-source voltage VGS1 (not shown in the figure) of the first transistor M1' is greater than the absolute value of the threshold voltage VTH1 (not shown in the figure) of the first transistor M1', that is, |VGS1|=|V5-VDD|>|VTH1|, so that the first transistor M1' is turned on. The second switch signal VG2 will have a sixth voltage V6 in the first delay period TD1, the second delay period TD2, the third delay period TD3 and the fourth delay period TD4 to turn on the second transistor M2', so that the absolute value of the gate-source voltage VGS2 (not shown in the figure) of the second transistor M2' is greater than the absolute value of the threshold voltage VTH2 (not shown in the figure) of the second transistor M2', that is, |VGS2|>|VTH2|, so that the second transistor M2' is turned on. The second switch signal VG2 also has a seventh voltage V7 in the third enable period TE3, and the seventh voltage V7 is the voltage during actual operation and makes the absolute value of the drain-gate voltage VDG2 of the second transistor M2' less than the absolute value of the breakdown voltage VBD2 (not shown in the figure) of the second transistor M2', that is, |VDG2|<|VBD2|. The third switch signal VG3 has a high voltage (for example, the voltage of the power supply terminal VDD) in the first delay period TD1 and the second delay period TD2 to turn off the third transistor M3', thereby preventing overshoot from occurring when the first transistor M1' and the second transistor M2' are switched. In addition, in the second enable period TE2, the third switch signal VG3 is reduced to the eighth voltage V8 to turn on the third transistor M3', so that the bias circuit (i.e., the semiconductor device 400) can operate normally.
[0033] Figure 6 FIG. 6 is a schematic diagram of an amplifier 600 according to an embodiment of the present disclosure. The amplifier 600 includes a first semiconductor device 610 and a second semiconductor device 620. The first semiconductor device 610 and the second semiconductor device 620 can each be composed of Figure 1A The semiconductor device 100 is implemented, that is, the first semiconductor device 610 and the second semiconductor device 620 each have a first transistor M1, a second transistor M2 and a third transistor M3, wherein the second transistor M2 is coupled to the first transistor M1 and the third transistor M3.
[0034] exist Figure 6In the embodiment of the present invention, the first semiconductor device 610 and the second semiconductor device 620 each have a second transistor M2 disposed between the third transistor M3 and the first transistor M1, but the present disclosure is not limited thereto. In another embodiment, the first semiconductor device 610 and the second semiconductor device 620 each have a plurality of transistors connected in series between the third transistor M3 and the first transistor M1 (for example, Figure 1B The plurality of transistors connected in series may be controlled by the same or similar switching signal, so the plurality of transistors connected in series have the same or similar operation.
[0035] The first semiconductor device 610 and the second semiconductor device 620 are coupled to each other to receive the same first switching signal VG1 , second switching signal VG2 , and third switching signal VG3 .
[0036] The gate of the first transistor M1 of the first semiconductor device 610 is used to receive the first differential input signal Vin (e.g., the inverted differential input signal), and the drain of the second transistor M2 of the first semiconductor device 610 is used to generate the first differential output signal Von (e.g., the inverted differential output signal). The gate of the first transistor M1 of the second semiconductor device 620 is used to receive the second differential input signal Vip (e.g., the non-inverted differential input signal), and the drain of the second transistor M2 of the second semiconductor device 620 is used to generate the second differential output signal Vop (e.g., the non-inverted differential output signal).
[0037] In operation, the first semiconductor device 610 and the second semiconductor device 620 are applicable to the signal waveforms of any of the multiple embodiments of Figures 2 to 3 above. Therefore, for each of the first semiconductor device 610 and the second semiconductor device 620, the first transistor M1 is used to be turned on in the first enable period TE1, the second transistor M2 is used to be turned on at least in the second enable period TE2, and the third transistor M3 is used to be turned on at least in the third enable period TE3. The first enable period TE1 includes a first delay period TD1, a second enable period TE2, and a second delay period TD2 arranged in sequence. The second enable period TE2 includes a third delay period TD3, a third enable period TE3, and a fourth delay period TD4 arranged in sequence.
[0038] Figure 7 FIG. 7 is a schematic diagram of a bias circuit 700 according to an embodiment of the present disclosure. The bias circuit 700 includes a first voltage generating circuit 701, a second voltage generating circuit 702, a third voltage generating circuit 703, and a semiconductor device 704. The semiconductor device 704 may be composed of Figure 1AThat is, the semiconductor device 704 includes a first transistor M1, a second transistor M2 and a third transistor M3, and the first transistor M1, the second transistor M2 and the third transistor M3 are sequentially connected in series between the power terminal VSS′ and the power terminal VDD′.
[0039] In some embodiments, the bias circuit 700 is coupled to Figure 6 The amplifier 600 is configured to provide a first switching signal VG1, a second switching signal VG2 and a third switching signal VG3 to the bias circuit 700. Figure 6 In one embodiment, the first reference voltage Vref1, the second reference voltage Vref2 and the third reference voltage Vref3 are controlled by an external operation circuit (not shown), so that the first switch signal VG1, the second switch signal VG2 and the third switch signal VG3 generated by the bias circuit 700 can have the signal waveform of any one of the embodiments of FIGS. 2 to 3 above.
[0040] The first voltage generating circuit 701 includes a first amplifier OP1, a current source CS, and a fourth transistor M4. The inverting input terminal of the first amplifier OP1 is coupled to the current source CS and the drain of the fourth transistor M4 to form a negative feedback. The non-inverting input terminal of the first amplifier OP1 is used to receive a first reference voltage Vref1. The output terminal of the first amplifier OP1 is used to output a first switching signal VG1 to the gate of the first transistor M1 and the gate of the fourth transistor M4 of the semiconductor device 704 to control the first transistor M1 of the semiconductor device 704 to be turned on during the first enable period TE1.
[0041] The second voltage generating circuit 702 includes a second amplifier OP2. The inverting input terminal of the second amplifier OP2 is coupled to the source of the second transistor M2 corresponding to it to form negative feedback, and the output terminal of the second amplifier OP2 is used to output the second switching signal VG2 to the second transistor M2 corresponding to it. In addition, the non-inverting input terminal of the second amplifier OP2 is used to receive the first reference voltage Vref1. The output terminal of the second amplifier OP2 is used to output the second switching signal VG2 to the gate of the second transistor M2 of the semiconductor device 704 to control the second transistor M2 of the semiconductor device 704 to be turned on at least in the second enable period TE2.
[0042] At Figure 7 In the embodiment of the present invention, the semiconductor device 704 includes a second transistor M2 disposed between the third transistor M3 and the first transistor M1, but the present disclosure is not limited thereto. In another embodiment, the semiconductor device 704 includes a plurality of transistors (for example, Figure 1BThe plurality of transistors connected in series may be controlled by the same or similar switching signal, so the plurality of transistors connected in series have the same or similar operation.
[0043] The third voltage generating circuit 703 includes a third amplifier OP3. The inverting input terminal and the output terminal of the third amplifier OP3 are coupled to each other to form a negative feedback, and the output terminal of the third amplifier OP3 is used to generate a third switching signal VG3. In addition, the non-inverting input terminal of the third amplifier OP3 is used to receive the second reference voltage Vref2. The output terminal of the third amplifier OP3 is used to output the third switching signal VG3 to the gate of the third transistor M3 of the semiconductor device 704 to control the third transistor M3 of the semiconductor device 704 to be turned on at least in the third enabling period TE3.
[0044] Certain words are used in the specification and the scope of the patent application to refer to specific components. However, those with ordinary knowledge in the relevant technical field should understand that the same component may be referred to by different nouns. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The "including" mentioned in the specification and claims is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal connected to the second element through other elements or connection means.
[0045] In addition, unless otherwise specified in the specification, any singular term also includes the plural term.
[0046] The above are only preferred embodiments of the present disclosure. Various modifications and equivalent changes may be made to the present disclosure without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.
[0047]
Explanation of symbols
[0048] 100,100',400: Semiconductor devices
[0049] 600: Amplifier
[0050] 610: First semiconductor device
[0051] 620: Second semiconductor device
[0052] 700: Bias circuit
[0053] 701: First voltage generating circuit
[0054] 702: Second voltage generating circuit
[0055] 703: Third voltage generating circuit
[0056] 704: Semiconductor devices
[0057] CS: Current Source
[0058] M1, M1': first transistor
[0059] M2, M2': Second transistor
[0060] M3, M3': The third transistor
[0061] M4: The fourth transistor
[0062] OP1: First Amplifier
[0063] OP2: Second amplifier
[0064] OP3: Third Amplifier
[0065] TE1: First enabling period
[0066] TE2: Second enabling period
[0067] TD1: First delay period
[0068] TD2: Second delay period
[0069] TD3: Third delay period
[0070] TD4: Fourth delay period
[0071] Tx: Transmit mode
[0072] Rx: receiving mode
[0073] VG1: First switch signal
[0074] VG2: Second switching signal
[0075] VG3: The third switching signal
[0076] VG4: Fourth switch signal
[0077] VD1, VD2: drain voltage
[0078] VDG1, VDG2: drain-gate voltage
[0079] VGS2, VGS3: Gate-source voltage
[0080] V1: first voltage
[0081] V2: Second voltage
[0082] V3: The third voltage
[0083] V4: fourth voltage
[0084] V5: Fifth voltage
[0085] V6: Sixth voltage
[0086] V7: Seventh voltage
[0087] V8: Eighth Voltage
[0088] VDD, VDD', VSS, VSS': power supply terminal
[0089] Vin: First differential input signal
[0090] Vip: Second differential input signal
[0091] Von: First differential output signal
[0092] Vop: Second differential output signal
[0093] Vref1: first reference voltage
[0094] Vref2: Second reference voltage
[0095] Vref3: The third reference voltage
Claims
1. A semiconductor device comprising: A first transistor, controlled by a first switch signal, configured to be turned on during a first enable period; a second transistor, controlled by a second switch signal, for being turned on at least in a second enable period, wherein the first enable period includes a first delay period, the second enable period, and a second delay period arranged in sequence; as well as The third transistor is controlled by a third switch signal and is used to be turned on at least in a third enable period, wherein the second transistor is coupled between the first transistor and the third transistor, and the second enable period includes a third delay period, the third enable period and a fourth delay period arranged in sequence. 2 . The semiconductor device according to claim 1 , wherein the second transistor is maintained on during the first enable period, and the third transistor is maintained on during the second enable period.
3. The semiconductor device according to claim 2, wherein the second transistor has an on-resistance, and the on-resistance of the third enabling period is smaller than the on-resistance of the first delay period, the on-resistance of the second delay period, the on-resistance of the third delay period, and the on-resistance of the fourth delay period.
4. The semiconductor device according to claim 2, wherein the second transistor has a threshold voltage and a breakdown voltage, wherein during the first delay period, the second delay period, the third delay period, and the fourth delay period, the voltage of the second switch signal is between the critical voltage and the breakdown voltage, In the third enabling period, the breakdown voltage is between the voltage of the second switch signal and the critical voltage.
5. The semiconductor device according to claim 1 , wherein the second transistor is turned on in the second enable period and is turned off in the first delay period and the second delay period, The third transistor is turned on in the third enable period, and is turned off in the first delay period, the second delay period, the third delay period, and the fourth delay period. 6 . The semiconductor device according to claim 1 , wherein a breakdown voltage of the third transistor is greater than a breakdown voltage of the first transistor, and greater than a breakdown voltage of the second transistor. 7 . The semiconductor device according to claim 1 , further comprising a fourth transistor, wherein the second transistor and the fourth transistor are both coupled in series between the third transistor and the first transistor. 8 . The semiconductor device according to claim 1 , wherein the first transistor, the second transistor, and the third transistor are all P-type transistors or all N-type transistors.
9. An amplifier, comprising: a first semiconductor device; as well as a second semiconductor device coupled to the first semiconductor device, The first semiconductor device and the second semiconductor device each include: A first transistor, controlled by a first switch signal, configured to be turned on during a first enable period; a second transistor controlled by a second switch signal and configured to be turned on at least in a second enable period, wherein the first enable period includes a first delay period, the second enable period, and a second delay period arranged in sequence; and a third transistor, controlled by a third switch signal, for being turned on at least in a third enable period, wherein the second transistor is coupled between the first transistor and the third transistor, and the second enable period includes a third delay period, the third enable period, and a fourth delay period arranged in sequence, The first transistor is used for receiving an input signal, and the third transistor is used for generating an output signal.
10. A bias circuit comprising: A semiconductor device comprising a first transistor, a second transistor and a third transistor, wherein the second transistor is coupled between the first transistor and the third transistor; A first voltage generating circuit, configured to output a first switching signal to control the first transistor to be turned on during a first enabling period; a second voltage generating circuit, configured to output a second switch signal to control the second transistor to be turned on at least in a second enable period, wherein the first enable period includes a first delay period, the second enable period, and a second delay period arranged in sequence, and the second voltage generating circuit and the second transistor form a negative feedback; as well as The third voltage generating circuit is used for outputting a third switch signal to control the third transistor to be turned on at least in a third enabling period, wherein the second enabling period includes a third delay period, the third enabling period and a fourth delay period arranged in sequence.