Noise shaping circuit and analog-to-digital converter

Abstract

Embodiments of the present disclosure provide a noise shaping circuit and analog-to-digital converter, which can be applied to the field of integrated circuit technology. The noise shaping circuit includes: a plurality of switches, a first capacitor, a second capacitor, and a buffer connected between the first capacitor and the second capacitor; the plurality of switches are configured to, in response to a switch control signal, alternately connect one of the first capacitor and the second capacitor as an integrating capacitor to an analog signal input terminal, so that the integrating capacitor provides an integrated voltage to the buffer based on a residual voltage provided by the analog signal input terminal and a capacitor voltage stored therein, and the other of the first capacitor and the second capacitor acts as a storage capacitor to receive and store the integrated voltage flowing through the buffer; the integrating capacitor is configured to output the integrated voltage to an output terminal of the noise shaping circuit, so that a digital logic circuit performs analog-to-digital conversion on the integrated voltage to obtain a residual voltage and provide it to the analog signal input terminal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and more particularly, to a noise shaping circuit and an analog-to-digital converter. Background Art

[0002] The rapid advancement of cutting-edge technologies such as deep space exploration and quantum computing has placed ever-more stringent demands on ADC performance, requiring high speed and precision even in extremely low-temperature environments. Noise shaping technology can be used to improve ADC accuracy.

[0003] However, traditional successive approximation noise-shaping circuits, which use operational amplifiers as integrators, face challenges in cryogenic environments, such as increased power consumption, poles introduced by gain error, and significant effects of voltage and temperature variations on gain fluctuations. Furthermore, traditional noise-shaping circuits combine passive switched-capacitor filtering with dynamic amplifiers to optimize the noise transfer function at low frequencies. However, PVT significantly impacts gain fluctuations, resulting in poor stability in cryogenic environments. Summary of the Invention

[0004] In view of this, the present disclosure provides a noise shaping circuit and an analog-to-digital converter.

[0005] One aspect of the present disclosure provides a noise shaping circuit, comprising: a plurality of switches, a first capacitor, a second capacitor, and a buffer connected between the first and second capacitors; the plurality of switches being configured to, in response to a switch control signal, alternately connect one of the first and second capacitors as an integrating capacitor to an analog signal input terminal, such that the integrating capacitor provides an integrated voltage to the buffer based on a residual voltage provided by the analog signal input terminal and a stored capacitor voltage thereof, and the other of the first and second capacitors being configured to function as a storage capacitor to receive and store the integrated voltage flowing through the buffer; and the integrating capacitor being configured to output the integrated voltage to an output terminal of the noise shaping circuit, such that a digital logic circuit performs analog-to-digital conversion on the integrated voltage to obtain the residual voltage and provide the residual voltage to the analog signal input terminal.

[0006] According to an embodiment of the present disclosure, the above-mentioned multiple switches include a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch; the above-mentioned first capacitor includes a first sub-capacitor and a second sub-capacitor, the above-mentioned second capacitor includes a third sub-capacitor and a fourth sub-capacitor, and the above-mentioned buffer includes a first buffer and a second buffer.

[0007] According to an embodiment of the present disclosure, the noise shaping unit is configured such that a first end of the first switch is connected to the analog signal input terminal, a second end of the first switch is connected to the first end of the first sub-capacitor, the second end of the first sub-capacitor is connected to the first end of the third switch and the second end of the fourth switch via the thirteenth switch, the second end of the third switch is connected to the first end of the first buffer and the first end of the output terminal of the noise shaping circuit, the second end of the first buffer is connected to the first end of the fifth switch and the first end of the fourth switch, and the second end of the fifth switch is connected to the second end of the third sub-capacitor via the eleventh switch; the first end of the second switch is connected to the analog signal input terminal, the second end of the second switch is connected to the first end of the third sub-capacitor, the first end of the sixth switch is connected to the second end of the third sub-capacitor, and the second end of the sixth switch is connected to the first end of the first buffer.

[0008] According to an embodiment of the present disclosure, the noise shaping unit is further configured such that the first end of the second sub-capacitor is connected to the second end of the first sub-capacitor via the thirteenth and fourteenth switches, respectively; the second end of the second sub-capacitor is connected to the first end of the seventh switch and the second end of the eighth switch, the second end of the seventh switch is connected to the first end of the second buffer and the first end of the comparator, the second end of the second buffer is connected to the first end of the ninth switch and the first end of the eighth switch, and the second end of the ninth switch is connected to the second end of the fourth sub-capacitor; the first end of the fourth sub-capacitor is connected to the second end of the third sub-capacitor via the eleventh and twelfth switches, respectively; the first end of the tenth switch is connected to the second end of the fourth sub-capacitor, and the second end of the tenth switch is connected to the first end of the second buffer.

[0009] According to an embodiment of the present disclosure, the switch control signal is a periodic signal, and the switch control signal includes a first sub-signal and a second sub-signal; the first sub-signal and the second sub-signal are alternately configured to be high level based on a time period.

[0010] According to an embodiment of the present disclosure, the plurality of switches are configured to, in response to the first sub-signal, control the first switch, the third switch, the fifth switch, the eleventh switch, and the thirteenth switch to be closed, and the second switch, the fourth switch, and the sixth switch to be open, so that the first sub-capacitor is connected to the analog signal input terminal as the integrating capacitor, so that the first sub-capacitor superimposes the capacitor voltage stored in itself with the margin voltage provided by the analog signal input terminal to obtain a first integrated voltage, and provides the first integrated voltage to the first buffer, and enables the third sub-capacitor to serve as the storage capacitor, receive the first integrated voltage flowing through the first buffer, and perform row storage; the multiple switches are further configured to, in response to the first sub-signal, control the seventh switch, the ninth switch, and the fourteenth switch to be closed, and control the eighth switch, the tenth switch, and the twelfth switch to be open, so that the second sub-capacitor is connected to the first sub-capacitor as the integration capacitor, so that the second sub-capacitor superimposes the capacitor voltage stored in itself, the capacitor voltage stored in itself by the first sub-capacitor, and the margin voltage provided by the analog signal input terminal to obtain a second integration voltage, and provides the second integration voltage to the second buffer, and enables the fourth sub-capacitor to serve as the storage capacitor to receive and store the second integration voltage flowing through the second buffer.

[0011] According to an embodiment of the present disclosure, the above-mentioned multiple switches are configured to control the above-mentioned second switch, the above-mentioned fourth switch, the above-mentioned sixth switch, the above-mentioned eleventh switch, and the above-mentioned thirteenth switch to be closed in response to the above-mentioned second sub-signal, and control the above-mentioned first switch, the above-mentioned third switch, and the above-mentioned fifth switch to be opened, so that the above-mentioned third sub-capacitor is connected to the above-mentioned analog signal input terminal as the above-mentioned integrating capacitor, so that the above-mentioned third sub-capacitor superimposes the above-mentioned capacitor voltage stored in itself with the above-mentioned residual voltage provided by the above-mentioned analog signal input terminal to obtain a third integrated voltage, and provides the above-mentioned third integrated voltage to the above-mentioned first buffer, and makes the above-mentioned first sub-capacitor serve as the above-mentioned storage capacitor to receive the third integrated voltage flowing through the above-mentioned first buffer. and store them; the multiple switches are further configured to, in response to the second sub-signal, control the eighth switch, the tenth switch, and the twelfth switch to be closed, and control the seventh switch, the ninth switch, and the fourteenth switch to be opened, so that the fourth sub-capacitor is connected to the third sub-capacitor as the integration capacitor, so that the fourth sub-capacitor superimposes the capacitor voltage stored in itself, the capacitor voltage stored in itself by the third sub-capacitor, and the margin voltage provided by the analog signal input terminal to obtain a fourth integration voltage, and provides the fourth integration voltage to the second buffer, and enables the second sub-capacitor to serve as the storage capacitor to receive and store the fourth integration voltage flowing through the second buffer.

[0012] According to an embodiment of the present disclosure, the buffer includes a differential buffer, and the noise shaping circuit is further configured to connect the first capacitor or the second capacitor between multiple output terminals of the differential buffer to process the differential voltage output by the differential buffer.

[0013] According to an embodiment of the present disclosure, the above-mentioned multiple switches are configured as a charge pump switch structure, and the above-mentioned charge pump switch structure is configured to control the conduction and shutdown of multiple switch tubes in response to a two-phase non-overlapping clock signal to achieve an increase in the overdrive voltage of each of the above-mentioned multiple switches.

[0014] Another aspect of the present disclosure provides an analog-to-digital converter, comprising: the above-mentioned noise shaping circuit, a capacitor array, an amplifier, and a digital logic circuit; wherein the noise shaping circuit outputs an integrated voltage to the amplifier based on the residual voltage provided by the capacitor array; the amplifier and the digital logic circuit perform analog-to-digital conversion on the integrated voltage to obtain a conversion result, wherein the conversion result includes the residual voltage; and the digital logic circuit provides the residual voltage to the capacitor array.

[0015] The noise shaping circuit provided by the embodiments of the present disclosure ensures the continuity of the integration process by alternating between multiple integration capacitors and multiple storage capacitors, combined with the switching of multiple switches. This not only avoids the interference that may be caused by directly reading the integration results during the integration process, but also enables the expansion of higher-order structures, thereby more finely quantizing noise and improving the signal-to-noise ratio of the analog-to-digital converter. In addition, by introducing a buffer and storage capacitor to store the integration results, the circuit can achieve ideal integration without the use of an amplifier, so as to be used for subsequent analog-to-digital conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 The figure schematically shows a circuit structure diagram of a noise shaping circuit according to an embodiment of the present disclosure.

[0018] Figure 2 The figure schematically shows a circuit structure diagram of a noise shaping circuit according to a specific embodiment of the present disclosure.

[0019] Figure 3 The figure schematically shows a circuit structure diagram of a noise shaping circuit according to another specific embodiment of the present disclosure.

[0020] Figure 4 The figure schematically shows a noise shaping circuit diagram using differential integration according to a specific embodiment of the present disclosure.

[0021] Figure 5 The figure schematically shows a schematic diagram of the charge pump switch structure according to a specific embodiment of the present disclosure.

[0022] Figure 6 The figure schematically shows a circuit structure diagram of an analog-to-digital converter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0024] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0026] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0027] The core function of an analog-to-digital converter (ADC) is to accurately convert continuous analog signals into discrete digital signals. With the rapid advancement of cutting-edge technologies such as deep space exploration and quantum computing, ADC performance requirements are becoming increasingly stringent, requiring high speed and precision even in extremely low-temperature environments.

[0028] Under extremely low temperature conditions, the threshold voltage of the MOS tube becomes higher, the carrier activity slows down or even freezes, and the mismatch between devices of the same area is aggravated. These problems make it difficult for low-temperature ADCs to achieve the same performance as normal-temperature ADCs.

[0029] Noise shaping techniques can be used to improve ADC accuracy. Traditional successive approximation analog-to-digital converters (SAR ADCs) perform a binary search on the input signal during the comparator quantization stage. The voltage on the capacitor DAC successively approximates the input analog signal value. Since the SAR structure does not switch the signal after the least significant bit (LSB) is determined, the remaining voltage on the capacitor plate is an N-1-bit residual value. By extracting and processing this residual, quantization noise and comparator noise can be effectively shaped. Combined with oversampling, this further suppresses KT / C noise introduced by the in-band sampling switch, thereby improving the signal-to-noise ratio.

[0030] However, traditional successive approximation analog-to-digital converters (ADCs) use operational amplifiers (op amps) as integrators, which can lead to problems in cryogenic environments, such as increased power consumption, poles introduced by gain error, and significant effects of PVT (process, voltage, and temperature) variations on gain fluctuations. To meet the power consumption and process scaling characteristics of SAR structures, another approach to noise shaping is the fully passive NS-SAR structure. However, this structure only achieves lossy shaping, resulting in a shallow noise transfer function (NTF) at low frequencies. Furthermore, passive switched-capacitor filtering and dynamic amplifiers have been combined to optimize the low-frequency NTF, but PVT significantly impacts gain fluctuations and results in poor stability in cryogenic environments.

[0031] To address the aforementioned issues, embodiments of the present disclosure provide a noise shaping circuit and analog-to-digital converter. By alternating between multiple integration capacitors and multiple storage capacitors within the noise shaping circuit, combined with the switching of multiple switches, the circuit ensures the continuity of the integration process. This not only avoids interference that could result from directly reading the integration result during the integration process, but also enables the expansion of higher-order structures, resulting in more refined noise quantization and improved signal-to-noise ratio (SNR) of the analog-to-digital converter. Furthermore, by introducing a buffer and storage capacitor to store the integration result, the circuit achieves ideal integration without the use of an amplifier, allowing for subsequent analog-to-digital conversion.

[0032] Specifically, an embodiment of the present disclosure provides a noise shaping circuit, wherein the noise shaping circuit includes: multiple switches, a first capacitor, a second capacitor, and a buffer connected between the first capacitor and the second capacitor; the multiple switches are configured to respond to switch control signals to alternately connect one of the first capacitor and the second capacitor as an integrating capacitor to an analog signal input terminal, so that the integrating capacitor provides an integrated voltage to the buffer based on the residual voltage provided by the analog signal input terminal and the capacitor voltage stored in the integrating capacitor, and enables the other of the first capacitor and the second capacitor to serve as a storage capacitor to receive and store the integrated voltage flowing through the buffer; the integrating capacitor is configured to output the integrated voltage to the output terminal of the noise shaping circuit, so that the digital logic circuit performs analog-to-digital conversion on the integrated voltage to obtain a residual voltage and provide it to the analog signal input terminal.

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0034] According to an embodiment of the present disclosure, the noise shaping circuit proposed in the present disclosure includes multiple switches, a first capacitor, a second capacitor, and a buffer connected between the first capacitor and the second capacitor. Under the control of a switch control signal, the multiple switches respectively conduct different paths, alternately connecting one of the first capacitor and the second capacitor as an integrating capacitor to the analog signal input terminal to superimpose the unquantized residual voltage of the previous ADC operation cycle with the capacitor voltage stored in the integrating capacitor itself, and the other capacitor as a storage capacitor to store the integration result through the buffer. The buffer can be used to isolate the integrating capacitor and the storage capacitor to reduce the mutual influence between the capacitors and provide a stable input for subsequent ADC conversion.

[0035] Figure 1 The figure schematically shows a circuit structure diagram of a noise shaping circuit according to an embodiment of the present disclosure.

[0036] like Figure 1 As shown, the multiple switches include, for example, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, and a tenth switch S10; wherein the multiple switches also include, for example, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, and a fourteenth switch S14; the first capacitor includes, for example, a first sub-capacitor Co1 and a second sub-capacitor Co2; the second capacitor includes, for example, a third sub-capacitor Ce1 and a fourth sub-capacitor Ce2; and the buffer includes, for example, a first buffer BUFF1 and a second buffer BUFF2, so as to form a second-order noise shaping circuit.

[0037] Specifically, a first end of the first switch S1 is connected to the analog signal input end and the output end of the noise shaping circuit, respectively; a second end of the first switch S1 is connected to the first end of the first sub-capacitor Co1; a second end of the first sub-capacitor Co1 is connected to the first end of the third switch S3 and the second end of the fourth switch S4 via the thirteenth switch S13, respectively; a second end of the third switch S3 is connected to the first end of the first buffer BUFF1 and the output end of the noise shaping circuit, a second end of the first buffer BUFF1 is connected to the first end of the fifth switch S5 and the first end of the fourth switch S4, respectively; a second end of the fifth switch S5 is connected to the second end of the third sub-capacitor Ce1 via the eleventh switch S11.

[0038] Among them, the first end of the second switch S2 is connected to the analog signal input end and the output end of the noise shaping circuit respectively, the second end of the second switch S2 is connected to the first end of the third sub-capacitor Ce1, the first end of the sixth switch S6 is connected to the second end of the third sub-capacitor Ce1, and the second end of the sixth switch S6 is connected to the first end of the first buffer BUFF1.

[0039] The first end of the second sub-capacitor Co2 is connected to the second end of the first sub-capacitor Co1 via the thirteenth switch S13 and the fourteenth switch S14, respectively. The second end of the second sub-capacitor Co2 is connected to the first end of the seventh switch S7 and the second end of the eighth switch S8. The second end of the seventh switch S7 is connected to the first end of the second buffer BUFF2 and the output end of the noise shaping circuit, respectively. The second end of the second buffer BUFF2 is connected to the first end of the ninth switch S9 and the first end of the eighth switch S8, respectively. The second end of the ninth switch S9 is connected to the second end of the fourth sub-capacitor Ce2.

[0040] The first end of the fourth sub-capacitor Ce2 is connected to the second end of the third sub-capacitor Ce1 via the eleventh switch S11 and the twelfth switch S12 respectively. The first end of the tenth switch S10 is connected to the second end of the fourth sub-capacitor Ce2. The second end of the tenth switch S10 is connected to the first end of the second buffer BUFF2.

[0041] like Figure 1As shown, the multiple switches further include, for example, a first grounding switch QE1, a second grounding switch QE2, a third grounding switch QE3, and a fourth grounding switch QE4. A first end of the first grounding switch QE1 is connected to a first end of the third sub-capacitor Ce1, and a second end of the first grounding switch QE1 is grounded. A first end of the second grounding switch QE2 is connected to a fourth sub-capacitor Ce2, and a second end of the second grounding switch QE2 is grounded. A first end of the third grounding switch QE3 is connected to a first end of the first sub-capacitor Co1, and a second end of the first grounding switch QE4 is grounded. A first end of the fourth grounding switch QE4 is connected to a second sub-capacitor Co2, and a second end of the fourth grounding switch QE4 is grounded.

[0042] According to embodiments of the present disclosure, a switch control signal can be used to characterize the operating cycle of an analog-to-digital converter (ADC), such as the ADC's sampling period or conversion period. The switch control signal includes a first sub-signal and a second sub-signal, which alternately maintain different levels over time. For example, when the first sub-signal is high, the second sub-signal is low.

[0043] According to an embodiment of the present disclosure, multiple switches perform a ping-pong operation on the first capacitor and the second capacitor based on the control of the first sub-signal and the second sub-signal, so that the first capacitor and the second capacitor alternately serve as an integration capacitor or a storage capacitor, thereby realizing a continuous integration process without using a closed-loop amplifier in the noise shaping circuit.

[0044] For example, when the first sub-signal is at a high level during the 2k-1th cycle, the first capacitor functions as an integrating capacitor and the second capacitor functions as a storage capacitor. The first capacitor integrates the unquantized residual voltage during the 2k-2th cycle with its own integrated voltage stored during the 2k-2th cycle, outputting the integrated voltage during the 2k-1th cycle for quantization. This integrated voltage is also stored in the second capacitor via a buffer.

[0045] For example, when the second sub-signal is at a high level during the 2kth cycle, the second capacitor functions as an integrating capacitor and the first capacitor functions as a storage capacitor. The second capacitor integrates the unquantized residual voltage during the 2k-1th cycle with its own integrated voltage stored during the 2k-1th cycle, outputting the integrated voltage during the 2kth cycle for quantization. This integrated voltage is also stored in the first capacitor via a buffer.

[0046] Figure 2 The figure schematically shows a circuit structure diagram of a noise shaping circuit according to a specific embodiment of the present disclosure.

[0047] like Figure 2As shown, during the operation cycle when the first sub-signal CLKS1 is at a high level, the first switch S1, the third switch S3, the fifth switch S5, the first grounding switch QE1, the second grounding switch QE2, the eleventh switch S11, and the thirteenth switch S13 are closed, and the second switch S2, the fourth switch S4, the sixth switch S6, the third grounding switch QE3, and the fourth grounding switch QE4 are opened, so that the first sub-capacitor Co1 is connected to the analog signal input terminal as an integrating capacitor, so that the first sub-capacitor Co1 can store the capacitor voltage V Co1 The analog signal input provides a margin voltage V res The first integral voltage is obtained by superposition and used as the output voltage V out2 Output from the output terminal; at the same time, the first sub-capacitor Co1 provides the first integrated voltage to the first buffer BUFF1. The third sub-capacitor Ce1 acts as a storage capacitor, receiving the first integrated voltage flowing through the first buffer BUFF1 as the voltage V stored in the third sub-capacitor Ce1 itself. Ce1 At this time, the voltage V stored in the third sub-capacitor Ce1 itself Ce1 =V Co1 +V res .

[0048] In addition, during the operation cycle when the first sub-signal CLKS1 is at a high level, the seventh switch S7, the ninth switch S9, and the fourteenth switch S14 are closed, and the eighth switch S8, the tenth switch S10, and the twelfth switch S12 are opened, so that the second sub-capacitor Co2 is connected to the first sub-capacitor Co1 as an integrating capacitor, so that the second sub-capacitor Co2 can store the capacitor voltage V Co2 , the capacitor voltage V stored in the first sub-capacitor itself Co1 The analog signal input provides a margin voltage V res The second integral voltage is obtained by superposition and used as the output voltage V out3 Output from the output terminal; at the same time, provide the second integrated voltage to the second buffer BUFF2. The fourth sub-capacitor Ce2 acts as a storage capacitor, receiving the second integrated voltage flowing through the second buffer BUFF2 as the voltage V stored in the fourth sub-capacitor Ce2 itself. Ce2 At this time, the voltage V stored in the fourth sub-capacitor Ce2 itself Ce2 =V Co1 +V Co2+ V res .

[0049] Figure 3 The figure schematically shows a circuit structure diagram of a noise shaping circuit according to another specific embodiment of the present disclosure.

[0050] like Figure 3As shown, during the operation cycle when the second sub-signal CLKS2 is at a high level, the second switch S2, the fourth switch S4, the sixth switch S6, the third ground switch QE3, the fourth ground switch QE4, the eleventh switch S11, and the thirteenth switch S13 are closed, and the first switch S1, the third switch S3, the fifth switch S5, the first ground switch QE1, and the second ground switch QE2 are opened, so that the third sub-capacitor Ce1 is connected to the analog signal input terminal as an integrating capacitor, so that the third sub-capacitor Ce1 can store the capacitor voltage V Ce1 The analog signal input provides a margin voltage V res The third integrated voltage is obtained by superposition and used as the output voltage V out2 Output from the output terminal; at the same time, provide the third integrated voltage to the first buffer BUFF1. The first sub-capacitor Co1 acts as a storage capacitor, receiving the third integrated voltage flowing through the first buffer BUFF1 as the voltage V stored in the first sub-capacitor Co1 itself. Co1 At this time, the voltage V stored in the first sub-capacitor Co1 itself Co1 =V Ce1 +V res .

[0051] In addition, during the operation cycle when the second sub-signal CLKS2 is at a high level, the eighth switch S8, the tenth switch S10, and the twelfth switch S12 are closed, and the seventh switch S7, the ninth switch S9, and the fourteenth switch S14 are opened, so that the fourth sub-capacitor Ce2 is connected to the third sub-capacitor Ce1 as an integrating capacitor, so that the fourth sub-capacitor Ce2 can store the capacitor voltage V Ce2 , the capacitor voltage V stored in the third sub-capacitor Ce1 itself Ce1 The analog signal input provides a margin voltage V res The fourth integrated voltage is obtained by superposition and used as the output voltage V out3 Output from the output terminal; at the same time, provide the fourth integrated voltage to the second buffer BUFF2. The second sub-capacitor Co2 serves as a storage capacitor, receiving the fourth integrated voltage flowing through the second buffer BUFF2 as the voltage V stored in the second sub-capacitor Co2 itself. Co2 At this time, the voltage V stored in the second sub-capacitor Co2 itself Co2 =V Ce1 + V Ce2+ V res .

[0052] Based on this, the disclosed embodiments alternately use multiple integration capacitors and multiple storage capacitors in a noise shaping circuit. Combined with the switching of multiple switches, this ensures the continuity of the integration process. This not only avoids the interference that could result from directly reading the integration result during the integration process, but also enables the expansion of higher-order structures, allowing for more precise quantization of noise and improving the signal-to-noise ratio of the analog-to-digital converter. Furthermore, by introducing a buffer and storage capacitors to store the integration result, the circuit achieves ideal integration without the use of an amplifier, allowing for subsequent analog-to-digital conversion.

[0053] According to an embodiment of the present disclosure, the noise shaping unit is further configured to connect the first capacitor or the second capacitor between the multiple output terminals of the buffer to process the differential voltage output by the buffer.

[0054] According to the embodiments of the present disclosure, since single-ended integration has problems such as the DC component of the integrating capacitor being easily saturated, buffer offset, and common-mode voltage mismatch, a differential buffer can be used, and the integrating capacitor can be set between multiple output terminals of the differential buffer. The differential buffer and the integrating capacitor can be used to perform differential integration, thereby using the differential signal to offset part of the DC offset to avoid saturation of the integrating capacitor and buffer offset.

[0055] According to embodiments of the present disclosure, the buffer and storage capacitor can also be chopped to achieve differential integration. Under the same kT / C noise, using differential integration can reduce the total storage capacitor size in the differential ADC by four times compared to single-ended integration, thereby reducing circuit complexity and cost. Furthermore, using chopping technology to periodically flip the noise shaping circuit can reduce flicker noise in the buffer, thereby reducing its impact on the integration result.

[0056] Figure 4 The figure schematically shows a noise shaping circuit diagram using differential integration according to a specific embodiment of the present disclosure.

[0057] like Figure 4 As shown in the figure, in a second-order noise shaping circuit using differential integration, the first sub-capacitor Co1 is stacked on the upper plate of the capacitor of the digital-to-analog conversion circuit. At the same time, the second sub-capacitor Co2 is stacked on the lower plate of the capacitor of the digital-to-analog conversion circuit. According to the principle of charge conservation of capacitors, when a new signal voltage is added to the capacitor, it will be added to the original voltage on the capacitor. Therefore, this stacking operation realizes the integration result of the current input signal and the previous operation cycle, that is, the capacitor voltage V stored in the first sub-capacitor Co1 itself. Co1 And the capacitor voltage V stored in the second sub-capacitor Co2 itself Co2 Specifically, the digital-to-analog converter (DAC) generates an unquantized residual voltage V according to the input digital code. res The noise shaping circuit obtains the residual voltage V from the DAC plate.res , the margin voltage V res Based on the superposition of the integral capacitor and the voltage stored on the integral capacitor, the integral result is obtained, that is, V Ce2 =V Co1 + V Co2+ V res After the integration is completed, the integration result can be compared by starting the comparator to determine whether the integration result has reached the conversion threshold and trigger the ADC sampling or conversion process. In the next operation cycle, the noise shaping circuit is flipped to perform the chopping operation, and the third sub-capacitor Ce1 is stacked on the capacitor p-plate of the digital-to-analog conversion circuit. At the same time, the fourth sub-capacitor Ce2 is stacked on the capacitor n-plate of the digital-to-analog conversion circuit to achieve the capacitor voltage V stored in the third sub-capacitor Ce1 itself. Ce1 and the capacitor voltage V stored in the fourth sub-capacitor Ce2 itself Ce2 The noise shaping circuit obtains the remaining voltage V from the DAC plate. res , the margin voltage V res Based on the superposition of the integral capacitor and the voltage stored on the integral capacitor, the integral result is obtained, that is, V Co2 =V Ce1 + V Ce2+ V res .

[0058] According to an embodiment of the present disclosure, multiple switches are configured as a charge pump switch structure, and the charge pump switch structure is configured to control the conduction and shutdown of multiple switch tubes in response to a two-phase non-overlapping clock signal to achieve an increase in the overdrive voltage of each of the multiple switches.

[0059] According to an embodiment of the present disclosure, due to the increase in threshold voltage at low temperatures, the traditional switch has a slow opening speed and a large on-resistance. Therefore, multiple switches in the present disclosure all adopt a charge pump switch structure, which includes multiple switch tubes. The multiple switch tubes realize charge transfer and voltage increase under the control of two-phase non-overlapping clock signals.

[0060] Figure 5 The figure schematically shows a schematic diagram of the charge pump switch structure according to a specific embodiment of the present disclosure.

[0061] like Figure 5 As shown, the charge pump switch structure includes a first switch transistor M1, a second switch transistor M2, a third switch transistor M3, a fourth switch transistor M4, and a fifth switch transistor M5, as well as a first switch capacitor C1 and a second switch capacitor C2. The two-phase non-overlapping clock signals controlling the charge pump switch structure include a first clock signal CLKS and a second clock signal CLKSB.

[0062] The source of the first switch M1 is connected to the power supply VDD, the drain of the first switch M1 is connected to the top plate of the first switched capacitor C1, and the gate of the first switch M1 is connected to the top plate of the second switched capacitor C2. The source of the second switch M2 is connected to the power supply VDD, the drain of the second switch M2 is connected to the top plate of the second switched capacitor C2, and the gate of the second switch M2 is connected to the top plate of the first switched capacitor C1. The source of the third switch M3 is connected to the CLKSBOOST signal line, the drain of the third switch M3 is connected to the top plate of the first switched capacitor C1, and the gate of the third switch M3 is connected to the power supply VDD to ensure conduction during the boost phase. The source of the fourth switch tube M4 is connected to the first clock signal CLKS, the drain of the fourth switch tube M4 is connected to the CLKSBOOST signal line, and the gate of the fourth switch tube M4 is connected to the power supply VDD to ensure that it is turned on in the reset phase and turned off in the boost phase; the gate of the fifth switch tube M5 is connected to the CLKSBOOST signal line, the source of the fifth switch tube M5 is connected to the input voltage VIN, and the drain of the fifth switch tube M5 is connected to the output voltage VOUT.

[0063] According to an embodiment of the present disclosure, the charge pump switch structure includes a reset stage and a boost stage.

[0064] Specifically, during the reset phase, when the first clock signal CLKS is low and the second clock signal CLKSB is high, the fourth switch M4 turns on, pulling the CLKSBOOST signal line to a low level. Simultaneously, the lower plates of the first and second switched capacitors C1 and C2 are connected to the low-level VSS and high-level VDD, respectively, preparing for the subsequent boost phase. During this phase, the first switch M1 turns on and charges the top plate of the first switched capacitor C1, while the second and third switches M2 and M3 are off.

[0065] During the boost phase, when the first clock signal CLKS is high (VDD), the second clock signal CLKSB is low, and the fourth switch M4 is turned off. The connection states of the bottom plates of the first and second switched capacitors C1 and C2 are reversed, with the bottom plate of the first switched capacitor C1 at high VDD and the bottom plate of the second switched capacitor C2 at low VSS. Because the first switched capacitor C1 has already been charged to VDD during the reset phase, the voltage on the top plate of the first switched capacitor C1 rises to 2VDD during the boost phase. At this point, the third switch M3 turns on, transferring the voltage on the top plate of the first switched capacitor C1 to the CLKSBOOST signal line, achieving a boosted output, thereby turning on the fifth switch M5.

[0066] Based on this, the embodiments of the present disclosure precisely control the two-phase non-overlapping clock signals to ensure that the charge pump switch structure smoothly transitions between the reset and boost stages, thereby outputting a stable boost voltage, significantly improving the overdrive voltage of multiple switches while reducing resistance, so that it maintains good linearity, thereby avoiding nonlinear errors that may occur in integration.

[0067] Figure 6 The figure schematically shows a circuit structure diagram of an analog-to-digital converter according to an embodiment of the present disclosure.

[0068] like Figure 6 As shown, the analog-to-digital converter includes a capacitor array 1 , a noise shaping circuit 2 , an amplifier 3 and a digital logic circuit 4 .

[0069] According to an embodiment of the present disclosure, the noise shaping circuit 2 can output an integrated voltage to the amplifier 3 based on the residual voltage provided by the capacitor array 1, and implement integration using capacitor stacking. In addition, since the buffer is simple and has little effect on PVT alignment, and a differential buffer is used as a buffer, and the integration and storage capacitors are integrated and stored, a continuous integration process is achieved without using a closed-loop amplifier by alternating integration and storage operations between multiple capacitors, thereby achieving a sharp NTF with zero close to the unit circle. At the same time, quantization noise or other types of noise are pushed to a higher frequency range, achieving a lower noise level and higher resolution within the target bandwidth.

[0070] According to an embodiment of the present disclosure, capacitor array 1 can be used to sample and hold the charge of an input signal. During the sampling phase, capacitor array 1 captures the charge of the input signal; during the holding phase, capacitor array 1 retains the captured charge for subsequent circuit processing. Capacitor array 1 also provides a margin voltage Vres to noise shaping circuit 2 and receives margin voltage Vres feedback from digital logic circuit 4 for the next round of sampling and holding.

[0071] According to an embodiment of the present disclosure, the amplifier 3 may be used to enhance the amplitude of the integrated voltage so that the subsequent digital logic circuit 4 can accurately identify and convert it.

[0072] According to an embodiment of the present disclosure, digital logic circuit 4 can be used to perform analog-to-digital conversion on the amplified integrated voltage to obtain a conversion result, wherein the conversion result includes the residual voltage Vres. Digital logic circuit 4 feeds the residual voltage Vres back to the capacitor array, so that the capacitor array performs the next round of sampling, holding, and integration based on the fed-back residual voltage. Through multiple iterations, the analog-to-digital converter gradually approaches the true value of the input signal and outputs a high-precision digital signal.

[0073] In one embodiment of the present disclosure, this method achieves a 93.3 dB SNDR over a 250 kHz bandwidth with an oversampling ratio (OSR) of 10. Since this analog-to-digital conversion circuit achieves an SNDR greater than 90 dB over a bandwidth greater than 100 kHz, it demonstrates that signal integrity is well maintained during the conversion process while suppressing noise and distortion. Meanwhile, it consumes 340 μW of power, demonstrating that this analog-to-digital conversion circuit maintains low energy consumption while providing high performance.

[0074] Based on this, the embodiments of the present disclosure utilize a noise shaping circuit and multiple iterations to create an analog-to-digital converter that approximates the true value of the input signal, achieving high-precision, low-noise, and low-power analog-to-digital conversion. Furthermore, the noise shaping circuit proposed in the present disclosure can push quantization noise or other types of noise to higher frequencies, thereby achieving lower noise levels within the target bandwidth.

[0075] The embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that any implementations not depicted or described in the drawings or the main text of the specification are known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods described in the embodiments; those skilled in the art may easily modify or replace them.

[0076] Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted when they may cause confusion in understanding the present disclosure.

[0077] Furthermore, the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but are merely illustrative of the contents of the embodiments of the present disclosure. In addition, in the claims, any reference signs placed between brackets should not be construed as limiting the claims.

[0078] Unless otherwise indicated, the numerical parameters in this specification and the appended claims are approximate and can vary depending on the desired properties obtained through the content of this disclosure. In particular, all numbers used in the specification and claims to express composition amounts, reaction conditions, etc. are to be understood as being modified in all cases by the term "about." Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0079] The use of ordinal numbers such as "first," "second," and "third" in the specification and claims to modify corresponding elements does not in itself mean that the elements have any ordinal number, nor does it represent the order of one element relative to another or the order in the manufacturing method. The use of such ordinal numbers is only used to clearly distinguish one element with a certain name from another element with the same name.

[0080] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.

[0081] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A noise shaping circuit, wherein: The noise shaping circuit includes: a plurality of switches, a first capacitor, a second capacitor, and a buffer connected between the first capacitor and the second capacitor; The plurality of switches are configured to, in response to a switch control signal, alternately connect one of the first capacitor and the second capacitor as an integrating capacitor to the analog signal input terminal, so that the integrating capacitor provides an integrated voltage to the buffer based on a residual voltage provided by the analog signal input terminal and a capacitor voltage stored therein, and to connect the other of the first capacitor and the second capacitor as a storage capacitor to receive and store the integrated voltage flowing through the buffer; The integrating capacitor is configured to output the integrated voltage to the output terminal of the noise shaping circuit, so that the digital logic circuit performs analog-to-digital conversion on the integrated voltage to obtain the residual voltage and provide it to the analog signal input terminal; The plurality of switches include a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch; the first capacitor includes a first sub-capacitor and a second sub-capacitor, the second capacitor includes a third sub-capacitor and a fourth sub-capacitor, and the buffer includes a first buffer and a second buffer; The noise shaping circuit is configured such that a first end of the first switch is connected to the analog signal input end, a second end of the first switch is connected to the first end of the first sub-capacitor, a second end of the first sub-capacitor is connected to the first end of the third switch and the second end of the fourth switch via the thirteenth switch, a second end of the third switch is connected to the first end of the first buffer and the first end of the output end of the noise shaping circuit, a second end of the first buffer is connected to the first end of the fifth switch and the first end of the fourth switch, and a second end of the fifth switch is connected to the second end of the third sub-capacitor via the eleventh switch; a first end of the second switch connected to the analog signal input terminal, a second end of the second switch connected to the first end of the third sub-capacitor, a first end of the sixth switch connected to the second end of the third sub-capacitor, and a second end of the sixth switch connected to the first end of the first buffer; The noise shaping circuit is further configured such that the first end of the second sub-capacitor is connected to the second end of the first sub-capacitor via the thirteenth and fourteenth switches, respectively; the second end of the second sub-capacitor is connected to the first end of the seventh switch and the second end of the eighth switch, the second end of the seventh switch is connected to the first end of the second buffer and the first end of the comparator, the second end of the second buffer is connected to the first end of the ninth switch and the first end of the eighth switch, and the second end of the ninth switch is connected to the second end of the fourth sub-capacitor; The first end of the fourth sub-capacitor is connected to the second end of the third sub-capacitor via the eleventh switch and the twelfth switch, respectively. The first end of the tenth switch is connected to the second end of the fourth sub-capacitor. The second end of the tenth switch is connected to the first end of the second buffer.

2. The circuit according to claim 1, wherein The switch control signal is a periodic signal, and includes a first sub-signal and a second sub-signal; the first sub-signal and the second sub-signal are alternately configured to be high level based on a time period.

3. The circuit according to claim 2, wherein The plurality of switches are configured to, in response to the first sub-signal, control the first switch, the third switch, the fifth switch, the eleventh switch, and the thirteenth switch to be closed, and the second switch, the fourth switch, and the sixth switch to be open, so that the first sub-capacitor functions as the integrating capacitor and is connected to the analog signal input terminal, so that the first sub-capacitor superimposes the capacitor voltage stored therein with the margin voltage provided by the analog signal input terminal to obtain a first integrated voltage, and provides the first integrated voltage to the first buffer, and the third sub-capacitor functions as the storage capacitor to receive and store the first integrated voltage flowing through the first buffer; The multiple switches are further configured to, in response to the first sub-signal, control the seventh switch, the ninth switch, and the fourteenth switch to be closed, and control the eighth switch, the tenth switch, and the twelfth switch to be open, so that the second sub-capacitor serves as the integrating capacitor and is connected to the first sub-capacitor, so that the second sub-capacitor superimposes the capacitor voltage stored in itself, the capacitor voltage stored in itself by the first sub-capacitor, and the margin voltage provided by the analog signal input terminal to obtain a second integrated voltage, and provides the second integrated voltage to the second buffer, and enables the fourth sub-capacitor to serve as the storage capacitor to receive and store the second integrated voltage flowing through the second buffer.

4. The circuit according to claim 2, wherein The plurality of switches are configured to, in response to the second sub-signal, control the second switch, the fourth switch, the sixth switch, the eleventh switch, and the thirteenth switch to be closed, and control the first switch, the third switch, and the fifth switch to be open, so that the third sub-capacitor is connected to the analog signal input terminal as the integrating capacitor, so that the third sub-capacitor superimposes the capacitor voltage stored in the third sub-capacitor with the margin voltage provided by the analog signal input terminal to obtain a third integrated voltage, provides the third integrated voltage to the first buffer, and enables the first sub-capacitor to function as the storage capacitor to receive and store the third integrated voltage flowing through the first buffer; The multiple switches are further configured to, in response to the second sub-signal, control the eighth switch, the tenth switch, and the twelfth switch to be closed, and control the seventh switch, the ninth switch, and the fourteenth switch to be open, so that the fourth sub-capacitor serves as the integrating capacitor and is connected to the third sub-capacitor, so that the fourth sub-capacitor superimposes the capacitor voltage stored in the fourth sub-capacitor, the capacitor voltage stored in the third sub-capacitor, and the margin voltage provided by the analog signal input terminal to obtain a fourth integrated voltage, and provides the fourth integrated voltage to the second buffer, and enables the second sub-capacitor to serve as the storage capacitor to receive and store the fourth integrated voltage flowing through the second buffer.

5. The circuit according to any one of claims 1 to 4, wherein: The buffer includes a differential buffer, and the noise shaping circuit is further configured to connect the first capacitor or the second capacitor between multiple output terminals of the differential buffer to process the differential voltage output by the differential buffer.

6. The circuit according to any one of claims 1 to 4, wherein: The multiple switches are configured as a charge pump switch structure, which is configured to control the on and off of the multiple switch tubes in response to a two-phase non-overlapping clock signal to achieve an increase in the overdrive voltage of each of the multiple switches.

7. An analog-to-digital converter, comprising: The noise shaping circuit, capacitor array, amplifier, and digital logic circuit according to any one of claims 1 to 6; wherein the noise shaping circuit outputs an integrated voltage to the amplifier based on the margin voltage provided by the capacitor array; The amplifier and the digital logic circuit perform analog-to-digital conversion on the integrated voltage to obtain a conversion result, wherein the conversion result includes the residual voltage; The digital logic circuit provides the margin voltage to the capacitor array.

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