IO-Link system synchronization method, device, equipment and medium

Abstract

The invention discloses an IO-Link system synchronization method and device, equipment and a medium, and relates to the technical field of field bus communication, and the method comprises the steps: judging whether slave equipment supports synchronization or not; if the slave equipment supports synchronization, writing a synchronous clock of a bus into the slave equipment which supports synchronization, so that the slave equipment adjusts a local clock into the synchronous clock; determining message transmission delays of slave devices supporting synchronization, comparing the message transmission delays, and determining the maximum message transmission delay; and writing the maximum message transmission delay into slave equipment supporting synchronization, so that the slave equipment executes a control command according to the input data when the timing time reaches the maximum message transmission delay. According to the method, the problems of clock skew and clock drift of the slave devices in the IO-Link system can be solved, the clock skew of the master device and the slave devices in the control device and the IO-Link system is eliminated, and synchronous action between the slave devices is ensured.

Description

Technical Field

[0001] The present application relates to the field of field bus communication technology, and in particular to an IO-Link system synchronization, device, equipment and computer-readable storage medium. Background Art

[0002] The IO-Link (full name: Input / Output Link) system includes master devices and slave devices, and is located in the bottom network of the industrial automation system. The master device of the IO-Link system usually integrates a gateway application, which is responsible for converting the data of the slave devices of the IO-Link system to access the upper-level industrial Ethernet or fieldbus, and connecting with the control-level devices (such as PLC). The slave devices of the IO-Link system are generally sensors and actuator devices, which are responsible for executing upper-level control commands or feedback sampling information. At present, each slave device in the IO-Link system has problems with clock offset and clock drift. There is a time offset when the slave device collects and executes data, which cannot meet the requirements of simultaneous operation of the equipment under some working conditions. The failure of the slave devices to act at the same time will cause mechanical interference and other problems. Therefore, how to solve this problem has become a technical problem that needs to be solved urgently by technicians in this field. Summary of the invention

[0003] The purpose of the present application is to provide an IO-Link system synchronization method, apparatus, device and computer readable, which can eliminate the clock offset and clock drift problems of slave devices in the IO-Link system, eliminate the clock deviation of the control device and the master and slave devices in the IO-Link system, and ensure synchronous action between slave devices.

[0004] In order to solve the above technical problems, the present application provides an IO-Link system synchronization method, which is applied to a master device, comprising:

[0005] Determine whether the slave device supports synchronization;

[0006] If the slave device supports synchronization, writing the synchronous clock of the bus into the slave device supporting synchronization, so that the slave device adjusts the local clock to the synchronous clock;

[0007] Determining a message transmission delay of a slave device supporting synchronization, and comparing each of the message transmission delays to determine a maximum message transmission delay;

[0008] The maximum message transmission delay is written into a slave device supporting synchronization, so that the slave device executes a control command according to input data when the timing time reaches the maximum message transmission delay.

[0009] In some embodiments, writing the synchronous clock of the bus to the slave device supporting synchronization includes:

[0010] In a first target cycle within a preset number of IO-Link cycles after a connection is established with a slave device supporting synchronization, the synchronous clock of the bus is written to the slave device supporting synchronization through on-demand data; wherein process data within the preset number of IO-Link cycles is invalid.

[0011] In some embodiments, determining a message transmission delay of a slave device supporting synchronization includes:

[0012] In a second target cycle within a preset number of IO-Link cycles after establishing a connection with a slave device supporting synchronization, obtaining a data receiving time of the slave device supporting synchronization; wherein the process data within the preset number of IO-Link cycles is invalid;

[0013] The message transmission delay of the slave device is determined according to the data receiving time of the slave device and the data sending time of the master device.

[0014] In some embodiments, there is a first time offset between the start time of the IO-Link cycle period corresponding to the slave device supporting synchronization and the start time of the bus cycle period; the bus cycle period is the message interaction period between the master device and the upper-level control device; the IO-Link cycle period is the message interaction period between the master device and the slave device.

[0015] In some embodiments, it also includes:

[0016] Determining a time margin according to a synchronization cycle of the bus;

[0017] The first time offset is determined according to the time margin and the conversion time; the conversion time is the time taken by the master device to parse the bus data and convert it into a message.

[0018] In some embodiments, it also includes:

[0019] After the previously preset number of IO-Link cycles are completed, valid process data is transmitted, and when the on-demand data is idle, the synchronous clock of the bus is written to the slave device supporting synchronization through the on-demand data.

[0020] In some embodiments, determining whether the slave device supports synchronization includes:

[0021] Determining whether the slave device has on-demand data and whether a value of the on-demand data is an expected value;

[0022] If the slave device has on-demand data and the value of the on-demand data is an expected value, the slave device supports synchronization.

[0023] In some embodiments, it also includes:

[0024] If the slave device does not support synchronization, determining a second time offset corresponding to the slave device that does not support synchronization; the second time offset is greater than the first time offset corresponding to the slave device that supports synchronization;

[0025] The start time of the synchronization cycle of the bus is offset by the second time offset to perform message interaction with a slave device that does not support synchronization.

[0026] In some embodiments, determining the second time offset corresponding to the slave device that does not support synchronization includes:

[0027] Determining an average value of the message request response time of the slave device that does not support synchronization when reading and writing page parameters of the slave device that does not support synchronization within a preset number of IO-Link cycle periods, based on the message request response time of the slave device that does not support synchronization;

[0028] determining a time offset increment of a slave device that does not support synchronization based on the average value;

[0029] Determining a time margin according to a synchronization cycle of the bus;

[0030] The second time offset is determined according to the time margin, the conversion time and the time offset increment; the conversion time is the time for the master device to parse the bus data and convert it into a message.

[0031] In order to solve the above technical problems, the present application also provides an IO-Link system synchronization device, including:

[0032] A judgment module, used to judge whether the slave device supports synchronization;

[0033] A synchronous clock writing module, used for writing the synchronous clock of the bus into the slave device supporting synchronization if the slave device supports synchronization, so that the slave device adjusts the local clock to the synchronous clock;

[0034] A message transmission delay determination module, used to determine the message transmission delay of the slave device supporting synchronization, and compare the message transmission delays to determine the maximum message transmission delay;

[0035] The message transmission delay writing module is used to write the maximum message transmission delay into the slave device supporting synchronization, so that the slave device executes the control command according to the input data when the timing time reaches the maximum message transmission delay.

[0036] In order to solve the above technical problems, the present application also provides an IO-Link system synchronization device, including:

[0037] Memory for storing computer programs;

[0038] A processor is used to implement the steps of the IO-Link system synchronization method as described above when executing the computer program.

[0039] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the IO-Link system synchronization method as described above are implemented.

[0040] The IO-Link system synchronization method provided in the present application includes: determining whether a slave device supports synchronization; if the slave device supports synchronization, writing the synchronous clock of the bus into the slave device supporting synchronization, so that the slave device adjusts the local clock to the synchronous clock; determining the message transmission delay of the slave device supporting synchronization, and comparing each of the message transmission delays to determine the maximum message transmission delay; writing the maximum message transmission delay into the slave device supporting synchronization, so that the slave device executes a control command according to input data when the timing time reaches the maximum message transmission delay.

[0041] It can be seen that in the IO-Link system synchronization method provided by the present application, the master device sends the synchronization clock to the slave device, and the slave device adjusts the local clock to the synchronization clock to achieve clock synchronization of each slave device. In addition, the master device sends the maximum message transmission delay to the slave device, and the slave device uniformly executes the control command when the timing reaches the maximum message transmission delay to achieve synchronous action between slave devices. The application of this method can eliminate the clock offset and clock drift problems of slave devices in the IO-Link system, eliminate the clock deviation of the control device and the master and slave devices in the IO-Link system, and ensure synchronous action between slave devices.

[0042] The IO-Link system synchronization device, equipment, and computer-readable storage medium provided in this application all have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the prior art and the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A flowchart of an IO-Link system synchronization method provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of a main device workflow provided in an embodiment of the present application;

[0046] Figure 3 A schematic diagram of a slave device workflow provided by an embodiment of the present application;

[0047] Figure 4 A schematic diagram of an IO-Link system synchronization device provided in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of an IO-Link system synchronization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The core of this application is to provide an IO-Link system synchronization method, device, equipment and computer-readable, which can eliminate the clock offset and clock drift problems of slave devices in the IO-Link system, eliminate the clock deviation of the control device and the master and slave devices in the IO-Link system, and ensure synchronous action between slave devices.

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] Please refer to Figure 1 , Figure 1 A schematic diagram of a flow chart of an IO-Link system synchronization method provided in an embodiment of the present application, the method is applied to a master device, reference Figure 1 As shown, the method includes:

[0052] S101: Determine whether the slave device supports synchronization;

[0053] A complete IO-Link synchronization system usually includes a control-level device, one or more master devices, and multiple slave devices. The master device is responsible for connecting to the upper-level system through a fieldbus that supports synchronization, such as EtherCAT. A master device integrates multiple ports for point-to-point communication with multiple slave devices, and is responsible for data exchange between the control-level device and the slave device. The slave device is responsible for executing the control commands of the control-level device and feeding back information.

[0054] The IO-Link system synchronization method provided in this embodiment is executed by the master device. After the master device establishes a field bus connection, it obtains the synchronization information of the field bus, including the synchronization clock, synchronization cycle, synchronization information, etc. The master device establishes a connection with the slave device. After the master device establishes a connection with the slave device, valid PD (Process data) data is not sent for the time being. The master device determines whether the slave device supports synchronization, that is, determines whether the slave device supports synchronization.

[0055] In some embodiments, determining whether the slave device supports synchronization includes:

[0056] Determine whether the slave device has on-demand data and whether the value of the on-demand data is an expected value;

[0057] If the slave has on-demand data and the value of the on-demand data is the expected value, then the slave supports synchronization.

[0058] After the master device establishes a connection with the slave device, it does not send valid PD data for the time being. The master device determines whether the slave device supports synchronization by reading the OD (On-request data) data of the slave device. If the slave device has on-demand data and the value of the on-demand data is the expected value, the slave device supports synchronization. Otherwise, the slave device does not support synchronization. The expected value is a value used to identify that the slave device supports synchronization. For example, the expected value is 100. If the slave device has on-demand data and the value of the on-demand data is 100, the slave device supports synchronization. Based on the OD data, it is possible to quickly and accurately determine whether the slave device supports synchronization.

[0059] The method provided in this embodiment for determining whether a slave device supports synchronization based on the value of the on-demand data can quickly and accurately determine whether a device supports synchronization.

[0060] S102: If the slave device supports synchronization, the synchronous clock of the bus is written into the slave device supporting synchronization, so that the slave device adjusts the local clock to the synchronous clock;

[0061] For the slave device supporting synchronization, the master device writes the synchronization clock of the field bus to the slave device supporting synchronization, and the slave device supporting synchronization adjusts the local clock to the synchronization clock to eliminate the clock offset.

[0062] In some embodiments, writing a synchronous clock of a bus to a slave device that supports synchronization includes:

[0063] In the first target cycle within the first preset number of IO-Link cycles after establishing a connection with a slave device supporting synchronization, the synchronous clock of the bus is written to the slave device supporting synchronization through on-demand data; wherein the process data within the first preset number of IO-Link cycles is invalid.

[0064] After the master device establishes a connection with the slave device, in the first target cycle within the first n IO-Link cycles, the master device cyclically uses OD data to write the synchronization clock to the slave device that supports synchronization to synchronize the clock of the slave device. n is a preset number of times. For example, after the master device establishes a connection with the slave device, in the odd IO-Link cycles within the first n (n>=10) IO-Link cycles, the master device can use OD data to write the synchronization clock to the slave device that supports synchronization to synchronize the clock of the slave device.

[0065] Writing the synchronization clock to the slave device supporting synchronization in the first target cycle within the first preset number of IO-Link cycles after establishing a connection with the slave device supporting synchronization can ensure that the synchronization clock can be written to each slave device supporting synchronization, ensure that each slave device supporting synchronization can perform clock synchronization, and that writing the synchronization clock to the slave device and obtaining the data receiving time of the slave device do not affect each other.

[0066] S103: Determine the message transmission delay of the slave device supporting synchronization, and compare the message transmission delays to determine the maximum message transmission delay;

[0067] S104: The maximum message transmission delay is written into the slave device supporting synchronization, so that the slave device executes the control command according to the input data when the timing time reaches the maximum message transmission delay.

[0068] For slave devices supporting synchronization, the master device determines the message transmission delay of each slave device supporting synchronization, determines the maximum message transmission delay from each message transmission delay, and then writes the maximum message transmission delay to each slave device supporting synchronization.

[0069] In some embodiments, determining a message transmission delay for a slave device supporting synchronization includes:

[0070] In a second target cycle within a preset number of IO-Link cycles after establishing a connection with a slave device supporting synchronization, obtaining a data receiving time of the slave device supporting synchronization; wherein the process data within the preset number of IO-Link cycles is invalid;

[0071] The message transmission delay of the slave device is determined according to the data receiving time of the slave device and the data sending time of the master device.

[0072] After the master device establishes a connection with the slave device, in the second target cycle within the first n IO-Link cycles, the master device cyclically reads the data receiving time of the slave device in the previous IO-Link cycle, and subtracts the data sending time of the master device from the data receiving time of the slave device to obtain the message transmission delay of the slave device. For example, after the master device establishes a connection with the slave device, in the even-numbered IO-Link cycles within the first n IO-Link cycles, the master device cyclically reads the data receiving time of the slave device in the previous IO-Link cycle, and subtracts the data sending time of the master device from the data receiving time of the slave device to obtain the message transmission delay of the slave device.

[0073] In the n+1th IO-Link cycle, the maximum message transmission delay is written to each slave device that supports synchronization through OD data. The master device sets the PD data to be valid and starts to transmit PD data normally.

[0074] Acquiring the data reception time of the slave device supporting synchronization in the second target period within the first preset number of IO-Link cycle periods after establishing a connection with the slave device supporting synchronization can ensure that the data reception time of the slave device supporting synchronization is obtained, ensure that accurate and reliable message transmission delay can be obtained, and obtaining the data reception time of the slave device and writing the synchronization clock to the slave device do not affect each other.

[0075] In some embodiments, it also includes:

[0076] After the preset number of IO-Link cycles are completed, the valid process data is transmitted, and when the on-demand data is idle, the synchronous clock of the bus is written to the slave device that supports synchronization through the on-demand data.

[0077] After the preset number of IO-Link cycles ends, in each subsequent IO-Link cycle, the master device obtains the synchronization information of the field bus before sending data, performs output data refresh operations, and writes the bus synchronization clock to the slave device that supports synchronization when the OD data is idle, which can eliminate the clock drift generated by each device during the continuous operation of the IO-Link system. After sending the message, the master device waits for the response from the slave device and refreshes the input data. The data interaction between the master device and the field bus adopts the original mechanism of the field bus.

[0078] During the effective PD data cyclic transmission process, after the synchronization cycle, the slave device receives the input data sent by the master device and refreshes the internal data cache of the slave device. At the same time, the slave device starts the timer. When the timer reaches the maximum message transmission delay, the slave device executes the control command according to the input data, refreshes the output data, and sends a message to respond to the master device.

[0079] In addition to the above embodiments of determining the message transmission delay of the slave device supporting synchronization, in some embodiments, determining the message transmission delay of the slave device supporting synchronization includes:

[0080] The message transmission delay of the slave device supporting synchronization is determined according to the OD data of the slave device supporting synchronization; the OD data includes the message transmission delay of the slave device. In the first n cycles after the connection is established, the PD data, i.e. the transmission data, is invalid. The slave device starts timing at the beginning of each IO-Link cycle, and stops timing after completely receiving the message sent by the master device. The time counted is the message transmission delay of the slave device. The slave device writes the message transmission delay to the OD data of the slave device and responds when the master device reads the OD data.

[0081] In some embodiments, there is a first time offset between the start time of the IO-Link cycle period corresponding to the slave device supporting synchronization and the start time of the bus cycle period; the bus cycle period is the message interaction period between the master device and the upper-level control device; the IO-Link cycle period is the message interaction period between the master device and the slave device.

[0082] The start time of the IO-Link cycle corresponding to the slave device supporting synchronization is the same as the bus cycle, and there is a first time offset between the start time of the IO-Link cycle corresponding to the slave device supporting synchronization and the start time of the bus cycle, thereby staggering the start time of the IO-Link cycle and the start time of the bus cycle, ensuring that the slave device is synchronized after the synchronization information is obtained from the field bus. The bus cycle refers to the message interaction cycle between the master device and the upper control device, i.e., the control level device. The IO-Link cycle refers to the message interaction cycle between the master device and the slave device.

[0083] In some embodiments, it also includes:

[0084] Determine the time margin according to the synchronization cycle of the bus;

[0085] The first time offset is determined according to the time margin and the conversion time; the conversion time is the time for the master device to parse the bus data and convert it into a message.

[0086] This embodiment aims to determine a first time offset between the start time of the IO-Link cycle period corresponding to the slave device supporting synchronization and the start time of the bus cycle period. The first time offset T offset1 =t exc +T idle ; T idle = T cyc / 20.

[0087] T cyc is the synchronization period.idle is the time margin, which is to prevent the main device from being overloaded. exc A safety margin is built in when the data is not fully parsed before the IO-Link cycle starts due to large jitter. exc The time it takes for the master to parse the fieldbus data and convert it into IO-Link messages. During the first n IO-Link cycles after the connection is established, the master calculates the appropriate value to ensure that the remaining time can complete a single IO-Link cycle request response action.

[0088] Determining the first time offset based on the time margin and the conversion time can ensure that data parsing is completed before the IO-Link cycle starts, thereby ensuring that message interaction is carried out normally after the IO-Link cycle starts.

[0089] For specific IO-Link systems, it is possible to monitor the exc Then the PID algorithm is introduced to control t exc Compensation suppression is performed to achieve better synchronization between bus data and IO-Link data.

[0090] In some embodiments, it also includes:

[0091] If the slave device does not support synchronization, determining a second time offset corresponding to the slave device that does not support synchronization; the second time offset is greater than the first time offset corresponding to the slave device that supports synchronization;

[0092] The start time of the bus synchronization cycle is offset by a second time offset to perform message interaction with a slave device that does not support synchronization.

[0093] For slave devices that do not support synchronization, the master device determines a second time offset corresponding to the slave device that does not support synchronization, and the second time offset is greater than the first time offset corresponding to the slave device that supports synchronization. This ensures that the slave device can maintain a certain degree of synchronization accuracy with other slave devices that support synchronization even if it does not support synchronization.

[0094] In some embodiments, determining the second time offset corresponding to the slave device that does not support synchronization includes:

[0095] Determining an average value of the message request response time of the slave device that does not support synchronization when reading and writing page parameters of the slave device that does not support synchronization within a preset number of IO-Link cycle periods, based on the message request response time of the slave device that does not support synchronization;

[0096] Determine the time offset increment of the slave device that does not support synchronization based on the average value;

[0097] Determine the time margin according to the synchronization cycle of the bus;

[0098] The second time offset is determined according to the time margin, the conversion time and the time offset increment; the conversion time is the time for the master device to parse the bus data and convert it into a message.

[0099] The second time offset T offset2 =t exc +T idle +(T tx_rx -T 10bit ) / 2);T idle = T cyc / 20.

[0100] T cyc is the synchronization period, T idle is the time margin, t exc The time it takes for the master device to parse the fieldbus data and convert it into IO-Link messages. tx_rx T is the average message request response time of the slave device that does not support synchronization; 10bit It is the maximum interval for a standard IO-Link slave device to respond to a master device request, and the time it takes for 10-bit data transmission at the master-slave communication rate. (T tx_rx -T 10bit ) / 2 is the time offset increment.

[0101] A second time offset greater than the first time offset is determined according to the time margin, the time offset increment and the conversion time, so that the slave device can maintain synchronization performance with a certain accuracy with other slave devices that support synchronization without supporting synchronization.

[0102] For the master and slave devices of IO-Link Class A ports, the master device can configure the IQ pin as output, and the slave device can configure the IQ pin as input. After receiving the synchronization signal of the field bus and introducing the maximum transmission delay, the master device controls the IQ pin to output a pulse signal, and the slave device executes the control command after receiving the pulse signal to achieve hardware synchronization.

[0103] refer to Figure 2 As shown, in some embodiments, the workflow of the master device is as follows:

[0104] The master device establishes a fieldbus connection and obtains the synchronization information of the fieldbus. The master device determines whether the IO-Link connection is established. If not, the IO-Link connection is established, and after the IO-Link connection is established, the clock synchronization cycle and transmission delay calculation are performed, the maximum message transmission delay is sent, and the transmission data is set to be valid. If it is established, the output data is refreshed, the clock synchronization is performed, the message is sent and received, and the input data is refreshed.

[0105] refer to Figure 3As shown, in some embodiments, the workflow of a slave device supporting synchronization is as follows:

[0106] Establish an IO-Link connection from the device, synchronize the local clock, and receive the message. Determine whether the transmitted data is valid. If not, calculate the message transmission delay, perform clock offset compensation, obtain the maximum message transmission delay, set the transmission data valid, and send the message. If the transmission is valid, refresh the input data, wait for the transmission delay, and when the timing reaches the maximum transmission delay, execute the control command and refresh the output data.

[0107] In summary, in the IO-Link system synchronization method provided by the present application, the master device sends the synchronization clock to the slave device, and the slave device adjusts the local clock to the synchronization clock to achieve clock synchronization of each slave device. In addition, the master device sends the maximum message transmission delay to the slave device, and the slave device uniformly executes the control command when the timing reaches the maximum message transmission delay, thereby achieving synchronous action between slave devices. The application of this method can eliminate the clock offset and clock drift problems of slave devices in the IO-Link system, eliminate the clock deviation of the control device and the master and slave devices in the IO-Link system, and ensure synchronous action between slave devices.

[0108] The present application also provides an IO-Link system synchronization device, and the device described below can be referred to in correspondence with the method described above. Figure 4 , Figure 4 A schematic diagram of an IO-Link system synchronization device provided in an embodiment of the present application, combined with Figure 4 As shown, the device comprises:

[0109] A judging module 10 is used to judge whether the slave device supports synchronization;

[0110] A synchronous clock writing module 20 is used to write the synchronous clock of the bus into the slave device supporting synchronization if the slave device supports synchronization, so that the slave device adjusts the local clock to the synchronous clock;

[0111] The message transmission delay determination module 30 is used to determine the message transmission delay of the slave device supporting synchronization, and compare the message transmission delays to determine the maximum message transmission delay;

[0112] The message transmission delay writing module 40 is used to write the maximum message transmission delay into the slave device supporting synchronization, so that the slave device executes the control command according to the input data when the timing time reaches the maximum message transmission delay.

[0113] Based on the above embodiment, as a specific implementation mode, the synchronous clock writing module 20 is specifically used for:

[0114] In the first target cycle within the first preset number of IO-Link cycles after establishing a connection with a slave device supporting synchronization, the synchronous clock of the bus is written to the slave device supporting synchronization through on-demand data; wherein the process data within the first preset number of IO-Link cycles is invalid.

[0115] Based on the above embodiment, as a specific implementation manner, the message transmission delay determination module 30 includes:

[0116] A data receiving time acquisition unit is used to acquire the data receiving time of the slave device supporting synchronization in a second target cycle within a preset number of IO-Link cycles after a connection is established with the slave device supporting synchronization; wherein the process data in the preset number of IO-Link cycles is invalid;

[0117] The message transmission delay determination unit is used to determine the message transmission delay of the slave device according to the data receiving time of the slave device and the data sending time of the master device.

[0118] On the basis of the above embodiments, as a specific implementation method, there is a first time offset between the start time of the IO-Link cycle period corresponding to the slave device supporting synchronization and the start time of the bus cycle period; the bus cycle period is the message interaction period between the master device and the upper-level control device; the IO-Link cycle period is the message interaction period between the master device and the slave device.

[0119] Based on the above embodiment, as a specific implementation method, it also includes:

[0120] A time margin determination module, used for determining the time margin according to the synchronization cycle of the bus;

[0121] The first time offset determination module is used to determine the first time offset according to the time margin and the conversion time; the conversion time is the time for the master device to parse the bus data and convert it into a message.

[0122] Based on the above embodiment, as a specific implementation method, it also includes:

[0123] The effective process data transmission module is used to transmit effective process data after the IO-Link cycle period of the preset number of times ends, and when the on-demand data is idle, the synchronous clock of the bus is written to the slave device that supports synchronization through the on-demand data.

[0124] Based on the above embodiment, as a specific implementation, the judgment module 10 includes:

[0125] A judging unit, used for judging whether the slave device has on-demand data and whether the value of the on-demand data is an expected value;

[0126] The determining unit is configured to determine that if the slave device has on-demand data and the value of the on-demand data is an expected value, the slave device supports synchronization.

[0127] Based on the above embodiment, as a specific implementation method, it also includes:

[0128] A second time offset determination module, for determining a second time offset corresponding to the slave device that does not support synchronization if the slave device does not support synchronization; the second time offset is greater than the first time offset corresponding to the slave device that supports synchronization;

[0129] The message interaction module is used to perform message interaction with a slave device that does not support synchronization at a second time offset from the start time of the synchronization cycle of the bus.

[0130] Based on the above embodiment, as a specific implementation manner, the second time offset determination module includes:

[0131] an average value determining unit, for determining an average value of a message request response time of a slave device that does not support synchronization according to a message request response time of a slave device that does not support synchronization when reading and writing a page parameter of the slave device that does not support synchronization within a preset number of IO-Link cycle periods;

[0132] a time offset increment determination unit, configured to determine a time offset increment of a slave device that does not support synchronization according to the average value;

[0133] A time margin determination unit, used to determine the time margin according to the synchronization cycle of the bus;

[0134] The second time offset determination unit is used to determine the second time offset according to the time margin, the conversion time and the time offset increment; the conversion time is the time for the master device to parse the bus data and convert it into a message.

[0135] This application also provides an IO-Link system synchronization device, reference Figure 5 As shown, the device includes a memory 1 and a processor 2 .

[0136] Memory 1, used for storing computer programs;

[0137] Processor 2 is used to execute the computer program to implement the following steps:

[0138] Determine whether the slave device supports synchronization; if the slave device supports synchronization, write the synchronous clock of the bus to the slave device that supports synchronization, so that the slave device adjusts the local clock to the synchronous clock; determine the message transmission delay of the slave device that supports synchronization, and compare the message transmission delays to determine the maximum message transmission delay; write the maximum message transmission delay to the slave device that supports synchronization, so that the slave device executes the control command according to the input data when the timing time reaches the maximum message transmission delay.

[0139] For an introduction to the equipment provided in this application, please refer to the above method embodiments, and this application will not go into details here.

[0140] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

[0141] Determine whether the slave device supports synchronization; if the slave device supports synchronization, write the synchronous clock of the bus to the slave device that supports synchronization, so that the slave device adjusts the local clock to the synchronous clock; determine the message transmission delay of the slave device that supports synchronization, and compare the message transmission delays to determine the maximum message transmission delay; write the maximum message transmission delay to the slave device that supports synchronization, so that the slave device executes the control command according to the input data when the timing time reaches the maximum message transmission delay.

[0142] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0143] For an introduction to the computer-readable storage medium provided in this application, please refer to the above method embodiment, and this application will not go into details here.

[0144] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0145] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0146] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0147] The IO-Link system synchronization method, device, equipment and medium provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for synchronizing an IO-Link system, characterized in that: Applicable to main equipment, including: Determine whether the slave device supports synchronization; If the slave device supports synchronization, writing the synchronous clock of the bus into the slave device supporting synchronization, so that the slave device adjusts the local clock to the synchronous clock; Determining a message transmission delay of a slave device supporting synchronization, and comparing each of the message transmission delays to determine a maximum message transmission delay; The maximum message transmission delay is written into a slave device supporting synchronization, so that the slave device executes a control command according to input data when the timing time reaches the maximum message transmission delay.

2. The IO-Link system synchronization method according to claim 1, characterized in that: Writing the synchronous clock of the bus into the slave device supporting synchronization comprises: In a first target cycle within a preset number of IO-Link cycles after establishing a connection with a slave device supporting synchronization, writing the synchronous clock of the bus to the slave device supporting synchronization through on-demand data; wherein the process data in the preset number of IO-Link cycles is invalid; The method further comprises: After the previously preset number of IO-Link cycles are completed, valid process data is transmitted, and when the on-demand data is idle, the synchronous clock of the bus is written to the slave device supporting synchronization through the on-demand data.

3. The IO-Link system synchronization method according to claim 1, characterized in that: Determining the message transmission delay of the slave device supporting synchronization includes: In a second target cycle within a preset number of IO-Link cycles after establishing a connection with a slave device supporting synchronization, obtaining a data receiving time of the slave device supporting synchronization; wherein the process data within the preset number of IO-Link cycles is invalid; The message transmission delay of the slave device is determined according to the data receiving time of the slave device and the data sending time of the master device.

4. The IO-Link system synchronization method according to claim 2 or 3, characterized in that: There is a first time offset between the start time of the IO-Link cycle period corresponding to the slave device supporting synchronization and the start time of the bus cycle period; the bus cycle period is the message interaction period between the master device and the upper-level control device; the IO-Link cycle period is the message interaction period between the master device and the slave device.

5. The IO-Link system synchronization method according to claim 4, characterized in that: Also includes: Determining a time margin according to a synchronization cycle of the bus; Determine the first time offset according to the time margin and the conversion time; The conversion time is the time it takes for the master device to parse the bus data and convert it into a message.

6. The IO-Link system synchronization method according to claim 1, characterized in that: Also includes: If the slave device does not support synchronization, determining a second time offset corresponding to the slave device that does not support synchronization; The second time offset is greater than the first time offset corresponding to the slave device supporting synchronization; The start time of the synchronization cycle of the bus is offset by the second time offset to perform message interaction with a slave device that does not support synchronization.

7. The IO-Link system synchronization method according to claim 6, characterized in that: The determining of the second time offset corresponding to the slave device that does not support synchronization comprises: Determining an average value of the message request response time of the slave device that does not support synchronization when reading and writing page parameters of the slave device that does not support synchronization within a preset number of IO-Link cycle periods, based on the message request response time of the slave device that does not support synchronization; determining a time offset increment of a slave device that does not support synchronization based on the average value; Determining a time margin according to a synchronization cycle of the bus; The second time offset is determined according to the time margin, the conversion time and the time offset increment; the conversion time is the time for the master device to parse the bus data and convert it into a message.

8. An IO-Link system synchronization device, characterized in that: include: A judgment module, used to judge whether the slave device supports synchronization; A synchronous clock writing module, used for writing the synchronous clock of the bus into the slave device supporting synchronization if the slave device supports synchronization, so that the slave device adjusts the local clock to the synchronous clock; A message transmission delay determination module, used to determine the message transmission delay of the slave device supporting synchronization, and compare the message transmission delays to determine the maximum message transmission delay; The message transmission delay writing module is used to write the maximum message transmission delay into the slave device supporting synchronization, so that the slave device executes the control command according to the input data when the timing time reaches the maximum message transmission delay.

9. An IO-Link system synchronization device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the IO-Link system synchronization method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the IO-Link system synchronization method according to any one of claims 1 to 7 are implemented.

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