Multi-state asynchronous routing network architecture

Abstract

The invention discloses a polymorphic asynchronous routing network architecture. The polymorphic asynchronous routing network architecture comprises an input asynchronous bus, a fan-out layer, a middle layer, a fan-in layer, an output asynchronous bus and a configuration register, the fan-out layer is used for driving a one-in two-out asynchronous routing node in the layer to fan out an event data packet input into an asynchronous bus to the middle layer; the middle layer is used for driving a 2-in 2-out asynchronous routing node in the layer to transmit an event data packet from the fan-out layer to the fan-in layer; the fan-in layer is used for fan-in of event data packets of the middle layer to an output asynchronous bus by a 2-in 1-out asynchronous routing node in the driving layer; and the configuration register is used for respectively storing the pre-configuration routing schemes corresponding to the fan-out layer, the middle layer and the fan-in layer. According to the invention, when switching among unicast, multicast, broadcast and other modes, a circuit does not need to be reconstructed, so that a data transmission pipeline is not blocked; and the dynamic power consumption does not exist on the routing node without the data packet and the bus.

Description

Technical Field

[0001] The present application belongs to the field of hardware communication technology, and in particular, relates to a polymorphic asynchronous routing network architecture. Background Art

[0002] The bus is an important channel for data transmission between modules in a computer system, and its design directly affects the performance and reliability of the system. In traditional synchronous systems, the bus protocol is usually driven by a clock signal; in different application scenarios, the synchronous bus needs to handle the number of input sources, the number of output targets, and the source (target) routing positioning of different data transmission tasks, which are generally divided into the following three situations:

[0003] 1. Unicast: In unicast communication, data packets are sent from a source node to a specific destination node; this communication mode is the most common in the network and is suitable for point-to-point communication;

[0004] 2. Multicast: Multicast communication refers to sending data packets from a source node to multiple specific destination nodes; this method efficiently supports group communication and avoids repeatedly sending data to each receiving node;

[0005] 3. Broadcast: Broadcast communication sends data packets from a source node to all destination nodes in the network to ensure that each node can receive the information; broadcast plays an important role in applications such as ARP requests and DHCP services in local area networks.

[0006] In synchronous bus design, due to the reliance on clock edges for driving, these three methods often need to be implemented through different hardware protocols, which means a large redundant circuit cost; some studies have tried to use configuration registers to achieve the reconfigurability of bus functions, achieving functional reuse of a single circuit at the cost of redundant functions and additional configuration time. However, this solution is costly when switching functions, and has poor application effects in high-speed systems such as AI accelerators;

[0007] Asynchronous circuits, also known as self-timed circuits, have significant advantages such as reduced power consumption, event triggering, and improved electromagnetic compatibility because they do not rely on global clock signals for synchronization. These characteristics have made asynchronous circuits increasingly popular in high-performance computing, bandwidth-constrained devices, and noise-sensitive applications. Since the data flow of asynchronous circuits can itself be used to drive control flow, there is an opportunity to meet the challenge of low-cost communication solutions by designing asynchronous data packets with special information fields and customizing node circuits with identification and routing functions; however, the design of a unified hardware protocol for the three communication modes of unicast, multicast, and broadcast has not yet been fully realized. Summary of the invention

[0008] To address the deficiencies in the prior art, this application proposes a polymorphic asynchronous routing network architecture, which is described in detail as follows:

[0009] A polymorphic asynchronous routing network architecture, comprising:

[0010] Input asynchronous bus, fan-out layer, middle layer, fan-in layer, output asynchronous bus and configuration registers;

[0011] The fan-out layer includes a 1-input 2-output asynchronous routing node, which is used to drive the 1-input 2-output asynchronous routing node to fan out the event data packet on the input asynchronous bus to the middle layer;

[0012] The middle layer includes a 2-input 2-output asynchronous routing node, which is used to drive the 2-input 2-output asynchronous routing node to transfer the event data packet from the fan-out layer to the fan-in layer;

[0013] The fan-in layer includes a 2-input 1-output asynchronous routing node, which is used to drive the 2-input 1-output asynchronous routing node to fan in the event data packet of the middle layer to the output asynchronous bus;

[0014] The configuration register is used to store the pre-configured routing schemes corresponding to the fan-out layer, the middle layer, and the fan-in layer respectively.

[0015] Optionally, the format of the event data packet includes a data field and an information field, the data field is used to carry event content; the information field is marked with an information stamp to provide various types of asynchronous routing nodes with results of determining whether the event content implements a data stream structure.

[0016] Optionally, the information stamp includes:

[0017] A code stamp is used to write a code number to the target object of the event data packet transmission;

[0018] The address stamp is used to further encode the target object based on the coding number written into the target object;

[0019] Function reserved stamp, used to customize routing behavior.

[0020] Optionally, the written code numbers are the same or different.

[0021] Optionally, after receiving the event data packet input, the 1-input 2-output asynchronous routing node extracts the code number in the event data packet and compares it with the threshold code in the corresponding preconfigured routing scheme. If the code number in the event data packet is the same as the threshold code, the event data packet is transmitted to the straight branch of the 1-input 2-output asynchronous routing node; otherwise, it is transmitted to the side branch of the 1-input 2-output asynchronous routing node.

[0022] Optionally, the driving 2-input 1-output asynchronous routing node fans-in the event data packet of the middle layer to the output asynchronous bus, including: only the event data packet of one branch of the upper input branch or the lower input branch of the 2-input 1-output asynchronous routing node is processed normally, when the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other branch needs to wait for the processing of one branch to be completed before continuing processing.

[0023] Optionally, when the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other branch needs to wait for the processing of one branch to be completed before continuing to process, which is achieved by using click signal generation and chip selection logic circuit.

[0024] Optionally, the 2-input 2-output asynchronous routing node is a combination of a 1-input 2-output asynchronous routing node and a 2-input 1-output asynchronous routing node.

[0025] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0026] 1. When switching between unicast, multicast, broadcast and other modes, there is no need to reconstruct the circuit and thus freeze the data transmission pipeline;

[0027] 2. Data transmission on the polymorphic asynchronous routing network architecture is event-driven data transmission, and there is no dynamic power consumption on the routing nodes and buses without data packets;

[0028] 3. Data transmission on the polymorphic asynchronous routing network architecture is not sensitive to timing and has high robustness. It can adapt well to work scenarios with high versatility requirements, such as a large number of input objects and output targets of various types.

[0029] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures specifically pointed out in the description, claims and drawings.

[0030] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings.

[0031] Advantages of additional aspects of the present application will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a diagram of a polymorphic asynchronous routing network architecture shown in an embodiment of the present application;

[0034] Figure 2 A diagram showing the data packet format of a polymorphic asynchronous routing network shown in an embodiment of the present application;

[0035] Figure 3 This is a diagram of a polymorphic asynchronous routing network structure at a 4-layer link layer as shown in an embodiment of the present application;

[0036] Figure 4 This is an example diagram of routing behavior of a polymorphic asynchronous routing network of a 4-layer link layer in unicast mode as shown in an embodiment of the present application;

[0037] Figure 5 This is an example diagram of routing behavior of a polymorphic asynchronous routing network of a 4-layer link layer in broadcast and multicast modes as shown in an embodiment of the present application;

[0038] Figure 6 This is an example diagram of routing behavior of a polymorphic asynchronous routing network of a 4-layer link layer in a multi-transmitter multicast mode as shown in an embodiment of the present application;

[0039] Figure 7 This is an example diagram of routing behavior of a random object simplex transmission behavior combined with three working modes as shown in an embodiment of the present application;

[0040] Figure 8 This is a working principle diagram of three basic asynchronous routing nodes shown in the embodiments of the present application;

[0041] Fig. 9 This is a basic configuration structure diagram of three basic asynchronous routing nodes shown in the embodiments of the present application. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0043] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0044] In the description of the present application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0045] This application designs a low-cost, flexible and efficient hardware communication protocol by utilizing the characteristics of data flow driving control flow in the asynchronous circuit paradigm. By defining the routing data packet protocol and customizing several basic routing node circuits, a complex asynchronous polymorphic simplex routing NoC (Network On Chip) structure is finally constructed; this routing NoC can support three communication modes, unicast, multicast and broadcast, by simply setting the configuration register without redundant routing circuits, control structures, and additional routing delays. Due to its polymorphic and simplex characteristics, the number of input objects and the number of output objects are arbitrary. The polymorphic asynchronous routing network architecture of this application is also named as the random object emission asynchronous routing network. It can improve the bandwidth utilization of the bus while ensuring the asynchronous pipeline timing correctness and data integrity of the data, and can provide technical support for the extensive data transmission needs of complex circuit architectures.

[0046] The technical solution provided by this application is described in detail as follows:

[0047] A polymorphic asynchronous routing network architecture, such as Figure 1 As shown, including:

[0048] Input asynchronous bus, fan-out layer, middle layer, fan-in layer, output asynchronous bus and configuration registers;

[0049] The fan-out layer includes a 1-input 2-output asynchronous routing node, which is used to drive the 1-input 2-output asynchronous routing node to fan out the event data packet on the input asynchronous bus to the middle layer;

[0050] The middle layer includes a 2-input 2-output asynchronous routing node, which is used to drive the 2-input 2-output asynchronous routing node to transfer the event data packet from the fan-out layer to the fan-in layer;

[0051] The fan-in layer includes a 2-input 1-output asynchronous routing node, which is used to drive the 2-input 1-output asynchronous routing node to fan in the event data packet of the middle layer to the output asynchronous bus;

[0052] The configuration register is used to store the pre-configured routing schemes corresponding to the fan-out layer, the middle layer, and the fan-in layer respectively.

[0053] Specifically in this embodiment, a polymorphic asynchronous routing network architecture (referred to as polymorphic asynchronous NoC) with chaotic object simplex transmission characteristics is mainly composed of an input asynchronous bus, a fan-out layer, a bufferfly layer (equivalent to the middle layer of the polymorphic asynchronous routing network architecture in this application), a fan-in layer, an output asynchronous bus layer, and a configuration register. Among them, the fan-out layer, the bufferfly layer, and the fan-in layer undertake the main routing tasks, and are responsible for realizing the data transfer from any number and any position of the input asynchronous bus to any number and any position of the output asynchronous bus. The fan-out layer is mainly responsible for fanning out the data on the corresponding input asynchronous bus to 2, and its function is implemented by the basic asynchronous routing node 1to2 (equivalent to the 1-input and 2-output asynchronous routing node in this application); the fan-in layer is the opposite, fanning the data of the two branches to the same output asynchronous bus, and its function is implemented by the basic asynchronous routing node 2to1 (equivalent to the 2-input and 1-output asynchronous routing node in this application); the bufferfly layer is configured as a commonly used bufferfly NoC structure, and its function is implemented by the basic asynchronous routing node 2to2 (equivalent to the 2-input and 2-output asynchronous routing node in this application).

[0054] The main advantages of the polymorphic asynchronous NoC architecture in this embodiment are:

[0055] 1. Data flow is control flow: Data packets are transmitted in the routing network, and the routing information encoded in the data packets directly determines the routing behavior of the polymorphic asynchronous NoC. This feature is implemented by each asynchronous routing node, so there is no independent control module;

[0056] 2. Data transmission on polymorphic asynchronous NoC is event-driven data transmission, and there is no dynamic power consumption on routing nodes and buses without data packets;

[0057] 3. Polymorphic asynchronous NoC supports broadcast, multicast, and unicast modes simultaneously. NoC can switch between the three modes without changing the configuration information in the register.

[0058] In a feasible specific implementation scheme, the format of the event data packet includes a data field and an information field, wherein the data field is used to carry the event content; an information stamp is marked inside the information field to provide various types of asynchronous routing nodes with the result of determining whether the event content implements the data stream structure;

[0059] Specifically, the format of the data packet transmitted on the polymorphic asynchronous NoC in this embodiment is as follows: Figure 2 As shown in the figure, it can be mainly divided into the data domain and the information domain. The data domain is used to carry specific data bits, which is the content subject to be transmitted; various information stamps are marked inside the information domain, which are used to provide asynchronous routing nodes to determine the specific data flow structure. Figure 2 In the figure, x represents the bit width of info, which includes three types of information: ID, remain, and pixel coordinates, and n represents the bit width of the data part in the transmitted data packet.

[0060] In a feasible specific implementation scheme, the information stamp includes:

[0061] A code stamp is used to write a code number to the target object of the event data packet transmission;

[0062] The address stamp is used to further encode the target object based on the coding number written into the target object;

[0063] Function reserved stamp, used to customize routing behavior.

[0064] Specifically in this embodiment, the information stamps inside the information domain include: a write ID stamp (equivalent to the coding stamp in the application), an Address stamp (address stamp) and a Remain stamp (function reserved stamp), wherein the write ID stamp is the write ID number of the transmission target object of the data packet. Since the write IDs of the transmission targets can be the same, the polymorphic asynchronous NoC can easily implement random object transmission behavior; the Address stamp is more specific address information, which is used for further encoding based on the write ID; the Remain stamp is a reserved information domain, which is used to customize specific routing behaviors in combination with various applications.

[0065] In a feasible specific implementation scheme, after receiving the event data packet input, the 1-input 2-output asynchronous routing node extracts the code number in the event data packet and compares it with the threshold code in the corresponding preconfigured routing scheme. If the code number in the event data packet is the same as the threshold code, the event data packet is transmitted to the straight branch of the 1-input 2-output asynchronous routing node, otherwise it is transmitted to the side branch of the 1-input 2-output asynchronous routing node.

[0066] In a feasible specific implementation scheme, the driver of the 2-input 1-output asynchronous routing node fans-in the event data packet of the middle layer to the output asynchronous bus, including: only the event data packet of one branch of the upper input branch or the lower input branch of the 2-input 1-output asynchronous routing node is processed normally, when the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other branch needs to wait for the processing of one branch to be completed before continuing processing.

[0067] In a feasible specific implementation scheme, when the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other side needs to wait for the processing of one side to be completed before continuing to process, which is achieved by using click signal generation and chip selection logic circuit.

[0068] In a feasible specific implementation scheme, the 2-input 2-output type asynchronous routing node is composed of a combination of a 1-input 2-output type asynchronous routing node and a 2-input 1-output type asynchronous routing node.

[0069] In order to explain the neuron circuit of the present application in more detail, a specific example is given below. Taking n=4 as an example, the overall principle block diagram of the technical solution of the present application is as follows: Figure 3 As shown, it mainly includes: 4 input asynchronous buses, 4 output asynchronous buses, a configuration register group dedicated to each asynchronous routing layer, and 4 layers of asynchronous routing networks with Bufferfly-like structures. Among them, the first layer of asynchronous routing network consists of 4 1to2 asynchronous routing nodes. After receiving the event data packet from the input asynchronous bus, this type of node will determine the routing scheme to be one of the three types of full transmission, forwarding straight branch, and forwarding deviated branch according to the information in the configuration register and the specific information field in the event data packet; the second and third asynchronous routing layers are composed of 2 2to2 asynchronous routing nodes. After receiving the event, one of the input branches above or below the node can drive the node to transfer data to the next layer. The transfer method is the same as that of the 1to2 routing node; the fourth asynchronous routing layer is composed of 4 2to1 asynchronous routing nodes. The fan-in processing method of its asynchronous events is the same as that of the 2to2 type. This node integrates the input events of the two input branches to a corresponding output asynchronous bus.

[0070] The polymorphic asynchronous routing network can achieve delay-free data transmission mode switching, which is specifically manifested in the ability to quickly switch between unicast, multicast, and broadcast modes. This feature makes the polymorphic asynchronous routing network particularly suitable for applications with complex data transmission, such as AI neural network acceleration or mounted buses. The specific routing behavior of the polymorphic asynchronous routing network is very complex and difficult to describe by formulas or codes. Examples will be given below to illustrate.

[0071] The specific routing situation of polymorphic asynchronous NoC in unicast mode is as follows Figure 4As shown, four situations are specifically shown, corresponding to the routing behaviors when the input source is block 1 and the target is 4 rows respectively, where t1 represents the specific transmission position of the data packet at the first asynchronous time step. Figure 4 Block 1 represents the first asynchronous input bus. Due to its symmetry, in unicast mode, the specific block of the data source has no essential difference to the routing behavior of the polymorphic asynchronous NoC. When the asynchronous input bus (block) corresponds to the asynchronous output data block (row), it has the shortest routing path (3 hops). At this time, the polymorphic asynchronous NoC achieves the minimum data transmission delay, which only consumes 3 asynchronous time steps. Figure 4 (c) shows that when the time is not corresponding, 5 asynchronous time steps are required, as shown in Figure 4 (c) It is worth noting that data transmission is performed in a pipeline form, that is, Figure 4 The throughput of the four routing cases is the same, with only some differences in latency.

[0072] In broadcast and multicast modes, the specific routing of polymorphic asynchronous NoC is as follows: Figure 5 As shown, 8 cases are shown in the figure, corresponding to different routing cases when the input source is block 1 and the output object is different numbers of rows at different positions. This behavior depends on the data packet's written ID information stamp and the data interaction between the asynchronous routing nodes. None of the 8 cases depends on circuit reconstruction. Figure 5 (c) shows the routing when broadcasting to all 4 rows. At this time, except for row 1, the remaining rows require a delay of 5 asynchronous time steps to construct an asynchronous pipeline. The principle is the same as that of unicast mode. The behavior of polymorphic asynchronous NoC in broadcast mode can be regarded as an overlap of unicast mode. This feature relies on the event-driven nature of the asynchronous routing nodes and the bus between nodes. Polymorphic asynchronous routing nodes allow multicast objects to be switched without interrupting the pipeline. This feature relies on the duplication of the written ID information stamp.

[0073] In the case of multiple transmitting sources, the specific routing of the polymorphic asynchronous NoC is as follows: Figure 6 As shown, all enabled states of data sources are shown respectively ( Figure 6 (a)), partially enabled ( Figure 6 (b)) and the worst case when all data sources are enabled ( Figure 6 (c)) four cases; a, b, c, d represent data packets from different asynchronous input buses, and their subscripts represent different moments; for example, a1 represents the location of the data packet at time step 1 ( Figure 7 similar).

[0074] When all data sources are enabled, each block and row are multicasted one by one. At this time, the four asynchronous data streams do not pass through the same routing node, there is no arbitration behavior of asynchronous events, and the transmission delay is the shortest (3 asynchronous time steps). When the data source is partially enabled, only some links are enabled. Since there are no events in the remaining links and no 01 flip of digital signals, there is no dynamic power consumption. Figure 6 As shown in (c), the complete misalignment of the data source and the target row is one of the worst working conditions in the multicast mode. At this time, each block and row do not correspond to each other, and the asynchronous data streams compete with each other for key asynchronous routing nodes (2to2), which may increase the throughput of the data stream while increasing the delay.

[0075] By taking advantage of the characteristics of asynchronous circuit data flow, i.e. control flow, a non-redundantly supported polymorphic routing network is constructed without a controller. The random object simplex transmission behavior realized based on this network is as follows: Figure 7 As shown. Among them, Figure 7 (a) shows the extreme case where there are four input sources and only one output target. At this time, due to the limited bandwidth of the output asynchronous bus, the four data flows are regulated by the arbitration mechanism of the asynchronous routing node. This arbitration mechanism relies on the specific blocking behavior of the asynchronous routing node during the asynchronous handshake. Figure 7 (b) shows the multi-source multi-target situation. More specifically, the data from the four input blocks will be delivered to two target rows at the same time. At this point, it can be considered that the data of all blocks are multicast to rows 0 and 3, and the data streams of each block conform to the multicast behavior specifications. In this case, the data bandwidth overhead is doubled, but due to the event-driven nature of the asynchronous routing nodes and the structural characteristics of the multi-state asynchronous NoC architecture, the two aggregated output data streams do not increase latency at the expense of latency, and their throughput and latency are the same as the multi-source single-target situation. Figure 7 (c) shows the multi-source multi-target case, where the input sources are two and the number of output rows is three. Unlike the multi-source multi-target case, the data of block 1 is unicast to rows 0 and 3, while the data of block 2 is unicast to row 3, and the data streams of blocks 1 and 2 conform to the multicast behavior specifications. The circuit characteristics of the three transmission modes of unicast, multicast, and broadcast mixed with each other and switched without delay enable the polymorphic asynchronous NoC to perform data transmission with arbitrary number and position of input sources and arbitrary number and position of input targets, thus giving data transmission strong robustness, versatility, and flexibility.

[0076] like Figure 3 As shown in Figure 1, the polymorphic asynchronous NoC is mainly composed of three basic routing nodes: 1to2, 2to2, and 2to1. Its working principle is as follows: Figure 8 As shown. Among them, Figure 8(a) shows the working principle of the 1to2 routing node. After receiving external data input, it extracts the write ID (routing ID) information in the packet information field and compares it with the threshold ID (i.e., threshold code) in the corresponding register. If the routing ID information is the same as the threshold ID, the data is transmitted to the straight branch, otherwise it is transmitted to the side branch. Figure 8 (b) shows the working principle of the 2to1 asynchronous routing node. Its input has two branches, one above and one below. Under the action of the chip select signal, only one branch's data can be processed normally, and the other branch needs to wait for the processing to be completed. This mechanism is implemented using the handshake mechanism of the asynchronous click circuit. It uses the characteristic of stalling the next event handshake application when processing the current handshake signal. When there is no chip select signal, both branches will stall the handshake behavior of the previous node of their respective branches until the current handshake processing is completed. The working principle of the 2to2 asynchronous routing node is shown in Figure 1. Figure 8 As shown in (c), it can be regarded as a combination of a 1to2 asynchronous routing node and a 2to1 asynchronous routing node, that is, the data output of the 2to1 asynchronous routing node is equivalent to the external data input of the 1to2 asynchronous routing node.

[0077] The specific circuits of the three basic routing nodes that constitute the polymorphic asynchronous routing network are as follows: Fig. 9 As shown in Figure 2, they are the reconstruction and variants of the Fork and merge circuit components of click. The circuit structure of the 1to2 asynchronous routing node is shown in Figure 2. Fig. 9 As shown in (a), its key routing components are marked with gray boxes, including several nand and or gates. When the current handshake request signal InA_Req is valid, a MUX circuit with a comparator will compare Threshold (threshold ID) with Info (write ID), and then Figure 8 The same handshake signal transmission scheme as the discrimination scheme shown in (a) pulls up outB_Req or OutC_Req. The next-level asynchronous routing component will pull up the corresponding ACK signal after responding to the handshake request. This signal will drive the core circuit to generate a click signal and drive the core circuit to generate a handshake signal InA_Ack signal for handshaking with the previous-level asynchronous routing component. Fig. 9(b) shows the specific circuit of the 2to1 asynchronous routing node, which is composed of two sets of integrated click signal generation and chip select logic circuits. Among them, after the handshake signal of a branch is generated, it will drive the corresponding sel_a / sel_b signal to be generated, and this signal will drive the or gate to generate a click_out signal, which will transmit the handshake request signal OutC_Req to the next level routing component. When the next level responds to the handshake and generates the corresponding return handshake signal OutC_Ack, it will drive a click_in signal. This signal is also affected by the chip select signal sel_a / sel_b, and will generate a return handshake response signal on the corresponding branch. In this way, the 2to1 asynchronous routing node can be implemented as follows. Figure 8 (b) The working principle shown. Fig. 9 (c) shows the circuit of a 2to2 asynchronous routing node, which can be viewed as a combination of 1to2 and 2to1 asynchronous routing nodes.

[0078] The present application provides a polymorphic asynchronous routing network architecture, the design of which achieves the following beneficial technical effects:

[0079] 1. When switching between unicast, multicast, broadcast and other modes, there is no need to reconstruct the circuit and thus freeze the data transmission pipeline;

[0080] 2. Data transmission on polymorphic asynchronous NoC is event-driven data transmission, and there is no dynamic power consumption on routing nodes and buses without data packets;

[0081] 3. Data transmission on polymorphic asynchronous NoC is insensitive to timing and has high robustness. It can adapt well to work scenarios with high versatility requirements, such as large numbers of input objects and output targets of various types.

[0082] Although this specification is described according to implementation modes, not every implementation mode includes only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0083] In the description of the present application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, invention, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, invention, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, invention, article or device including the elements.

[0084] Therefore, the above description is only a preferred embodiment of the present application and is not intended to limit the scope of implementation of the present application; that is, all equivalent changes made according to the scope of the claims of the present application are within the protection scope of the claims of the present application.

[0085] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

[0086] The applicant of this application has made a detailed explanation and description of the implementation examples of this application in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of this application, and the detailed description is only to help readers better understand the spirit of this application, and it is not a limitation on the scope of protection of this application. On the contrary, any improvements or modifications based on the inventive spirit of this application should fall within the scope of protection of this application.

Claims

1. A polymorphic asynchronous routing network architecture, characterized in that: include: Input asynchronous bus, fan-out layer, middle layer, fan-in layer, output asynchronous bus and configuration registers; The fan-out layer includes a 1-input 2-output asynchronous routing node, which is used to drive the 1-input 2-output asynchronous routing node to fan out the event data packet on the input asynchronous bus to the middle layer; The middle layer includes a 2-input 2-output asynchronous routing node, which is used to drive the 2-input 2-output asynchronous routing node to transfer the event data packet from the fan-out layer to the fan-in layer; The fan-in layer includes a 2-input 1-output asynchronous routing node, which is used to drive the 2-input 1-output asynchronous routing node to fan in the event data packet of the middle layer to the output asynchronous bus; The configuration register is used to store the pre-configured routing schemes corresponding to the fan-out layer, the middle layer, and the fan-in layer respectively.

2. The polymorphic asynchronous routing network architecture according to claim 1, characterized in that: The format of the event data packet includes a data field and an information field. The data field is used to carry the event content. The information field is marked with an information stamp to provide various types of asynchronous routing nodes with the result of determining whether the event content implements the data stream structure.

3. The polymorphic asynchronous routing network architecture according to claim 2, characterized in that: The information stamp includes: A code stamp is used to write a code number to the target object of the event data packet transmission; The address stamp is used to further encode the target object based on the coding number written into the target object; Function reserved stamp, used to customize routing behavior.

4. The polymorphic asynchronous routing network architecture according to claim 3, characterized in that: The written code numbers are the same or different.

5. The polymorphic asynchronous routing network architecture according to claim 1, characterized in that: After receiving the event data packet input, the 1-input 2-output asynchronous routing node extracts the code number in the event data packet and compares it with the threshold code in the corresponding preconfigured routing scheme. If the code number in the event data packet is the same as the threshold code, the event data packet is transmitted to the straight branch of the 1-input 2-output asynchronous routing node, otherwise it is transmitted to the side branch of the 1-input 2-output asynchronous routing node.

6. The polymorphic asynchronous routing network architecture according to claim 1, characterized in that: The driving 2-input 1-output asynchronous routing node fans in the event data packet of the middle layer to the output asynchronous bus, including: only the event data packet of one branch of the upper input branch or the lower input branch of the 2-input 1-output asynchronous routing node is processed normally, when the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other branch needs to wait for the processing of one branch to be completed before continuing to process.

7. The polymorphic asynchronous routing network architecture according to claim 6, characterized in that: When the event data packet of one branch of the 2-input 1-output asynchronous routing node is processed, the other branch needs to wait for the processing of one branch to be completed before continuing to process, which is achieved by using click signal generation and chip selection logic circuit.

8. The polymorphic asynchronous routing network architecture according to claim 1, characterized in that: The 2-input 2-output asynchronous routing node is a combination of a 1-input 2-output asynchronous routing node and a 2-input 1-output asynchronous routing node.

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