Image data acquisition method, image acquisition device, storage medium and electronic equipment

Abstract

The embodiment of the invention discloses an image data acquisition method, a storage medium and an image acquisition device, and belongs to the field of image processing. Through a double-lens orthogonal synchronization mode, that is, when the first image sensor (sensor0) outputs half-frame data, the synchronization pulse signal is triggered to control the second image sensor (sensor1) to start to output frame data of the second image sensor (sensor1), so that accurate and synchronous acquisition of image data of the two sensors is realized. According to the synchronization mode, the problem of data coverage possibly occurring under the condition that each sensor only has a single buffer area is avoided, and data output of the two sensors is carried out alternately, so that the integrity and accuracy of data are ensured.

Description

Technical Field

[0001] The present application relates to the field of image processing, and in particular to an image data acquisition method, an image acquisition device, a storage medium and an electronic device. Background Art

[0002] With the advancement of technology and the improvement of user needs, more and more user devices are equipped with dual-lens systems, aiming to capture richer image information through dual perspectives, thereby enhancing the device's shooting function and user experience. In order to achieve this function, related technologies generally use real-time synchronization to collect image data output by two image sensors.

[0003] In real-time synchronous acquisition mode, two image sensors (such as sensor0 and sensor1) are configured to synchronously output their respective image data after receiving the frame synchronization pulse signal (FCYNC) from the microcontroller (MCU). This mechanism ensures the temporal consistency of image data acquisition, which facilitates subsequent image processing and analysis. Figure 1 As shown in the data output timing diagram, after receiving the frame synchronization pulse signal, sensor0 and sensor1 output image data 0 and image data 1 respectively, and the image acquisition device simultaneously acquires the data of the two image sensors and passes it to the image encoder for further processing.

[0004] However, the real-time synchronous acquisition method faces some challenges in practical applications. First, the requirements for the back-end image encoder are high. In the case of only one set of image processor / encoder, since the two image sensors output data at the same time, the system needs to buffer the frame data first, and then output it serially to the image encoder for processing. This requires the system to be equipped with four frame buffers, two for each image sensor, to ensure that data is not overwritten or lost during the data output process. In order to meet this requirement, a large-capacity memory is required, which increases the hardware cost and complexity of the device.

[0005] In addition, another solution is to use two sets of image processors / encoders to process the data of the two image sensors respectively. Although this method can avoid the problem of using large-capacity memory, it will obviously further increase hardware overhead and power consumption, which is not conducive to the lightweight and energy-saving design of the device. Summary of the invention

[0006] The embodiments of the present application provide an image data acquisition method, an image acquisition device, a storage medium, and an electronic device, which can solve the problem of large hardware overhead and high cost in image data acquisition in related technologies. The technical solution is as follows:

[0007] In a first aspect, an embodiment of the present application provides an image data acquisition method, which is applied to a first image sensor sensor0, a second image sensor sensor1, an image acquisition device, an image processing module, a first buffer module and a second buffer module; the image acquisition device includes: a first data writing module frame0wr, a second data writing module frame1wr, a first counter module hsync0cnt, a second counter module hsync1cnt, a frame data reading module framerd and a frame synchronization generation module fsync1gen;

[0008] Wherein, the collection method includes:

[0009] The first writing module receives image row data from the first image sensor, and writes the received data into the first buffer module;

[0010] The first counter module records the number of image row data output by the first image sensor; when the recorded number of rows is equal to N / 2, a first frame data reading signal S0-1 is sent to the frame data reading module, and a synchronization indication signal S0-2 is sent to the frame synchronization generating module; N represents N graphic row data contained in an image frame;

[0011] The frame data reading module reads the data of the first image sensor from the first buffer module in response to the first frame data reading signal S0-1, and sends the read data to the image processing module for processing;

[0012] The frame synchronization generating module generates a synchronization pulse signal FSYNC1 in response to the synchronization indication signal S0-2, and sets a delay time △t, and sends the synchronization pulse signal to the second image sensor after the delay time △T;

[0013] The second image sensor outputs image line data in response to the synchronization pulse signal;

[0014] The second data writing module receives the image row data from the second image sensor, and writes the received data into the second buffer module;

[0015] The second counter module records the number of rows of image row data output by the second image sensor, and when the recorded number of rows is equal to N / 2, sends a second frame reading signal S1-1 to the frame data reading module;

[0016] The frame data reading module reads the image data of the second image sensor from the second buffer module in response to the second frame data reading signal S1 - 1 , and sends the read data to the image processing module for processing.

[0017] In a second aspect, an embodiment of the present application provides a WiFi data transmission device, a first data writing module frame0wr, a second data writing module frame1wr, a first counter module hsync0cnt, a second counter module hsync1cnt, a frame data reading module framerd and a frame synchronization generation module fsync1gen;

[0018] Wherein, the first writing module is used to receive image row data from the first image sensor, and write the received data into the first buffer module;

[0019] The first counter module is used to record the number of image row data output by the first image sensor; when the recorded number of rows is equal to N / 2, a first frame data reading signal S0-1 is sent to the frame data reading module, and a synchronization indication signal S0-2 is sent to the frame synchronization generating module; N represents N graphic row data contained in an image frame;

[0020] The frame data reading module is used to read the data of the first image sensor from the first buffer module in response to the first frame data reading signal S0-1, and send the read data to the image processing module for processing;

[0021] The frame synchronization generating module is used to generate a synchronization pulse signal FSYNC1 in response to the synchronization indication signal S0-2, and to set a delay time △t, and to send the synchronization pulse signal to the second image sensor after the delay time △T;

[0022] The second image sensor is used to output image line data in response to the synchronization pulse signal;

[0023] The second data writing module is used to receive the image row data from the second image sensor, and write the received data into the second buffer module;

[0024] The second counter module is used to record the number of rows of image row data output by the second image sensor, and when the recorded number of rows is equal to N / 2, send a second frame reading signal S1-1 to the frame data reading module;

[0025] The frame data reading module is further configured to read the image data of the second image sensor from the second buffer module in response to the second frame data reading signal S1 - 1 , and send the read data to the image processing module for processing.

[0026] In a third aspect, an embodiment of the present application provides a computer storage medium, wherein the computer storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor and executing the above-mentioned method steps.

[0027] In a fourth aspect, an embodiment of the present application provides an image acquisition device, which may include: a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the above-mentioned method steps.

[0028] In a fifth aspect, an embodiment of the present application provides an electronic device, including the above-mentioned image acquisition device, a first image sensor sensor0, a second image sensor sensor1, an image processing module and a buffer module.

[0029] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0030] The frame synchronization generation module fsync1gen generates a synchronization pulse signal FSYNC1 in response to the synchronization indication signal S0-2, and sets a reasonable delay time △t, ensuring that the second image sensor sensor1 can accurately synchronize and start outputting its image data after the first image sensor sensor0 outputs half of the image frame data. This precise frame synchronization mechanism helps to avoid the misalignment or loss of image data, and ensures the integrity and consistency of image data. The first buffer module and the second buffer module are used to store image data from the first image sensor and the second image sensor, respectively. The number of rows of image row data is accurately recorded by the counter module (hsync0cnt and hsync1cnt), and the frame data reading operation is triggered when the preset threshold (N / 2) is reached, ensuring the effective use of the buffer module and the timely reading of data. This design helps to reduce the waste of data waiting time and storage space, and improves the efficiency of data processing. The frame data reading module framerd can read image data from the first buffer module and the second buffer module respectively according to the first frame data reading signal S0-1 and the second frame data reading signal S1-1, and send it to the image processing module for processing. This parallel processing method helps to improve the throughput and efficiency of data processing, so that image data can be analyzed and utilized more quickly. Compared with the traditional real-time synchronous acquisition method, this technical solution achieves flexible control and scheduling of the output data of the two image sensors by introducing a frame synchronization generation module and a counter module. This helps to reduce the dependence on large-capacity storage, reduces hardware costs, and makes the system structure more concise and efficient. This technical solution is not only applicable to two image sensors with the same performance, but can also adapt to image sensors of different performance or types by adjusting parameters and configurations. In addition, with the continuous development of technology, this technical solution can be further expanded and optimized to adapt to application scenarios with higher resolution, faster frame rate or more complex image processing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 It is a data output timing diagram of the synchronous acquisition mode in the related art;

[0033] Figure 2 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0034] Figure 3It is a flowchart of a method for collecting image data provided by an embodiment of the present application;

[0035] Figure 4 is an output timing diagram of the image sampling device before adjustment provided by an embodiment of the present application;

[0036] Figure 5 is an adjusted output timing diagram of the image sampling device provided by the present application;

[0037] Figure 6 This is another structural schematic diagram of an image acquisition device provided by the present application. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0039] See also Figure 2 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, includes: a first image sensor sensor0, a second image sensor sensor1, an image acquisition device DUAL_ORG_CTL, an image processing module, and an external memory, wherein a first buffer module and a second buffer module ( Figure 2 The image acquisition device comprises: a first data writing module frame0wr, a second data writing module frame1wr, a first counter module hsync0cnt, a second counter module hsync1cnt, a frame data reading module framerd and a frame synchronization generating module fsync1gen.

[0040] The first image sensor and the second image sensor are respectively connected to an image acquisition device, and the image acquisition device is respectively connected to an external memory and an image processing module ( Figure 1 connected to the image processor or encoder in the image processing unit.

[0041] The following will be combined with the attached Figure 3 , the image data acquisition method provided in the embodiment of the present application is described in detail. Among them, the image data acquisition method in the embodiment of the present application can be Figure 1 Sites in .

[0042] See also Figure 3 , is a flow chart of a method for collecting image data provided in an embodiment of the present application. The method of the present application may include the following steps:

[0043] S301 . A first writing module receives image row data from a first image sensor, and writes the received data into a first buffer module.

[0044] Among them, the first data writing module (frame0wr) is responsible for receiving continuous image line data from the first image sensor (sensor0). These data are usually read from the image sensor in a row-by-row scanning manner, and each row of data contains the pixel information of the image on that row. In order to ensure the continuity and integrity of the data, the first data writing module will write each row of image data received into the first buffer module in real time. This first buffer module can be a temporary storage area, such as SRAM or FIFO queue, for temporarily storing data read from the image sensor for subsequent processing.

[0045] S302, the first counter module records the number of rows of image row data output by the first image sensor; when the recorded number of rows is equal to N / 2, a first frame data reading signal S0-1 is sent to the frame data reading module, and a synchronization indication signal S0-2 is sent to the frame synchronization generating module.

[0046] The first counter module (hsync0cnt) is responsible for recording the number of rows of image row data output from the first image sensor. N represents the total number of image row data contained in a complete image frame. When the number of rows recorded by the counter reaches N / 2, it means that the first image sensor has output data of half an image frame. At this time, the first counter module will send a first frame data reading signal S0-1 to the frame data reading module (framerd), indicating that it can read the data of the first image sensor from the buffer module. At the same time, the first counter module will also send a synchronization indication signal S0-2 to the frame synchronization generation module (fsync1gen), notifying it that it can start preparing to generate a synchronization pulse signal.

[0047] S303 , the frame data reading module responds to the first frame data reading signal S0 - 1 , reads the data of the first image sensor from the first buffer module, and sends the read data to the image processing module for processing.

[0048] After receiving the first frame data reading signal S0-1, the frame data reading module reads the data of the first image sensor from the first buffer module. The data may be data of one or more image rows, depending on the processing capability and requirements of the image processing module. The read data is then sent to the image processing module for processing such as denoising, enhancement, compression, etc.

[0049] S304 , the frame synchronization generating module generates a synchronization pulse signal FSYNC1 in response to the synchronization indication signal S0 - 2 , and sets a delay time △t, and sends the synchronization pulse signal to the second image sensor after the delay time △t.

[0050] Among them, after receiving the synchronization indication signal S0-2, the frame synchronization generation module will generate a synchronization pulse signal FSYNC1. This synchronization pulse signal is used to trigger the second image sensor to start outputting image data. In order to ensure that the data of the two image sensors can be processed synchronously, the frame synchronization generation module will also set a delay time △t. This delay time is usually determined according to the characteristics of the two image sensors and the processing speed of the image processing module. After the delay time △t, the frame synchronization generation module will send the synchronization pulse signal FSYNC1 to the second image sensor.

[0051] Furthermore, the delay time △t is the duration of DLY_LINE image line data;

[0052] The delay time △T is set, including:

[0053] When the first counter module detects that the number of recorded rows is equal to N, it sends a row recording signal S0-3 to the second counter module;

[0054] The second counter module obtains the number of rows N1 currently recorded in response to the row record signal S0-3, and sends the number of rows N1 recorded to the frame synchronization generation module;

[0055] The frame synchronization module compares the relationship between N1 and a preset maximum threshold MAX_LINE and a preset minimum threshold MIN_LINE;

[0056] If N1>MAX_LINE, the frame synchronization module adds 1 to the current DLY_LINE;

[0057] If N1<MIN_LINE, the frame synchronization module will reduce the current DLY_LINE by 1;

[0058] If MIN_LINE≤N1≤MAX_LINE, the frame synchronization module keeps the current DLY_LINE unchanged.

[0059] The delay time △t is set to the duration of DLY_LINE image line data. This DLY_LINE value is not fixed, but can be dynamically adjusted according to the synchronization of the two image sensors. The following is the detailed process of setting the delay time △t:

[0060] 1. The first counter module sends a line recording signal.

[0061] When the first counter module (hsync0cnt) detects that the number of recorded lines is equal to N, that is, the first image sensor has output a complete image frame of data, it will send a line recording signal S0-3 to the second counter module (hsync1cnt). This signal is used to notify the second counter module that the first image sensor has completed the data output of the current frame.

[0062] 2. The second counter module obtains and records the number of rows.

[0063] After receiving the line recording signal S0-3, the second counter module will obtain the number of lines currently recorded N1. This N1 value represents the number of lines of image line data that the second image sensor has output after receiving the synchronization pulse signal FSYNC1 and starting to output data until the first counter module sends the line recording signal S0-3.

[0064] 3. The second counter module sends the row number to the frame synchronization generation module.

[0065] After obtaining the number of lines N1, the second counter module will send it to the frame synchronization generation module (fsync1gen). The frame synchronization generation module will use this N1 value to adjust the value of DLY_LINE to optimize the synchronization performance of the two image sensors.

[0066] 4. The frame synchronization module compares the number of rows N1 with a preset threshold.

[0067] After receiving the line number N1, the frame synchronization generation module compares it with the preset maximum threshold MAX_LINE and the preset minimum threshold MIN_LINE. These two thresholds are used to determine the adjustment range and direction of DLY_LINE.

[0068] If N1>MAX_LINE: This means that the second image sensor outputs too many lines after receiving the synchronization pulse signal, that is, the data output of the second image sensor is too much ahead of the first image sensor. In order to mitigate this advance, the frame synchronization module will add 1 to the current DLY_LINE value, thereby increasing the delay time △t.

[0069] If N1 < MIN_LINE: This means that the second image sensor outputs too few lines after receiving the synchronization pulse signal, that is, the data output of the second image sensor lags too much relative to the first image sensor. In order to accelerate this lag, the frame synchronization module will reduce the current DLY_LINE value by 1, thereby reducing the delay time △t.

[0070] If MIN_LINE≤N1≤MAX_LINE: This indicates that the synchronization error between the data output of the second image sensor and the first image sensor is within an acceptable range. At this time, the frame synchronization module will keep the current DLY_LINE value unchanged, that is, the delay time △t will not be adjusted.

[0071] Through the above process, the frame synchronization generation module can dynamically adjust the value of DLY_LINE according to the synchronization status of the two image sensors, thereby optimizing the delay time △t and ensuring that the data of the two image sensors can be processed synchronously more accurately.

[0072] Furthermore, the frame synchronization generation module is not only responsible for generating the synchronization pulse signal FSYNC1 and setting the delay time △t, but also optimizes and adjusts the synchronization performance of the two image sensors through the internally set delay register, target register and deviation register. The following are the functions of these registers and their detailed relationship with the threshold setting:

[0073] 1. Delay register.

[0074] The delay register is used to store the DLY_LINE value, which indicates the duration of the delay time △t for the number of image lines of data. The DLY_LINE value can be dynamically adjusted according to the synchronization of the two image sensors to ensure the best synchronization performance.

[0075] 2. Destination register.

[0076] The target register is used to store the expected number of lines EXP_LINE, which is a preset value indicating the number of lines of image line data that the second image sensor should output after receiving the synchronization pulse signal FSYNC1 under ideal conditions. The EXP_LINE value is usually determined based on the characteristics of the two image sensors and the processing speed of the image processing module.

[0077] 3. Deviation register.

[0078] The deviation register is used to store the deviation line number DEV_LINE, which is an allowable line number deviation range used to determine the maximum threshold MAX_LINE and the minimum threshold MIN_LINE. The DEV_LINE value can be set according to the actual application requirements and the accuracy requirements of image processing.

[0079] 4.Threshold setting.

[0080] The maximum threshold MAX_LINE and the minimum threshold MIN_LINE are calculated based on the target number of rows EXP_LINE and the deviation number of rows DEV_LINE. Specifically:

[0081] Maximum threshold MAX_LINE: equal to the target number of lines EXP_LINE plus the deviation number of lines DEV_LINE, that is, MAX_LINE = EXP_LINE + DEV_LINE. This value represents the upper limit of the number of lines output by the second image sensor after receiving the synchronization pulse signal. If the actual number of lines output exceeds this value, it indicates that the data output of the second image sensor is too much ahead of the first image sensor, and the delay time △t needs to be increased.

[0082] Minimum threshold MIN_LINE: equal to the target number of lines EXP_LINE minus the deviation number of lines DEV_LINE, that is, MIN_LINE = EXP_LINE-DEV_LINE. This value represents the lower limit of the number of lines output by the second image sensor after receiving the synchronization pulse signal. If the actual number of lines output is lower than this value, it indicates that the data output of the second image sensor lags too much relative to the first image sensor, and the delay time △t needs to be reduced.

[0083] Through the above settings, the frame synchronization generation module can more accurately control the synchronization performance of the two image sensors to ensure that they can output synchronized image data. In practical applications, the values ​​of EXP_LINE and DEV_LINE can be adjusted according to the specific image sensor characteristics and image processing requirements to achieve the best synchronization effect.

[0084] S305 . The second image sensor outputs image line data in response to the synchronization pulse signal.

[0085] After receiving the synchronization pulse signal FSYNC1, the second image sensor (sensor1) starts to output image row data. These data are also read from the image sensor in a row-by-row scanning manner, and each row of data contains pixel information of the image on that row.

[0086] S306: The second data writing module receives the image row data from the second image sensor, and writes the received data into the second buffer module.

[0087] The second data writing module (frame1wr) is responsible for receiving continuous image line data from the second image sensor and writing the data into the second buffer module. Similar to the first data writing module, the second buffer module is also used to temporarily store the data read from the second image sensor for subsequent processing.

[0088] S307 , the second counter module records the number of rows of image row data output by the second image sensor, and when the recorded number of rows is equal to N / 2, sends a second frame reading signal S1 - 1 to the frame data reading module.

[0089] The second counter module (hsync1cnt) is responsible for recording the number of rows of image row data output from the second image sensor. When the number of rows recorded by the counter reaches N / 2, it means that the second image sensor has also output half of the image frame data. At this time, the second counter module will send a second frame data reading signal S1-1 to the frame data reading module, indicating that it can read the data of the second image sensor from the second buffer module.

[0090] S308 , the frame data reading module reads the image data of the second image sensor from the second buffer module in response to the second frame data reading signal S1 - 1 , and sends the read data to the image processing module for processing.

[0091] After receiving the second frame data reading signal S1-1, the frame data reading module will read the data of the second image sensor from the second buffer module. These data are also sent to the image processing module (or image processing module) for processing. In this way, the data of the two image sensors are synchronously collected, stored and processed.

[0092] For example, assume that there is an image sensor with a resolution of 1920x1080 (i.e., N=1080), and each image frame contains 1080 lines of image data. In step S302, when the first counter module records the 540th line (N / 2=1080 / 2=540), it sends a first frame data reading signal S0-1 to the frame data reading module and sends a synchronization indication signal S0-2 to the frame synchronization generation module. Then, in step S304, the frame synchronization generation module generates a synchronization pulse signal FSYNC1 and sets an appropriate delay time △t (e.g., 10 milliseconds) to ensure that the second image sensor can synchronously start outputting image data after receiving the synchronization pulse signal. In step S305, the second image sensor starts to output image data, which is written into the buffer module by the second data writing module in step S306. When the second counter module records the 540th line (in step S307), it sends a second frame data reading signal S1-1 to the frame data reading module. Finally, in step S308, the frame data reading module reads the data of the second image sensor from the buffer module and sends it to the image processing module for processing. In this way, the data of the two image sensors are synchronously collected and processed.

[0093] See also Figure 4As shown, it is an output timing diagram of the image sampling device provided by the embodiment of the present application before adjustment. When two identical image sensors sensor0 and sensor1 are used and the configuration parameters are the same, the frame rate and the line output time are equal, and one of them is configured as a synchronous mode triggered by an external FSYNC pin. t1 is the time when the image sampling device outputs frame data 0, which is equal to the time when sensor0 outputs the number of lines N / 2. t3 is the time when sensor1 outputs frame data after receiving the FSYNC1 pulse. t2 is the frame interval time when the image sampling device outputs frame data 0 and frame data 1, which is theoretically consistent with t3 because the line output time of sensor0 / 1 is consistent. In actual application, the interval of t2 should not be too short or too long. When t2 is small, it will affect the normal operation of the back-end image processor or encoder. For example, frame data 1 comes just after receiving frame data 0, there is a delay in processing and the encoding has not been completed; when t2 is long, it will cause the interval between frame data 1 and frame data 0 to be insufficient, resulting in problems such as t2 being small.

[0094] See also Figure 5 As shown, it is an adjusted output timing diagram of the image sampling device provided by the embodiment of the present application. When the frame synchronization generation module receives the synchronization indication signal S0-2 sent by the first counter module, it outputs the synchronization pulse signal FSYNC1 after a certain line delay t4, so that the second image sensor sensor1 can output the frame data later. Under a reasonable adjustment mechanism, the time t2 can be made more reasonable. The frame synchronization generation module integrates a delay register, a target register and a deviation register to dynamically adjust the size of the delay time △t.

[0095] In summary, the beneficial effects of implementing the embodiments of the present application include: when the first image sensor (sensor0) normally outputs half-frame data, it triggers the synchronization pulse signal FSYNC1, which accurately controls the second image sensor (sensor1) to start outputting its frame data. This design ensures that the output data of sensor0 and sensor1 remain synchronized in time, providing a reliable data basis for subsequent image processing.

[0096] In traditional image acquisition methods, each image sensor usually requires one or two independent image frame buffers to store its output data. However, this approach may cause data coverage issues when resources are limited.

[0097] This technical solution precisely controls the output timing of the two sensors so that sensor1 starts to output its data while sensor0 outputs half a frame of data, thereby avoiding the data overwriting problem that may occur in a single buffer. As a result, the system can use only two image frame buffers to alternately store data from the two sensors, significantly reducing memory requirements.

[0098] Since the technical solution does not need to equip two image sensors with two sets of image processing modules respectively, it can save hardware resources and reduce system costs. At the same time, since the frame rate is not reduced, the system can still maintain efficient data processing capabilities.

[0099] Precise synchronization control ensures that the image data from the two sensors can be consistent in time, which is crucial for subsequent image processing (such as image stitching, stereo matching, etc.). Precise synchronization also helps to improve the real-time and accuracy of image processing, thereby improving the quality and effect of the final image.

[0100] The present application also provides a computer storage medium, which can store multiple instructions, and the instructions are suitable for being loaded and executed by a processor as described above. Figure 3 The method steps of the embodiment shown in the figure can be found in the specific implementation process. Figure 3 The specific description of the illustrated embodiment will not be repeated here.

[0101] The present application also provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the image data acquisition method described in the above embodiments.

[0102] See also Figure 6 , is a schematic diagram of the structure of an image acquisition device provided in an embodiment of the present application. Figure 6 As shown, the image acquisition device 600 may include: at least one processor 601 , at least one input interface 604 , an output interface 603 , a memory 605 , and at least one communication bus 602 .

[0103] The communication bus 602 is used to realize the connection and communication between these components.

[0104] The output interface 603 may include a display screen (Display) and a camera (Camera), and the optional output interface 603 may also include a standard wired interface and a wireless interface.

[0105] The input interface 604 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0106] The processor 601 may include one or more processing cores. The processor 601 uses various interfaces and lines to connect various parts of the entire terminal 600, and executes various functions of the terminal 600 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 605, and calling data stored in the memory 605.

[0107] Among them, the memory 605 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 605 includes a non-transitory computer-readable storage medium. The memory 605 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 605 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned method embodiments, etc.; the data storage area may store data involved in the above-mentioned method embodiments, etc. The memory 605 may optionally be at least one storage device located away from the aforementioned processor 601. As Figure 6 As shown, the memory 605 as a computer storage medium may include an operating system, a network communication module, a user interface module, and an application program.

[0108] exist Figure 6 In the image acquisition device 600 shown in FIG. 1 , the processor 601 can be used to call the application program stored in the memory 605 and specifically execute the following steps: Figure 4 The specific process can be referred to Figure 4 As shown, no further description is given here.

[0109] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0110] What is disclosed above is only a preferred embodiment of the present application, and it certainly cannot be used to limit the scope of rights of the present application. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present application are still within the scope of the invention.

Claims

1. A method for collecting image data, characterized in that: Applicable to a first image sensor sensor0, a second image sensor sensor1, an image acquisition device, an image processing module, a first buffer module, and a second buffer module; the image acquisition device comprises: a first data writing module frame0wr, a second data writing module frame1wr, a first counter module hsync0cnt, a second counter module hsync1cnt, a frame data reading module framerd, and a frame synchronization generating module fsync1gen; Wherein, the collection method includes: The first writing module receives image row data from the first image sensor, and writes the received data into the first buffer module; The first counter module records the number of image row data output by the first image sensor; when the recorded number of rows is equal to N / 2, a first frame data reading signal S0-1 is sent to the frame data reading module, and a synchronization indication signal S0-2 is sent to the frame synchronization generating module; N represents N graphic row data contained in an image frame; The frame data reading module reads the data of the first image sensor from the first buffer module in response to the first frame data reading signal S0-1, and sends the read data to the image processing module for processing; The frame synchronization generating module generates a synchronization pulse signal FSYNC1 in response to the synchronization indication signal S0-2, and sets a delay time △t, and sends the synchronization pulse signal to the second image sensor after the delay time △T; The second image sensor outputs image line data in response to the synchronization pulse signal; The second data writing module receives the image row data from the second image sensor, and writes the received data into the second buffer module; The second counter module records the number of rows of image row data output by the second image sensor, and when the recorded number of rows is equal to N / 2, sends a second frame reading signal S1-1 to the frame data reading module; The frame data reading module reads the image data of the second image sensor from the second buffer module in response to the second frame data reading signal S1 - 1 , and sends the read data to the image processing module for processing.

2. The method according to claim 1, characterized in that The delay time △t is the duration of DLY_LINE image line data; Wherein, setting the delay time ΔT comprises: When the first counter module detects that the number of recorded rows is equal to N, it sends a row recording signal S0-3 to the second counter module; The second counter module obtains the number of rows N1 currently recorded in response to the row record signal S0-3, and sends the number of rows N1 recorded to the frame synchronization generation module; The frame synchronization module compares the relationship between N1 and a preset maximum threshold MAX_LINE and a preset minimum threshold MIN_LINE; If N1>MAX_LINE, the frame synchronization module increases the current DLY_LINE by 1; If N1<MIN_LINE, the frame synchronization module reduces the current DLY_LINE by 1; If MIN_LINE≤N1≤MAX_LINE, the frame synchronization module keeps the current DLY_LINE unchanged.

3. The method according to claim 2, characterized in that The frame synchronization generation module is provided with: a delay register, a target register and a deviation register, the delay register is used to store DLY_LINE, the target register is used to store the expected line number EXP_LINE, and the deviation register is used to store the deviation line number DEV_LINE; The maximum threshold MAX_LINE=EXP_LINE+DEV_LINE, and the minimum threshold MIN_LINE=EXP_LINE-DEV_LINE.

4. The method according to claim 1, 2 or 3, characterized in that: The data buffer module is SRAM.

5. An image acquisition device, characterized in that: include: A first data writing module frame0wr, a second data writing module frame1wr, a first counter module hsync0cnt, a second counter module hsync1cnt, a frame data reading module framerd and a frame synchronization generating module fsync1gen; Wherein, the first writing module is used to receive image row data from the first image sensor, and write the received data into the first buffer module; The first counter module is used to record the number of image row data output by the first image sensor; when the recorded number of rows is equal to N / 2, a first frame data reading signal S0-1 is sent to the frame data reading module, and a synchronization indication signal S0-2 is sent to the frame synchronization generating module; N represents N graphic row data contained in an image frame; The frame data reading module is used to read the data of the first image sensor from the first buffer module in response to the first frame data reading signal S0-1, and send the read data to the image processing module for processing; The frame synchronization generating module is used to generate a synchronization pulse signal FSYNC1 in response to the synchronization indication signal S0-2, and to set a delay time △t, and to send the synchronization pulse signal to the second image sensor after the delay time △T; The second image sensor is used to output image line data in response to the synchronization pulse signal; The second data writing module is used to receive the image row data from the second image sensor, and write the received data into the second buffer module; The second counter module is used to record the number of rows of image row data output by the second image sensor, and when the recorded number of rows is equal to N / 2, send a second frame reading signal S1-1 to the frame data reading module; The frame data reading module is further configured to read the image data of the second image sensor from the second buffer module in response to the second frame data reading signal S1 - 1 , and send the read data to the image processing module for processing.

6. A computer storage medium, characterized in that: The computer storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the method steps according to any one of claims 1 to 6.

7. An image sampling device, characterized in that: include: A processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the method steps as claimed in any one of claims 1 to 4.

8. An electronic device, characterized in that: It comprises the image sampling device as claimed in claim 5 or 7, a first image sensor sensor0, a second image sensor sensor1, an image processing module, a first buffer module, and a second buffer module.

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