Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package comprises a first semiconductor chip and a second semiconductor chip which are directly combined together, the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, a first connection pad and a first test pad on the first wiring structure, a first passivation film, a first interlayer insulating film, a connection pad opening, and a test pad opening. The first semiconductor chip comprises a first semiconductor substrate, a first front-side bonding pad and a first rear-side bonding pad; a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and a first rear-side bonding pad bonded to the first front-side bonding pad on a fourth surface of the second semiconductor substrate, without any gap between the first semiconductor chip and the second semiconductor chip, and the first test pad is not electrically connected to the second semiconductor chip.

Description

[0001] This application is a divisional application of the invention patent application with the application date of July 25, 2022, application number 202210876662.X, and invention name “Semiconductor Package”. Technical Field

[0002] The present disclosure relates to a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, to a semiconductor package including semiconductor chips stacked in a die-to-wafer (D2W) manner and a method of manufacturing the semiconductor package. Background Art

[0003] With the rapid development of the electronics industry and the diversification of user needs, electronic devices have gradually become smaller, lighter and more functional. Semiconductor packages for such electronic devices are required to have not only compact size and light weight but also multifunctionality. For example, two or more types of semiconductor chips can be incorporated into a single semiconductor package, so that the size of the semiconductor package can be greatly reduced, and both the storage capacity and the function of the semiconductor package can also be improved.

[0004] In order to increase the storage capacity of the semiconductor package, the semiconductor chips can be stacked in a chip-on-wafer (CoW) method or a die-to-wafer (D2W) method. The CoW method may refer to a method in which a semiconductor chip is stacked on a wafer (or another semiconductor chip) via a connecting member (e.g., a bump or solder). The D2W method may refer to a method in which a semiconductor chip is stacked on a wafer (or another semiconductor chip) by pad (also referred to as "pad") to pad bonding (pad-to-pad bonding) or bonding using an anisotropic conductive film (ACF). Summary of the invention

[0005] According to an embodiment of the present disclosure, a semiconductor package is provided, which includes a first semiconductor chip and a second semiconductor chip combined together, wherein the first semiconductor chip includes: a first semiconductor substrate having a first surface and a second surface opposite to each other, a first semiconductor element layer and a first wiring structure sequentially stacked on the first surface of the first semiconductor substrate, a first connection pad and a first test pad connected to the first wiring structure on the first wiring structure, and a first front side bonding pad connected to the first connection pad, and the second semiconductor chip includes: a second semiconductor substrate having a third surface and a fourth surface opposite to the third surface and facing the first surface, a second semiconductor element layer and a second wiring structure sequentially stacked on the third surface of the second semiconductor substrate, and a first back side bonding pad bonded to the first front side bonding pad on the fourth surface of the second semiconductor substrate, and the first test pad is not electrically connected to the second semiconductor chip.

[0006] According to an embodiment of the present disclosure, a semiconductor package is provided, which includes: a semiconductor substrate having a first surface and a second surface opposite to each other; a semiconductor element layer and a wiring structure, which are sequentially stacked on the first surface of the semiconductor substrate; a connection pad, which is on the top surface of the wiring structure and connected to the wiring structure; a test pad, which is on the top surface of the wiring structure and is separated from the connection pad and connected to the wiring structure; a first liner film and a second liner film, which are sequentially stacked on the top surface of the wiring structure; a connection pad opening, which exposes the connection pad through the first liner film and the second liner film; a test pad opening, which exposes the test pad through the first liner film and does not penetrate the second liner film; and a front side bonding pad, which is connected to the connection pad in the connection pad opening.

[0007] According to an embodiment of the present disclosure, a semiconductor package is provided, which includes: a base substrate; and a plurality of semiconductor chips stacked sequentially on the base substrate; wherein each of the plurality of semiconductor chips includes: a semiconductor substrate having a first surface facing the top surface of the base substrate and a second surface opposite to the first surface; a semiconductor element layer and a wiring structure stacked sequentially on the first surface of the semiconductor substrate; a connection pad and a test pad connected to the wiring structure and exposed from the wiring structure; a front side bonding pad connected to the connection pad and not connected to the test pad; a back side bonding pad on the second surface of the semiconductor substrate; and a through via that passes through the semiconductor substrate to connect the wiring structure and the back side bonding pad.

[0008] According to the foregoing and other embodiments of the present disclosure, a method for manufacturing a semiconductor package is provided, the method comprising: providing a first semiconductor substrate having a first surface and a second surface opposite to each other; sequentially forming a first semiconductor element layer and a first wiring structure on the first surface of the first semiconductor substrate; forming a first connection pad and a first test pad on the first wiring structure, the first connection pad and the first test pad being connected to the first wiring structure; forming a first liner film on the first wiring structure, the first connection pad and the first test pad; forming a test pad opening, the test pad opening passing through the first liner film to expose the first test pad; forming a second liner film on the first liner film; and forming a front side bonding pad, the front side bonding pad passing through the first liner film and the second liner film to be connected to the first connection pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings.

[0010] Figure 1 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0011] Figure 2A and Figure 2B yes Figure 1 An enlarged cross-sectional view of region R1.

[0012] Figure 3A and Figure 3B yes Figure 1 A plan view of a first connection pad and a first test pad.

[0013] Figure 4 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0014] Figure 5 yes Figure 4 An enlarged cross-sectional view of region R2.

[0015] Figure 6 yes Figure 4 A plan view of a first connection pad and a first test pad.

[0016] Figures 7 to 10 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0017] Figures 11 to 20 is a cross-sectional view of a stage in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0018] Figure 21 to Figure 23 is a cross-sectional view of a stage in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] In the following we will refer to Figures 1 to 10 A semiconductor package according to some embodiments of the present disclosure is described.

[0020] Figure 1 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. Figure 2A and Figure 2B yes Figure 1 An enlarged cross-sectional view of region R1. Figure 3A and Figure 3B It is shown Figure 1 A plan view of a first connection pad and a first test pad.

[0021] Reference Figures 1 to 3B , a semiconductor package according to some embodiments of the present disclosure may include a first semiconductor chip 100 and a second semiconductor chip 200. Each of the first semiconductor chip 100 and the second semiconductor chip 200 may be an integrated circuit (IC) obtained by integrating hundreds to millions of semiconductor elements into a single chip.

[0022] For example, the first semiconductor chip 100 and the second semiconductor chip 200 may be an application processor (AP), such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, or an application-specific IC (ASIC). In another example, the first semiconductor chip 100 and the second semiconductor chip 200 may be a volatile memory (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM)) or a non-volatile memory (e.g., a flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), a resistive random access memory (RRAM). In some embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 may form a multi-chip semiconductor package, such as a high bandwidth memory (HBM).

[0023] The first semiconductor chip 100 may include a first semiconductor substrate 110, a first through via 115, a first semiconductor element layer 120, a first wiring structure 130, a first connection pad 142, a first test pad 144, a first passivation film 152, a first interlayer insulating film 154, a first liner film 162, a second interlayer insulating film 156, a second liner film 164, a first front side bonding pad 172, a first back side insulating film 190 and a first back side bonding pad 195.

[0024] The first semiconductor substrate 110 may be, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the first semiconductor substrate 110 may be a silicon substrate, or may include, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0025] The first semiconductor substrate 110 may have a first surface 110a and a second surface 110b opposite to each other. The first surface 110a of the first semiconductor substrate 110 may be an effective surface for forming the first semiconductor element layer 120. In the following description, the first surface 110a of the first semiconductor substrate 110 may also be referred to as the front side of the first semiconductor substrate 110, and the second surface 110b of the first semiconductor substrate 110 may also be referred to as the back side of the first semiconductor substrate 110.

[0026] The first semiconductor element layer 120 may be formed on the first surface 110a of the first semiconductor substrate 110. The first semiconductor element layer 120 may include various fine electronic elements, such as metal oxide semiconductor field effect transistors (MOSFETs) (e.g., complementary metal oxide semiconductor (CMOS) transistors), system large scale integration (LSI), flash memory, DRAM, SRAM, electrically erasable programmable read-only memory (EEPROM), PRAM, MRAM, RRAM, image sensors (e.g., CMOS imaging sensors), micro-electromechanical systems (MEMS), active elements, and passive elements.

[0027] The first wiring structure 130 may cover the first semiconductor element layer 120. The first wiring structure 130 may be electrically connected to the first semiconductor element layer 120. For example, the first wiring structure 130 may include a first inter-wiring insulating film 132 and a first wiring pattern 134 disposed in the first inter-wiring insulating film 132. The first wiring pattern 134 may form a multi-layer structure and may be electrically connected to the first semiconductor element layer 120. The layout of the first wiring pattern 134, the number of the first wiring patterns 134, and the number of layers formed by the first wiring patterns 134 are merely exemplary and are not particularly limited.

[0028] For example, the first wiring pattern 134 may include a conductive film and a barrier film, and the barrier film is provided between the first inter-wiring insulating film 132 and the conductive film. The conductive film may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu). The barrier film may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0029] The first through via 115 may penetrate the first semiconductor substrate 110. The first through via 115 may be electrically connected to the first wiring structure 130. For example, the first through via 115 may pass through the first semiconductor substrate 110 and the first semiconductor element layer 120 to connect to the lowermost layer of the first wiring pattern 134. The first through via 115 may include, for example, at least one of Cu, a Cu alloy (e.g., CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, or CuW), W, a W alloy, nickel (Ni), ruthenium (Ru), and cobalt (Co).

[0030] The first connection pad 142 and the first test pad 144 may be spaced apart from each other and may be formed on the first wiring structure 130. The first connection pad 142 and the first test pad 144 may be electrically connected to the first wiring structure 130. For example, a first wiring groove 142t exposing a portion of the uppermost layer of the first wiring pattern 134 may be formed in the first inter-wiring insulating film 132. At least a portion of the first connection pad 142 may be formed in the first inter-wiring insulating film 132 and may be connected to the first wiring pattern 134. For example, a second wiring groove 144t exposing other portions of the uppermost layer of the first wiring pattern 134 may be formed in the first inter-wiring insulating film 132. At least a portion of the first test pad 144 may be formed in the second wiring groove 144t and may be connected to the first wiring pattern 134.

[0031] The number of the first connection pads 142 and the first test pads 144 and the layout of the first connection pads 142 and the first test pads 144 are merely exemplary and are not particularly limited. Figure 3A As shown in , the first connection pads 142 may be arranged in a lattice form on the XY plane, for example, arranged in a two-dimensional matrix pattern along the X direction and the Y direction. A plurality of first test pads 144 may be provided on both sides of each array of the first connection pads 142, for example, a plurality of first test pads 144 may be located at each of two opposite ends of the matrix pattern of the first connection pads 142. In another example, as Figure 3B As shown in , four first test pads 144 may be arranged near four corners of the first semiconductor chip 100 .

[0032] For example, Figure 1 As shown in FIG. 1 , the first wiring pattern 134 connected to the first connection pad 142 and the first wiring pattern 134 connected to the first test pad 144 may not be connected to each other. In another example, the first wiring pattern 134 connected to the first connection pad 142 may be electrically connected to the first wiring pattern 134 connected to the first test pad 144.

[0033] The first connection pad 142 and the first test pad 144 may include, for example, at least one of W, Al, and Cu. For example, the first connection pad 142 and the first test pad 144 may include Al.

[0034] For example, Figure 2A As shown in FIG. 1 , the top surface of the first test pad 144 may include a groove 144h. The groove 144h of the first test pad 144 may be formed during the test process of the first semiconductor chip 100. This will be referred to later. Fig.14 Give a description.

[0035] like Figure 1 and Figure 2A As shown in FIG. 1 , the first connection pad 142 and the first test pad 144 may protrude from the first wiring structure 130 (e.g., protrude above the first wiring structure 130). For example, the top surface of the first connection pad 142 and the top surface of the first test pad 144 may be formed to be higher than the top surface of the first wiring structure 130, for example, relative to the first semiconductor element layer 120. Therefore, the first connection pad 142 and the first test pad 144 may be exposed from the first wiring structure 130.

[0036] Reference Figure 2A , the width W11 of the first connection pad 142 and the width W12 of the first test pad 144 may be, for example, about 100 μm. For example, the width W11 of the first connection pad 142 and the width W12 of the first test pad 144 may be about 10 μm to about 70 μm. The width W11 of the first connection pad 142 may be greater than the width of the first wiring trench 142t, and the width W12 of the first test pad 144 may be greater than the width of the second wiring trench 144t. In some embodiments, the width W12 of the first test pad 144 may be greater than the width W11 of the first connection pad 142. Figure 2A As shown in , each of the widths W11 and W12 refers to a maximum width measured at a widest portion between opposite sidewalls of a corresponding one of the first connection pad 142 and the first test pad 144 (eg, along an uppermost surface of the first wiring structure 130 ).

[0037] The first passivation film 152 may be formed on the first wiring structure 130, the first connection pad 142, and the first test pad 144. For example, the first passivation film 152 may be conformally formed along the contours of the first wiring structure 130, the first connection pad 142, and the first test pad 144. The first passivation film 152 may protect the first connection pad 142 and the first test pad 144 from external impact or moisture. The first passivation film 152 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0038] The first interlayer insulating film 154 may be formed on the first passivation film 152. The first interlayer insulating film 154 may cover the top surface of the first passivation film 152. In some embodiments, the first interlayer insulating film 154 may have a flat top surface. For example, the top surface of the first interlayer insulating film 154 may extend parallel to the uppermost top surface of the first wiring structure 130. The first interlayer insulating film 154 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first interlayer insulating film 154 may include tetraethyl orthosilicate (TEOS).

[0039] A first liner film 162 may be formed on the first interlayer insulating film 154. The first liner film 162 may cover a top surface of the first interlayer insulating film 154. In some embodiments, the first liner film 162 may conformally extend along a flat top surface of the first interlayer insulating film 154. The first liner film 162 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0040] In some embodiments, the first liner film 162 may include a different material from the first interlayer insulating film 154. For example, the first interlayer insulating film 154 may include a silicon oxide film, and the first liner film 162 may include a silicon nitride film.

[0041] The first passivation film 152, the first interlayer insulating film 154, and the first liner film 162 may expose the first test pad 144. For example, a test pad opening 174t may be formed through the first passivation film 152, the first interlayer insulating film 154, and the first liner film 162 to expose at least a portion of the top surface of the first test pad 144. Figure 3A and Figure 3B As shown in FIG. 1 , in a plan view, the test pad opening 174t (eg, an oval dashed line) may overlap at least a portion of the first test pad 144 (eg, a shaded rectangle overlapping the oval dashed line).

[0042] The second interlayer insulating film 156 may be formed on the first liner film 162. The second interlayer insulating film 156 may cover the top surface of the first liner film 162. In some embodiments, the second interlayer insulating film 156 may have a flat top surface. For example, the top surface of the second interlayer insulating film 156 may extend parallel to the uppermost top surface of the first wiring structure 130. The second interlayer insulating film 156 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the second interlayer insulating film 156 may include TEOS.

[0043] In some embodiments, a portion of the second interlayer insulating film 156 may pass through the first passivation film 152, the first interlayer insulating film 154, and the first liner film 162 to contact the first test pad 144. Figure 2A and Figure 2BAs shown in FIG. 1 , a portion of the second interlayer insulating film 156 may fill the test pad opening 174 t .

[0044] The second liner film 164 may be formed on the second interlayer insulating film 156. The second liner film 164 may cover the top surface of the second interlayer insulating film 156. In some embodiments, the second liner film 164 may conformally extend along the flat top surface of the second interlayer insulating film 156. The second liner film 164 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0045] In some embodiments, the second liner film 164 may include a different material from the second interlayer insulating film 156. For example, the second interlayer insulating film 156 may include a silicon oxide film, and the second liner film 164 may include a silicon nitride film.

[0046] In some embodiments, the first liner film 162 and the second liner film 164 may include different materials. For example, the first liner film 162 may include a SiN film, and the second liner film 164 may include a SiCN film.

[0047] The first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, and the second liner film 164 may expose the first connection pad 142. For example, a connection pad opening 172t that exposes at least a portion of the top surface of the first connection pad 142 may be formed through the first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, and the second liner film 164. Figure 3A and Figure 3B As shown in FIG. 1 , in a plan view, the connection pad opening 172 t (eg, a solid curve) may overlap at least a portion of the first connection pad 142 (eg, a shaded rectangle overlapping the solid curve).

[0048] In some embodiments, unlike the connection pad opening 172t, the test pad opening 174t may not penetrate the second interlayer insulating film 156 and the second liner film 164. That is, the test pad opening 174t may be formed in the first passivation film 152, the first interlayer insulating film 154, and the first liner film 162, but not in the second interlayer insulating film 156 and the second liner film 164.

[0049] The first front side bonding pad 172 may be formed on the first connection pad 142. The first front side bonding pad 172 may be connected to the first connection pad 142 through the first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, and the second liner film 164. For example, the first front side bonding pad 172 may be formed in the connection pad opening 172t and may be connected to the first connection pad 142. The first front side bonding pad 172 may be exposed from the second liner film 164. For example, the top surface of the first front side bonding pad 172 may be disposed in the same plane as the top surface of the second liner film 164, for example, the top surface of the first front side bonding pad 172 and the top surface of the second liner film 164 may face the same direction and may be coplanar.

[0050] The first front side bonding pad 172 may be connected to the first test pad 144. For example, as has been mentioned above, a portion of the second interlayer insulating film 156 may fill the test pad opening 174t.

[0051] The first front side bonding pad 172 may include, for example, at least one of W, Al, and Cu. Preferably, the first front side bonding pad 172 may include Cu.

[0052] For example, the width W21 of the first front side bonding pad 172 may be about 10 μm or less (e.g., about 5 μm to about 10 μm). In some embodiments, the width W22 of the test pad opening 174t may be greater than the width W21 of the first front side bonding pad 172. Figure 2A As shown in , each of the widths W21 and W22 refers to a maximum width measured at the widest portion between the first front side bonding pad 172 and the facing sidewall of a corresponding one of the test pad openings 174t.

[0053] For example, the height H11 of the first front side bonding pad 172 may be about 5 μm or less (e.g., about 3 μm to about 5 μm). Since the first front side bonding pad 172 penetrates the second interlayer insulating film 156 and the second liner film 164 in addition to the first liner film 162, the height H11 of the first front side bonding pad 172 may be greater than the first dummy pad 174 (see FIG. Figure 5 ) is larger in height H12.

[0054] The first backside insulating film 190 may be formed on the second surface 110b of the first semiconductor substrate 110. The first backside insulating film 190 may cover the second surface 110b of the first semiconductor substrate 110. The first backside insulating film 190 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the first backside insulating film 190 may include a silicon oxide film.

[0055] The first rear side bonding pad 195 may be formed on the second surface 110b of the first semiconductor substrate 110. The first rear side bonding pad 195 may be exposed from the first rear side insulating film 190 (e.g., exposed through the first rear side insulating film 190). For example, the bottom surface of the first rear side bonding pad 195 may be disposed in the same plane as the bottom surface of the first rear side insulating film 190, for example, the first rear side bonding pad 195 may penetrate the entire thickness of the first rear side insulating film 190 to have the same thickness as the first rear side insulating film 190 and to have a bottom surface coplanar with the bottom surface of the first rear side insulating film 190.

[0056] The first rear side bonding pad 195 may be electrically connected to the first through via 115. For example, the first through via 115 may be directly connected to the top surface of the first rear side bonding pad 195, for example, through the first semiconductor substrate 110. The first rear side bonding pad 195 may be electrically connected to the first wiring structure 130 and / or the first semiconductor element layer 120 through the first through via 115.

[0057] The first backside bonding pad 195 may include, for example, at least one of W, Al, and Cu. For example, the first backside bonding pad 195 may include Cu.

[0058] The second semiconductor chip 200 may include a second semiconductor substrate 210, a second through via 215, a second semiconductor element layer 220, a second wiring structure 230, a second connection pad 242, a second test pad 244, a second passivation film 252, a third interlayer insulating film 254, a third lining film 262, a fourth interlayer insulating film 256, a fourth lining film 264, a second front side bonding pad 272, a second back side insulating film 290 and a second back side bonding pad 295. The second semiconductor substrate 210, the second through via 215, the second semiconductor element layer 220, the second wiring structure 230, the second connection pad 242, the second test pad 244, the second passivation film 252, the third interlayer insulating film 254, the third liner film 262, the fourth interlayer insulating film 256, the fourth liner film 264, the second front side bonding pad 272, the second back side insulating film 290 and the second back side bonding pad 295 may correspond to the first semiconductor substrate 110, the first through via 115, the first semiconductor element layer 120, the first wiring structure 130, the first connection pad 142, the first test pad 144, the first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, the second liner film 164, the first front side bonding pad 172, the first back side insulating film 190 and the first back side bonding pad 195, respectively.

[0059] The first semiconductor chip 100 and the second semiconductor chip 200 can be combined together in a die-to-wafer (D2W) method. For example, the first front side bonding pad 172 of the first semiconductor chip 100 and the second back side bonding pad 295 of the second semiconductor chip 200 can be combined together, for example, the first front side bonding pad 172 and the second back side bonding pad 295 can be directly connected to each other via direct surface contact between the surfaces facing them. As a result, the first semiconductor chip 100 and the second semiconductor chip 200 can be electrically connected. In detail, the first semiconductor element layer 120 and / or the first wiring structure 130 of the first semiconductor chip 100 can be electrically connected to the second semiconductor element layer 220 and / or the second wiring structure 230 of the second semiconductor chip 200 via the first connection pad 142, the first front side bonding pad 172, the second back side bonding pad 295 and the second through via 215.

[0060] For example, Figure 2A As shown in , the width of the second rear side bonding pad 295 (e.g., the maximum width along the surface in contact with the first front side bonding pad 172) can be the same as the width W21 of the first front side bonding pad 172. In another example, the width of the second rear side bonding pad 295 can be less than or greater than the width W21 of the first front side bonding pad 172.

[0061] The first test pads 144 of the first semiconductor chip 100 may not be electrically connected to the second semiconductor chip 200, for example, the first test pads 144 may be electrically isolated from the second semiconductor chip 200. For example, as already mentioned above, a portion of the second interlayer insulating film 156 may be formed in the test pad opening 174t (for example, completely filling the test pad opening 174t), and the second backside bonding pads 295 may not be connected to the first test pads 144.

[0062] In some embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 may be bonded via hybrid bonding. Hybrid bonding refers to a method of bonding a metal to an insulating film (eg, an oxide film) or a metal to a polymer. Figure 2A As shown in FIG. 1 , the first front side bonding pad 172 may be attached to the second back side bonding pad 295, and the second liner film 164 may be attached to the second back side insulating film 290. For example, the first semiconductor chip 100 and the second semiconductor chip 200 may be bonded via Cu-oxide hybrid bonding.

[0063] In other embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 may be bonded via metal bonding. Figure 2BAs shown in FIG. 1 , the first front side bonding pad 172 may be attached to the second back side bonding pad 295, and the second liner film 164 may be spaced apart from the second back side insulating film 290. For example, the first semiconductor chip 100 and the second semiconductor chip 200 may be bonded via Cu-Cu bonding.

[0064] As the demand for compactness, lightness, and versatility of semiconductor packages increases, a method of simply stacking semiconductor chips via a chip-on-wafer (CoW) method may have limitations. For example, it may be difficult to ensure appropriate thermal properties for connection members (e.g., bumps or solder) because of limitations in smoothly releasing heat.

[0065] On the contrary, according to example embodiments, the semiconductor chips (e.g., the first semiconductor chip 100 and the second semiconductor chip 200) of the semiconductor package can be combined together in a D2W method, thereby having improved thermal properties. For example, as already mentioned above, the first front side bonding pad 172 of the first semiconductor chip 100 and the second back side bonding pad 295 of the second semiconductor chip 200 can, for example, be directly combined together and can include Cu, for example, each of the first front side bonding pad 172 and the second back side bonding pad 295 can include Cu and can be combined with each other via Cu-Cu bonding, and the Cu-Cu bonding has a lower thermal resistance than a connecting member (e.g., a bump or solder). Therefore, a semiconductor package with improved thermal properties can be provided.

[0066] In addition, the semiconductor package according to some embodiments of the present disclosure may include a test pad (eg, first test pad 144) capable of providing a test function for a semiconductor chip (eg, first semiconductor chip 100). Therefore, a semiconductor package that can facilitate a test process can be provided.

[0067] Figure 4 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. Figure 5 yes Figure 4 An enlarged cross-sectional view of region R2. Figure 6 It is shown Figure 4 For convenience, the above referenced Figures 1 to 3B A description of an element or feature described.

[0068] Reference Figures 4 to 6 , the first semiconductor chip 100 may further include a first dummy pad 174, and the second semiconductor chip 200 may further include a second dummy pad 274. The first dummy pad 174 may be formed on the first test pad 144, and the second dummy pad 274 may be formed on the second test pad 244. The structure of the second dummy pad 274 may be the same as that of the first dummy pad 174.

[0069] In detail, the first dummy pad 174 may be formed on the first test pad 144 and may be connected to the first test pad 144 through the first passivation film 152, the first interlayer insulating film 154, and the first liner film 162. For example, the first dummy pad 174 may be formed in the test pad opening 174t (e.g., completely fill the test pad opening 174t) and may be connected to the first test pad 144. The first dummy pad 174 may be exposed from the first liner film 162. For example, the top surface of the first dummy pad 174 may be arranged in the same plane as the top surface of the first liner film 162, for example, coplanar with the top surface of the first liner film 162. The first dummy pad 174 may include, for example, at least one of W, Al, and Cu. For example, the first dummy pad 174 may include Cu.

[0070] For example, the width W22 of the first dummy pad 174 may be about 10 μm or less (eg, about 5 μm to about 10 μm). In some embodiments, the width W22 of the first dummy pad 174 may be greater than the width W21 of the first front side bonding pad 172 .

[0071] For example, the height H12 of the first dummy pad 174 may be about 5 μm or less (e.g., about 3 μm to about 5 μm). Since the first front side bonding pad 172 penetrates the second interlayer insulating film 156 and the second liner film 164 in addition to the first liner film 162, the height H11 of the first front side bonding pad 172 may be greater than the height H12 of the first dummy pad 174.

[0072] The first dummy pad 174 may not be electrically connected to the second semiconductor chip 200. For example, the second interlayer insulating film 156 may be formed on the first liner film 162 and the first dummy pad 174. The second interlayer insulating film 156 may cover the top surface of the first liner film 162 and the top surface of the first dummy pad 174. Therefore, the second backside bonding pad 295 may not be connected to the first test pad 144.

[0073] Figures 7 to 10 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. Figures 1 to 6 A description of an element or feature described.

[0074] Reference Figure 7 or Figure 8 , a semiconductor package according to some embodiments of the present disclosure may include a base substrate 500 and a semiconductor chip stack ( 100 , 200 , 300 , and 400 ).

[0075] The base substrate 500 may be a package substrate for forming a semiconductor package. For example, the base substrate 500 may be a printed circuit board (PCB), a ceramic substrate, or an interposer. In another example, the base substrate 500 may be a wafer level package (WLP) substrate manufactured at a wafer level. In yet another example, the base substrate 500 may be a semiconductor chip including a semiconductor element. The base substrate 500 will be described below as a semiconductor chip including a base semiconductor substrate 510.

[0076] The semiconductor chip stack (100, 200, 300, and 400) may include a plurality of stacked semiconductor chips, namely, a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a fourth semiconductor chip 400. For example, the second semiconductor chip 200 may be stacked on the fourth semiconductor chip 400, the first semiconductor chip 100 may be stacked on the second semiconductor chip 200, and the third semiconductor chip 300 may be stacked on the first semiconductor chip 100. The semiconductor chip stack (100, 200, 300, and 400) may form a multi-chip semiconductor package (e.g., HBM).

[0077] Each of the first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300 and the fourth semiconductor chip 400 may include a semiconductor substrate 110, 210, 310 or 410, a through via 115, 215, 315 or 415, a semiconductor element layer 120, 220, 320 or 420, a wiring structure 130, 230, 330 or 430, a connection pad 142, 242, 342 or 442, a test pad 144, 244, 344 or 444, a front side bonding pad 172, 272, 372 or 472 and a back side bonding pad 195, 295, 395 or 495. The semiconductor substrate 110, 210, 310 or 410, the through via 115, 215, 315 or 415, the semiconductor element layer 120, 220, 320 or 420, the wiring structure 130, 230, 330 or 430, the connection pad 142, 242, 342 or 442, the test pad 144, 244, 344 or 444, the front side bonding pad 172, 272, 372 or 472 and the back side bonding pad 195, 295, 395 or 495 may correspond to Figure 1 The first semiconductor substrate 110, the first through via 115, the first semiconductor element layer 120, the first wiring structure 130, the first connection pad 142, the first test pad 144, the first front side bonding pad 172 and the first back side bonding pad 195 are shown in FIG. 1 , and thus their detailed description will be omitted.

[0078] The semiconductor chip stack (100, 200, 300, and 400) may be stacked on a base substrate 500. For example, a first base pad 595 may be formed on a top surface of the base semiconductor substrate 510. The fourth semiconductor chip 400 may be electrically connected to the base substrate 500 via the first base pad 595. For example, the front side bonding pad 472 of the fourth semiconductor chip 400 may be directly connected to the first base pad 595 of the base substrate 500, for example.

[0079] In some embodiments, the base substrate 500 may further include a base through-via 515, a second base pad 540, and a base connection member 545. The second base pad 540 may be formed on the bottom surface of the base semiconductor substrate 510. The base through-via 515 may connect the first base pad 595 and the second base pad 540 through the base semiconductor substrate 510. The base connection member 545 may be connected to the second base pad 540. The semiconductor package according to some embodiments of the present disclosure may be electrically connected to an external device (e.g., a panel of an electronic device) via the base connection member 545. The base connection member 545 may include, for example, at least one of a solder ball, a bump, an under bump metallurgy (UBM), and a combination thereof. For example, the base connection member 545 may include a metal (e.g., tin (Sn)).

[0080] The test pads 144, 244, 344, and 444 may not be connected to the first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400, respectively, and vice versa. Figure 7 As shown in Figure 1 The second interlayer insulating film 156), the test pad 144, the test pad 244, the test pad 344 and the test pad 444 may not be electrically connected to the back side bonding pad 195, the back side bonding pad 295, the back side bonding pad 395 and the back side bonding pad 495, respectively.

[0081] Reference Figure 8 In some embodiments, each of the first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400 may further include a dummy pad 174, 274, 374, or 474. The dummy pad 174, 274, 374, or 474 may correspond to Figures 4 to 6 The first dummy pads 174 are provided in the embodiment of the present invention, and thus their detailed description will be omitted.

[0082] Reference Fig. 9 or Fig.10 , a semiconductor package according to some embodiments of the present disclosure may include a PCB 10 , an interposer 20 , a logic semiconductor chip 30 , and a molding member 50 .

[0083] The interposer 20 may be stacked on the PCB 10. The interposer 20 may be electrically connected to the PCB 10. For example, the base pad 14 may be formed on the top surface of the PCB 10, and the first interposer pad 22 may be formed on the bottom surface of the interposer 20. The base pad 14 and the first interposer pad 22 may be connected to each other via a first connection member 25. The first connection member 25 may include, for example, at least one of a solder ball, a bump, a UBM, and a combination thereof. For example, the first connection member 25 may include a metal (e.g., Sn).

[0084] The interposer 20 may be placed between the PCB 10 and the semiconductor chip stack (100, 200, 300, and 400). The semiconductor chip stack (100, 200, 300, and 400) may be stacked on the top surface of the interposer 20. The interposer 20 may be a silicon interposer or an organic interposer. In some embodiments, the interposer 20 may include a silicon interposer. The interposer 20 may facilitate the connection between the logic semiconductor chip 30 and the semiconductor chip stack (100, 200, 300, and 400), and may be used to reduce the warpage of the semiconductor package according to some embodiments of the present disclosure.

[0085] The logic semiconductor chip 30 may be an integrated circuit (IC) obtained by integrating hundreds to millions of semiconductor elements into a single chip. The logic semiconductor chip 30 may be an AP (eg, a CPU, a GPU, a FPGA, a DSP, a cryptographic processor, a microprocessor, a microcontroller, or an ASIC).

[0086] The logic semiconductor chip 30 may be mounted on the top surface of the interposer 20. For example, the second interposer pad 24 may be formed on the top surface of the interposer 20, and the first chip pad 32 may be formed on the bottom surface of the logic semiconductor chip 30. The second interposer pad 24 and the first chip pad 32 may be connected to each other via a second connection member 35. The second connection member 35 may include, for example, at least one of a microbump, a UBM, and a combination thereof. For example, the second connection member 35 may include a metal (e.g., Sn).

[0087] In some embodiments, a first underfill 52 may be formed between the interposer 20 and the logic semiconductor chip 30. The first underfill 52 may fill the space between the interposer 20 and the logic semiconductor chip 30. In addition, the first underfill 52 may cover the second connection member 35. The first underfill 52 may prevent breakage of the logic semiconductor chip 30 by fixing the logic semiconductor chip 30 on the interposer 20. For example, the first underfill 52 may include an insulating polymer material (e.g., epoxy molding compound (EMC)).

[0088] The semiconductor chip stack (100, 200, 300, and 400) may form a multi-chip semiconductor package (e.g., HBM). In some embodiments, the buffer semiconductor chip 40 may be placed between the interposer 20 and the semiconductor chip stack (100, 200, 300, and 400). The buffer semiconductor chip 40 may facilitate the connection between the interposer 20 and the semiconductor chip stack (100, 200, 300, and 400) and the connection between the logic semiconductor chip 30 and the semiconductor chip stack (100, 200, 300, and 400). For example, the buffer semiconductor chip 40 may be an AP (e.g., a CPU, a GPU, an FPGA, a DSP, a cryptographic processor, a microprocessor, a microcontroller, or an ASIC).

[0089] The buffer semiconductor chip 40 may be mounted on the top surface of the interposer 20 to be spaced apart from the logic semiconductor chip 30. For example, the second chip pad 42 may be formed on the bottom surface of the buffer semiconductor chip 40. The second interposer pad 24 and the second chip pad 42 may be connected to each other via a third connection member 45. The third connection member 45 may include, for example, at least one of a microbump, a UBM, and a combination thereof. For example, the third connection member 45 may include a metal (e.g., Sn).

[0090] In some embodiments, a second underfill 54 may be formed between the interposer 20 and the buffer semiconductor chip 40. The second underfill 54 may fill the space between the interposer 20 and the buffer semiconductor chip 40. In addition, the second underfill 54 may cover the third connection member 45. The second underfill 54 may prevent breakage of the buffer semiconductor chip 40 by fixing the buffer semiconductor chip 40 on the interposer 20. For example, the second underfill 54 may include an insulating polymer material (e.g., EMC).

[0091] The molding member 50 may be formed on the top surface of the interposer 20. The molding member 50 may cover at least a portion of the logic semiconductor chip 30 and at least a portion of the semiconductor chip stack (100, 200, 300, and 400). For example, the molding member 50 may cover the side surface of the logic semiconductor chip 30 and the side surface of the semiconductor chip stack (100, 200, 300, and 400). The molding member 50 is shown as exposing only the top surface of the logic semiconductor chip 30 and the top surface of the semiconductor chip stack (100, 200, 300, and 400). Optionally, the molding member 50 may also cover the top surface of the logic semiconductor chip 30 and the top surface of the semiconductor chip stack (100, 200, 300, and 400).

[0092] For example, the molding member 50 may include an insulating polymer material (e.g., EMC). In some embodiments, the first underfill 52 and the second underfill 54 may include a material different from the molding member 50. For example, the first underfill 52 and the second underfill 54 may include an insulating material having greater fluidity than the molding member 50. Therefore, the first underfill 52 and the second underfill 54 may effectively fill the narrow space between the interposer 20 and the logic semiconductor chip 30 and / or between the interposer 20 and the semiconductor chip stack (100, 200, 300, and 400).

[0093] In the following we will refer to Figures 1 to 23 A method of manufacturing a semiconductor package according to some embodiments of the present disclosure is described.

[0094] Figures 11 to 20 is a cross-sectional view of a stage in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. Figures 1 to 10 A description of an element or feature described.

[0095] Reference Fig.11 , a first through via 115 , a first semiconductor element layer 120 , a first wiring structure 130 , a first connection pad 142 , a first test pad 144 , and a first passivation film 152 may be formed on the first semiconductor substrate 110 .

[0096] For example, a first semiconductor substrate 110 having a first surface 110a and a second surface 110b may be provided. A first semiconductor element layer 120 may be formed on the first surface 110a of the first semiconductor substrate 110. A first through-via 115 may be formed in the first semiconductor substrate 110 and the first semiconductor element layer 120, for example, the first through-via 115 may be formed through the first semiconductor substrate 110 and the first semiconductor element layer 120. A first wiring structure 130 may be formed on the first semiconductor element layer 120. The first connection pad 142 and the first test pad 144 may be spaced apart from each other and may be formed on the first wiring structure 130.

[0097] Thereafter, a first passivation film 152 may be formed on the first wiring structure 130, the first connection pad 142, and the first test pad 144. The first passivation film 152 may conformally extend along contours of the first wiring structure 130, the first connection pad 142, and the first test pad 144. The first passivation film 152 may be formed by high density plasma chemical vapor deposition (HDPCVD).

[0098] Reference Fig.12 , a first interlayer insulating film 154 and a first liner film 162 may be sequentially formed on the first passivation film 152 .

[0099] For example, a first interlayer insulating film 154 covering the first passivation film 152 may be formed. The first interlayer insulating film 154 may be formed by, for example, plasma enhanced chemical vapor deposition (PECVD), low temperature chemical vapor deposition (LTCVD), or atomic layer deposition (ALD). The first interlayer insulating film 154 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first interlayer insulating film 154 may include TEOS.

[0100] Thereafter, a first liner film 162 covering the first interlayer insulating film 154 may be formed. In some embodiments, the first interlayer insulating film 154 may be planarized before forming the first liner film 162. The first interlayer insulating film 154 may be planarized by, for example, chemical mechanical polishing (CMP). The first liner film 162 may extend along the flat top surface of the first interlayer insulating film 154. The first liner film 162 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first liner film 162 may include a SiN film.

[0101] Reference Fig.13 , a test pad opening 174 t is formed in the first interlayer insulating film 154 and the first liner film 162 .

[0102] For example, an etching process may be performed to expose at least a portion of the top surface of the first test pad 144. The etching process may include a dry etching process for the first interlayer insulating film 154 and the first liner film 162. As a result, a test pad opening 174t may be formed, which passes through the first interlayer insulating film 154 and the first liner film 162 to expose at least a portion of the top surface of the first test pad 144.

[0103] Reference Fig.14 , a test process for the first test pad 144 may be performed using the test pad opening 174t. The test process may be performed to test the function and electrical connection of the first semiconductor chip 100.

[0104] For example, a test device including a probe TP may be provided. The test device may perform a test process by placing the probe TP in physical contact with the first test pad 144. This type of contact test process may have higher performance than a non-contact test process.

[0105] In some embodiments, a groove 144h may be formed in the first test pad 144. For example, when the probe TP physically contacts the first test pad 144 during a test process, the groove 144H may be formed on the top surface of the first test pad 144.

[0106] Reference Fig.15, a second interlayer insulating film 156 and a second liner film 164 may be sequentially formed on the first liner film 162 .

[0107] For example, the second interlayer insulating film 156 may be formed covering the first liner film 162. The second interlayer insulating film 156 may be formed by PECVD, LTCVD, or ALD.

[0108] The second interlayer insulating film 156 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the second interlayer insulating film 156 may include TEOS.

[0109] In some embodiments, the second interlayer insulating film 156 may be filled with Fig.14 Therefore, a portion of the second interlayer insulating film 156 may contact the first test pad 144 .

[0110] Thereafter, a second liner film 164 covering the second interlayer insulating film 156 may be formed. In some embodiments, the second interlayer insulating film 156 may be planarized before forming the second liner film 164. The second interlayer insulating film 156 may be planarized by CMP. The second liner film 164 may extend along the planarized top surface of the second interlayer insulating film 156.

[0111] The second liner film 164 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, but the present disclosure is not limited thereto. For example, the second liner film 164 may include a SiCN film.

[0112] Reference Fig.16 , forming a first front side bonding pad 172 connected to the first connection pad 142.

[0113] For example, an opening (eg, a first opening) that exposes at least a portion of the top surface of the first connection pad 142 may be formed through the first passivation film 152, the first interlayer insulating film 154, the first liner film 162, the second interlayer insulating film 156, and the second liner film 164. Figure 2A and Figure 2B After that, a conductive film may be formed on the second liner film 164 to fill the opening. The conductive film may be formed by, for example, a damascene process.

[0114] Thereafter, the conductive film may be planarized. The conductive film may be planarized by, for example, CMP. In some embodiments, the second liner film 164 may be used as an etch stop layer during the planarization of the conductive film. As a result, a first front side bonding pad 172 may be formed, and the top surface of the first front side bonding pad 172 is disposed in the same plane as the top surface of the second liner film 164.

[0115] The first front side bonding pad 172 may include, for example, at least one of W, Al, and Cu. For example, the first front side bonding pad 172 may include Cu.

[0116] Reference Fig.17 , a recessing process is performed on the second surface 110 b of the first semiconductor substrate 110 .

[0117] For example, a backgrinding process may be performed on the second surface 110b of the first semiconductor substrate 110. As a result of the recessing process, a portion of the first through via 115 may be exposed. For example, the recessing process may be performed until the second surface 110b of the first semiconductor substrate 110 becomes lower than the top surface of the first through via 115. In this example, the first through via 115 protruding beyond the second surface 110b of the first semiconductor substrate 110 may be formed (e.g., the first through via 115 protruding above the second surface 110b of the first semiconductor substrate 110 may be formed).

[0118] Reference Fig.18 A first backside insulating film 190 is formed on the second surface 110 b of the first semiconductor substrate 110 .

[0119] For example, the first through via 115 may be planarized. The first through via 115 may be planarized by, for example, CMP. As a result, a protruding portion of the first through via 115 may be removed. Thereafter, a first backside insulating film 190 covering the second surface 110b of the first semiconductor substrate 110 and the first through via 115 may be formed. The first backside insulating film 190 may be formed by, for example, CVD.

[0120] Reference Fig.19 , forming a first rear side bonding pad 195 connected to the first through via 115 .

[0121] For example, an opening may be formed through the first backside insulating film 190 to expose at least a portion of the top surface of the first through via 115. Thereafter, a conductive film may be formed to fill the opening. The conductive film may be formed by, for example, a damascene process.

[0122] Thereafter, the conductive film may be planarized. The conductive film may be planarized by, for example, CMP. As a result, a first rear side bonding pad 195 may be formed, the top surface of which is disposed in the same plane as the top surface of the first rear side insulating film 190.

[0123] The first backside bonding pad 195 may include, for example, at least one of W, Al, and Cu. For example, the first backside bonding pad 195 may include Cu.

[0124] In this way, one can obtain Figure 1 The first semiconductor chip 100 is provided.

[0125] Reference Fig. 20 , the first semiconductor chip 100 and the second semiconductor chip 200 may be combined together. The second semiconductor chip 200 may be manufactured in a similar manner to the first semiconductor chip 100, and thus, a detailed description of how to manufacture the second semiconductor chip 200 will be omitted.

[0126] The first semiconductor chip 100 and the second semiconductor chip 200 may be bonded together in a D2W method. For example, the first front side bonding pad 172 of the first semiconductor chip 100 and the second back side bonding pad 295 of the second semiconductor chip 200 may be bonded. As a result, the first semiconductor chip 100 and the second semiconductor chip 200 may be electrically connected.

[0127] Figure 21 to Figure 23 is a cross-sectional view of a stage in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. Figures 1 to 20 A description of an element or feature described. Fig.21 Shown in Fig.14 The following are steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0128] Reference Fig.21 , forming a first dummy pad 174 connected to the first test pad 144. For example, a conductive film may be formed to fill the test pad opening 174t. The conductive film may be formed by, for example, a damascene process.

[0129] Thereafter, the conductive film may be planarized. The conductive film may be planarized by, for example, CMP. In some embodiments, the first liner film 162 may be used as an etch stop layer during planarization of the conductive film. As a result, a first dummy pad 174 may be formed, and the top surface of the first dummy pad 174 is disposed in the same plane as the top surface of the first liner film 162.

[0130] The first dummy pad 174 may include, for example, at least one of W, Al, and Cu. For example, the first dummy pad 174 may include Cu.

[0131] Reference Fig. 22 , a second interlayer insulating film 156 and a second liner film 164 are sequentially formed on the first liner film 162 and the first dummy pad 174. The second interlayer insulating film 156 and the second liner film 164 are formed similarly to Fig.15 The formation of the second interlayer insulating film 156 and the second liner film 164 is described below, and therefore, their detailed descriptions will be omitted.

[0132] Reference Fig.23, forming a first front side bonding pad 172 connected to the first connection pad 142. The formation of the first front side bonding pad 172 is similar to Fig.16 The formation of the first front side bonding pad 172 is described below, and therefore, a detailed description thereof will be omitted.

[0133] Afterwards, you can execute Figures 17 to 20 In this way, we can obtain Figures 4 to 6 semiconductor packages.

[0134] By way of summary and review, embodiments of the present disclosure provide a semiconductor package with improved thermal properties. Embodiments of the present disclosure also provide a method of manufacturing a semiconductor package with improved thermal properties.

[0135] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted only in a general and descriptive sense, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, unless otherwise specifically indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor package, comprising: A first semiconductor chip, comprising: a first semiconductor substrate having a first surface and a second surface opposite to each other; a first semiconductor element layer formed on the first surface of the first semiconductor substrate; a first wiring structure formed on the first semiconductor element layer, the first wiring structure comprising a first inter-wiring insulating film and a first wiring pattern arranged in the first inter-wiring insulating film; a first connection pad and a first test pad formed on the first wiring structure, the first connection pad and the first test pad being connected to the first wiring pattern; a first passivation film formed on the first wiring structure, the first connection pad and the first test pad; a first interlayer insulating film formed on the first passivation film; a connection pad opening penetrating the first interlayer insulating film and the first passivation film and exposing at least a portion of a top surface of the first connection pad; a test pad opening penetrating the first interlayer insulating film and the first passivation film and exposing at least a portion of a top surface of the first test pad; a first front side bonding pad formed in the connection pad opening and connected to the first connection pad through the first interlayer insulating film and the first passivation film; and a first back side bonding pad formed on the second surface of the first semiconductor substrate; and a second semiconductor chip, bonded to the first semiconductor chip, the second semiconductor chip comprising: a second semiconductor substrate, having a third surface and a fourth surface opposite to each other, the fourth surface facing the first surface of the first semiconductor substrate; a second semiconductor element layer and a second wiring structure, formed on the third surface of the second semiconductor substrate; and a second backside bonding pad, on the fourth surface of the second semiconductor substrate, the second backside bonding pad being bonded to the first frontside bonding pad of the first semiconductor chip, The first semiconductor chip and the second semiconductor chip are directly combined together without any gap between the first semiconductor chip and the second semiconductor chip, and The first test pad of the first semiconductor chip is not electrically connected to the second semiconductor chip.

2. The semiconductor package according to claim 1, wherein: The first connection pad and the first test pad protrude from the first wiring structure.

3. The semiconductor package according to claim 1, wherein: The top surface of the first front side bonding pad is arranged in the same plane as the top surface of the first semiconductor chip.

4. The semiconductor package according to claim 1, further comprising: A first liner film, a second interlayer insulating film, and a second liner film are stacked on the first interlayer insulating film, The first front side bonding pad is connected to the first connection pad through the second liner film, the second interlayer insulating film, the first liner film, the first interlayer insulating film and the first passivation film.

5. The semiconductor package according to claim 4, wherein: A portion of the second interlayer insulating film is disposed in the test pad opening.

6. The semiconductor package according to claim 5, wherein: The top surface of the first front side bonding pad and the top surface of the second liner film are arranged in the same plane.

7. The semiconductor package according to claim 4, further comprising: A first dummy pad is formed in the test pad opening and is connected to the first test pad through the first interlayer insulating film and the first passivation film.

8. The semiconductor package according to claim 7, wherein: A top surface of the first dummy pad and a top surface of the first liner film are disposed on the same plane.

9. The semiconductor package according to claim 4, further comprising: A second backside insulating film is formed on the fourth surface of the second semiconductor substrate and bonded to the second liner film.

10. The semiconductor package according to claim 9, wherein: The second rear side insulating film surrounds the second rear side bonding pad.

11. The semiconductor package according to claim 1, further comprising: A first back-side insulating film is formed on the second surface of the first semiconductor substrate.

12. The semiconductor package according to claim 11, wherein The first rear side insulating film surrounds the first rear side bonding pad.

13. A semiconductor package, comprising: A base substrate, comprising: a base semiconductor substrate having a top surface and a bottom surface opposite to each other; a first base pad formed on the top surface of the base semiconductor substrate; a second base pad formed on the bottom surface of the base semiconductor substrate; a base through-via hole penetrating the base semiconductor substrate to connect the first base pad and the second base pad; and an insulating film formed on the top surface of the base semiconductor substrate and surrounding the first base pad; and A plurality of semiconductor chips are sequentially stacked on a base substrate, each of the plurality of semiconductor chips comprising: a semiconductor substrate having a first surface facing a top surface of the base substrate and a second surface opposite to the first surface; a semiconductor element layer formed on the first surface of the semiconductor substrate; a wiring structure formed on the semiconductor element layer, the wiring structure comprising an inter-wiring insulating film and a wiring pattern provided in the inter-wiring insulating film; a connection pad and a test pad connected to the wiring pattern and protruding from the wiring structure; and a front side bonding pad connected to the connection pad, wherein the front side bonding pad of a first semiconductor chip among the plurality of semiconductor chips is connected to a first base pad of the base substrate, and The base substrate and the first semiconductor chip are directly combined together, and there is no gap between the base substrate and the first semiconductor chip.

14. The semiconductor package according to claim 13, wherein: Each of the plurality of semiconductor chips further comprises: a passivation film formed on the wiring structure, the connection pad, and the test pad; and The first interlayer insulating film is formed on the passivation film.

15. The semiconductor package according to claim 14, wherein: Each of the plurality of semiconductor chips further includes a first liner film, a second interlayer insulating film, and a second liner film stacked on the first interlayer insulating film, and The front side bonding pad is connected to the connection pad through the second liner film, the second interlayer insulating film, the first liner film, the first interlayer insulating film and the passivation film.

16. The semiconductor package according to claim 15, wherein: Part of the second interlayer insulating film is in direct contact with the test pad.

17. The semiconductor package according to claim 16, wherein: The surface of the front side bonding pad and the surface of the second liner film are arranged in the same plane.

18. The semiconductor package according to claim 15, further comprising: The dummy pad is connected to the test pad through the first interlayer insulating film and the passivation film.

19. The semiconductor package according to claim 18, wherein: The surface of the dummy pad and the surface of the first liner film are arranged on the same plane.

20. The semiconductor package according to claim 13, wherein Each of the plurality of semiconductor chips further comprises: A back-side insulating film is formed on the second surface of the semiconductor substrate.

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