Recessed gate HEMT processing with reverse etch

Abstract

The invention relates to recessed gate HEMT processing with reverse etch. A process forms a high electron mobility transistor (HEMT) device having a recessed gate without damaging a sensitive region of the HEMT device. The process utilizes a first epitaxial growth process to grow a first set of layers of the HEMT. The epitaxial growth process is then stopped and a passivation layer is formed on the first set of layers. The passivation layer is then patterned to provide a passivation structure at a desired location of the recessed gate electrode. A channel layer and one or more barrier layers are then formed in a second epitaxial growth process in the presence of a passivation structure. The result is that the channel layer and the barrier layer are grown around the passivation structure. The passivation structure is then removed, thereby effectively leaving a recess in the channel layer. A gate electrode is then formed in the recess.

Description

Technical Field

[0001] The present disclosure relates to field effect high electron mobility transistor (HEMT) devices and processes for manufacturing the same. Background Art

[0002] HEMT devices are known in which the conducting channel is based on the formation of a two-dimensional electron gas (2DEG) layer with high mobility at a heterojunction, i.e. at the interface between semiconductor materials with different band gaps. For example, HEMT devices are known based on a heterojunction between an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer.

[0003] HEMT devices based on AlGaN / GaN heterojunctions or heterostructures offer several advantages that make them particularly suitable and widely used in different applications. For example, the high breakdown threshold of HEMT devices is used for high-performance power switching; the high electron mobility in the conducting channel allows for high-frequency amplifiers; and the high electron concentration in the 2DEG allows for low on-resistance (R ON ). In addition, HEMT devices used in radio frequency (RF) applications generally provide better RF performance than similar silicon LDMOS devices.

[0004] Some HEMT devices may include a recessed gate. However, the process used to form the recessed gate may cause damage to sensitive layers. This may result in poor device function or even inoperability of the device.

[0005] All subject matter discussed in the background section is not necessarily prior art, and should not be assumed to be prior art simply because it is discussed in the background section. Therefore, any recognition of a problem existing in the prior art discussed in the background section or related to such subject matter should not be considered prior art unless it is explicitly stated to be prior art. Instead, the discussion of any subject matter in the background section should be considered as part of the inventor's approach to solving a particular problem, which itself may also be inventive. Summary of the invention

[0006] Embodiments of the present disclosure provide a HEMT device having a recessed gate without damaging the sensitive areas of the HEMT device. Embodiments of the present disclosure implement a first epitaxial growth process to grow a first set of layers of the HEMT. The epitaxial growth process is then stopped and a passivation layer is formed on the first set of layers. The passivation layer is then patterned to provide a passivation structure at the desired location of the recessed gate electrode. A channel layer and one or more barrier layers are then formed in a second epitaxial growth process in the presence of the passivation structure. The result is that the channel layer and barrier layer grow around the passivation structure. The passivation structure is then removed, effectively leaving a recess in the channel layer. A gate electrode is then formed in the recess. The result of this process is the formation of a recessed gate electrode without damaging the channel layer in the back barrier layer.

[0007] In one embodiment, a method includes depositing a back barrier layer of a HEMT using a first epitaxial growth process, and depositing a passivation layer on the back barrier layer. The method includes forming a passivation residue on the back barrier layer by patterning the passivation layer, and depositing a channel layer and a barrier layer of the HEMT on the back barrier layer by performing a second epitaxial growth process in the presence of the passivation residue. The method includes forming a recess in the channel layer by removing the passivation residue, and forming a gate electrode of the HEMT in the recess.

[0008] In one embodiment, a method includes depositing a back barrier layer of a high electron mobility transistor (HEMT) using a first epitaxial growth process, and depositing a first portion of a channel layer of the HEMT on the back barrier layer using the first epitaxial growth process. The method includes depositing a passivation layer on the first portion of the channel layer, and forming a passivation residue on the first portion of the channel layer by patterning the passivation layer. The method includes depositing a second portion of the channel layer and a barrier layer of the HEMT on the first portion of the channel layer by performing a second epitaxial growth process in the presence of the passivation residue, removing the passivation residue, and forming a gate electrode of the HEMT in a recess.

[0009] In one embodiment, a method includes forming a gallium nitride layer in a first epitaxial growth process and forming a dielectric structure on the gallium nitride layer. The method includes forming a channel layer of a HEMT on the gallium nitride layer in the presence of the dielectric structure in a second epitaxial growth process after forming the dielectric structure, wherein a sidewall of the channel layer abuts the dielectric structure. The method includes removing the dielectric structure after forming the channel layer and forming a gate electrode of the HEMT at the location of the dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A-1G is a cross-sectional view of a single transistor at various stages in forming a HEMT according to one embodiment.

[0011] Figure 2A-2F is a cross-sectional view of a single transistor at various stages in forming a HEMT according to one embodiment.

[0012] Figure 3A-Figure 3F is a cross-sectional view of a single transistor at various stages in forming a HEMT according to one embodiment.

[0013] Figure 4 is a flow chart of a method for forming a HEMT according to one embodiment.

[0014] Figure 5 is a flow chart of a method for forming a HEMT according to one embodiment.

[0015] Figure 6 is a flow chart of a method for forming a HEMT according to one embodiment. DETAILED DESCRIPTION

[0016] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, one skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known systems, components, and circuit systems associated with integrated circuits are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0017] Unless the context requires otherwise, throughout the specification and the appended claims, the word "comprise" and variations thereof, such as "include" and "including", are to be interpreted in an open, inclusive sense, i.e., "including but not limited to". In addition, the terms "first", "second" and similar sequential indicators are to be interpreted as interchangeable unless the context clearly dictates otherwise.

[0018] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0019] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally used in its broadest sense, that is, to mean "and / or" unless the content clearly dictates otherwise.

[0020] Figure 1A-1G According to one embodiment, when forming the HEMT 101 (see Figure 1G ) is a cross-sectional view of a single transistor 100 at various stages of the process.

[0021] exist Figure 1A In one embodiment, a single transistor 100 includes a substrate 102. The substrate 102 may include a semiconductor material. In one embodiment, the substrate 102 includes silicon. However, the substrate 102 may include other types of semiconductor materials or crystals, such as sapphire, silicon carbide, aluminum nitride. In some embodiments, the substrate 102 may include one or more layers of dielectric material. The substrate 102 may include other materials suitable for forming a HEMT.

[0022] exist Figure 1A In one embodiment, a first epitaxial growth process has been performed to form a stack of layers 104. During the first epitaxial growth process, the stack of layers is epitaxially grown from substrate 102. The individual separate layers can be formed by adjusting the parameters of the epitaxial growth process in situ. For example, the epitaxial growth process can include flowing one or more gases or other materials into a deposition chamber where a single transistor 100 (which at this stage is part of a semiconductor wafer) is located. The temperature, pressure, and materials can be adjusted throughout the epitaxial growth process to form the various layers of stack 104. In some cases, when one layer of stack 104 is completed, a purge process can be performed to purge any excess gas or byproducts in the deposition chamber before starting the growth of the next layer.

[0023] In one embodiment, a first epitaxial growth process forms a layer 106 on the substrate 102. In one embodiment, the layer 106 comprises aluminum nitride. The aluminum nitride layer 106 may be formed as a precursor to forming multiple gallium nitride layers. Aluminum nitride may be selected as the first layer because gallium may damage the substrate 102, especially when the substrate 102 comprises silicon. Thus, the epitaxial growth process first forms the aluminum nitride layer 106 so that the gallium nitride layer can be subsequently formed. Alternatively, other materials may be used for the layer 106 and subsequent layers without departing from the scope of the present disclosure.

[0024] After forming layer 106, superlattice 108 is formed on layer 106 during a first epitaxial growth process. Superlattice 108 is formed on layer 106. Figure 1A 108 is shown as a single layer. However, in practice, superlattice 108 may include a large number of layers. In the example where layer 106 is aluminum nitride and subsequent layers of gallium nitride are to be formed, the first layer of superlattice 108 may include an aluminum gallium nitride layer in which the percentage of aluminum is high and the percentage of gallium is low to enable epitaxial growth from the aluminum nitride layer. Subsequent layers of superlattice 108 include aluminum gallium nitride in which the concentration of gallium increases and the concentration of aluminum decreases. Finally, the top layer of superlattice 108 may include gallium nitride without any aluminum. Superlattice 108 may include up to 200 layers. Superlattice 108 may include other materials and structures without departing from the scope of the present disclosure.

[0025] After forming the superlattice 108, a layer 110 is formed on top of the superlattice 108. In an example where the superlattice 108 is a transition structure including multiple layers that gradually transition from aluminum nitride to gallium nitride, the layer 110 may include gallium nitride. In one embodiment, the gallium nitride layer 110 includes a P-type dopant. In one embodiment, the gallium nitride layer 110 is doped with carbon atoms. The total thickness of the layer 110 may be about 2 μm. The total thickness of the superlattice 108 may also be about 2 μm. The composition of the layers 110 and 108 may facilitate the formation of a HEMT device that can operate at very high voltages. For example, the composition of the layers 110 and 108 may facilitate the HEMT device to operate at more than 600V between the terminals of the HEMT device. Other materials, thicknesses, and operating voltages may be used without departing from the scope of the present disclosure.

[0026] After forming layer 110, a back barrier layer 112 is formed on layer 110 using a first epitaxial growth process. In an example where layer 110 includes carbon-doped gallium nitride, back barrier layer 112 may include gallium nitride. Gallium nitride back barrier layer 112 may be doped with P-type atoms. In one example, back barrier layer 112 may be doped with magnesium atoms. The thickness of back barrier layer 112 may be between 50 nm and 300 nm. Other materials and thicknesses may be used for back barrier layer 112 without departing from the scope of the present disclosure. In addition, as will be explained below, in some embodiments, back barrier layer 112 may not exist.

[0027] exist Figure 1B In the embodiment, the first epitaxial growth process has been stopped. After the first epitaxial growth process has been stopped, a passivation layer 114 is formed on the layer stack 104. Figure 1B In the example of FIG. 1 , the passivation layer 114 is formed directly on the top surface of the back barrier layer 112. The passivation layer 114 may include a dielectric material having a thickness between 200 nm and 400 nm, however, other thicknesses may be utilized without departing from the scope of the present disclosure.

[0028] In one embodiment, the passivation layer 114 includes silicon oxide. The silicon oxide can be formed using an atomic layer deposition (ALD) process. The passivation layer can also include a tetraethyl orthosilicate (TEOS) layer on the silicon oxide. TEOS can be formed by CVD, ALD, or other suitable deposition processes. Other processes and materials can be utilized without departing from the scope of the present disclosure.

[0029] exist Figure 1CIn the embodiment of the present invention, the passivation layer 114 is patterned to form a dielectric structure 116 on the back barrier layer 112. The dielectric structure 116 corresponds to the passivation residue or the residue of the passivation layer 114. In particular, the passivation layer 114 can be patterned using a photolithography process to remove the passivation layer 114 except for the portion corresponding to the dielectric structure 116. In one embodiment, the patterning process can include forming a mask on the passivation layer 114, and then performing a wet or dry etch in the presence of the mask to remove the portion of the passivation layer 114 not covered by the mask. This leaves the dielectric structure 116. After the wet or dry etching process, a wet treatment can then be performed to repair any damage to the back barrier layer 112 that may have occurred during the wet or dry etching process. Other processes for forming the dielectric structure 116 can be utilized without departing from the scope of the present disclosure. As will be explained in more detail below, the dielectric structure 116 is positioned at the location of the recess where the gate electrode of the HEMT device will be formed.

[0030] exist Figure 1D According to one embodiment, a second epitaxial growth process is performed in the presence of the dielectric structure 116. The second epitaxial growth process forms the channel layer 118 and the barrier layer 120.

[0031] In one embodiment, channel layer 118 is gallium nitride and has a thickness between 50 nm and 150 nm. In one embodiment, channel layer 118 is intrinsic gallium nitride and does not include any doping. Channel layer 118 corresponds to a layer that forms an electron gas during operation of the transistor. Free electrons flow through the channel region based on the bias between the source and drain electrodes and the control voltage applied to the gate electrode, as will be described in more detail below. The channel layer may have other materials and thicknesses without departing from the scope of the present disclosure.

[0032] In one embodiment, barrier layer 120 includes aluminum gallium nitride. The percentage of aluminum can be between 15% and 30%, but other compositions can be utilized without departing from the scope of the present disclosure. Barrier layer 120 can have a thickness between 30nm and 70nm. Other compositions and thicknesses can be utilized for barrier layer 120 without departing from the scope of the present disclosure.

[0033] Because dielectric structure 116 does not share the crystal structure of back barrier layer 112, the epitaxial growth process does not cause gallium nitride or aluminum gallium nitride to grow from dielectric structure 116. Thus, layers 118 and 120 are not grown on top of dielectric structure 116. Layers 118 and 120 are located over the sidewalls of dielectric structure 116.

[0034] exist Figure 1DIn the embodiment of the present invention, a dielectric cap layer 122 is also formed on layer 120. Dielectric layer 122 may include silicon nitride and may have a thickness between 20 nm and 50 nm. Other materials and thicknesses may be utilized without departing from the scope of the present disclosure.

[0035] exist Figure 1E In the embodiment of the present invention, an etching process is performed to remove dielectric structure 116, thereby effectively leaving recess 126 and channel layer 118, barrier layer 120 and dielectric cap layer 122. As will be explained in more detail below, recess 126 corresponds to the location where the gate electrode of the HEMT will be formed. The etching process selectively etches the material of dielectric structure 116 relative to the material of channel layer 118, barrier layer 120 and dielectric cap layer 122. Because the etching process does not etch the material of layers 112, 118 and 120, there is little or no damage to layers 112, 118 and 120.

[0036] about Figure 1A-1E The process for forming the gate recess 126 shown in FIG. 1 is in contrast to other possible solutions for forming the gate recess in the channel layer 118 and the barrier layer 120. For example, in another possible solution, the dielectric structure is not formed, but the gate recess is formed by masking and etching the barrier layer 120 and the channel layer 118. However, a problem with this possible solution is that the etching process also partially etches the back barrier layer 112 or otherwise damages the back barrier layer 112 and the sidewalls of the layers 120 and 118. Advantageously, with respect to FIG. 1 , the gate recess 126 is formed by masking and etching the barrier layer 120 and the channel layer 118. Figure 1A-1E The process described forms gate recess 126 by growing channel layer 118 and barrier layer 120 in the presence of dielectric structure 116. The wet etch that removes dielectric structure 116 causes little or no damage to back barrier layer 112 because the etch chemistry used to remove the material of dielectric structure 116 does not match the materials of layers 112, 118, and 120.

[0037] exist Figure 1F In one embodiment, a gate electrode 128 is formed in the gate recess 126. The gate electrode 128 may include a gate dielectric 130 and a gate metal 132. The gate dielectric 130 contacts the back barrier layer 112, the sidewalls of the layers 118, 120 and 122, and the top surface of the layer 122. The gate dielectric 130 may include aluminum oxide (aluminum oxide) or other suitable materials such as AlN, SiN, SiO2. The gate dielectric 130 may be deposited by ALD, CVD, PVD or other suitable deposition processes. The gate dielectric 130 may have a thickness between 10 nm and 50 nm. Other thicknesses and materials may be utilized for the gate dielectric 130 without departing from the scope of the present disclosure.

[0038] The gate metal 132 fills the remaining portion of the gate recess 126. In particular, the gate metal 132 contacts the gate metal 132 in the gate recess 126 and on the top of the dielectric cap layer 122. The gate metal 132 may include tungsten and may be deposited by PVD, ALD, CVD, or other suitable deposition processes. The gate metal 132 may include other materials and configurations without departing from the scope of the present disclosure. For example, although the gate metal 132 is shown as a single gate metal, in practice, there may be multiple gate metals.

[0039] First, a gate dielectric 130 and a gate metal 132 may be deposited on the entire top surface of the dielectric cap layer 122. Thereafter, a photolithography and etching process may be performed to pattern the gate electrode 128, such as Figure 1F The gate electrode 128 may have other configurations without departing from the scope of the present disclosure.

[0040] exist Figure 1G In accordance with one embodiment, a source electrode 134 and a drain electrode 136 are formed. The source electrode 134 and the drain electrode 136 may be formed after the gate electrode 128 is formed. In particular, a photolithography process may be performed to form a trench that partially extends into the channel layer 118. A source / drain metal may then be deposited and patterned to form the source electrode 134 and the drain electrode 136. The source / drain metal may include TiAl, TaAl, Au, or other suitable conductive materials. The source / drain metal may be deposited by PVD, ALD, CVD, or other suitable deposition processes. As can be seen, the source electrode 134 is closer to the gate electrode 128 than the drain electrode 136. This may be beneficial to the electrical function of the HEMT 101.

[0041] The HEMT 101 may include various other layers, including passivation layers and other dielectric layers, to isolate and protect the source / drain metals from the gate electrode 128. The HEMT may be operated by applying a control voltage to the gate electrode 128 and biasing the source electrode 134 and the drain electrode 136. Depending on the control and bias voltages, the HEMT may be turned on or off. When the HEMT is turned on, the current of the electron gas may flow through the channel layer 118 and through the bottom of the gate electrode 128 between the drain electrode 136 and the source electrode 134.

[0042] Figure 2A-2F is a cross-sectional view of integrated circuit 100 at various stages of forming HEMT 101 according to one embodiment. Figure 2A-2F The HEMT 101 process is similar in many ways to the Figure 1A-1G The procedures shown are essentially similar. Unless otherwise stated, Figure 2A-2F The materials and processes shown can be compared with those Figure 1A-1G The materials and procedures described are essentially similar.

[0043] exist Figure 2A In one embodiment, a first epitaxial growth process has been performed. The first epitaxial growth process forms a stack 104 of layers as described above. However, Figure 2A The epitaxial growth process 104 also forms a first portion 118a of the channel layer. This may be beneficial for embodiments where the gate recess does not extend through the entire channel layer 118, as will be explained in more detail below.

[0044] exist Figure 2B In one embodiment, a passivation layer 114 is formed on the first portion 118a of the channel layer. Figure 2C In accordance with one embodiment, the passivation layer 114 is patterned to form a dielectric structure 116 on a top surface of the first portion 118a of the channel layer.

[0045] exist Figure 2D In one embodiment, a second epitaxial growth process is performed in the presence of the dielectric structure 116. The second epitaxial growth process forms the second portion 118b of the channel layer and the barrier layer 120. A dielectric cap layer 122 is also formed. The first portion 118a of the channel layer and the second portion 118b of the channel layer are the same material. Although the first portion 118a of the channel layer and the second portion 118b of the channel layer are Figure 2D They are shown as different layers in FIG. 1 , but in reality, they form a single channel layer 118 after the second epitaxial growth process.

[0046] exist Figure 2E In one embodiment, an etching process is performed to form a gate recess 126. The etching process removes the dielectric structure 116. The bottom of the gate recess 126 corresponds to the top of the first portion 118a of the channel layer. The second portion 118b of the channel layer, the barrier layer 120, and the sidewalls of the dielectric cap layer 122 are exposed in the gate recess 126.

[0047] exist Figure 2F In accordance with one embodiment, gate electrode 128, source electrode 134, and drain electrode 136 are formed. Gate dielectric 130 contacts the sidewalls of second portion 118b of channel layer, barrier layer 120, and dielectric cap layer 122. Processing of HEMT 101 is substantially complete.

[0048] Figure 3A-Figure 3F is a cross-sectional view of integrated circuit 100 at various stages of forming HEMT 101 according to one embodiment. Figure 3A-Figure 3F The HEMT 101 process is similar in many ways to the Figure 1A-1GThe procedures shown are essentially similar. Unless otherwise stated, Figure 3A-Figure 3F The materials and processes shown can be compared with those Figure 1A-1G The materials and procedures described are essentially similar.

[0049] exist Figure 3A In one embodiment, a first epitaxial growth process has been performed. The first epitaxial growth process forms a stack 104 of layers as described above. However, Figure 3A The epitaxial growth process does not form the back barrier layer 112. Figure 3A-Figure 3F In an embodiment of the present invention, the HEMT 101 does not include a back barrier layer.

[0050] exist Figure 3B In one embodiment, a passivation layer 114 is formed on layer 110. Figure 3C In accordance with one embodiment, the passivation layer 114 is patterned to form a dielectric structure 116 on a top surface of the layer 110 .

[0051] exist Figure 3D In one embodiment, a second epitaxial growth process is performed in the presence of dielectric structure 116. The second epitaxial growth process forms channel layer 118 and barrier layer 120. A dielectric cap layer 122 is also formed.

[0052] exist Figure 3E In one embodiment, an etching process is performed to form gate recess 126. The etching process removes dielectric structure 116. The bottom of gate recess 126 corresponds to the top of layer 110. Sidewalls of channel layer 118, barrier layer 120, and dielectric cap layer 122 are exposed in gate recess 126.

[0053] exist Figure 3F In accordance with one embodiment, gate electrode 128, source electrode 134, and drain electrode 136 are formed. Gate dielectric 130 contacts the top surface of layer 110 and the sidewalls of channel layer 118, barrier layer 120, and dielectric cap layer 122. Processing of HEMT 101 is substantially complete.

[0054] Figure 4 4 is a flow chart of a method 400 for forming a HEMT device according to one embodiment. The method 400 may utilize Figure 1A-Figure 3FThe method 400 includes depositing a back barrier layer of the HEMT using a first epitaxial growth process. At 404, the method 400 includes depositing a passivation layer on the back barrier layer. At 406, the method 400 includes forming a passivation residue on the back barrier layer by patterning the passivation layer. At 408, the method 400 includes depositing a channel layer and a barrier layer of the HEMT on the back barrier layer by performing a second epitaxial growth process in the presence of the passivation residue. At 410, the method 400 includes forming a recess in the channel layer by removing the passivation residue. At 412, the method 400 includes forming a gate electrode of the HEMT in the recess.

[0055] Figure 5 is a flow chart of a method 500 for forming a HEMT device according to one embodiment. The method 500 may utilize Figure 1A-Figure 3F The method 500 includes depositing a back barrier layer of the HEMT using a first epitaxial growth process. At 504, the method 500 includes depositing a first portion of a channel layer of the HEMT on the back barrier layer using the first epitaxial growth process. At 506, the method 500 includes depositing a passivation layer on the first portion of the channel layer. At 508, the method 500 includes forming a passivation residue on the first portion of the channel layer by patterning the passivation layer. At 510, the method 500 includes depositing a second portion of the channel layer and a barrier layer of the HEMT on the first portion of the channel layer by performing a second epitaxial growth process in the presence of the passivation residue. At 512, the method 500 includes removing the passivation residue. At 514, the method 500 includes forming a gate electrode of the HEMT in the recess.

[0056] Figure 6 6 is a flow chart of a method 600 for forming a HEMT device according to one embodiment. The method 600 may utilize Figure 1A-Figure 3F The method 600 includes forming a gallium nitride layer in a first epitaxial growth process. At 604, the method 600 includes forming a dielectric structure on the gallium nitride layer. At 606, the method 600 includes forming a channel layer of the HEMT on the gallium nitride layer in the presence of the dielectric structure in a second epitaxial growth process after forming the dielectric structure, wherein a sidewall of the channel layer abuts the dielectric structure. At 608, the method 600 includes removing the dielectric structure after forming the channel layer. At 610, the method 600 includes forming a gate electrode of the HEMT in the location of the dielectric structure.

[0057] In one embodiment, a method includes depositing a back barrier layer of a HEMT using a first epitaxial growth process, and depositing a passivation layer on the back barrier layer. The method includes forming a passivation residue on the back barrier layer by patterning the passivation layer, and depositing a channel layer and a barrier layer of the HEMT on the back barrier layer by performing a second epitaxial growth process in the presence of the passivation residue. The method includes forming a recess in the channel layer by removing the passivation residue, and forming a gate electrode of the HEMT in the recess.

[0058] In one embodiment, the method includes depositing a dielectric cap layer on the barrier layer before removing the passivation residue. In one embodiment, forming the gate electrode includes depositing a gate dielectric layer on the sidewalls of the channel layer and the barrier layer in the recess and on the top surface of the dielectric cap layer, patterning the gate dielectric layer, and filling the recess by depositing a gate metal on the liner layer in the recess.

[0059] In one embodiment, a first epitaxial growth process forms an aluminum nitride layer on a semiconductor substrate, forms a superlattice on the aluminum nitride layer, forms a first layer of gallium nitride doped with carbon on the superlattice, and forms a back barrier layer on the first layer of gallium nitride. In one embodiment, the back barrier layer is a second layer of gallium nitride. In one embodiment, the back barrier layer is doped with magnesium. In one embodiment, the channel is a third layer of gallium nitride. In one embodiment, the barrier layer is aluminum gallium nitride. In one embodiment, the method includes forming a source electrode of the HEMT in contact with the channel layer and a drain electrode of the HEMT. The drain electrode is farther from the gate electrode than the source electrode.

[0060] In one embodiment, a method includes depositing a back barrier layer of a high electron mobility transistor (HEMT) using a first epitaxial growth process, and depositing a first portion of a channel layer of the HEMT on the back barrier layer using the first epitaxial growth process. The method includes depositing a passivation layer on the first portion of the channel layer, and forming a passivation residue on the first portion of the channel layer by patterning the passivation layer. The method includes depositing a second portion of the channel layer and a barrier layer of the HEMT on the first portion of the channel layer by performing a second epitaxial growth process in the presence of the passivation residue, removing the passivation residue, and forming a gate electrode of the HEMT in a recess.

[0061] In one embodiment, the method includes depositing a dielectric cap layer on the barrier layer before removing the passivation residue. In one embodiment, forming the gate electrode includes depositing a gate dielectric layer on the sidewalls of the channel layer and the barrier layer in the recess and on the top surface of the dielectric cap layer, patterning the gate dielectric layer, and filling the recess by depositing a gate metal on the liner layer in the recess.

[0062] In one embodiment, removing the passivation residue includes performing a wet etch.

[0063] In one embodiment, the first portion of the channel layer and the second portion of the channel layer are gallium nitride.The first portion of the channel layer and the second portion of the channel layer may include intrinsic gallium nitride.

[0064] In one embodiment, the method includes forming a source electrode of the HEMT and a drain electrode of the HEMT in contact with the channel layer.

[0065] In one embodiment, a method includes forming a gallium nitride layer in a first epitaxial growth process and forming a dielectric structure on the gallium nitride layer. The method includes forming a channel layer of a HEMT on the gallium nitride layer in the presence of the dielectric structure in a second epitaxial growth process after forming the dielectric structure, wherein a sidewall of the channel layer abuts the dielectric structure. The method includes removing the dielectric structure after forming the channel layer and forming a gate electrode of the HEMT in the location of the dielectric structure.

[0066] In one embodiment, forming the dielectric structure includes depositing a dielectric layer on the gallium nitride layer and patterning the dielectric layer. In one embodiment, the channel layer includes gallium nitride.

[0067] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments according to the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents enjoyed by these claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. A method comprising: Depositing a back barrier layer of a high electron mobility transistor (HEMT) by a first epitaxial growth process; depositing a passivation layer on the back barrier layer; forming a passivation residue on the back barrier layer by patterning the passivation layer; depositing a channel layer and a barrier layer of the HEMT on the back barrier layer by performing a second epitaxial growth process in the presence of the passivation residue; forming a recess in the channel layer by removing the passivation residue; as well as A gate electrode of the HEMT is formed in the recess. 2 . The method of claim 1 , comprising depositing a dielectric cap layer on the barrier layer before removing the passivation residue.

3. The method according to claim 2, wherein: Forming the gate electrode comprises: depositing a gate dielectric layer on sidewalls of the channel layer and the barrier layer in the recess and on a top surface of the dielectric cap layer; patterning the gate dielectric layer; and The recess is filled by depositing a gate metal on the liner layer in the recess.

4. The method according to claim 1, wherein: The first epitaxial growth process forms an aluminum nitride layer on a semiconductor substrate, forms a superlattice on the aluminum nitride layer, forms a first layer of gallium nitride doped with carbon on the superlattice, and forms the back barrier layer on the first layer of gallium nitride.

5. The method according to claim 4, wherein: The back barrier layer is a second layer of gallium nitride.

6. The method according to claim 5, wherein: The back barrier layer is doped with magnesium.

7. The method according to claim 6, wherein: The channel layer is a third layer of gallium nitride.

8. The method according to claim 7, wherein: The barrier layer is aluminum gallium nitride. 9 . The method of claim 1 , comprising forming a source electrode of the HEMT and a drain electrode of the HEMT in contact with the channel layer.

10. The method according to claim 9, wherein: The drain electrode is farther from the gate electrode than the source electrode.

11. A method comprising: Depositing a back barrier layer of a high electron mobility transistor (HEMT) by a first epitaxial growth process; depositing a first portion of a channel layer of the HEMT on the back barrier layer using a first epitaxial growth process; depositing a passivation layer on the first portion of the channel layer; forming a passivation residue on a first portion of the channel layer by patterning the passivation layer; depositing a second portion of the channel layer and a barrier layer of the HEMT on the first portion of the channel layer by performing a second epitaxial growth process in the presence of the passivation residue; removing the passivation residue; as well as A gate electrode of the HEMT is formed in the recess.

12. The method of claim 11, comprising depositing a dielectric cap layer on the barrier layer prior to removing the passivation residue.

13. The method according to claim 12, wherein: Forming the gate electrode comprises: depositing a gate dielectric layer on sidewalls of the channel layer and the barrier layer in the recess and on a top surface of the dielectric cap layer; patterning the gate dielectric layer; and The recess is filled by depositing a gate metal on the gate dielectric layer in the recess.

14. The method according to claim 11, wherein: Removing the passivation residue includes performing a wet etch.

15. The method according to claim 11, wherein: The first portion of the channel layer and the second portion of the channel layer are gallium nitride.

16. The method according to claim 15, wherein: The first portion of the channel layer and the second portion of the channel layer include intrinsic gallium nitride. 17 . The method of claim 11 , comprising forming a source electrode of the HEMT and a drain electrode of the HEMT in contact with the channel layer.

18. A method comprising: forming a gallium nitride layer in a first epitaxial growth process; forming a dielectric structure on the gallium nitride layer; After forming the dielectric structure, in a second epitaxial growth process, forming a channel layer of a high electron mobility transistor (HEMT) on the gallium nitride layer in the presence of the dielectric structure, wherein a sidewall of the channel layer is adjacent to the dielectric structure; removing the dielectric structure after forming the channel layer; as well as A gate electrode of the HEMT is formed at the location of the dielectric structure.

19. The method of claim 18, wherein forming the dielectric structure comprises depositing a dielectric layer on the gallium nitride layer and patterning the dielectric layer.

20. The method according to claim 19, wherein: The channel layer includes gallium nitride.

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