Medium voltage transistor structure and manufacturing method thereof

Abstract

A medium voltage transistor structure includes a substrate, a gate structure disposed on the substrate, a source lightly doped region and a drain lightly doped region embedded in the substrate at both sides of the gate structure, a conductive structure contacting the drain lightly doped region, and a gate electrode disposed on the gate structure. A first gap wall surrounds the gate structure and a second gap wall surrounds the conductive structure. The first gap wall contacts the second gap wall.

Description

Technical Field

[0001] The present invention relates to a medium voltage transistor structure, and in particular to a medium voltage transistor structure which reduces the spacing by arranging a conductive structure above a substrate and a manufacturing method thereof. Background Art

[0002] Compared with liquid crystal display panels, organic light emitting diode (OLED) display panels have the advantages of simple manufacturing process, wide viewing angle, low cost, thin thickness, wide operating temperature range and self-luminescence, etc. Therefore, organic light emitting diodes can be used as pixels in display panels and have a trend of gradually replacing liquid crystal display panels.

[0003] As users pursue higher image quality in display devices and the design and manufacturing technology of organic light emitting diode display devices mature, the number of unit pixels on an organic light emitting diode panel increases day by day, so that the spacing between the pixels of the organic light emitting diode needs to be reduced. Summary of the invention

[0004] In view of this, the present invention provides a medium voltage transistor with a reduced pitch, which is particularly suitable for being used as a switch element of an active matrix organic light emitting diode.

[0005] According to a preferred embodiment of the present invention, a medium-voltage transistor structure includes a substrate, a gate structure arranged on the substrate, a source lightly doped region and a drain lightly doped region buried in the substrate on both sides of the gate structure, a conductive structure contacting the drain lightly doped region, a first spacer surrounding the gate structure and a second spacer surrounding the conductive structure, wherein the first spacer contacts the second spacer.

[0006] According to another preferred embodiment of the present invention, a layout of a medium voltage transistor includes a substrate, wherein the substrate includes an active region and a shallow trench isolation surrounding the active region, wherein the active region includes four corners, a gate structure is arranged on the substrate, the gate structure extends along a first direction, the gate structure and the active region are staggered and cover the shallow trench isolation, and a conductive structure is arranged on one side of the gate structure, the conductive structure extends along the first direction, wherein the conductive structure covers the shallow trench isolation and covers the four corners of one of the active regions.

[0007] According to another preferred embodiment of the present invention, a method for manufacturing a medium-voltage transistor structure includes providing a substrate, then forming a source lightly doped region and a drain lightly doped region buried in the substrate, and then forming a medium-voltage dielectric layer between the source lightly doped region and the drain lightly doped region, and then simultaneously forming a first polysilicon layer and a second polysilicon layer, wherein the first polysilicon layer and the medium-voltage dielectric layer overlap, and the second polysilicon layer covers a portion of the drain lightly doped region, and finally forming a first spacer and a second spacer, wherein the first spacer surrounds the first polysilicon layer and the medium-voltage dielectric layer, the second spacer surrounds the second polysilicon layer, and the first spacer contacts the second spacer.

[0008] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 4 A schematic diagram of a method for manufacturing a medium voltage transistor structure according to a first preferred embodiment of the present invention;

[0010] Figures 5 and 6 A schematic diagram of a method for manufacturing a medium voltage transistor structure according to a second preferred embodiment of the present invention;

[0011] Figure 7 A schematic diagram of a layout of a medium voltage transistor according to a preferred embodiment of the present invention;

[0012] Figure 8 A schematic diagram of a layout of a medium voltage transistor according to another preferred embodiment of the present invention;

[0013] Fig. 9 A schematic diagram of a layout of a medium voltage transistor structure according to another preferred embodiment of the present invention;

[0014] Fig.10 A schematic diagram of a layout of a medium voltage transistor according to another preferred embodiment of the present invention is shown.

[0015] Main component symbols

[0016] 10: Base

[0017] 12: Shallow Trench Isolation

[0018] 14: Mask layer

[0019] 16: Source lightly doped region

[0020] 18: Drain lightly doped region

[0021] 20: Medium voltage dielectric layer

[0022] 22: Low voltage dielectric layer

[0023] 24a: first polysilicon layer

[0024] 24b: second polysilicon layer

[0025] 26a: first spacer

[0026] 26b: Second spacer

[0027] 26c: The third spacer

[0028] 28: Source doping region

[0029] 30a: first metal silicide

[0030] 30b: Second metal silicide

[0031] 30c: third metal silicide

[0032] 32a: first conductive plug

[0033] 32b: second conductive plug

[0034] 32c: third conductive plug

[0035] 34a: Corner

[0036] 34b: Angle

[0037] 34c: Angle

[0038] 34d: Angle

[0039] 100: Medium voltage transistor structure

[0040] 200: Medium voltage transistor structure

[0041] 300:Layout

[0042] 400:Layout

[0043] 500:Layout

[0044] 600:Layout

[0045] A: Active area

[0046] C: Conductive structure

[0047] DC: Virtual conductive structure

[0048] G: Gate structure

[0049] ILD: Interlayer Dielectric DETAILED DESCRIPTION

[0050] Figures 1 to 4 A method for manufacturing a medium voltage transistor structure is shown in accordance with a first preferred embodiment of the present invention.

[0051] like Figure 1 As shown, a substrate 10 is first provided, and a shallow trench isolation 12 is disposed on the substrate 10. The shallow trench isolation 12 defines an active region A on the substrate 10. Then, a mask layer 14 is formed to cover the active region A of the substrate 10. The position of the mask layer 14 will be used as the position of the gate structure of the medium voltage transistor in the future. Then, an ion implantation process is performed using the mask layer 14 as a mask to form a source lightly doped region 16 and a drain lightly doped region 18 buried in the substrate 10 on both sides of the mask layer 14.

[0052] like Figure 2 As shown, the mask layer 14 is removed, and then a medium-voltage dielectric layer 20 is formed to at least cover the surface of the substrate 10 between the source lightly doped region 16 and the drain lightly doped region 18, and a low-voltage dielectric layer 22 is formed to at least cover a portion of the drain lightly doped region 18 and a portion of the shallow trench isolation 12. The medium-voltage dielectric layer 20 can be formed by a deposition process to form a medium-voltage material layer, and the medium-voltage material layer includes materials such as silicon oxide and silicon oxynitride. The formation method of the low-voltage dielectric layer 22 includes an oxidation manufacturing process or a deposition manufacturing process. For example, a low-voltage material layer is first formed by a deposition manufacturing process, and the low-voltage material layer includes silicon oxide. Then, a polysilicon layer is fully formed to cover the active area A of the substrate 10. The polysilicon layer, the medium-voltage material layer and the low-voltage material layer are patterned to simultaneously form a first polysilicon layer 24a and a second polysilicon layer 24b. After the medium-voltage material layer is patterned, the remaining medium-voltage material layer serves as the medium-voltage dielectric layer 20. After the low-voltage material layer is patterned, the remaining low-voltage material layer serves as the low-voltage dielectric layer 22, wherein the first polysilicon layer 24a and the medium-voltage dielectric layer 20 overlap, and the second polysilicon layer 24b and the low-voltage dielectric layer 22 overlap, that is, the second polysilicon layer 24b covers part of the drain lightly doped region 18.

[0053] like Figure 3As shown, a spacer material layer (not shown) is formed to cover the substrate 10, the first polysilicon layer 24a and the second polysilicon layer 24b, and then the spacer material layer is etched to form a first spacer 26a and a second spacer 26b, the first spacer 26a surrounds the first polysilicon layer 24a and the medium voltage dielectric layer 20, and the second spacer 26b surrounds the second polysilicon layer 24b and the low voltage dielectric layer 22. It is worth noting that the first spacer 26a directly above the drain lightly doped region 18 contacts the second spacer 26b, that is, the drain lightly doped region 18 is covered by the first polysilicon layer 24a, the second polysilicon layer 24b, the first spacer 26a and the second spacer 26b. Next, an ion implantation process is performed using the first polysilicon layer 24a, the second polysilicon layer 24b, the first spacer 26a and the second spacer 26b as masks to form a source doped region 28 in the source lightly doped region 16.

[0054] like Figure 4 As shown, a metal silicide manufacturing process is performed using the first spacer 26a and the second spacer 26b as masks to transform a portion of the first polysilicon layer 24a into a first metal silicide 30a, a portion of the second polysilicon layer 24b into a second metal silicide 30b, and a portion of the source doping region 28 into a third metal silicide 30c, and then an interlayer dielectric layer ILD is formed to cover the substrate 10, and then a first conductive plug 32a and a second conductive plug 32b are formed. A third conductive plug 32c is located in the dielectric layer ILD, the first conductive plug 32a contacts the first metal silicide 30a, the second conductive plug 32b contacts the second metal silicide 30b, and the third conductive plug 32c contacts the third metal silicide 30c, and then a current is formed between the source doped region 28, the source lightly doped region 16, and the second polysilicon layer 24b at 8 to 10 volts to destroy the low-voltage dielectric layer 22. At this time, the medium-voltage transistor structure 100 of the present invention has been completed. Because 8 to 10 volts is a voltage that exceeds the low-voltage dielectric layer 22 can withstand, the low-voltage dielectric layer 22 will be broken down and its resistance will drop rapidly, so the low-voltage dielectric layer 22 becomes a conductor. When the medium-voltage transistor structure 100 is subsequently operated, the current can flow between the source doped region 28, the substrate 10, the low-voltage dielectric layer 22, and the second polysilicon layer 24b.

[0055] Figures 5 and 6 A method for manufacturing a medium voltage transistor structure according to a second preferred embodiment of the present invention is shown, wherein components having the same function and position will use the same component numbers as those in the first preferred embodiment.

[0056] Figure 5 To continue Figure 1 The difference between the second preferred embodiment and the first preferred embodiment is that the first preferred embodiment Figure 2In the second preferred embodiment, the low voltage dielectric layer 22 is formed. Figure 5 In the embodiment, no low voltage dielectric layer is formed, and the second polysilicon layer 24b is directly formed to cover and contact the drain lightly doped region 18. Figure 6 As shown, the first spacer 26a, the second spacer 26b, the source doping region 28, the first metal silicide 30a, the second metal silicide 30b, the third metal silicide 30c, the interlayer dielectric layer ILD, the first conductive plug 32a, the second conductive plug 32b and the third conductive plug 32c, the formation method of the above elements is the same as that described in the first preferred embodiment, and no further description is given here, so that the medium voltage transistor structure 200 of the present invention has been completed. Since the medium voltage transistor structure 200 does not have a low voltage dielectric layer, it is not necessary to pre-destroy the low voltage dielectric layer.

[0057] According to a preferred embodiment of the present invention, Figure 4 As shown, a medium voltage transistor structure 100 includes a substrate 10, and the substrate 10 includes a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate, or a silicon-on-insulator substrate. A shallow trench isolation 12 is disposed on the substrate, the shallow trench isolation 12 comprises silicon oxide, and the shallow trench isolation 12 defines an active region A on the substrate, a gate structure G is disposed on the active region A of the substrate 10, a source lightly doped region 16 and a drain lightly doped region 18 are buried in the substrate 10 on both sides of the gate structure G, a source doped region 28 is disposed in the source lightly doped region 16, wherein no drain doped region is disposed in the drain lightly doped region 18, a conductive structure C contacts the drain lightly doped region 18 and the shallow trench isolation 12, a first spacer 26a surrounds the gate structure G, a second spacer 26b surrounds the conductive structure C, the second spacer 26b contacts the drain lightly doped region 18, wherein the first spacer 26a and the second spacer 26b above the drain lightly doped region 18 are combined together. The first spacer 26a and the second spacer 26b preferably comprise insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. The drain lightly doped region 18 , the source lightly doped region 16 and the source doped region 28 contain N-type or P-type dopants. The doping concentrations of the source lightly doped region 16 and the drain lightly doped region 18 are the same, and the doping concentration of the source doped region 28 is greater than that of the source lightly doped region 16 .

[0058] The upper surface of the gate structure G is aligned with the upper surface of the conductive structure C. The gate structure G includes a medium voltage dielectric layer 20, a first polysilicon layer 24a and a first metal silicide 30a arranged from bottom to top. The conductive structure C includes a low voltage dielectric layer 22, a second polysilicon layer 24b and a second metal silicide 30b arranged from bottom to top on the substrate 10. The low voltage dielectric layer 22 contacts the drain lightly doped region 18. The thickness of the medium voltage dielectric layer 20 is greater than the thickness of the low voltage dielectric layer 22. When the medium voltage transistor structure 100 is turned on, current will flow between the source doped region 28, the substrate 10, the drain lightly doped region 18, the low voltage dielectric layer 22 and the conductive structure C.

[0059] According to another preferred embodiment of the present invention, Figure 6 As shown, the difference between the medium-voltage transistor structure 200 and the medium-voltage transistor structure 100 is that there is no low-voltage dielectric layer in the conductive structure of the medium-voltage transistor structure 200, so the second polysilicon layer 24b of the medium-voltage transistor structure 200 is in direct contact with the drain lightly doped region 18, and other components are the same as the medium-voltage transistor structure 100 and will not be repeated here.

[0060] Figure 7 FIG. 1 is a layout of a medium voltage transistor according to a preferred embodiment of the present invention, wherein Figure 4 and Figure 6 Both Figure 7 The side view along the tangent line II' is shown in FIG. Figure 7 For the sake of clarity and simplicity in the illustration, the first metal silicide, the second metal silicide, the third metal silicide, the source lightly doped region, the source doped region, the drain lightly doped region and the interlayer dielectric layer are omitted.

[0061] like Figure 7 As shown, a layout 300 of a medium voltage transistor includes a substrate 10, wherein the substrate includes an active region A and a shallow trench isolation 12 surrounding the active region A, wherein the outline of the active region A includes four corners 34a / 34b / 34c / 34d, a gate structure G is disposed on the substrate 10, the gate structure G extends along a first direction X, the gate structure G and the active region A are staggered, and both ends of the gate structure G cover the shallow trench isolation 12, a conductive structure C is disposed on one side of the gate structure G, the conductive structure C extends along the first direction X, wherein the conductive structure C covers two of the four corners 34a / 34b / 34c / 34d of the active region D and covers the shallow trench isolation 12, that is, the conductive structure C covers one end of the active region A, and in addition, along the first direction X, the length of the conductive structure C is equal to the length of the gate structure G.

[0062] Figure 8FIG. 1 is a layout of a medium voltage transistor according to another preferred embodiment of the present invention, wherein Figure 4 and Figure 6 Both Figure 8 The side view along the J-J' tangent line is shown in FIG. Figure 8 For the sake of clarity and simplicity in the illustration, the first metal silicide, the second metal silicide, the third metal silicide, the source lightly doped region, the source doped region, the drain lightly doped region and the interlayer dielectric layer are omitted.

[0063] Figure 8 and Figure 7 The difference is Figure 8 In the first direction X, the length of the conductive structure C is less than the length of the gate structure G, so the conductive structure C only covers one corner 34b of the four corners 34a / 34b / 34c / 34d of the active region A and covers the shallow trench isolation 12, and Figure 8 The dummy conductive structure DC further includes a dummy conductive structure DC contacting the drain lightly doped region (not shown) and the shallow trench isolation 12. The dummy conductive structure DC and the conductive structure C are arranged on the same side of the gate structure G and the dummy conductive structure DG and the conductive structure C are not connected. The dummy conductive structure DC only covers one corner 34a of the four corners 34a / 34b / 34c / 34d of the active region A and covers the shallow trench isolation 12, and the corner 34a covered by the dummy conductive structure DC is different from the corner 34b covered by the conductive structure C. In addition, the dummy conductive structure DC and the conductive structure C are stacked in the same order with the same material layers, for example Figure 4 The low voltage dielectric layer 22, the second polysilicon layer 24b and the second metal silicide 30b are stacked from bottom to top, or as described above. Figure 6 As described above, the second polysilicon layer 24b and the second metal silicide 30b are stacked from bottom to top. A third spacer 26c surrounds the dummy conductive structure DC, and the third spacer 26c contacts the second spacer 26b and the first spacer 26a.

[0064] Fig. 9 FIG. 1 is a layout of a medium voltage transistor according to another preferred embodiment of the present invention, wherein Figure 4 and Figure 6 Both Fig. 9 The side view along the tangent line K-K' is shown in FIG. Fig. 9 For the sake of clarity and simplicity in the illustration, the first metal silicide, the second metal silicide, the third metal silicide, the source lightly doped region, the source doped region, the drain lightly doped region and the interlayer dielectric layer are omitted.

[0065] Fig. 9 and Figure 8 The difference is Fig. 9In the embodiment, no dummy conductive structure is provided, so the interlayer dielectric layer directly contacts the drain lightly doped region. For the positions of the interlayer dielectric layer and the drain lightly doped region, please refer to Figure 4 or Figure 6 .

[0066] Fig.10 A layout of a medium voltage transistor structure according to another preferred embodiment of the present invention is shown, wherein components having the same function and position will use the same component numbers as those in the first preferred embodiment.

[0067] like Fig.10 As shown, the upper layout 500 is composed of two medium-voltage transistor structures without using a conductive structure, and the lower layout 600 is composed of two medium-voltage transistor structures using a conductive structure. A drain doping region (not shown) is provided in the drain lightly doped region (not shown) of the medium-voltage transistor structure of the layout 500, and the upper surface of the drain doping region is the upper surface of the substrate. The medium-voltage transistor structure of the layout 600 uses a conductive structure C to replace part of the drain doping region. Therefore, compared with the layout 500, the active area A corresponding to the drain doping region in the layout 600 becomes smaller, so the spacing P2 between adjacent medium-voltage transistors in the layout 600 becomes smaller. In addition, in the layout 500 and the layout 600, the distance S between adjacent active areas A is the same. According to a preferred embodiment of the present invention, the spacing of the medium-voltage transistors in the layout 600 is the spacing P2, and the spacing of the medium-voltage transistors in the layout 500 is the spacing P1, and the spacing P2 is 0.85 times the spacing P1.

[0068] The medium voltage transistor structure of the present invention is suitable for any device that requires high density. For example, the medium voltage transistor structure can be used as a semiconductor switch for pixels in an active matrix organic light emitting diode display. Since the medium voltage transistor structure of the present invention has a reduced pitch, it can provide a higher pixel density. In addition, the use of a conductive structure can avoid the leakage problem of the medium voltage transistor structure while reducing the pitch. Furthermore, since the operating current of the organic light emitting diode is extremely small, even if the current of the medium voltage transistor structure is reduced, the organic light emitting diode can still be operated. Therefore, in the above Figure 8 In the embodiment, in order to reduce the leakage current, the length of the conductive structure is shortened, so as to reduce the leakage current by reducing the total current.

[0069] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A medium voltage transistor structure, comprising: substrate; A gate structure is disposed on the substrate; A source lightly doped region and a drain lightly doped region are buried in the substrate on both sides of the gate structure; A conductive structure, contacting the drain lightly doped region; A first spacer surrounds the gate structure; and A second spacer wall surrounds the conductive structure; The first spacer contacts the second spacer.

2. The medium voltage transistor structure as described in claim 1, wherein the gate structure comprises a medium voltage dielectric layer, a first polysilicon layer and a first metal silicide arranged from bottom to top on the substrate, and the conductive structure comprises a second polysilicon layer and a second metal silicide arranged from bottom to top on the substrate, and the second polysilicon layer contacts the drain lightly doped region.

3. The medium-voltage transistor structure as described in claim 1, wherein the gate structure includes a medium-voltage dielectric layer, a first polysilicon layer and a first metal silicide arranged from bottom to top on the substrate, and the conductive structure includes a low-voltage dielectric layer, a second polysilicon layer and a second metal silicide arranged from bottom to top on the substrate, and the low-voltage dielectric layer contacts the drain lightly doped region. 4 . The medium voltage transistor structure as claimed in claim 3 , wherein a thickness of the medium voltage dielectric layer is greater than a thickness of the low voltage dielectric layer. 5 . The medium voltage transistor structure as claimed in claim 1 , wherein an upper surface of the gate structure and an upper surface of the conductive structure are aligned. 6 . The medium voltage transistor structure as claimed in claim 1 , further comprising a source doped region disposed in the source lightly doped region, wherein no drain doped region is disposed in the drain lightly doped region. 7 . The medium voltage transistor structure as claimed in claim 1 , wherein the second spacer contacts the drain lightly doped region.

8. A layout of a medium voltage transistor, comprising: A substrate, wherein the substrate includes an active region and shallow trench isolation surrounds the active region, wherein the active region includes four corners; A gate structure is disposed on the substrate, the gate structure extends along a first direction, the gate structure and the active region are interlaced and cover the shallow trench isolation; and A conductive structure is disposed on one side of the gate structure and extends along the first direction; wherein the conductive structure covers the shallow trench isolation and covers one of the four corners. 9 . The layout of the medium voltage transistor as claimed in claim 8 , further comprising a first spacer surrounding the gate structure and a second spacer surrounding the conductive structure, wherein the first spacer contacts the second spacer. 10 . The layout of the medium voltage transistor as claimed in claim 8 , further comprising: a source lightly doped region and a drain lightly doped region buried in the active region on both sides of the gate structure, and the conductive structure contacts the drain lightly doped region. 11 . The layout of the medium voltage transistor as claimed in claim 8 , wherein along the first direction, a length of the conductive structure is smaller than a length of the gate structure.

12. The layout of the medium voltage transistor as described in claim 11 further includes a dummy conductive structure contacting the drain lightly doped region and the shallow trench isolation, the dummy conductive structure and the conductive structure are arranged on the same side of the gate structure and the dummy conductive structure and the conductive structure are not connected, and the dummy conductive structure covers another one of the four corners. 13 . The layout of the medium voltage transistor as claimed in claim 12 , wherein the dummy conductive structure and the conductive structure are stacked in the same material layer and in the same order. 14 . The layout of the medium voltage transistor as claimed in claim 11 , wherein the conductive structure covers only one of the four corners. 15 . The layout of the medium voltage transistor as claimed in claim 8 , wherein along the first direction, the length of the conductive structure is equal to the length of the gate structure, and the conductive structure covers two of the four corners.

16. A method for manufacturing a medium voltage transistor structure, comprising: providing a substrate; forming a source lightly doped region and a drain lightly doped region buried in the substrate; Forming a medium voltage dielectric layer between the source lightly doped region and the drain lightly doped region; Simultaneously forming a first polysilicon layer and a second polysilicon layer, wherein the first polysilicon layer overlaps the medium voltage dielectric layer, and the second polysilicon layer covers a portion of the drain lightly doped region; and A first spacer and a second spacer are formed, wherein the first spacer surrounds the first polysilicon layer and the medium voltage dielectric layer, the second spacer surrounds the second polysilicon layer, and the first spacer contacts the second spacer.

17. The method for manufacturing a medium voltage transistor structure according to claim 16, further comprising: Using the first polysilicon layer, the second polysilicon layer, the first spacer and the second spacer as masks, an ion implantation process is performed to form a source doped region in the source lightly doped region; A metal silicide manufacturing process is performed to transform a portion of the first polysilicon layer into a first metal silicide, a portion of the second polysilicon layer into a second metal silicide, and a portion of the source doped region into a third metal silicide.

18. The method for manufacturing the medium voltage transistor structure according to claim 16, further comprising: After forming the medium voltage dielectric layer and before forming the second polysilicon layer, a low voltage dielectric layer is formed to cover the drain lightly doped region, wherein the low voltage dielectric layer and the second polysilicon layer overlap.

19. The method for manufacturing a medium voltage transistor structure according to claim 18, further comprising: A current is formed between the source lightly doped region and the second polysilicon layer at 8 to 10 volts to destroy the low voltage dielectric layer. 20 . The method for manufacturing a medium voltage transistor structure as claimed in claim 18 , wherein a thickness of the medium voltage dielectric layer is greater than a thickness of the low voltage dielectric layer.

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