Terminal structure of SGT device

Abstract

The invention discloses a terminal structure of an SGT device. First grooves in a primitive cell region are arranged in parallel. The terminal area surrounds the peripheral side of the primitive cell area, and first terminal structures in the first direction terminal areas on the two sides of the arrangement direction of the first grooves comprise second groove structures formed by second shielding dielectric layers and second shielding conductive material layers, wherein the second shielding dielectric layers are filled in second grooves parallel to the first grooves, and the second groove structures are connected with the source electrodes; a second termination structure in the second direction termination region includes a first trench extension structure and a plurality of floating regions formed in the drift region surface region. According to the invention, the withstand voltage of the terminal area can be improved, the process difficulty can be reduced, and the process window is improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a terminal structure of a shielded gate trench (SGT) device. Background Art

[0002] Compared with the traditional trench MOSFET, the SGT MOSFET adds a source field plate in the drift region 2. By utilizing the source field plate and the lateral depletion of the drift region 2, the doping concentration of the drift region 2 can be greatly increased without reducing the breakdown voltage of the device, thereby obtaining a lower specific on-resistance.

[0003] like Figure 1 FIG. 1 is a cross-sectional structure diagram of a device unit of an existing SGT MOSFET. Taking an N-type device as an example, the device unit of the existing SGT MOSFET includes:

[0004] A heavily doped N-type semiconductor substrate 1 such as a silicon substrate, after being thinned, serves as a drain region and is connected to a drain electrode composed of a back metal layer. The semiconductor substrate 1 is used for mechanical support, and it is desired that the doping concentration of the semiconductor substrate 1 is as high as possible and the thickness of the semiconductor substrate 1 is as thin as possible, so as to reduce the resistance of the semiconductor substrate 1.

[0005] The drift region 2 is N-type doped. The doping concentration and thickness of the drift region 2 determine the breakdown voltage of the device. The higher the breakdown voltage of the device, the thicker the drift region 2 needs to be.

[0006] The trench structure formed in the trench 13 includes a source field plate composed of a shielding conductive material layer 4 such as shielding polysilicon connected to a source composed of a front metal layer 10 , and a polysilicon gate 5 . Figure 1 The trench structure in the embodiment is a top-bottom structure, that is, the polysilicon gate 5 is located on the top of the shielding conductive material layer 4 .

[0007] The isolation layer between the shielding conductive material layer 4 and the bottom surface and the side of the bottom area of ​​the groove 13 is the shielding dielectric layer 3, and the shielding dielectric layer 3 is usually made of an oxide layer such as SiO2; the thickness of the shielding dielectric layer 3 is also related to the breakdown voltage. The higher the breakdown voltage that the device needs to withstand, the thickness of the shielding dielectric layer 3 needs to be increased accordingly; usually for a 100V SGTMOSFET device, the thickness of the shielding dielectric layer 3 is usually about The depth of the groove 13 is usually between 5 and 6 microns.

[0008] A gate oxide layer 6 is provided between the polysilicon gate 5 and the side surface of the trench 13 .

[0009] An inter-gate oxide layer 12 is isolated between the shielding conductive material layer 4 and the polysilicon gate 5 .

[0010] A P-type doped channel region 7 is formed on the surface of the drift region 2 , usually by blanket implantation.

[0011] A source region 8 heavily doped with N type is formed in the surface region of the channel region 7 .

[0012] The source region 8 is connected to the source electrode composed of the front metal layer 10 through a contact hole (CT) or a through hole 9 that passes through the interlayer film 11 at the top. The bottom of the through hole 9 at the top of the source region 8 also passes through the source region 8 and realizes connection with the channel region 7.

[0013] Figure 1 Only the formation area of ​​one device unit is shown. In fact, multiple device units are connected in parallel in the original cell area, that is, the active area, so there are multiple grooves 13. The area between the grooves 13 is a platform area (mesa), and the position of the through hole 9 is in the middle of the mesa.

[0014] The difficulty in designing the SGT MOSFET terminal lies in the design of the source field plate; the voltage resistance of the device is mainly borne by the source field plate and its corresponding isolation layer, namely the shielding dielectric layer.

[0015] like Figure 2 , which is a top view of the structure of the existing SGT MOSFET; Figure 2 Only the layout structure of the trench is shown. In the active area, the trenches 13 are strip-shaped and arranged in parallel. For the filling structure in the trenches 13, please refer to Figure 1 shown.

[0016] The width of the spaced regions between the grooves 13, ie, the land regions, is denoted by d1.

[0017] The terminal structure includes a terminal trench structure formed in an annular trench 14, and the annular trench 14 surrounds the circumference of the active region.

[0018] The terminal trench structure only includes the first shielding dielectric layer and the first shielding conductive material layer, and does not include the polysilicon gate, the gate oxide layer and the inter-gate oxide layer. Figure 1 The growth process of the shielding dielectric layer 3 is the same as that of the first shielding conductive material layer and the shielding conductive material layer 4. However, the top surface of the first shielding conductive material layer 4 is flush with the top surface of the annular groove 14, and Figure 1 The top surface of the shielding conductive material layer 4 is lowered to the bottom area of ​​the trench 13 by etching back, and the shielding dielectric layer 3 is also etched back to only cover the side surface of the bottom area of ​​the trench 13 and the bottom surface of the trench 13 .

[0019] The first shielding conductive material layer is also connected to the source and forms a source field plate of the terminal region.

[0020] For a typical 100V SGT MOSFET, the pitch of the cell region is usually between 2.2 and 2.6 microns, and the width d1 of Mesa is usually between 0.5 and 0.8 microns; wherein the pitch is the sum of the width of the trench 13 and the width d1 of Mesa.

[0021] like Figure 2 As shown, since the annular groove 14 is an annular structure and the groove 13 is a strip structure, the end of the groove 13 in the extension direction will have a spacing with the corresponding annular groove 14, as shown in FIG. Figure 2 As shown in d2 and d3, the spacing d2 is the spacing between the end of the groove 13 and the groove segment in the annular groove 14 that is perpendicular to the groove 13, and the spacing d3 is the spacing between the arc segment at the top corner of the annular groove 14 and the corresponding end of the groove 13.

[0022] The selection of the spacing d2 and d3 is crucial to the withstand voltage of the device; if the spacing d2 and d3 are too small, the drift region 2 in the transition region will be depleted, so that the electric lines are easily concentrated at the bottom of the groove, so the electric field strength at the bottom of the groove increases, resulting in a decrease in the breakdown voltage of the device. If the spacing d2 and d3 are too large, the drift region 2 in the transition region will be insufficiently depleted, and the electric field strength on the surface of the silicon wafer, i.e., the semiconductor substrate 1, i.e., the surface area of ​​the drift region 2 will increase, which will also result in a decrease in the breakdown voltage of the device.

[0023] Figure 2 In the terminal structure shown, the selection of the spacings d2 and d3 requires three-dimensional TCAD simulation, which also brings great difficulty to the simulation design.

[0024] In addition, the optimal distances of the spacings d2 and d3 are related to the doping concentration of the drift region 2, the thickness of the source oxide layer, i.e., the shielding dielectric layer 3, and the depth of the trench. The spacings d2 and d3 need to be smaller than the Mesa width d1, usually between 30% and 70% of the Mesa width d1; the typical condition is that the spacings d2 and d3 are half of the Mesa width.

[0025] The reduction in the width of Mesa at the terminal brings difficulties to the process implementation; in addition, the reduction in the width of Mesa will also cause it to be more affected by process changes such as changes in the source field plate size, which will cause the process window (Process Window) to narrow. Summary of the invention

[0026] The technical problem to be solved by the present invention is to provide a terminal structure of an SGT device, which can improve the withstand voltage of the terminal area, reduce the process difficulty and improve the process window.

[0027] In order to solve the above technical problems, in the terminal structure of the SGT device provided by the present invention, the terminal region surrounds the peripheral side of the original cell region.

[0028] In the primitive cell region, the SGT device includes a plurality of device unit structures.

[0029] Each of the device unit structures comprises:

[0030] A first trench structure is formed in the first trench, wherein the first trenches are arranged in parallel; the first trench structure comprises a first shielding dielectric layer, a first shielding conductive material layer, a gate dielectric layer, a gate conductive material layer and an inter-gate dielectric layer; the first shielding conductive material layer is connected to a source electrode composed of a front metal layer.

[0031] A drift region doped with a first conductivity type, the drift region further extending into the termination region.

[0032] A channel region doped with a second conductivity type is also formed in a surface region of the drift region of the original cell region, and the channel region is connected to the source.

[0033] The first direction is the arrangement direction of each of the first grooves, and the second direction is the extension direction of each of the first grooves; the terminal area is divided into a first direction terminal area and a second direction terminal area, the first direction terminal area is located on both sides of the original cell area along the first direction; the second direction terminal area is located on both sides of the original cell area along the second direction.

[0034] The terminal structure includes a first terminal structure formed in the first direction terminal region and a second terminal structure formed in the second direction terminal region.

[0035] The first terminal structure includes at least one second trench structure, the second trench structure is formed in the second trench, and the second trench is parallel to the first trench; the second trench structure includes a second shielding dielectric layer formed on the inner surface of the second trench and a second shielding conductive material layer filled in the second trench, and the second shielding conductive material layer completely fills the gap of the second trench inside the second shielding dielectric layer; in the first direction, the first edge of the channel region and the inner side surface of the innermost second trench are self-aligned; the second shielding conductive material layer is connected to the source.

[0036] The second terminal structure includes a first trench extension structure, and the first trench extension structure is formed by extending the first trench structure to the second direction terminal region; in the second direction, the second edge of the channel region is located at the edge of the original cell region; the second terminal structure also includes a plurality of floating regions doped with the second conductive type; a plurality of floating regions are arranged in the drift region outside the channel region between each of the first trench extension structures and between the outermost first trench extension structure and the innermost second trench structure; the floating region is used to reduce the curvature effect of the second edge of the channel region, and the floating region and the first trench extension structure together improve the withstand voltage of the second direction terminal region.

[0037] A further improvement is that the first terminal structure also includes one or more third groove structures located outside the outermost second groove structure, the third groove structure is formed in the third groove, and the third groove is parallel to the first groove; the third groove structure includes a third shielding dielectric layer formed on the inner surface of the third groove and a third shielding conductive material layer filled in the third groove, the third shielding conductive material layer completely fills the gap of the third groove inside the third shielding dielectric layer; the third shielding conductive material layer is floating.

[0038] A further improvement is that the process structures of the floating regions and the channel regions are the same.

[0039] A further improvement is that each of the floating regions and the channel region is defined by the same photomask and formed by the same ion implantation process.

[0040] A further improvement is that, in the second direction, the corresponding floating areas are aligned.

[0041] A further improvement is that the terminal structure also includes a third terminal structure.

[0042] The third terminal structure includes one or more fourth groove structures, each of which is formed in a fourth annular groove, and the fourth annular groove surrounds the third groove and the outside of the first groove. The fourth groove structure includes a fourth shielding dielectric layer formed on the inner surface of the fourth annular groove and a fourth shielding conductive material layer filled in the fourth annular groove, and the fourth shielding conductive material layer completely fills the gap of the fourth annular groove inside the fourth shielding dielectric layer; the fourth shielding conductive material layer is floatingly arranged or connected to the source or the drain.

[0043] A further improvement is that the end of the second groove structure is aligned with the corresponding end of the first groove extension structure.

[0044] A further improvement is that the first groove extension structure has an equal-width section and a first widened section; the equal-width section is adjacent to the original cell area and the width of the equal-width section is equal to the width of the first groove structure; the first widened section is away from the original cell area and the width of the first widened section is greater than the width of the equal-width section.

[0045] The second groove structure has a second widened section aligned with the first widened section.

[0046] A further improvement is that the width of the first widening section is uniform; or, the width of the first widening section gradually increases in a direction from the original cell region outward.

[0047] A further improvement is that the widths of the second grooves are equal to those of the first grooves, and the spacings between the first grooves, between the first grooves and the second grooves, and between the second grooves are equal.

[0048] A further improvement is that the materials of the first shielding dielectric layer, the second shielding dielectric layer, the third shielding dielectric layer and the fourth shielding dielectric layer are the same material formed at the same time.

[0049] The first shielding conductive material layer, the second shielding conductive material layer, the third shielding conductive material layer and the fourth shielding conductive material layer are made of the same material formed at the same time.

[0050] A further improvement is that the material of the first shielding dielectric layer includes an oxide layer.

[0051] A further improvement is that the oxide layer of the first shielding dielectric layer is a thermal oxide layer or a stacked layer of a thermal oxide layer and a CVD oxide layer.

[0052] A further improvement is that the materials of the first shielding conductive material layer, the second shielding conductive material layer, the third shielding conductive material layer and the fourth shielding conductive material layer include polysilicon.

[0053] A further improvement is that the material of the gate dielectric layer includes an oxide layer.

[0054] The material of the inter-gate dielectric layer includes an oxide layer.

[0055] The gate conductive material layer is made of polysilicon.

[0056] A further improvement is that the SGT device is an SGT MOSFET; a drain region heavily doped with the first conductivity type is formed on the back side of the drift region, and a drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0057] A further improvement is that the SGT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type.

[0058] Alternatively, the SGT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0059] In the present invention, the second trench structure of the first terminal structure is parallel to the first trench structure of the original cell region. At the same time, no gate conductive material layer is provided in the second trench structure, so the second shielding dielectric layer can be located on the entire inner surface of the second trench, i.e., the bottom surface and the entire side surface. At the same time, no source region is provided on the top of the drift region of the first direction terminal region. In this way, when the device is reverse biased, the high voltage connected to the drift region will eventually be completely borne by the second shielding dielectric layer, and the critical breakdown field strength of the second shielding dielectric layer, such as the oxide layer, is much greater than the critical breakdown electric field of the semiconductor material, such as silicon, that forms the drift region. Therefore, the voltage resistance of the first direction terminal region can be guaranteed and the first direction terminal region will not become a weak point region, and finally the breakdown voltage of the entire device can be improved.

[0060] In the present invention, the first trench extension structure of the second terminal structure is an extension structure of the first trench structure, so there is no end structure in the first trench structure, so it can avoid the problems of lower breakdown voltage, increased process difficulty and reduced process window caused by the end setting of the first trench structure at the edge of the original cell region in the existing structure. The present invention also sets a floating area in the second terminal structure, and the floating area is used to reduce the curvature effect of the second edge of the channel region, so as to reduce the concentration of electric lines caused by the curvature effect of the second edge of the channel region, thereby improving the breakdown voltage; at the same time, the first trench extension structure of the present invention can laterally deplete the drift region of the second direction terminal region, so as to increase the depletion of the drift region, thereby increasing the breakdown voltage of the device and increasing the doping concentration of the drift region under the condition of keeping the breakdown voltage unchanged or increasing, thereby reducing the specific on-resistance of the device, so the second terminal structure of the present invention combines the setting of the floating area and the setting of the first trench extension structure to improve the breakdown voltage of the device.

[0061] Therefore, the first terminal structure and the second terminal structure of the present invention can respectively improve the withstand voltage of the first direction terminal area and the second direction terminal area, and finally improve the withstand voltage of the terminal area, thereby improving the breakdown voltage of the device; at the same time, the first terminal structure and the second terminal structure of the present invention are both straight structures, without a curved structure, and no spacing area is set between the end of the groove and the straight section of the groove, thereby eliminating the disadvantages of lower breakdown voltage, increased process difficulty and reduced process window caused by setting the spacing area. Therefore, the present invention can improve the withstand voltage of the terminal area, reduce process difficulty and improve the process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0063] Figure 1 It is a cross-sectional structural diagram of a device unit of an existing SGT MOSFET;

[0064] Figure 2 This is a top view of the existing SGT MOSFET structure;

[0065] Figure 3 is a top view of the SGT device according to the first embodiment of the present invention;

[0066] Figure 4A is a cross-sectional structural diagram of a device unit of an SGT device according to a first embodiment of the present invention;

[0067] Figure 4B is along Figure 3 The cross-sectional structure diagram at the midline aa;

[0068] Figure 4C is along Figure 3 The cross-sectional structure diagram at the midline bb;

[0069] Figure 5 is a top view of the SGT device according to the second embodiment of the present invention;

[0070] Figure 6 It is a top view of the SGT device according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0071] like Figure 3 , which is a top view of the SGT device of the first embodiment of the present invention; Figure 4A , which is a cross-sectional structural diagram of a device unit of an SGT device according to a first embodiment of the present invention; Figure 4B As shown, it is along Figure 3 The cross-sectional structure diagram at the midline aa; Figure 4C As shown, it is along Figure 3 Cross-sectional structural diagram at the center line bb; in the terminal structure of the SGT device according to the embodiment of the present invention, the terminal region surrounds the peripheral side of the original cell region 201.

[0072] In the primary cell region 201 , the SGT device includes a plurality of device unit structures.

[0073] like Figure 4A As shown, each device unit structure includes:

[0074] The first trench structure formed in the first trench 101; Figure 3 As shown, the first trenches 101 are arranged in parallel.

[0075] The first trench structure includes a first shielding dielectric layer 303, a first shielding conductive material layer 304, a gate dielectric layer 306, a gate conductive material layer 305 and an inter-gate dielectric layer 312; the first shielding conductive material layer 304 is connected to the source electrode composed of the front metal layer 310, Figure 4A The front metal layer 310 shown in FIG. 3 is the front metal layer 310 corresponding to the source. The front metal layer 310 also forms a gate (not shown). Figure 4A The corresponding section is shown.

[0076] A drift region 302 doped with a first conductivity type, the drift region 302 also extends into the termination region.

[0077] A channel region 307 doped with the second conductivity type is also formed in the surface region of the drift region 302 of the original cell region 201 , and the channel region 307 is connected to the source.

[0078] A heavily doped source region 308 of the first conductivity type is formed in the surface region of the channel region 307 and is self-aligned with the first trench 101. The source region 308 is connected to the source electrode through a contact hole 309 passing through the interlayer film 311 at the top, and the contact hole 309 corresponding to the source region 308 also passes through the source region 308 to achieve contact with the channel region 307.

[0079] In the first embodiment of the present invention, the SGT device is an SGT MOSFET; a first conductive type heavily doped drain region 301 is formed on the back side of the drift region 302 , and a drain electrode (not shown) composed of a back metal layer is formed on the back side of the drain region 301 .

[0080] like Figure 3 As shown, the first direction is the arrangement direction of the first trenches 101 , and the second direction is the extension direction of the first trenches 101 . Figure 3 , the first direction is the Y direction and the second direction is the X direction.

[0081] The terminal area is divided into a first direction terminal area 202a and a second direction terminal area 202b. The first direction terminal area 202a is located at both sides of the original cell area 201 along the first direction; the second direction terminal area 202b is located at both sides of the original cell area 201 along the second direction.

[0082] The terminal structure includes a first terminal structure formed in the first direction terminal region 202a and a second terminal structure formed in the second direction terminal region 202b.

[0083] The first terminal structure includes at least one second trench structure, and the second trench structure is formed in the second trench 102 . The second trench 102 is parallel to the first trench 101 .

[0084] like Figure 4BAs shown, the second trench structure includes a second shielding dielectric layer 303a formed on the inner surface of the second trench 102 and a second shielding conductive material layer 304a filled in the second trench 102, and the second shielding conductive material layer 304a completely fills the gap of the second trench 102 inside the second shielding dielectric layer 303a; in the first direction, the first edge of the channel region 307 and the inner side surface of the innermost second trench 102 are self-aligned; the second shielding conductive material layer 304a is connected to the source. Figure 3 In the embodiment, the region 203 is an implantation region of the channel region 307 , and the channel region 307 is self-aligned and formed in the surface region of the drift region 302 between the first trenches 101 and between the first trench 101 and the innermost second trench 102 .

[0085] The second terminal structure includes a first trench extension structure, and the first trench extension structure is formed by extending the first trench structure to the second direction terminal region 202b. Figure 3 In the embodiment, the first trench extension structure is the first trench structure in the second direction terminal region 202b located outside the original cell region 201. The internal structure of the first trench extension structure is the same as that of the first trench structure, and only the position is different. For the internal structure of the first trench extension structure, please refer to Figure 4A shown.

[0086] In the first embodiment of the present invention, the end of the second trench structure is aligned with the end of the corresponding first trench extension structure.

[0087] like Figure 4C As shown, in the second direction, the second edge of the channel region 307 is located at the edge of the original cell region 201; the second terminal structure also includes a plurality of floating regions 307a doped with the second conductive type; a plurality of floating regions 307a are arranged in the drift region 302 outside the channel region 307 between each first trench extension structure and between the outermost first trench extension structure and the innermost second trench structure; the floating regions 307a are used to reduce the curvature effect of the second edge of the channel region 307, and the floating regions 307a and the first trench extension structure together improve the withstand voltage of the second direction terminal region 202b. Figure 3 In the embodiment, the region 204 is an implantation region of the floating region 307 a , and an overlapping region of the region 204 and the drift region 302 is a formation region of the floating region 307 a .

[0088] like Figure 3As shown, the first terminal structure also includes more than one third trench structure located outside the outermost second trench structure, the third trench structure is formed in the third trench 103, and the third trench 103 is parallel to the first trench 101; the third trench structure includes a third shielding dielectric layer (not shown) formed on the inner surface of the third trench 103 and a third shielding conductive material layer (not shown) filled in the third trench 103, the third shielding conductive material layer completely fills the gap of the third trench 103 inside the third shielding dielectric layer; the third shielding conductive material layer is set in a floating manner. The structure of the third shielding conductive material layer and the third shielding dielectric layer in the third trench 103 and Figure 4B , the second shielding conductive material layer 304a and the second shielding dielectric layer 303a are similar in structure in the second trench 102. The difference between the two is that the third shielding conductive material layer is not connected to any electrode, so it is a floating structure; while the second shielding conductive material layer 304a is connected to the source, so it is a source field plate.

[0089] In the first embodiment of the present invention, the process structures of the floating regions 307 a and the channel regions 307 are the same.

[0090] Each floating region 307a and the channel region 307 are defined by the same photomask and formed by the same ion implantation process. Figure 3 As shown, the region 203 and the region 204 are patterns defined on the same photomask. After ion implantation according to the definition of the photomask, a channel region 307 and a floating region 307a are formed in the surface region of the corresponding drift region 302 at the bottom.

[0091] Preferably, in the second direction, the corresponding floating regions 307 a are aligned.

[0092] In the first embodiment of the present invention, the widths of the second trenches 102 and the first trenches 101 are equal, and the spacing between the first trenches 101 , the spacing between the first trenches 101 and the second trenches 102 , and the spacing between the second trenches 102 are equal.

[0093] The materials of the first shielding dielectric layer 303, the second shielding dielectric layer 303a, the third shielding dielectric layer and the fourth shielding dielectric layer are the same materials formed at the same time. In some embodiments, the material of the first shielding dielectric layer 303 includes an oxide layer. The oxide layer of the first shielding dielectric layer 303 is a thermal oxide layer or a superposition layer of a thermal oxide layer and a CVD oxide layer. A thicker first shielding dielectric layer 303 can be obtained by using a structure in which a thermal oxide layer and a CVD oxide layer are superposed. The thermal oxide layer is an oxide layer formed by a thermal oxidation process, and the CVD oxide layer is an oxide layer formed by a CVD process.

[0094] The materials of the first shielding conductive material layer 304, the second shielding conductive material layer 304a, the third shielding conductive material layer and the fourth shielding conductive material layer are the same material formed at the same time. In some embodiments, the materials of the first shielding conductive material layer 304, the second shielding conductive material layer 304a, the third shielding conductive material layer and the fourth shielding conductive material layer include polysilicon.

[0095] The material of the gate dielectric layer 306 includes an oxide layer.

[0096] The material of the inter-gate dielectric layer 312 includes an oxide layer.

[0097] The gate conductive material layer 305 is made of polysilicon.

[0098] In the first embodiment of the present invention, the SGT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the SGT device can be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0099] In the first embodiment of the present invention, the second trench structure of the first terminal structure is parallel to the first trench structure of the original cell region 201. At the same time, the gate conductive material layer 305 is not provided in the second trench structure, so the second shielding dielectric layer 303a can be located on the entire inner surface of the second trench 102, that is, the bottom surface and the entire side surface. At the same time, no source region is provided on the top of the drift region 302 of the first direction terminal region 202a. In this way, when the device is reverse biased, the high voltage connected to the drift region 302 will eventually be completely borne by the second shielding dielectric layer 303a, and the critical breakdown field strength of the second shielding dielectric layer 303a, such as an oxide layer, is much greater than the critical breakdown electric field of the semiconductor material forming the drift region 302, such as silicon. Therefore, the voltage resistance of the first direction terminal region 202a can be guaranteed and the first direction terminal region 202a will not become a weak point area, and finally the breakdown voltage of the entire device can be improved.

[0100] In the first embodiment of the present invention, the first trench extension structure of the second terminal structure is an extension structure of the first trench structure, so there is no end structure in the first trench structure, thereby avoiding the problems of reduced breakdown voltage, increased process difficulty and reduced process window caused by the end setting of the first trench structure at the edge of the original cell area 201 in the existing structure. The first embodiment of the present invention further provides a floating region 307a in the second terminal structure, and the floating region 307a is used to reduce the curvature effect of the second edge of the channel region 307, thereby reducing the concentration of electric lines caused by the curvature effect of the second edge of the channel region 307, thereby improving the breakdown voltage; at the same time, the first trench extension structure of the first embodiment of the present invention can laterally deplete the drift region 302 of the second direction terminal region 202b, so as to increase the depletion of the drift region 302, thereby increasing the breakdown voltage of the device and increasing the doping concentration of the drift region 302 while keeping the breakdown voltage unchanged or increasing, thereby reducing the specific on-resistance of the device. Therefore, the second terminal structure of the first embodiment of the present invention combines the setting of the floating region 307a and the setting of the first trench extension structure to improve the breakdown voltage of the device.

[0101] Therefore, the first terminal structure and the second terminal structure of the first embodiment of the present invention can respectively improve the withstand voltage of the first direction terminal area 202a and the second direction terminal area 202b, and finally improve the withstand voltage of the terminal area, thereby improving the breakdown voltage of the device; at the same time, the first terminal structure and the second terminal structure of the first embodiment of the present invention are both straight structures, without a curved structure, and no spacing area is set between the end of the groove and the straight section of the groove, thereby eliminating the disadvantages of lower breakdown voltage, increased process difficulty and reduced process window caused by setting the spacing area. Therefore, the first embodiment of the present invention can improve the withstand voltage of the terminal area, reduce the process difficulty and improve the process window.

[0102] The principle of withstanding breakdown voltage of the terminal structure of the first embodiment of the present invention is further described as follows:

[0103] In the region in the aa direction, i.e., the first direction terminal region 202a, the principle of withstanding the breakdown voltage of the first terminal structure is:

[0104] like Figure 4B As shown, no channel region and source region are formed in the surface area of ​​the drift region 302 , so the potential of the drift region 302 is the drain potential.

[0105] At the same time, the second trench structure only has the second shielding conductive material layer 304a, and there is no gate structure in the top region of the second trench 102, so the source field plate formed by connecting the second shielding conductive material layer 304a and the source electrode can be closer to the surface region of the drift region 302 at the top of the semiconductor substrate 301. In this way, the voltage between the source field plate and the drain electrode will be completely borne on the second shielding dielectric layer 303a, and when it breaks down, the breakdown voltage is completely borne by the second shielding dielectric layer 303a; because the critical breakdown field strength of the oxide layer is much greater than that of the material of the semiconductor substrate 301, such as silicon, it is ensured that it will not become a weak point.

[0106] In the region in the bb direction, i.e., the second direction terminal region 202b, the principle of withstanding the breakdown voltage of the second terminal structure is:

[0107] In order to reduce the curvature effect of the channel region 307, a floating region 307a is used to increase its breakdown voltage; Figure 4C Three floating areas 307 a are drawn in the figure. Actually, the number of floating areas 307 a may be more than or less than three; however, they are needed to reduce the curvature effect.

[0108] However, because the doping concentration of the drift region 302 of the SGT device is high, even if the curvature reduction effect is adopted, the breakdown voltage of the device is still low; however, for the device structure of the first embodiment of the present invention, Figure 3 In the embodiment, the drift region 302 in the second direction terminal region 202b is surrounded by source field plates, i.e., source field plates formed by connecting the first shielding conductive material layer 304 and the second shielding conductive material layer 304a in the first trench extension structure to the source. Therefore, the source field plates on both sides of the drift region 302 can laterally deplete the drift region 302. By relying on the lateral depletion of the drift region 302 by the source field plates, the equivalent doping concentration will be greatly reduced, and the achievable withstand voltage will also be greatly increased.

[0109] like Figure 5 As shown, it is a top view of the SGT device of the second embodiment of the present invention; the difference between the second embodiment of the present invention and the first embodiment of the present invention is that in the second embodiment of the present invention: the first trench extension structure has an equal-width section 101b and a first widening section 101a; the equal-width section 101b is adjacent to the original cell area 201 and the width of the equal-width section 101b is equal to the width of the first trench structure; the first widening section 101a is away from the original cell area 201 and the width of the first widening section 101a is greater than the width of the equal-width section 101b.

[0110] The second groove structure has a second widened section 102a aligned with the first widened section 101a.

[0111] The first widening section 101a and the second widening section 102a can increase the depletion of the drift region 302 between the first widening section 101a or the second widening section 102a, and the equivalent doping concentration of the drift region 302 can be reduced, which can further improve the withstand voltage of the device.

[0112] The provision of the equal-width section 101 b can ensure that the first widening section 101 a and the second widening section 102 a will not have an adverse effect on the performance of the original cell area 201 , especially the boundary area of ​​the original cell area 201 .

[0113] Figure 5 In the embodiment, the width of the first widening section 101a is uniform. In other embodiments, the width of the first widening section 101a gradually increases from the original cell area 201 to the outside.

[0114] like Figure 6 , which is a top view of the SGT device of the third embodiment of the present invention; the difference between the third embodiment of the present invention and the first embodiment of the present invention is that in the third embodiment of the present invention:

[0115] The terminal structure also includes a third terminal structure. The third terminal structure includes one or more fourth groove structures, each of which is formed in a fourth annular groove 104, and the fourth annular groove 104 surrounds the third groove 103 and the outside of the first groove 101. The fourth groove structure includes a fourth shielding dielectric layer formed on the inner surface of the fourth annular groove 104 and a fourth shielding conductive material layer filled in the fourth annular groove 104. The fourth shielding conductive material layer completely fills the gap of the fourth annular groove 104 inside the fourth shielding dielectric layer. The filling structure of the fourth shielding conductive material layer and the fourth shielding dielectric layer in the fourth annular groove 104 is the same as that in the cross section. Figure 4B The second shielding conductive material layer 304 a and the second shielding dielectric layer 303 a are shown as filling structures in the second trench 102 .

[0116] Preferably, the fourth shielding conductive material layer is connected to the source electrode. In some embodiments, the fourth shielding conductive material layer can also be floating; or the fourth shielding conductive material layer is connected to the drain electrode.

[0117] In the third embodiment of the present invention, since the first terminal structure and the second terminal structure are arranged inside the third terminal structure, the distance between the fourth annular groove 104 of the third terminal structure and the ends of the first groove 101, the second groove 102 and the third groove 103 inside becomes unimportant, and there can be a very wide degree of freedom.

[0118] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A terminal structure of an SGT device, characterized in that: The terminal region surrounds the circumference of the protocell region; In the primitive cell region, the SGT device includes a plurality of device unit structures; Each of the device unit structures comprises: A first trench structure is formed in the first trench, wherein the first trenches are arranged in parallel; the first trench structure comprises a first shielding dielectric layer, a first shielding conductive material layer, a gate dielectric layer, a gate conductive material layer and an inter-gate dielectric layer; the first shielding conductive material layer is connected to a source electrode composed of a front metal layer; a drift region doped with a first conductivity type, the drift region further extending into the terminal region; A channel region doped with a second conductivity type is also formed in a surface region of the drift region of the original cell region, and the channel region is connected to the source electrode; The first direction is the arrangement direction of each of the first grooves, and the second direction is the extension direction of each of the first grooves; the terminal area is divided into a first direction terminal area and a second direction terminal area, the first direction terminal area is located on both sides of the original cell area along the first direction; the second direction terminal area is located on both sides of the original cell area along the second direction; The terminal structure includes a first terminal structure formed in the first direction terminal region and a second terminal structure formed in the second direction terminal region; The first terminal structure includes at least one second trench structure, the second trench structure is formed in the second trench, and the second trench is parallel to the first trench; the second trench structure includes a second shielding dielectric layer formed on the inner surface of the second trench and a second shielding conductive material layer filled in the second trench, and the second shielding conductive material layer completely fills the gap of the second trench inside the second shielding dielectric layer; in the first direction, the first edge of the channel region and the inner side surface of the innermost second trench are self-aligned; the second shielding conductive material layer is connected to the source; The second terminal structure includes a first trench extension structure, and the first trench extension structure is formed by extending the first trench structure to the second direction terminal region; in the second direction, the second edge of the channel region is located at the edge of the original cell region; the second terminal structure also includes a plurality of floating regions doped with the second conductive type; a plurality of floating regions are arranged in the drift region outside the channel region between each of the first trench extension structures and between the outermost first trench extension structure and the innermost second trench structure; the floating region is used to reduce the curvature effect of the second edge of the channel region, and the floating region and the first trench extension structure together improve the withstand voltage of the second direction terminal region.

2. The terminal structure of the SGT device according to claim 1, characterized in that: The first terminal structure further includes one or more third groove structures located outside the outermost second groove structure, wherein the third groove structure is formed in a third groove, and the third groove is parallel to the first groove; The third trench structure includes a third shielding dielectric layer formed on the inner surface of the third trench and a third shielding conductive material layer filled in the third trench, wherein the third shielding conductive material layer completely fills the gap of the third trench inside the third shielding dielectric layer; the third shielding conductive material layer is floatingly arranged.

3. The terminal structure of the SGT device according to claim 1, characterized in that: The process structures of the floating regions and the channel regions are the same.

4. The terminal structure of the SGT device according to claim 3, characterized in that: The floating regions and the channel regions are defined by the same photomask and formed by the same ion implantation process.

5. The terminal structure of the SGT device according to claim 4, characterized in that: In the second direction, the corresponding floating regions are aligned.

6. The terminal structure of the SGT device according to claim 2, characterized in that: The terminal structure also includes a third terminal structure; The third terminal structure includes one or more fourth groove structures, each of which is formed in a fourth annular groove, the fourth annular groove surrounds the third groove and the outside of the first groove, the fourth groove structure includes a fourth shielding dielectric layer formed on the inner surface of the fourth annular groove and a fourth shielding conductive material layer filled in the fourth annular groove, and the fourth shielding conductive material layer completely fills the gap of the fourth annular groove inside the fourth shielding dielectric layer; The fourth shielding conductive material layer is floatingly disposed, or connected to the source or the drain.

7. The terminal structure of the SGT device according to claim 1, characterized in that: An end of the second trench structure is aligned with an end of a corresponding first trench extension structure.

8. The terminal structure of the SGT device according to claim 1, characterized in that: The first trench extension structure has a uniform width section and a first widened section; the uniform width section is adjacent to the original cell region and the width of the uniform width section is equal to the width of the first trench structure; the first widened section is away from the original cell region and the width of the first widened section is greater than the width of the uniform width section; The second groove structure has a second widened section aligned with the first widened section.

9. The terminal structure of the SGT device according to claim 8, characterized in that: The width of the first widening section is uniform; or, the width of the first widening section gradually increases from the original cell region outward.

10. The terminal structure of the SGT device according to claim 1, characterized in that: The widths of the second trenches are equal to those of the first trenches, and the spacings between the first trenches, between the first trenches and the second trenches, and between the second trenches are equal.

11. The terminal structure of the SGT device according to claim 6, characterized in that: The materials of the first shielding dielectric layer, the second shielding dielectric layer, the third shielding dielectric layer and the fourth shielding dielectric layer are the same material formed at the same time; The first shielding conductive material layer, the second shielding conductive material layer, the third shielding conductive material layer and the fourth shielding conductive material layer are made of the same material formed at the same time.

12. The terminal structure of the SGT device according to claim 11, characterized in that: The material of the first shielding dielectric layer includes an oxide layer.

13. The terminal structure of the SGT device according to claim 11, characterized in that: The materials of the first shielding conductive material layer, the second shielding conductive material layer, the third shielding conductive material layer and the fourth shielding conductive material layer include polysilicon.

14. The terminal structure of the SGT device according to claim 1, characterized in that: The material of the gate dielectric layer includes an oxide layer; The material of the inter-gate dielectric layer includes an oxide layer; The gate conductive material layer is made of polysilicon.

15. The terminal structure of the SGT device according to claim 1, characterized in that: The SGT device is an SGT MOSFET; a drain region heavily doped with a first conductivity type is formed on the back side of the drift region, and a drain electrode composed of a back metal layer is formed on the back side of the drain region.

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