Formation of isolation regions with low parasitic capacitance and reduced damage

Abstract

The disclosure relates to forming isolation regions with low parasitic capacitance and reduced damage. A method includes forming a plurality of semiconductor regions; forming a plurality of gate stacks, wherein the plurality of gate stacks are on a first portion of the plurality of semiconductor regions; and etching the plurality of gate stacks to form a plurality of openings in the plurality of gate stacks. The plurality of openings includes a first opening in the first gate stack and a second opening in the second gate stack. The first opening and the second opening are in close proximity to each other and have an overlap with an overlap distance equal to or greater than a pitch of the plurality of semiconductor regions. The plurality of semiconductor regions are etched to extend the plurality of openings down between the dielectric isolation regions, and then the plurality of openings are filled to form fin isolation regions. The gate isolation region is spaced apart from the fin isolation region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to forming isolation regions with low parasitic capacitance and reduced damage. Background Art

[0002] Technological advances in integrated circuit (IC) materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous generations. In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometric size has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This shrinkage has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed in order to achieve these advances. For example, gate-all-around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods of manufacturing GAA transistors are under development.

[0004] The formation of a GAA transistor generally includes forming a long strip (comprising alternating semiconductor materials) and a long gate stack, and then forming an isolation region to cut the long strip and the long gate stack into shorter sections. The shorter sections can be used to form the channel layer and gate stack of the GAA transistor. Summary of the invention

[0005] According to an embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a plurality of semiconductor regions, the semiconductor regions having a first longitudinal direction, the first longitudinal direction being parallel to a first direction; forming a plurality of gate stacks, the gate stacks having a second longitudinal direction, the second longitudinal direction being parallel to a second direction, the second direction being perpendicular to the first direction, wherein the plurality of gate stacks are on a first portion of the plurality of semiconductor regions; etching the plurality of gate stacks to form a first plurality of openings, wherein the first plurality of openings separate the plurality of gate stacks into first shorter portions; filling the first plurality of openings to form a gate isolation region; etching the plurality of semiconductor regions to form a second plurality of openings, wherein the second plurality of openings separates the plurality of semiconductor regions into second shorter portions; and filling the second plurality of openings to form a fin isolation region, wherein the gate isolation region is spaced apart from the fin isolation region.

[0006] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a plurality of semiconductor regions; a gate stack, the gate stack comprising a plurality of portions aligned with a straight line; a plurality of gate isolation regions, the gate isolation regions having a longitudinal direction in a first direction; a plurality of fin isolation regions, the fin isolation regions having a longitudinal direction in a second direction, the second direction being perpendicular to the first direction, wherein the plurality of fin isolation regions separate the plurality of portions of the gate stack from each other and separate some of the plurality of semiconductor regions into shorter portions; and a plurality of source / drain regions on opposite sides of the gate stack, wherein the plurality of gate isolation regions are physically separated from the plurality of fin isolation regions and physically separated from the plurality of source / drain regions.

[0007] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor substrate; a plurality of shallow trench isolation regions located above a main portion of the semiconductor substrate; a plurality of transistors, comprising: a plurality of nanostructures, an upper nanostructure of the plurality of nanostructures overlapping with a corresponding lower nanostructure of the plurality of nanostructures; a plurality of gate stacks on the plurality of nanostructures, wherein the plurality of gate stacks include a first portion between the plurality of nanostructures; a plurality of gate isolation regions separating the plurality of gate stacks from each other, wherein the plurality of gate isolation regions have a bottom portion that contacts a top surface of the plurality of shallow trench isolation regions; and a plurality of fin isolation regions separating the plurality of nanostructures from each other, wherein the plurality of fin isolation regions include a second portion between the plurality of shallow trench isolation regions, the bottom portions of the plurality of fin isolation regions are lower than the shallow trench isolation regions, and wherein the plurality of fin isolation regions are physically spaced apart from the plurality of gate isolation regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noteworthy that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1-Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11 , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig. 13C , Fig.14 , Fig.15A , Fig. 15B , Fig.16A and Fig. 16B A diagram illustrating an intermediate stage in the formation of a gate-all-around (GAA) transistor in accordance with some embodiments.

[0010] Figure 17-Figure 21 The formation of a cut metal gate region is shown in accordance with some embodiments.

[0011] Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A and Fig.28B The formation of a continuous polysilicon on diffusion edge (CPODE) region by cutting a dummy gate stack is shown in accordance with some embodiments.

[0012] Fig.29A , Fig.29B , Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Fig.32A , Fig.32B , Fig.33A and Fig.33B The formation of a continuous metal on diffusion edge (CMODE) isolation region by cutting a replacement gate stack is shown in accordance with some embodiments.

[0013] Fig.34 Structures including inverters with different numbers of active gates are shown according to some embodiments.

[0014] Fig.35 A process flow for forming a GAA transistor is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] A gate all around (GAA) transistor, a cut metal gate (CMG) isolation region, a continuous polysilicon on diffusion edge (CPODE) isolation region, and a continuous metal on diffusion edge (CMODE) isolation region and a method for forming the same are provided. According to some embodiments of the present disclosure, the CMG isolation region is completely separated from the CPODE isolation region and the CMODE isolation region, and does not contact the CPODE isolation region and the CMODE isolation region. This reduces damage without increasing parasitic capacitance.

[0018] In the illustrated embodiment, the formation of a GAA transistor is used as an example to explain the concepts of the present disclosure. Other types of transistors such as fin field effect transistors (FinFETs), planar transistors, etc. may also employ the concepts of the present disclosure. The embodiments discussed herein are intended to provide examples of the subject matter of the present disclosure that can be made or used, and those of ordinary skill in the art will readily understand the modifications that may be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0019] Figure 1-Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11 , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig. 13C , Fig.14 , Fig.15A , Fig. 15B , Fig.16A and Fig. 16B FIG. 22 is a diagram showing an intermediate stage in the formation of a GAA transistor according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in the process flow shown in FIG.

[0020] refer to Figure 1 , showing a perspective view of a wafer 10. The wafer 10 includes a multilayer structure including a multilayer stack 22 on a substrate 20. According to some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., however other substrates and / or structures may be used, such as semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc. The substrate 20 may be doped as a p-type semiconductor, however in other embodiments, it may be doped as an n-type semiconductor.

[0021] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding process is shown as process 202 in the process flow 200 shown in Figure 22. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0022] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed at about Peace However, any suitable thickness may be used while remaining within the scope of the embodiments.

[0023] Once the first layer 22A is deposited on the substrate 20, the second layer 22B is deposited on the first layer 22B. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, etc., where the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon germanium, the second layer 22B can be formed of silicon, or vice versa. It should be understood that any suitable material combination can be used for the first layer 22A and the second layer 22B.

[0024] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22B using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, for example, the second layer 22A has a thickness in a range between about 4 nm and 7 nm, while the second layer 22 has a thickness in a range between about 8 nm and 12 nm.

[0025] Once the second layer 22B is formed on the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired topmost layer of the multilayer stack 22 is formed. According to some embodiments, the first layer 22A has the same or similar thickness as each other, and the second layer 22B has the same or similar thickness as each other. The first layer 22A may also have a thickness that is the same or different from the thickness of the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A throughout the description. According to an alternative embodiment, the second layer 22B is sacrificial and is removed in a subsequent process.

[0026] According to some embodiments, some pad oxide layers and hard mask layers (not shown) may be formed on the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0027] refer to Figure 2 , the multilayer stack 22 and a portion of the substrate 20 below are patterned in (one or more) etching processes to form a groove 23. The corresponding process is shown as process 204 in the process flow 200 shown in Figure 22. The groove 23 extends into the substrate 20. The rest of the multilayer stack is referred to as the multilayer stack 22' below. Below the multilayer stack 22', some portions of the substrate 20 are left, which are referred to as substrate strips 20' below. The multilayer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, the semiconductor layer 22A may be referred to alternatively as a sacrificial layer, and the semiconductor layer 22B may be referred to alternatively as a nanostructure. Portions of the multilayer stack 22' and the substrate strip 20' below are collectively referred to as semiconductor strips 24.

[0028] In the above-described illustrated embodiments, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0029] Figure 3The formation of isolation region 26 is described, and isolation region 26 is also referred to as shallow trench isolation (STI) region throughout the description. The corresponding process is shown as process 206 in process flow 200 shown in Figure 22. STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may also include a dielectric material on the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, may then be performed to flatten the top surface of the dielectric material, and the remaining portion of the dielectric material is the STI region 26.

[0030] The STI region 26 is then recessed so that the top portion of the semiconductor strip 24 protrudes higher than the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top portion of the multilayer stack 22' and the substrate strip 20'. The recessing of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. During the etching process, plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 26 is performed by a wet etching process. The etching chemical can include, for example, HF.

[0031] refer to Figure 4 , a dummy gate stack 30 and a gate spacer 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is shown as process 208 in the process flow 200 shown in Figure 22. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer or by depositing a dielectric layer such as a silicon oxide layer. The dummy gate electrode 34 may be formed, for example, using polysilicon or amorphous silicon, and other materials such as amorphous carbon may also be used.

[0032] Each dummy gate stack 30 may also include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multilayer thereof. The dummy gate stack 30 may span a single or multiple protruding fins 28 and the STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a longitudinal direction that is perpendicular to the longitudinal direction of the protruding fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layer by (one or more) patterning processes.

[0033] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon nitride carbon (SiCN), silicon oxynitride (SiON), silicon oxynitride carbon (SiOCN), etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers, and then performing (one or more) anisotropic etching processes on (one or more) dielectric layers. The remaining portion of (one or more) dielectric layers is the gate spacer 38.

[0034] According to an alternative embodiment, the Fig.19 The process shown forms one or more layers of gate spacers 38, and the resulting layers of gate spacers 38 include the same as those shown in FIG. Figures 19 to 21 For example, the gate spacer 38 may be formed of or include SiOCNH. The details of the formation process will be discussed in the following paragraphs.

[0035] Figure 5A and Figure 5B Shows Figure 4 Cross-sectional view of the structure shown. Figure 5A Shows Figure 4 The reference section A1-A1 in FIG. 2 passes through the portion of the protruding fin 28 that is not covered by the gate stack 30 and the gate spacer 38 and is perpendicular to the gate longitudinal direction. The fin spacer 38 on the sidewall of the protruding fin 28 is also shown. Figure 5B Shows Figure 4 The reference cross section BB in FIG. 2 is parallel to the longitudinal direction of the protruding fin 28 .

[0036] refer to Fig. 6A and Figure 6B, the portion of the protruding fin 28 that is not directly below the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. The corresponding process is shown as process 210 in the process flow 200 shown in Figure 22. For example, a dry etching process can be performed using C2F6, CF4, SO2, a mixture of HBr, Cl2 and O2, a mixture of HBr, Cl2, O2 and CH2F2, etc. to etch the multilayer semiconductor stack 22' and the substrate strip 20' below. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or can be lower than the bottom of the multilayer semiconductor stack (such as Figure 6B ). The etching may be anisotropic so that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown in FIG. Figure 6B shown.

[0037] refer to Fig. 7A and Figure 7B , the sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed from the edges of the corresponding upper and lower nanostructures 22B. The corresponding process is shown as process 212 in the process flow 200 shown in Figure 22. The lateral recess of the sacrificial semiconductor layer 22A can be achieved by a wet etching process using an etchant that is more selective to the material of the sacrificial semiconductor layer 22 (e.g., silicon germanium (SiGe)) than the material of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment in which the sacrificial semiconductor layer 22A is formed of silicon germanium and the nanostructure 22B is formed of silicon, an etchant such as hydrochloric acid (HCl) can be used to perform the wet etching process. The wet etching process can be performed using an immersion process, a spraying process, a spin coating process, etc.

[0038] According to alternative embodiments, the lateral recessing of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0039] refer to Fig. 8A and Figure 8B , forming the inner spacer 44. The corresponding process is shown as process 214 in the process flow 200 shown in FIG. 22. According to some embodiments, the formation of the inner spacer 44 includes depositing a conformal dielectric layer that extends into the lateral recess 41 ( Figure 7B Next, an etching process (also referred to as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral recess 41, leaving the portion of the spacer layer in the lateral recess 41. The remaining portion of the spacer layer is referred to as an inner spacer 44.

[0040] Fig.9A and Fig. 9BA cross-sectional view and a perspective view of forming source / drain regions 48 in recesses 42 by epitaxy are shown. The corresponding process is shown as process 216 in process flow 200 shown in FIG. 22 . Source / drain regions may be referred to individually or collectively as source or drain, depending on the context. According to some embodiments, source / drain regions 48 may exert stress on nanostructures 22B that serve as channels for corresponding GAA transistors, thereby improving performance.

[0041] According to some embodiments, the corresponding transistor is n-type, and the epitaxial source / drain region 48 is correspondingly formed to be n-type by doping with n-type dopants. For example, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown to form the epitaxial source / drain region 48. According to alternative embodiments, the corresponding transistor is p-type, and the epitaxial source / drain region 48 is correspondingly formed to be p-type by doping with p-type dopants. For example, silicon boron (SiB), silicon germanium boron (SiGeB), etc. can be grown to form the epitaxial source / drain region 48. After filling the recess 42 with the epitaxial source / drain region 48, further epitaxial growth of the epitaxial source / drain region 48 causes the epitaxial source / drain region 48 to expand horizontally, and a small facet can be formed. Further growth of the epitaxial source / drain region 48 may also cause adjacent epitaxial source / drain regions 48 to merge with each other, thereby forming a gap 49 ( Fig. 10C ).

[0042] After the epitaxial process, the epitaxial source / drain regions 48 may be further implanted with n-type impurities or p-type impurities to form source and drain regions, which are also indicated by reference numeral 48. According to an alternative embodiment of the present disclosure, when the epitaxial source / drain regions 48 are in-situ doped with n-type impurities or p-type impurities during epitaxy, the implantation process is skipped and the epitaxial source / drain regions 48 are also source / drain regions.

[0043] Fig. 10A and Fig. 10B A cross-sectional view of the structure after forming a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52 is shown. The corresponding process is shown as process 218 in the process flow 200 shown in Figure 22. CESL 50 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, using phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, undoped silicate glass, etc.

[0044] CESL 50 and ILD 52 are planarized by a planarization process such as a CMP process or a mechanical grinding process. According to some embodiments, the planarization process may remove hard mask 36 to expose dummy gate electrode 34, such as Fig. 10A According to alternative embodiments, the planarization process may expose hard mask 36 and stop on hard mask 36. According to some embodiments, after the planarization process, the top surfaces of dummy gate electrode 34 (or hard mask 36), gate spacer 38, and ILD 52 are flush within process variations.

[0045] Fig. 10C According to some embodiments Fig. 10A and 10B A top view of the structure shown. The multilayer stack 22', substrate strip 20' and protruding fin 28 (see Fig. 10A ) has a longitudinal direction in the X direction, and the corresponding cross-sectional view is referred to as an X-cut view. The gate stack 30 including the dummy gate electrode 34 (e.g., a polysilicon strip) has a longitudinal direction in the Y direction, and the corresponding cross-sectional view is referred to as a Y-cut view. The source / drain region 48 is formed based on some parts of the multilayer stack 22 ′ (e.g., Figure 5B and 10B ). The edges of the source / drain regions may be in contact with the gate spacer 38 or may be spaced apart from the gate spacer 38.

[0046] Fig.11 A top view of the formation of a cut metal gate (CMG) region 110 is shown, which is formed to separate / divide the dummy gate stack 30, thereby dividing the subsequently formed replacement (metal) gate stack 70 into shorter parts. The corresponding process is shown as process 220 in the process flow 200 shown in FIG. 22. The CMG isolation region 110 is also referred to as the gate isolation region 110. According to some embodiments, as Fig.11 As shown, the CMG isolation region 110 is formed by cutting the dummy gate stack 30. According to an alternative embodiment, the CMG isolation region 110 is formed by cutting the replacement gate stack 70, such as Fig.14 Therefore, the CMG isolation region 110 is Fig.11 1 is shown as a dotted line to indicate that the CMG isolation region 110 may have been formed in Fig.11 The structure shown may not have been formed in Fig.11 In the structure shown.

[0047] The detailed process of forming the CMG isolation region 110 can be obtained from Figure 17-21 Although Figure 17-21 A process of cutting the replacement gate stack 70 to form the CMG isolation region 110 is shown, but the same process can also be used to cut the dummy gate stack 30 .

[0048] Fig.11 1 further illustrates a top view of the formation of the fin isolation region 112. According to some embodiments, as Fig.11 As shown, the fin isolation region 112 is a continuous polysilicon on diffusion edge (CPODE) region, and its formation involves etching the dummy gate stack 30, the multilayer stack 22' and the substrate strip 20'. The corresponding process is also shown as process 220 in the process flow 200 shown in Figure 22. According to an alternative embodiment, the fin isolation region 112 is formed by cutting the replacement gate stack 70 and the semiconductor region below, as shown in Fig.14 Therefore, the fin isolation region 112 is Fig.11 1 is also shown as a dotted line to indicate that the fin isolation region 12 may have been formed in Fig.11 The structure shown may not have been formed in Fig.11 In the structure shown.

[0049] The detailed process of forming the fin isolation region 112 by cutting the dummy gate stack 30 is as follows: Fig.22A and FIG. 22B to FIG. 28A and Fig.28B The detailed process of forming the fin isolation region 112 by cutting and replacing the gate stack 70 is shown in FIG. Fig.29A and FIG. 29B to FIG. 33A and Fig.33B As shown, a discussion will follow.

[0050] Next, the dummy gate electrode 34 and the dummy gate dielectric 32 (and the hard mask 36, if any) are removed in one or more etching processes, thereby forming the recess 58, as shown in FIG. Fig. 12A and 12B As shown. The corresponding process is shown as process 222 in the process flow 200 shown in Figure 22. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by an anisotropic dry etching process. For example, the etching process can be performed using (one or more) reactive gases that selectively etches the dummy gate electrode 34 and the dummy gate dielectric 32 at a faster rate than the ILD 52. Each recess 58 exposes and / or overlies a portion of the multilayer stack 22', which includes a future channel region in a subsequently completed transistor. If the CMG isolation region 110 has been formed, the CMG isolation region 110 (as shown in dashed lines in Figure 12) separates the long recess 58 into shorter portions.

[0051] The sacrificial layer 22A is then removed to extend the recess 58 between the nanostructures 22B. The corresponding process is shown as process 224 in the process flow 200 shown in Figure 22. The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process) using an etchant that is selective to the material of the sacrificial layer 22A, while the nanostructures 22B, the substrate 20, and the STI regions 26 remain relatively unetched compared to the sacrificial layer 22. According to some embodiments in which the sacrificial layer 22A includes, for example, SiGe and the nanostructures 22B include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to remove the sacrificial layer 22A.

[0052] refer to Fig.13A and Fig. 13B , forming a gate dielectric 62 and a gate electrode 68, thereby forming a replacement gate stack 70. The corresponding process is shown as process 226 in the process flow 200 shown in Figure 22. According to some embodiments, each gate dielectric 62 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer can be formed of or include silicon oxide, which can be deposited by a conformal deposition process such as ALD or CVD or by an oxidation process. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, (one or more) high-k dielectric layers may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0053] A gate electrode 68 is also formed. In the formation, a conductive layer is first formed on the high-k dielectric layer and fills the remaining portion of the recess 58. The gate electrode 68 may include a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, the gate electrode 68 may include any number of layers, any number of work function layers, and may include a fill material. The gate dielectric 62 and the gate electrode 68 also fill the space between adjacent nanostructures 22B and fill the space between the bottom nanostructure 22 and the substrate strip 20' below. After filling the recess 58, a planarization process such as a CMP process or a mechanical grinding process is performed to remove excess portions of the gate dielectric and the material of the gate electrode 68, which are above the top surface of the ILD 52. The gate electrode 68 and the gate dielectric 62 are collectively referred to as the gate stack 70 of the resulting transistor.

[0054] Fig. 13C According to some embodiments Fig.13A and 13B Top view of the structure shown. Fig. 13C The structure shown is Fig.11 The structures shown are similar except that Fig. 10C The gate dummy stack 30 in the Fig. 13C The nanostructure 22B and the semiconductor strip 20' below have a lengthwise direction in the X direction.

[0055] As described above, CMG isolation region 110 may already be Fig.11 Alternatively, the CMG isolation region 110 may not have been formed. Similarly, the fin isolation region 112 may have been formed. Fig.11 Alternatively, the fin isolation region 112 may not have been formed. Therefore, if the CMG isolation region 110 and the fin isolation region 112 have not been formed, then Fig.14 The corresponding process is shown as process 228 in the process flow 200 shown in FIG.

[0056] The detailed process of forming the CMG isolation region 110 is as follows: Figure 17-Figure 21 The detailed process of forming the fin isolation region 112 by cutting and replacing the gate stack 70 is shown in FIG. Fig.29A and FIG. 29B to FIG. 33A and Fig.33B As shown, a discussion will follow.

[0057] According to some embodiments, Fig.11 and Fig.14 As shown, the CMG isolation region 110 is physically separated from the fin isolation region 112 and does not contact the fin isolation region 112. Therefore, the formation of the CMG isolation region 110 and the formation of the fin isolation region 112 do not affect each other. Therefore, the CMG isolation region 110 can be formed before or after forming the fin isolation region 112, regardless of whether the fin isolation region 112 is formed by cutting a dummy gate stack or a replacement gate stack.

[0058] Fig.15A Shows Fig.14 The cross section of the structure shown in FIG. 1 is a diagram in which a CMG isolation region 110 is formed to cut the long metal gate stack 70 into metal gate stacks (portions) 70A and 70B. Next, as shown in FIG. Fig.15A and Fig. 15B As shown, the gate stack 70 is recessed so that recesses (occupied by the CMG isolation regions 110) are formed directly above the gate stack 70 and between opposing portions of the gate spacers 38. A gate mask 74 including one or more layers of a dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each recess, followed by a planarization process to remove excess portions of the dielectric material extending over the ILD 52.

[0059] like Fig.15A and Fig. 15BAs shown, ILD 76 is deposited on ILD 52 and gate mask 74. The corresponding process is shown as process 230 in process flow 200 shown in FIG. 22. An etch stop layer (not shown) may or may not be deposited before forming ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, etc. ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0060] exist Fig.16A and Fig. 16B In the process, ILD 76, ILD 52, CESL 50 and gate mask 74 are etched to form a recess (occupied by contact plugs 80A and 80B) exposing the source / drain region 48 and / or the surface of gate stack 70. The recess can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.).

[0061] After the recess is formed, a silicide region 78 is formed on the source / drain region 48. The corresponding process is shown as process 232 in the process flow 200 shown in FIG. 22. A contact plug 80B is then formed on the silicide region 78. In addition, a contact 80A (also referred to as a gate contact plug) is formed in the recess and is above and contacts the gate electrode 68. The corresponding process is shown as process 234 in the process flow 200 shown in FIG. 22. In this way, transistors 82A and 82B are formed. Although Fig. 16B The contact plugs 80A and 80B are shown in the same cross section, but in various embodiments, the contact plugs 80 may be formed in different cross sections to reduce the risk of shorting each other.

[0062] Figures 17 to 21 The formation of CMG isolation regions 110 is shown in accordance with some embodiments. Fig.17 A cross-sectional view of an intermediate structure is shown. Fig.13A As shown, the gate stack 70 has been formed and includes the gate dielectric 62 and the gate electrode 68 , while the CMG isolation region 110 has not yet been formed.

[0063] According to some embodiments, hard mask layer 88 is deposited and may include a multi-layer structure including multiple layers. According to some embodiments, hard mask layer 88 includes silicon nitride layer 88A, silicon layer 88B, and silicon nitride layer 88C. According to alternative embodiments, a single-layer hard mask 88 is used, which may be formed of or include silicon nitride.

[0064] Then, an etching mask 90 is formed, such as Fig.18As shown. The etching mask 90 may also have a single-layer structure (which may include a photoresist) or a double-layer structure including a bottom anti-reflective coating (BARC) and a photoresist. Alternatively, the etching mask 90 may have three layers, which may include a bottom layer, an intermediate layer on the bottom layer, and a top layer, and the top layer may be a patterned photoresist. Grooves 92 are formed in the etching mask 90.

[0065] Next, hard mask layer 88 is etched using etch mask 90 so that trench 92 extends into hard mask layer 88. The etch may be anisotropic. According to some embodiments, trench 92 extends to the top surface of hard mask 88A. Etch mask 90 may be removed after trench 92 is formed in hard mask layer 88.

[0066] Next, the same Fig.19 As shown, replacement gate stack 70 is etched. The etching of replacement gate stack 70 is anisotropic. According to some embodiments, etching is performed until STI region 26 is exposed. Trench 92 may or may not extend into STI region 26. After the etching process, hard mask layer 88 may or may not be removed. Gate stack 70 is thus separated into gate stacks 70A and 70B.

[0067] In the subsequent process, a dielectric layer 110 is deposited, such as Fig. 20 The dielectric layer 110 may have a multi-layer structure (eg, including a dielectric layer 110A and a dielectric layer 110B) or may have a single-layer structure. The dielectric layer 110 and the sub-layers therein may include SiO, SiN, SiCON, SiCN, SiON, SiCO, etc.

[0068] After the dielectric layer 110 is deposited, a planarization process, such as a CMP process or a mechanical grinding process, is performed. The planarization process may be stopped on the top surface of the gate stack 70. The remaining portions of the dielectric layers 110A and 110B are collectively referred to as CMG isolation regions 110 hereinafter. Fig.21 As shown. Fig.21 After the process shown, perform Fig.15A , Fig. 15B , Fig.16A and Fig. 16B The remaining processes are shown to complete the formation of GAA transistors 82A and 82B.

[0069] The CMG isolation region 110 is formed by cutting the dummy gate stack 30 and Figures 17 to 21 The illustrations are substantially the same except that the dummy gate stack 30 is etched to form trenches, and the CMG isolation regions 110 are formed in the corresponding trenches.

[0070] Fig.22A and FIG. 22B to FIG. 28Aand Fig.28B The formation of the fin isolation region 112 according to some embodiments is shown (using a CPODE process). In the subsequent figures, the figures with the letter A after the corresponding figure number are from Fig.11 or Fig.14 The Y-cut (along the Y direction) in the figure is obtained, while the figure with the letter B after the corresponding figure number is obtained from Fig.11 Medium or Fig.14 The X-cut (along the X direction) is obtained.

[0071] Fig.22A and Fig. 22B Explained Fig. 10C The structures in the figure are obtained from the cross-sectional Y-cut and X-cut, respectively. Fig.22A and 22B Also corresponds to Fig. 10A and 10B .therefore, Fig.22A The multilayer stack 22 ′ and a dummy gate stack 30 on the multilayer stack 22 ′ are shown. Fig. 22B The source / drain regions 48 , the multilayer stack 22 ′, the internal spacers 44 , and the dummy gate stack 30 are shown.

[0072] refer to Fig.23A and Fig. 23B , forming a hard mask 116. The hard mask 116 may include a dielectric material such as SiN, silicon, etc. or a multilayer thereof. A patterned etching mask 117 is formed on the hard mask 116. Next, as shown in FIG. Fig.24A and Fig. 24B As shown, the hard mask 116 is etched to form an opening 118, through which the dummy gate electrode 34 is exposed. The hard mask 116 is then used to etch through the underlying dummy gate electrode 34 until the dummy gate dielectric 32 is exposed, as shown in FIG. Fig.25A and Fig.25B The etching is anisotropic, so that the edge of the dummy gate electrode 34 facing the opening 118 is vertical and straight. In the etching process, the dummy gate dielectric 32 can be used as an etch stop layer.

[0073] Then, the dummy gate dielectric 32 is removed, for example, by an isotropic etching process, thereby exposing the multilayer stack 22'. The resulting structure is as shown in FIG. Fig.26A and 26B Next, an etching process (or processes) is performed to remove the exposed multilayer stack 22', and then further etch the underlying semiconductor material, such as the semiconductor strip 20'. Thus, an opening 120 is formed between adjacent STI regions 26, such as Fig.27A and 27B Opening 120 may extend to a level below the bottom surface of STI region 26 to reduce leakage.

[0074] Fig.28A and Fig.28B Filling of openings 118 and 120 to form CPODE isolation region 112 is shown. According to some embodiments, the filling process may include depositing a dielectric liner 112A, followed by depositing a dielectric layer 112B on the dielectric liner. According to some embodiments, the material of dielectric liner 112A and dielectric layer 112B may be selected from SiN, SiO, SiON, SiOCN, SiCN, etc. or a combination thereof. A planarization process such as a CMP process may then be performed to form fin isolation region 112, which is a CPODE isolation region, also as shown in FIG. Fig.11 shown.

[0075] Fig.29A and FIG. 29B to FIG. 33A and Fig.33B The formation of the fin isolation region 112 formed by cutting the metal gate stack 70 is shown, so the fin isolation region 112 a is also a CMODE region. Fig.29A and Fig.29B Explained Fig. 13C The structure in the figure is obtained from the cross-section Y cutting and X cutting respectively. Fig.29A and Fig.29B Also corresponds to Fig.13A and Fig. 13B . Fig.29A and FIG. 29B to FIG. 33A and Fig.33B The process shown is Fig.22A and FIG. 22B to FIG. 28A and Fig.28B The illustrated embodiment is substantially the same except that a replacement gate stack (rather than a dummy gate stack) is etched.

[0076] Fig.29A and Fig.29B A replacement gate stack 70 is illustrated. A hard mask layer 126 is formed on the replacement gate stack 70. The hard mask layer 126 may have a similar structure and material as the hard mask layer 88 ( Fig.17 ). For example, the hard mask layer 126 may include a first silicon nitride layer, a silicon layer on the first silicon nitride layer, and a second silicon nitride layer on the silicon layer.

[0077] Fig. 30A and Fig. 30B The formation of an etch mask 128 is shown, which may be a triple layer according to some embodiments. For example, the triple layer may include a carbon base layer, an oxide-based intermediate layer, and a patterned photoresist as a top layer.

[0078] Fig.31A and 31B 1 shows that an opening 118 is formed in the hard mask layer 126 by etching. Next, as shown in FIG. Fig.32A and Fig.32B As shown, the replacement gate stack 70 and the semiconductor nanostructure 22B are etched in an anisotropic etching process to extend the opening 118 into the replacement gate stack 70. The portion of the semiconductor strip 20' directly below the opening 118 is then etched to form an opening 120.

[0079] Fig.33A and Fig.33B Filling of openings 118 and 120 to form fin isolation region 112 is shown, which is a CMODE isolation region. Process and Materials and References Fig.28A and Fig.28B The processes and materials of the region 112 discussed are basically the same and will not be repeated here. Fig.14 shown.

[0080] Fig.34 A top view of the CMG isolation region 110, the fin isolation region 112 and their relationship to the replacement gate stack 70 is shown. It should be understood that Fig.14 and Fig.34 The structures in are examples and may coexist in the same device die. According to some embodiments, the CMG isolation region 110 is formed to have a lengthwise direction parallel to the X direction, and the fin isolation region 112 is formed to have a lengthwise direction parallel to the Y direction.

[0081] Due to the separation of the CMG isolation region 110 from the fin isolation region 112, there may be some regions separating the CMG isolation region 110 from its adjacent fin isolation region 112. For example, Fig.34 Region 140 (including regions 140A, 140B, and 140C) is shown. Region 140, while part of a long gate stack strip, is not part of a transistor. According to some embodiments, part or all of region 140 is formed of the same material as replacement gate stack 70 and is formed in the same process as replacement gate stack 70.

[0082] According to some embodiments, some or all of the regions 140 are formed of the same material as the dummy gate stack 30 that is not replaced, and are formed in the same process as the dummy gate stack 30. According to yet another alternative embodiment, in the final structure after the transistor has been formed, some of the regions 140 are formed of the same material as the dummy gate stack 30, and are formed in the same process as the dummy gate stack 30, while some other regions 140 are formed of the same material as the replacement gate stack 70, and are formed in the same process as the replacement gate stack 70.

[0083] According to some embodiments, each region 140 can be electrically floating or electrically grounded, depending on the process and performance requirements of the circuit. According to some embodiments, some regions 140 are electrically grounded while other regions 140 are electrically floating, or alternatively, all regions 140 are electrically grounded or electrically floating.

[0084] The length of the CMG isolation regions 110 may be selected based on the layout of the circuit. According to some embodiments, in the formation of some CMG isolation regions 110, the gate spacers 38 on the opposite sides of the respective gate stacks 70 (or dummy gate stacks 30) are also etched, so that the CMG isolation regions 110 extend laterally (in the X direction) beyond the spacers 38. According to alternative embodiments, some or all of the CMG isolation regions 110 are bounded by opposing gate spacers 38. For example, Fig.34 As shown, dashed lines 142 indicate that gate spacers 38 may have opposite ends (left and / or right ends) that contact the gate spacers. Some of CMG isolation regions 110 may cut into gate spacers 38 and may extend laterally beyond gate spacers 38 into adjacent ILD regions.

[0085] The length of the CMG isolation region 110 may also extend longer than shown. Fig.34 , assuming that no source / drain region is formed in the region indicated by the dotted line 51 , the nearby CMG isolation region 110 may further extend to the left to a position indicated by the dotted line 144 .

[0086] According to some embodiments, the CMG isolation regions 110 are completely spaced apart from the fin isolation regions 112, and no CMG isolation regions 110 physically engage any fin isolation regions 112 throughout the respective device die and wafer. The CMG isolation regions 110 will also be spaced apart from and not in contact with the source / drain regions 48. Keeping the CMG isolation regions 110 spaced apart from the fin isolation regions 112 is advantageous because it will reduce the interaction between the formation processes of the CMG isolation regions 110 and the fin isolation regions 112. For example, in Fig.14 In FIG. 1 , if a long CMG isolation region is formed and includes the CMG isolation regions 110 - 1 and 110 - 2 and the portion in the dashed box 110 - 3 , the CMG isolation region will intersect the fin isolation region 112 in the dashed box 110 - 2 . Fig.33A As shown, STI region 26 is located directly below fin isolation region 112. CMG isolation region 110 will cut into fin isolation region 112, damaging underlying STI region 26 and undesirably forming a deep recess therein.

[0087] According to some embodiments, Fig.14 and 34As shown, the replacement gate stack 70 is formed as a long strip extending in the Y direction. CMG isolation regions 110 may be formed on some replacement gate stacks 70, while fin isolation regions 112 are formed on their adjacent replacement gate stacks 70. The formation of the CMG isolation regions 110 and the fin isolation regions 112 electrically isolates transistors used to form a functional circuit. For example, Fig.34 An inverter 150 is shown comprising four active gates. There may also be an inverter 152 having two active gates and an inverter 154 having a single active gate.

[0088] According to some embodiments, the width W1 ( Fig.14 ) may be in a range between about 5 nm and about 15 nm. The width W2 of the CMG isolation region 112 may be close to the width W3 of the STI region 26 ( Fig.33A ), which may be in a range between about 30 nm and about 50 nm according to some embodiments.

[0089] Embodiments of the present disclosure have some advantageous features. By forming CMG isolation regions (CPODE and / or CMODE isolation regions) that are spaced apart from and do not intersect the fin isolation regions, adverse effects such as damage to epitaxial regions, metals, and semiconductor nanostructures are eliminated. In addition, it is easy to space short CMG isolation regions from nearby epitaxial regions, and there is no need to reduce the width of the CMG isolation regions in order to pass between adjacent epitaxial regions. This advantageously eliminates the possibility of increasing parasitic capacitance and difficulties in the formation process due to the formation of narrow CMG isolation regions.

[0090] According to some embodiments of the present disclosure, a method includes: forming a plurality of semiconductor regions, the semiconductor regions having a first longitudinal direction, the first longitudinal direction being parallel to the first direction; forming a plurality of gate stacks, the gate stacks having a second longitudinal direction, the second longitudinal direction being parallel to the second direction, the second direction being perpendicular to the first direction, wherein the plurality of gate stacks are on a first portion of the plurality of semiconductor regions; etching the plurality of gate stacks to form a first plurality of openings, wherein the first plurality of openings separate the plurality of gate stacks into first shorter portions; filling the first plurality of openings to form a gate isolation region; etching the plurality of semiconductor regions to form a second plurality of openings, wherein the second plurality of openings separate the plurality of semiconductor regions into second shorter portions; and filling the second plurality of openings to form a fin isolation region, wherein the gate isolation region is spaced apart from the fin isolation region.

[0091] In one embodiment, the gate isolation regions and the fin isolation regions are in the device die, and wherein all gate isolation regions of the device die are spaced apart from all fin isolation regions of the device die. In one embodiment, etching a plurality of gate stacks comprises: etching a plurality of dummy gate stacks, and the method further comprises: after forming the gate isolation regions, replacing a first shorter portion of the dummy gate stack with a replacement gate stack. In one embodiment, etching a plurality of gate stacks comprises: etching a plurality of replacement gate stacks. In one embodiment, when the plurality of gate stacks are etched, gate spacers on sidewalls of the plurality of gate stacks are also etched.

[0092] In one embodiment, the method further comprises: forming a plurality of source / drain regions based on the second portion of the plurality of semiconductor regions, wherein the gate isolation region is physically separated from the nearest source / drain region. In one embodiment, in a top view of the plurality of semiconductor regions and the plurality of gate stacks, a gate isolation region of the gate isolation regions is between a first semiconductor region and a second semiconductor region of the plurality of semiconductor regions.

[0093] In one embodiment, a bottom of the second plurality of openings is lower than the dielectric isolation regions on opposite sides of the second plurality of openings. In one embodiment, etching the plurality of semiconductor regions includes etching the semiconductor nanostructures and the semiconductor strips below the semiconductor nanostructures.

[0094] According to some embodiments of the present disclosure, a structure includes: multiple semiconductor regions; a gate stack, the gate stack including multiple parts aligned with a straight line; multiple gate isolation regions, the gate isolation regions having a longitudinal direction in a first direction; multiple fin isolation regions, the fin isolation regions having a longitudinal direction in a second direction, the second direction being perpendicular to the first direction, wherein the multiple fin isolation regions separate the multiple parts of the gate stack from each other and separate some of the multiple semiconductor regions into shorter parts; and multiple source / drain regions on opposite sides of the gate stack, wherein the multiple gate isolation regions are physically separated from the multiple fin isolation regions and physically separated from the multiple source / drain electrode regions.

[0095] In one embodiment, the plurality of semiconductor regions comprise semiconductor nanostructures. In one embodiment, the plurality of semiconductor regions comprise semiconductor fins. In one embodiment, the semiconductor regions are located in a device die, and wherein within the device die, all gate isolation regions are spaced apart from all fin isolation regions. In one embodiment, the structure comprises a first gate spacer and a second gate spacer on opposite sides of a gate stack, wherein one of the gate isolation regions is between the first gate spacer and the second gate spacer. In one embodiment, the plurality of portions of the gate stack comprise metal gates. In one embodiment, the plurality of portions of the gate stack comprise a gate dielectric, the gate dielectric separating respective gate electrodes from the plurality of fin isolation regions.

[0096] According to some embodiments of the present disclosure, a structure includes: a semiconductor substrate; a plurality of shallow trench isolation regions located above a main portion of the semiconductor substrate; a plurality of transistors including: a plurality of nanostructures, wherein an upper nanostructure among the plurality of nanostructures overlaps with a corresponding lower nanostructure among the plurality of nanostructures; a plurality of gate stacks on the plurality of nanostructures, wherein the plurality of gate stacks include a first portion between the plurality of nanostructures; a plurality of gate isolation regions separating the plurality of gate stacks from each other, wherein the plurality of gate isolation regions have a bottom portion that contacts a top surface of the plurality of shallow trench isolation regions; and a plurality of fin isolation regions separating the plurality of nanostructures from each other, wherein the plurality of fin isolation regions include a second portion between the plurality of shallow trench isolation regions, the bottom portions of the plurality of fin isolation regions are lower than the shallow trench isolation regions, and wherein the plurality of fin isolation regions are physically spaced apart from the plurality of gate isolation regions.

[0097] In one embodiment, the plurality of gate isolation regions are separated from all source / drain regions of the plurality of transistors. In one embodiment, the plurality of transistors further include two gate spacers on opposite sides of one of the plurality of gate stacks, wherein one of the gate isolation regions forms an interface with the two gate spacers, and the interface is parallel to the longitudinal direction of the plurality of gate stacks. In one embodiment, the plurality of transistors further include two gate spacers on opposite sides of one of the plurality of gate stacks, wherein one of the gate isolation regions separates one of the two gate spacers into two portions.

[0098] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0099] Example 1 is a method for forming a semiconductor structure, comprising: forming a plurality of semiconductor regions, the semiconductor regions having a first longitudinal direction, the first longitudinal direction being parallel to a first direction; forming a plurality of gate stacks, the gate stacks having a second longitudinal direction, the second longitudinal direction being parallel to a second direction, the second direction being perpendicular to the first direction, wherein the plurality of gate stacks are on a first portion of the plurality of semiconductor regions; etching the plurality of gate stacks to form a first plurality of openings, wherein the first plurality of openings separate the plurality of gate stacks into first shorter portions; filling the first plurality of openings to form a gate isolation region; etching the plurality of semiconductor regions to form a second plurality of openings, wherein the second plurality of openings separates the plurality of semiconductor regions into second shorter portions; and filling the second plurality of openings to form a fin isolation region, wherein the gate isolation region is spaced apart from the fin isolation region.

[0100] Example 2 is the method of Example 1, wherein the gate isolation region and the fin isolation region are in a device die, and wherein all gate isolation regions of the device die are spaced apart from all fin isolation regions of the device die.

[0101] Example 3 is the method described in Example 1, wherein etching the multiple gate stacks includes: etching multiple dummy gate stacks, and the method further includes: after forming the gate isolation region, replacing the first shorter portion of the dummy gate stack with a replacement gate stack.

[0102] Example 4 is the method of Example 1, wherein etching the plurality of gate stacks comprises etching a plurality of replacement gate stacks.

[0103] Example 5 is the method of Example 1, wherein when the plurality of gate stacks are etched, gate spacers on sidewalls of the plurality of gate stacks are also etched.

[0104] Example 6 is the method of Example 1, further comprising: forming a plurality of source / drain regions based on a second portion of the plurality of semiconductor regions, wherein the gate isolation region is physically separated from the nearest source / drain region.

[0105] Example 7 is the method described in Example 1, wherein, in a top view of the multiple semiconductor regions and the multiple gate stacks, a gate isolation region in the gate isolation region is between a first semiconductor region and a second semiconductor region of the multiple semiconductor regions.

[0106] Example 8 is the method of Example 1, wherein bottoms of the second plurality of openings are lower than dielectric isolation regions on opposite sides of the second plurality of openings.

[0107] Example 9 is the method of Example 1, wherein etching the plurality of semiconductor regions comprises etching semiconductor nanostructures and semiconductor strips beneath the semiconductor nanostructures.

[0108] Example 10 is a semiconductor structure comprising: a plurality of semiconductor regions; a gate stack comprising a plurality of portions aligned with a straight line; a plurality of gate isolation regions having a longitudinal direction in a first direction; a plurality of fin isolation regions having a longitudinal direction in a second direction, the second direction being perpendicular to the first direction, wherein the plurality of fin isolation regions separate the plurality of portions of the gate stack from each other and separate some of the plurality of semiconductor regions into shorter portions; and a plurality of source / drain regions on opposite sides of the gate stack, wherein the plurality of gate isolation regions are physically separated from the plurality of fin isolation regions and physically separated from the plurality of source / drain regions.

[0109] Example 11 is the structure of Example 10, wherein the plurality of semiconductor regions include semiconductor nanostructures.

[0110] Example 12 is the structure of Example 10, wherein the plurality of semiconductor regions include semiconductor fins.

[0111] Example 13 is the structure of Example 10, wherein the semiconductor region is in a device die, and wherein within the device die, all gate isolation regions are spaced apart from all fin isolation regions.

[0112] Example 14 is the structure described in Example 10, further comprising: a first gate spacer and a second gate spacer on opposite sides of the gate stack, wherein one of the gate isolation regions is between the first gate spacer and the second gate spacer.

[0113] Example 15 is the structure of Example 10, wherein the multiple portions of the gate stack include metal gates.

[0114] Example 16 is the structure of Example 10, wherein the portions of the gate stack include a gate dielectric that separates the corresponding gate electrodes from the plurality of fin isolation regions.

[0115] Example 17 is a semiconductor structure comprising: a semiconductor substrate; a plurality of shallow trench isolation regions located above a main portion of the semiconductor substrate; a plurality of transistors comprising: a plurality of nanostructures, an upper nanostructure of the plurality of nanostructures overlapping with a corresponding lower nanostructure of the plurality of nanostructures; a plurality of gate stacks on the plurality of nanostructures, wherein the plurality of gate stacks include a first portion between the plurality of nanostructures; a plurality of gate isolation regions separating the plurality of gate stacks from each other, wherein the plurality of gate isolation regions have a bottom portion that contacts a top surface of the plurality of shallow trench isolation regions; and a plurality of fin isolation regions separating the plurality of nanostructures from each other, wherein the plurality of fin isolation regions include a second portion between the plurality of shallow trench isolation regions, the bottom portions of the plurality of fin isolation regions are lower than the shallow trench isolation regions, and wherein the plurality of fin isolation regions are physically spaced apart from the plurality of gate isolation regions.

[0116] Example 18 is the structure of Example 17, wherein the plurality of gate isolation regions are separated from all source / drain regions of the plurality of transistors.

[0117] Example 19 is the structure described in Example 17, wherein the multiple transistors further include two gate spacers on opposite sides of a gate stack among the multiple gate stacks, wherein one of the gate isolation regions forms an interface with the two gate spacers, and the interface is parallel to the longitudinal direction of the multiple gate stacks.

[0118] Example 20 is the structure described in Example 17, wherein the plurality of transistors further include two gate spacers on opposite sides of a gate stack among the plurality of gate stacks, wherein one of the gate isolation regions separates one of the two gate spacers into two parts.

Claims

1. A method for forming a semiconductor structure, comprising: forming a plurality of semiconductor regions, the semiconductor regions having a first longitudinal direction parallel to the first direction; forming a plurality of gate stacks, the gate stacks having a second longitudinal direction, the second longitudinal direction being parallel to a second direction, the second direction being perpendicular to the first direction, wherein the plurality of gate stacks are on a first portion of the plurality of semiconductor regions; etching the plurality of gate stacks to form a first plurality of openings, wherein the first plurality of openings separate the plurality of gate stacks into first shorter portions; filling the first plurality of openings to form gate isolation regions; etching the plurality of semiconductor regions to form a second plurality of openings, wherein the second plurality of openings separate the plurality of semiconductor regions into second shorter portions; and The second plurality of openings are filled to form a fin isolation region, wherein the gate isolation region is spaced apart from the fin isolation region.

2. The method according to claim 1, wherein: The gate isolation regions and the fin isolation regions are in a device die, and wherein all gate isolation regions of the device die are spaced apart from all fin isolation regions of the device die.

3. The method according to claim 1, wherein: Etching the plurality of gate stacks includes etching a plurality of dummy gate stacks, and the method further includes replacing the first shorter portion of the dummy gate stack with a replacement gate stack after forming the gate isolation region.

4. The method according to claim 1, wherein: Etching the plurality of gate stacks includes etching a plurality of replacement gate stacks.

5. The method according to claim 1, wherein: When the gate stacks are etched, the gate spacers on the sidewalls of the gate stacks are also etched.

6. The method according to claim 1, further comprising: A plurality of source / drain regions are formed based on a second portion of the plurality of semiconductor regions, wherein the gate isolation region is physically separated from a nearest source / drain region.

7. The method according to claim 1, wherein: In a top view of the plurality of semiconductor regions and the plurality of gate stacks, a gate isolation region in the gate isolation region is between a first semiconductor region and a second semiconductor region of the plurality of semiconductor regions.

8. The method according to claim 1, wherein: Bottom portions of the second plurality of openings are lower than dielectric isolation regions on opposite sides of the second plurality of openings.

9. A semiconductor structure comprising: multiple semiconductor regions; a gate stack comprising a plurality of portions aligned with a straight line; a plurality of gate isolation regions, the gate isolation regions having a lengthwise direction in a first direction; a plurality of fin isolation regions, the fin isolation regions having a lengthwise direction in a second direction, the second direction being perpendicular to the first direction, wherein the plurality of fin isolation regions separate the plurality of portions of the gate stack from each other and separate some of the plurality of semiconductor regions into shorter portions; and A plurality of source / drain regions are on opposite sides of the gate stack, wherein the plurality of gate isolation regions are physically separated from the plurality of fin isolation regions and physically separated from the plurality of source / drain regions.

10. A semiconductor structure comprising: Semiconductor substrate; a plurality of shallow trench isolation regions located above a main portion of the semiconductor substrate; Multiple transistors, including: a plurality of nanostructures, an upper nanostructure in the plurality of nanostructures overlapping a corresponding lower nanostructure in the plurality of nanostructures; a plurality of gate stacks on the plurality of nanostructures, wherein the plurality of gate stacks include a first portion between the plurality of nanostructures; a plurality of gate isolation regions separating the plurality of gate stacks from each other, wherein the plurality of gate isolation regions have bottoms that contact top surfaces of the plurality of shallow trench isolation regions; and A plurality of fin isolation regions separate the plurality of nanostructures from each other, wherein the plurality of fin isolation regions include a second portion between the plurality of shallow trench isolation regions, the bottoms of the plurality of fin isolation regions are lower than the shallow trench isolation regions, and wherein the plurality of fin isolation regions are physically spaced apart from the plurality of gate isolation regions.

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