Display substrate and display device

Abstract

This disclosure discloses a display substrate and a display device. The display substrate includes a substrate and a plurality of sub-pixels arrayed on the substrate; each sub-pixel includes: a data line pattern extending along a first direction; a power signal line pattern including a portion extending along the first direction; and a sub-pixel driving circuit, the sub-pixel driving circuit including: two switching transistors, a driving transistor, and a storage capacitor; a first electrode of the storage capacitor is coupled to the gate of the driving transistor, and a second electrode of the storage capacitor is coupled to the power signal line pattern; the second electrodes of both switching transistors are coupled to the first electrodes of the driving transistors, and the orthographic projection of the second electrode of at least one of the switching transistors onto the substrate at least partially overlaps with the orthographic projection of the power signal line pattern onto the substrate, and at least partially overlaps with the orthographic projection of the second electrode of the storage capacitor onto the substrate.

Description

[0001] This application is a divisional application of Chinese patent application No. 201980002702.4, filed on November 29, 2019. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diode (OLED) display products are widely used in various fields due to their advantages such as high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency.

[0004] As the application of OLED display products becomes more and more widespread, the requirements for the display quality of OLED display products are becoming higher and higher. There are many factors that affect the display quality of display products, among which the crosstalk phenomenon generated by the pixel circuit structure included in the display product has received widespread attention as an important factor.

[0005] Public content

[0006] The purpose of this disclosure is to provide a display substrate and a display device.

[0007] A first aspect of this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate; the sub-pixels comprising:

[0008] A data line pattern extending along the first direction;

[0009] A power signal line pattern, wherein the power signal line pattern includes a portion extending along the first direction;

[0010] A subpixel driving circuit includes: two switching transistors, a driving transistor, and a storage capacitor; a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the power signal line pattern; the second plates of the two switching transistors are both coupled to the first plates of the driving transistors, and the orthographic projection of the second plate of at least one of the two switching transistors onto the substrate at least partially overlaps with the orthographic projection of the power signal line pattern onto the substrate, and at least partially overlaps with the orthographic projection of the second plate of the storage capacitor onto the substrate.

[0011] Optionally, the second electrode of the two switching transistors and the first electrode of the driving transistor are integrally structured. The integral structure includes a first conductive portion extending along the first direction. The orthographic projection of the first conductive portion on the substrate has a first overlapping region with the orthographic projection of the power signal line pattern on the substrate and the orthographic projection of the second electrode plate of the storage capacitor on the substrate. The first overlapping region does not overlap with the orthographic projection of the data line pattern on the substrate.

[0012] Optionally, the orthographic projection of the first electrode of the driving transistor onto the substrate is located inside the orthographic projection of the second electrode of the storage capacitor onto the substrate.

[0013] Optionally, the sub-pixel further includes: a gate line pattern and a light emission control signal line pattern, both extending along the second direction, the second direction intersecting the first direction;

[0014] The sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switching transistors include a fourth transistor and a fifth transistor;

[0015] The gate of the fourth transistor is coupled to the gate line pattern, the first terminal of the fourth transistor is coupled to the data line pattern, the second terminal of the fourth transistor is coupled to the second terminal of the fifth transistor, the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first terminal of the fifth transistor is coupled to the power supply signal line pattern.

[0016] The gate of the first transistor is coupled to the gate line pattern, the second terminal of the first transistor is coupled to the gate of the driving transistor, the first terminal of the first transistor, the first terminal of the sixth transistor and the second terminal of the driving transistor are formed into an integral structure, the integral structure includes a second conductive portion extending along the first direction, the gate of the sixth transistor is coupled to the light emission control signal line pattern, and the second terminal of the sixth transistor is coupled to the light emission element in the sub-pixel.

[0017] The orthographic projection of the channel region of the driving transistor on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate; and along the second direction, the minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive portion on the substrate is less than the minimum distance between the orthographic projection of the channel region on the substrate and the orthographic projection of the second conductive portion on the substrate.

[0018] Optionally, the sub-pixel further includes: a gate line pattern and a light emission control signal line pattern, both extending along the second direction, the second direction intersecting the first direction;

[0019] The sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switching transistors include a fourth transistor and a fifth transistor;

[0020] The gate of the fourth transistor is coupled to the gate line pattern, the first terminal of the fourth transistor is coupled to the data line pattern, the second terminal of the fourth transistor is coupled to the second terminal of the fifth transistor, the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first terminal of the fifth transistor is coupled to the power supply signal line pattern.

[0021] The gate of the first transistor is coupled to the gate line pattern, the second terminal of the first transistor is coupled to the gate of the driving transistor, the first terminal of the first transistor, the first terminal of the sixth transistor and the second terminal of the driving transistor are formed into an integral structure, the integral structure includes a second conductive portion extending along the first direction, the gate of the sixth transistor is coupled to the light emission control signal line pattern, and the second terminal of the sixth transistor is coupled to the light emission element in the sub-pixel.

[0022] The orthographic projection of the channel region of the driving transistor on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate; the first electrode and the second electrode of the driving transistor both include a first portion extending along the second direction, and the length of the first portion of the first electrode along the second direction is different from the length of the first portion of the second electrode extending along the second direction.

[0023] Optionally, the sub-pixel further includes an initialization signal line pattern, the initialization signal line pattern including a portion extending along a second direction, the second direction intersecting the first direction, the initialization signal line pattern being used to transmit an initialization signal having a fixed potential;

[0024] The sub-pixel driving circuit further includes a second transistor coupled to the gate of the driving transistor, the second transistor comprising:

[0025] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern respectively, wherein the conductivity of the third conductor pattern is better than that of the first semiconductor pattern and the second semiconductor pattern.

[0026] A first gate pattern and a second gate pattern, wherein the orthographic projection of the first gate pattern on the substrate at least partially overlaps with the orthographic projection of the first semiconductor pattern on the substrate, and the orthographic projection of the second gate pattern on the substrate at least partially overlaps with the orthographic projection of the second semiconductor pattern on the substrate;

[0027] The orthographic projection of the third conductor pattern on the substrate does not overlap with the orthographic projection of the first gate pattern on the substrate, nor with the orthographic projection of the second gate pattern on the substrate;

[0028] The orthographic projection of the third conductor pattern onto the substrate at least partially overlaps with the orthographic projection of the initialization signal line pattern onto the substrate.

[0029] Optionally, the sub-pixel driving circuit further includes a first extension portion extending from the first semiconductor pattern, wherein the conductivity of the first extension portion is better than that of the first semiconductor pattern.

[0030] The first extension includes a first part, a second part, and a third part. The first part and the third part both extend along the first direction, and the second part extends along the second direction. One end of the second part is coupled to the first part, and the other end of the second part is coupled to the third part.

[0031] The end of the third portion furthest from the second portion is coupled to the first transistor.

[0032] Optionally, the sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the first transistor includes:

[0033] A fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern respectively, wherein the conductivity of the sixth conductor pattern is better than that of the fourth semiconductor pattern and the fifth semiconductor pattern;

[0034] A third gate pattern and a fourth gate pattern are coupled together, wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate;

[0035] The orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate, nor with the orthographic projection of the fourth gate pattern on the substrate.

[0036] Optionally, the sub-pixel further includes an initialization signal line pattern, the initialization signal line pattern including a portion extending along a second direction, the second direction intersecting the first direction, the initialization signal line pattern being used to transmit an initialization signal having a fixed potential;

[0037] The sub-pixel driving circuit also includes:

[0038] A first shielding component coupled to the initialization signal line pattern, wherein the orthographic projection of the first shielding component on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate.

[0039] Optionally, the sub-pixel further includes an initialization signal line pattern, the initialization signal line pattern including a portion extending along a second direction, the second direction intersecting the first direction, the initialization signal line pattern being used to transmit an initialization signal having a fixed potential;

[0040] The sub-pixel driving circuit also includes:

[0041] A first shielding component coupled to the initialization signal line pattern, a second shielding component coupled to the first shielding component, the orthographic projection of the second shielding component on the substrate at least partially overlapping the orthographic projection of the sixth conductor pattern on the substrate.

[0042] Optionally, the first shielding component is an extension structure extending from the initialization signal line pattern.

[0043] Optionally, the first shielding component and the initialization signal line pattern are disposed on different layers, and the orthographic projection of the first shielding component on the substrate and the orthographic projection of the initialization signal line pattern on the substrate have a first overlapping area. The first shielding component is coupled to the initialization signal line pattern through a first via disposed in the first overlapping area.

[0044] The second shielding component is disposed in a different layer from the first shielding component. The orthographic projection of the second shielding component on the substrate and the orthographic projection of the first shielding component on the substrate have a second overlapping area. The second shielding component and the first shielding component are coupled through a second through-hole disposed in the second overlapping area.

[0045] Optionally, the first shielding component is made of the same material as the data cable pattern.

[0046] Optionally, the display substrate includes a first interlayer insulating layer, wherein the first shielding component and the data line pattern are both located on the surface of the first interlayer insulating layer facing away from the substrate.

[0047] Optionally, the second shielding component is made of the same material as the initialization signal line pattern.

[0048] Optionally, the display substrate further includes a second interlayer insulating layer, wherein the second shielding component and the initialization signal line pattern are both located on the surface of the second interlayer insulating layer facing away from the substrate.

[0049] Optionally, the first electrode in the storage capacitor is reused as the gate of the driving transistor, the second electrode in the storage capacitor is made of the same material as the second shielding component, and the second electrode in the storage capacitor is located on the surface of the second interlayer insulating layer facing away from the substrate.

[0050] Optionally, the sub-pixel further includes: a reset signal line pattern extending along a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:

[0051] A first conductive connection portion, wherein the orthographic projection of the first conductive connection portion on the substrate covers at least a portion of the orthographic projection of the sixth conductor pattern on the substrate;

[0052] The second transistor has a first terminal coupled to the initialization signal line pattern via the first conductive connection portion, a second terminal coupled to the gate of the driving transistor, and a gate coupled to the reset signal line pattern.

[0053] Optionally, the sub-pixel further includes: a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and an initialization signal line pattern; the gate line pattern, the light emission control signal line pattern, the reset signal line pattern, and the initialization signal line pattern all extend along a second direction, and the second direction intersects with the first direction;

[0054] The two switching transistors include a fourth transistor and a fifth transistor;

[0055] The sub-pixel driving circuit further includes: a first transistor, a second transistor, a sixth transistor, and a seventh transistor;

[0056] The gate of the driving transistor is coupled to the second terminal of the first transistor, the first terminal of the driving transistor is coupled to the second terminal of the fifth transistor, and the second terminal of the driving transistor is coupled to the first terminal of the first transistor.

[0057] The gate of the first transistor is coupled to the gate line pattern;

[0058] The gate of the second transistor is coupled to the reset signal line pattern, the first terminal of the second transistor is coupled to the initialization signal line pattern, and the second terminal of the second transistor is coupled to the gate of the driving transistor.

[0059] The gate of the fourth transistor is coupled to the gate line pattern, the first terminal of the fourth transistor is coupled to the data line pattern, and the second terminal of the fourth transistor is coupled to the first terminal of the driving transistor.

[0060] The gate of the fifth transistor is coupled to the light-emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power supply signal line pattern.

[0061] The gate of the sixth transistor is pattern-coupled with the light-emitting control signal line, the first terminal of the sixth transistor is coupled with the second terminal of the driving transistor, and the second terminal of the sixth transistor is coupled with the corresponding light-emitting element in the sub-pixel.

[0062] The gate of the seventh transistor is coupled to a reset signal line pattern of the next sub-pixel adjacent to it along the first direction, the first electrode of the seventh transistor is coupled to an initialization signal line pattern of the next sub-pixel, and the second electrode of the seventh transistor is coupled to a light-emitting element in the sub-pixel.

[0063] A second aspect of this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arrayed on the substrate; the sub-pixels comprising:

[0064] A data line pattern extending along the first direction;

[0065] An initialization signal line pattern is provided, the initialization signal line pattern including a portion extending along a second direction, the second direction intersecting the first direction, the initialization signal line pattern being used to transmit an initialization signal having a fixed potential;

[0066] A sub-pixel driving circuit includes: a driving transistor, a first transistor coupled to the gate of the driving transistor, and a first shielding component coupled to the initialization signal line pattern, wherein the orthographic projection of the first shielding component on the substrate is located between the orthographic projection of the first transistor on the substrate and the orthographic projection of the target data line pattern on the substrate; the target data line pattern is included in the next sub-pixel adjacent to the sub-pixel along the second direction.

[0067] Optionally, the plurality of sub-pixels includes multiple rows of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels arranged along the second direction, and the initialization signal line patterns located in the same row of sub-pixels are sequentially coupled to form the initialization signal line corresponding to that row of sub-pixels;

[0068] The first shielding component extends along the first direction and is coupled to at least one of the initialization signal lines.

[0069] Optionally, the first shielding component is coupled to its two adjacent initialization signal lines.

[0070] Optionally, the first shielding component and the initialization signal line pattern are disposed on different layers. The orthographic projection of the first shielding component on the substrate and the orthographic projection of the initialization signal line pattern on the substrate have a first overlapping area. The first shielding component is coupled to the initialization signal line pattern through a first via disposed in the first overlapping area.

[0071] Optionally, the first shielding component is made of the same material as the data cable pattern.

[0072] Optionally, the display substrate includes a first interlayer insulating layer, wherein the first shielding component and the data line pattern are both located on the surface of the first interlayer insulating layer facing away from the substrate.

[0073] Optionally, the sub-pixel driving circuit further includes a second transistor coupled to the gate of the driving transistor, the second transistor comprising:

[0074] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern respectively, wherein the conductivity of the third conductor pattern is better than that of the first semiconductor pattern and the second semiconductor pattern.

[0075] A first gate pattern and a second gate pattern are coupled together, wherein the orthographic projection of the first gate pattern on the substrate at least partially overlaps with the orthographic projection of the first semiconductor pattern on the substrate, and the orthographic projection of the second gate pattern on the substrate at least partially overlaps with the orthographic projection of the second semiconductor pattern on the substrate;

[0076] The orthographic projection of the third conductor pattern on the substrate does not overlap with the orthographic projection of the first gate pattern on the substrate, nor with the orthographic projection of the second gate pattern on the substrate;

[0077] The orthographic projection of the third conductor pattern onto the substrate at least partially overlaps with the orthographic projection of the initialization signal line pattern onto the substrate.

[0078] Optionally, the sub-pixel driving circuit further includes a first extension portion extending from the first semiconductor pattern, wherein the conductivity of the first extension portion is better than that of the first semiconductor pattern.

[0079] The first extension includes a first part, a second part, and a third part. The first part and the third part both extend along the first direction, and the second part extends along the second direction. One end of the second part is coupled to the first part, and the other end of the second part is coupled to the third part.

[0080] The end of the third portion furthest from the second portion is coupled to the first transistor.

[0081] Optionally, the first transistor includes:

[0082] A fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern respectively, wherein the conductivity of the sixth conductor pattern is better than that of the fourth semiconductor pattern and the fifth semiconductor pattern;

[0083] A third gate pattern and a fourth gate pattern are coupled together, wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate;

[0084] The orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate, nor with the orthographic projection of the fourth gate pattern on the substrate.

[0085] Optionally, the orthographic projection of the first shielding component on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate.

[0086] Optionally, the sub-pixel driving circuit further includes:

[0087] A second shielding component coupled to the first shielding component, wherein the orthographic projection of the second shielding component on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate.

[0088] Optionally, the second shielding component and the first shielding component are disposed in different layers, and the orthographic projection of the second shielding component on the substrate and the orthographic projection of the first shielding component on the substrate have a second overlapping area. The second shielding component and the first shielding component are coupled through a second through-hole disposed in the second overlapping area.

[0089] Optionally, the second shielding component is made of the same material as the initialization signal line pattern.

[0090] Optionally, the display substrate further includes a second interlayer insulating layer, wherein the second shielding component and the initialization signal line pattern are both located on the surface of the second interlayer insulating layer facing away from the substrate.

[0091] Optionally, the sub-pixel further includes a power signal line pattern, the power signal line pattern including a portion extending along the first direction, the sub-pixel driving circuit further includes a storage capacitor, the first plate of the storage capacitor is multiplexed as the gate of the driving transistor, the second plate of the storage capacitor is coupled to the power signal line pattern, and the second plate of the storage capacitor is located on the surface of the second interlayer insulating layer facing away from the substrate.

[0092] Optionally, the sub-pixel further includes: a reset signal line pattern extending along a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:

[0093] A first conductive connection portion, wherein the orthographic projection of the first conductive connection portion on the substrate covers at least a portion of the orthographic projection of the sixth conductor pattern on the substrate;

[0094] The second transistor has a first terminal coupled to the initialization signal line pattern via the first conductive connection portion, a second terminal coupled to the gate of the driving transistor, and a gate coupled to the reset signal line pattern.

[0095] Optionally, the sub-pixel further includes: a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line pattern all extend along the second direction, and the power signal line pattern includes a portion extending along the first direction;

[0096] The sub-pixel driving circuit further includes: a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0097] The gate of the driving transistor is coupled to the second terminal of the first transistor, the first terminal of the driving transistor is coupled to the second terminal of the fifth transistor, and the second terminal of the driving transistor is coupled to the first terminal of the first transistor.

[0098] The gate of the first transistor is coupled to the gate line pattern;

[0099] The gate of the second transistor is coupled to the reset signal line pattern, the first terminal of the second transistor is coupled to the initialization signal line pattern, and the second terminal of the second transistor is coupled to the gate of the driving transistor.

[0100] The gate of the fourth transistor is coupled to the gate line pattern, the first terminal of the fourth transistor is coupled to the data line pattern, and the second terminal of the fourth transistor is coupled to the first terminal of the driving transistor.

[0101] The gate of the fifth transistor is coupled to the light-emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power supply signal line pattern.

[0102] The gate of the sixth transistor is pattern-coupled to the light-emitting control signal line, the first terminal of the sixth transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixth transistor is coupled to the light-emitting element in the sub-pixel.

[0103] The gate of the seventh transistor is coupled to a reset signal line pattern of the next sub-pixel adjacent to it along the first direction, the first electrode of the seventh transistor is coupled to an initialization signal line pattern of the next sub-pixel, and the second electrode of the seventh transistor is coupled to a light-emitting element in the sub-pixel.

[0104] Optionally, the sub-pixel further includes: a gate pattern, a light emission control signal line pattern, a reset signal line pattern, and a power signal line pattern; the gate pattern, the light emission control signal line pattern, and the reset signal line pattern all extend along the second direction, and the power signal line pattern includes a portion extending along the first direction; the orthographic projection of the first shielding member on the substrate overlaps with the orthographic projection of the gate pattern on the substrate and the orthographic projection of the light emission control signal line pattern on the substrate, respectively.

[0105] Based on the above-described display substrate technical solution, a third aspect of this disclosure provides a display device including the above-described display substrate.

[0106] Based on the above-described display substrate technical solution, a fourth aspect of this disclosure provides a method for manufacturing a display substrate, the method comprising: fabricating a plurality of sub-pixels arranged in an array on a substrate; the sub-pixels comprising: a data line pattern extending along a first direction; a power signal line pattern, the power signal line pattern including a portion extending along the first direction; a sub-pixel driving circuit, the sub-pixel driving circuit comprising: two switching transistors, a driving transistor, and a storage capacitor; a first electrode of the storage capacitor being coupled to the gate of the driving transistor, and a second electrode of the storage capacitor being coupled to the power signal line pattern; the second electrodes of the two switching transistors being coupled to the first electrodes of the driving transistors, and the orthographic projection of the second electrode of at least one of the two switching transistors onto the substrate at least partially overlapping the orthographic projection of the power signal line pattern onto the substrate, and at least partially overlapping the orthographic projection of the second electrode of the storage capacitor onto the substrate. Attached Figure Description

[0107] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0108] Figure 1 This is a schematic diagram of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0109] Figure 2 This is a timing diagram of the sub-pixel driving circuit provided in the embodiments of this disclosure;

[0110] Figure 3 This is a first layout schematic diagram of the sub-pixel driving circuit in a display substrate provided in an embodiment of the present disclosure;

[0111] Figure 4 This is a first layout schematic diagram of the active film layer provided in an embodiment of the present disclosure;

[0112] Figure 5 This is a first layout schematic diagram of the first gate metal layer provided in an embodiment of the present disclosure;

[0113] Figure 6 This is a first layout schematic diagram of the second gate metal layer provided in an embodiment of the present disclosure;

[0114] Figure 7 This is a schematic diagram of the first layout of the source / drain metal layer provided in an embodiment of this disclosure.

[0115] Figure 8 for Figure 3 A schematic diagram of the cross-section along the A1A2 direction;

[0116] Figure 9 This is a second layout schematic diagram of the sub-pixel driving circuit in the display substrate provided in an embodiment of the present disclosure;

[0117] Figure 10 This is a third layout schematic diagram of the sub-pixel driving circuit in a display substrate provided in an embodiment of this disclosure;

[0118] Figure 11 This is a fourth layout schematic diagram of the sub-pixel driving circuit in the display substrate provided in an embodiment of this disclosure;

[0119] Figure 12 This is a fifth layout schematic diagram of the sub-pixel driving circuit in the display substrate provided in an embodiment of this disclosure;

[0120] Figure 13 for Figure 11 A schematic diagram of the cross-section along the B1B2 direction;

[0121] Figure 14This is a sixth layout schematic diagram of the sub-pixel driving circuit in the display substrate provided in an embodiment of this disclosure;

[0122] Figure 15 This is a schematic diagram of the first layout of multiple sub-pixels in a display substrate provided in an embodiment of the present disclosure;

[0123] Figure 16 This is a seventh layout schematic diagram of the sub-pixel driving circuit in a display substrate provided in an embodiment of this disclosure;

[0124] Figure 17 for Figure 16 A schematic diagram of the cross-section along the C1C2 direction;

[0125] Figure 18 This is a schematic diagram of the second layout of the active film layer provided in an embodiment of the present disclosure;

[0126] Figure 19 This is an eighth layout schematic diagram of the sub-pixel driving circuit in the display substrate provided in an embodiment of this disclosure;

[0127] Figure 20 This is a ninth layout schematic diagram of the sub-pixel driving circuit in the display substrate provided in an embodiment of this disclosure;

[0128] Figure 21 This is a tenth layout schematic diagram of the sub-pixel driving circuit in a display substrate provided in an embodiment of this disclosure;

[0129] Figure 22 for Figure 21 A schematic diagram of the cross-section along the D1D2 direction;

[0130] Figure 23 This is a schematic diagram of the layout of the third metal layer;

[0131] Figure 24 This is a schematic diagram of a second layout of multiple sub-pixels in a display substrate provided in an embodiment of the present disclosure;

[0132] Figure 25 This is a schematic diagram illustrating the crosstalk phenomenon that occurs at the gate of a driving transistor in related technologies.

[0133] Figure 26 This disclosure provides an eleventh layout schematic diagram of the sub-pixel driving circuit in a display substrate. Detailed Implementation

[0134] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0135] In related technologies, there are various reasons for crosstalk in OLED display products. The main crosstalk is the crosstalk generated by the data line patterns around the driving transistor in the sub-pixel driving circuit. More specifically, when the sub-pixel driving circuit is laid out, the area around the driving transistor also includes various transistors with other functions. These transistors are all composed of multiple layers of conductive patterns. Moreover, the area around the driving transistor is also provided with various signal line patterns for transmitting different signals. When the sub-pixel driving circuit is working, the signal changes on the conductive patterns and signal line patterns of the various transistors can easily generate crosstalk to the driving transistor, thereby affecting the working performance of the driving transistor.

[0136] Based on the existence of the above problems, the inventors of this disclosure have discovered through research that the crosstalk that affects the working performance of the driving transistor mainly includes: crosstalk problems caused by coupling between the data line pattern and the gate of the driving transistor, and crosstalk problems caused by coupling between the data line pattern and the first electrode of the driving transistor.

[0137] The inventors of this disclosure further discovered that a pattern with a fixed potential can be formed on the first electrode of the driving transistor. By using this pattern with a fixed potential to shield the first electrode of the driving transistor, the coupling effect between the data line pattern located near the first electrode of the driving transistor and the first electrode of the driving transistor is reduced, thereby weakening the crosstalk problem caused by the data line pattern to the driving transistor and enabling the display product to achieve a better display effect.

[0138] It should be noted that one or more embodiments described herein correspond to a display substrate having a 7T1C (i.e., 7 thin-film transistors and 1 capacitor) sub-pixel driving circuit. In another embodiment, the display substrate may include different sub-pixel driving circuits, for example, with more or less than 7 thin-film transistors, and including one or more capacitors.

[0139] like Figure 1 As shown, the display substrate provided in this disclosure includes multiple sub-pixels, and each sub-pixel may include: a gate pattern GATE, a first reset signal line pattern RST1, a first initialization signal line pattern VINT1, a data line pattern DATA, a light emission control signal line pattern EM, a power supply signal line pattern VDD, a second reset signal line pattern RST2, and a second initialization signal line pattern VINT2.

[0140] Each sub-pixel's driving circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. Additionally, Figure 1It also includes a first capacitor C1, which is a parasitic capacitor.

[0141] Taking a sub-pixel driving circuit as an example, each transistor in the sub-pixel driving circuit is a P-type transistor. The first transistor T1 has a dual-gate structure. The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE. The source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3. The drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0142] The second transistor T2 has a dual-gate structure. The gate 202g of the second transistor T2 is coupled to the first reset signal line pattern RST1, the source S2 of the second transistor T2 is coupled to the first initialization signal line pattern VINT1, and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0143] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the source S4 of the fourth transistor T4 is coupled to the data line pattern DATA, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0144] The gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern EM, the source S5 of the fifth transistor T5 is coupled to the power supply signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0145] The gate 206g of the sixth transistor T6 is coupled to the light-emitting control signal line pattern EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light-emitting element OLED.

[0146] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the anode of the light-emitting element OLED, and the source S7 of the seventh transistor T7 is coupled to the second initialization signal line pattern VINT2.

[0147] The first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.

[0148] like Figure 2 As shown, when the sub-pixel driving circuit with the above structure is working, each working cycle includes a first reset period P1, a write compensation period P2, a second reset period P3, and a light emission period P4.

[0149] During the first reset period P1, the first reset signal input to the first reset signal line pattern RST1 is at an active level, the second transistor T2 is turned on, and the initialization signal transmitted by the first initialization signal line pattern VINT1 is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs held on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0150] During the write compensation period P2, the first reset signal is at an inactive level, the second transistor T2 is off, and the gate scan signal input to the gate pattern GATE is at an active level, controlling the first transistor T1 and the fourth transistor T4 to turn on. The data line pattern DATA writes the data signal and transmits it to the source S3 of the third transistor T3 via the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, causing the third transistor T3 to form a diode structure. Therefore, by working together, the first transistor T1, the third transistor T3, and the fourth transistor T4 can compensate for the threshold voltage of the third transistor T3. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to eventually reach Vdata + Vth, where Vdata represents the data signal voltage value and Vth represents the threshold voltage of the third transistor T3.

[0151] During the second reset period P3, the gate scan signal is at an inactive level, the first transistor T1 and the fourth transistor T4 are both turned off, the second reset signal input to the second reset signal line RST2 is at an active level, controlling the seventh transistor T7 to turn on, and the initialization signal transmitted by the second initialization signal line pattern VINT2 is input to the anode of the light-emitting element OLED, controlling the light-emitting element OLED not to emit light.

[0152] During the light-emitting period P4, the light-emitting control signal written in the light-emitting control signal line pattern EM is at an effective level, controlling the fifth transistor T5 and the sixth transistor T6 to conduct, so that the power signal transmitted by the power signal line pattern VDD is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on. The gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power signal. The leakage current generated based on this gate-source voltage flows to the anode of the corresponding light-emitting element OLED, driving the corresponding light-emitting element OLED to emit light.

[0153] like Figure 3 As shown, the layout of each film layer corresponding to the sub-pixel driving circuit is as follows when fabricating the above sub-pixel driving circuit:

[0154] An active film layer, a gate insulating layer, a first gate metal layer, a first interlayer insulating layer, a second gate metal layer, a second interlayer insulating layer, a first source / drain metal layer, and a third interlayer insulating layer are sequentially stacked along a direction away from the substrate.

[0155] like Figure 4 As shown, the active film layer is used to form the channel region (e.g., 101pg~107pg), source formation region (e.g., 101ps~107ps), and drain formation region (e.g., 101pd~107pd) of each transistor in the sub-pixel driving circuit. Due to doping, the conductivity of the active film layer corresponding to the source and drain formation regions is better than that of the active film layer corresponding to the channel region. The active film layer can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0156] In addition, it is worth noting that the active film layers corresponding to the source forming region and the drain forming region can be directly used as the corresponding source or drain. Alternatively, a metal material can be used to make the source that contacts the source forming region and the drain that contacts the drain forming region.

[0157] like Figure 5 As shown, the first gate metal layer is used to form the gates of each transistor in the sub-pixel driving circuit (e.g., 201g to 207g), as well as the gate line pattern GATE, the light emission control signal line pattern EM, the first reset signal line pattern RST1, and the second reset signal line pattern RST2 included in the display substrate. The gate 203g of the third transistor T3 in each sub-pixel driving circuit is reused as the first plate Cst1 of the storage capacitor Cst in the sub-pixel driving circuit.

[0158] like Figure 6 As shown, the second gate metal layer is used to form the second electrode plate Cst2 of the storage capacitor Cst, and the display substrate includes the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2.

[0159] like Figure 1 , Figure 3 and 7 As shown, the first source-drain metal layer is used to form the source (e.g., S1 to S7) and drain (e.g., D1 to D7) of each transistor in the sub-pixel driving circuit, as well as the data line pattern (e.g., DATA1 and DATA2) and power signal line pattern VDD included in the display substrate.

[0160] For more details, please continue reading. Figure 3 , Figures 7-10The gate 201g of the first transistor T1 covers the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.

[0161] The gate 202g of the second transistor T2 covers the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source formation region 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation region 102pd.

[0162] The gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.

[0163] The gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source S4 of the fourth transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain formation region 104pd.

[0164] The gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.

[0165] The gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.

[0166] The gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.

[0167] The gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.

[0168] It needs to be explained that, Figure 1 The connecting lines 401, 402, and 403 are all formed by the first source / drain metal layer, and their specific layout is as follows: Figure 3 and Figure 7 As shown. Figure 1 The first capacitor C1 in the figure is a parasitic capacitance, such as Figure 3As shown, the orthographic projection of the second plate Cst2 of the storage capacitor Cst onto the substrate overlaps with the orthographic projection of the downward extension of the fourth drain formation region 104pd corresponding to the fourth transistor T4 onto the substrate. This overlapping region forms the first capacitor C1 shown.

[0169] Furthermore, in the display substrate provided in this disclosure, the multiple sub-pixels can be arranged in an array. The multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and each column of sub-pixels includes multiple sub-pixels arranged along a first direction. The first direction intersects with the second direction. The gate pattern GATE, the first reset signal line pattern RST1, the first initialization signal line pattern VINT1, the light emission control signal line pattern EM, the second reset signal line pattern RST2, and the second initialization signal line pattern VINT2 included in the sub-pixels can all extend along the second direction. The data line pattern DATA and the power signal line pattern VDD included in the sub-pixels both extend along the first direction.

[0170] The gate line pattern GATE located in the same row can be formed into a single gate line structure. The first reset signal line pattern RST1 located in the same row can be formed into a single first reset signal line structure. The first initialization signal line pattern VINT1 located in the same row can be formed into a single first initialization signal line structure. The light emission control signal line pattern EM located in the same row can be formed into a single light emission control signal line structure. The second reset signal line pattern RST2 located in the same row can be formed into a single second reset signal line structure. The second initialization signal line pattern VINT2 located in the same row can be formed into a single second initialization signal line structure. The data line pattern DATA located in the same column can be formed into a single data line structure. The power signal line pattern VDD located in the same column can be formed into a single power signal line structure.

[0171] To simplify the layout space of subpixels, the second reset signal line corresponding to a row of subpixels can be reused as the first reset signal line corresponding to the adjacent next row of subpixels; similarly, the second initialization signal line corresponding to a row of subpixels can be reused as the first initialization signal line corresponding to the adjacent next row of subpixels.

[0172] like Figure 3As shown, in some embodiments, taking a sub-pixel driving circuit included in a sub-pixel as an example, in a first direction (such as the Y direction), the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gates of the seventh transistor T7, the sixth transistor T6, and the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first and second sides of the gate of the driving transistor are two opposite sides of the gate of the driving transistor in the first direction. Further, the first side of the gate of the driving transistor can be the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor can be the lower side of the gate of the driving transistor T1. The lower side, for example, is the side of the display substrate used for bonding the IC, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor further away from the IC.

[0173] In some embodiments, such as Figure 3 As shown, in the second direction (e.g., the X direction), the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor T1. For example, the third and fourth sides of the gate of the driving transistor are two opposite sides of the gate of the driving transistor in the second direction X; further, the third side of the gate of the driving transistor can be the left side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor can be the right side of the gate of the driving transistor. The left and right sides, for example, in the same sub-pixel, the first data line pattern DATA1 is located to the left of the power signal line pattern VDD, and the power signal line pattern VDD is to the right of the first data line pattern DATA1.

[0174] Please see Figure 3 and Figure 8 This disclosure provides a display substrate, including: a substrate 50 and a plurality of sub-pixels arrayed on the substrate 50; the sub-pixels include:

[0175] Data line pattern extending along the first direction (e.g.) Figure 3 (DATA1 in the middle);

[0176] Initialize signal line pattern (e.g.) Figure 3VINT1 in the original text), the initialization signal line pattern includes a portion extending along a second direction, which intersects with the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;

[0177] Sub-pixel driving circuit, the sub-pixel driving circuit including: driving transistor (e.g. Figure 3 T3), a first transistor T1 coupled to the gate of the driving transistor, and a first shielding member 404 coupled to the initialization signal line pattern, wherein the orthographic projection of the first shielding member 404 on the substrate 50 is located at the orthographic projection of the first transistor T1 on the substrate 50 and the target data line pattern (e.g., T3), the first transistor T1 coupled to the gate of the driving transistor, and the first shielding member 404 coupled to the initialization signal line pattern, wherein the first shielding member 404 is coupled to ... shielding member 404 is coupled to the gate of the driving transistor, and the first shielding member 404 is coupled to the initialization signal line pattern, wherein the first Figure 3 The target data line pattern is included in the next sub-pixel adjacent to the sub-pixel along the second direction between the orthographic projections of DATA2 on the substrate 50.

[0178] Specifically, the aforementioned display substrate generally includes multiple sub-pixels arranged in an array, each sub-pixel including: a data line pattern extending along a first direction (such as...). Figure 3 DATA1 in the diagram), and the initialization signal line pattern extending at least partially along the second direction (such as...). Figure 3 The data line pattern is used to transmit data signals, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential. For example, the first direction includes the Y direction, and the second direction includes the X direction.

[0179] The target data line pattern is: the data line pattern included in the next sub-pixel adjacent to the current sub-pixel along the second direction.

[0180] Each sub-pixel also includes a sub-pixel driving circuit and a light-emitting element corresponding to the sub-pixel driving circuit. The light-emitting element includes an anode, an organic light-emitting material layer, and a cathode stacked together. The anode of the light-emitting element is coupled to the corresponding sub-pixel driving circuit. Under the drive signal provided by the sub-pixel driving circuit, the light-emitting element emits light.

[0181] More specifically, such as Figure 1 , Figure 3 and Figure 4 As shown, taking the sub-pixel driving circuit including the aforementioned 7T1C as an example, the gate 203g of the third transistor T3 (i.e., the driving transistor) is coupled to the drain D1 of the first transistor T1 via a connection line 401, and the drain D3 of the third transistor T3 is coupled to the source S1 of the first transistor T1. Along the X direction, the orthogonal projection of the first channel region 101pg of the first transistor T1 onto the substrate 50 coincides with the target data line pattern (e.g., ...). Figure 3The minimum distance between the orthographic projections of DATA2) on the substrate 50 is less than the minimum distance between the orthographic projection of the third channel region 103pg of the third transistor T3 on the substrate 50 and the minimum distance between the orthographic projection of the target data line pattern on the substrate 50. It is noteworthy that the orthographic projections of the aforementioned channel regions (e.g., the first channel region 101pg and the third channel region 103pg) on ​​the substrate 50 and the minimum distance between the orthographic projections of the target data line pattern (e.g., the first channel region 101pg and the third channel region 103pg) on ​​the substrate 50 and the target data line pattern (e.g., the first channel region 101pg and the third channel region 103pg) on ​​the substrate 50 are less than the minimum distance between the orthographic projections of the third channel region 103pg of the third transistor T3 on the substrate Figure 3 The minimum distance between the orthographic projections of DATA2 on the substrate 50 refers to the boundary of the channel region closest to the target data line pattern in its orthographic projection on the substrate 50, and the boundary of the target data line pattern (e.g., DATA2). Figure 3 The minimum distance between the orthographic projections of DATA2 on the substrate 50.

[0182] In the sub-pixel driving circuit of the above structure, when the data signal transmitted by the target data line pattern changes, it will affect the performance of the first transistor T1. Since the first transistor T1 is coupled to the third transistor T3 through the connection line 401, it will affect the working performance of the third transistor T3.

[0183] In this embodiment of the disclosure, a pattern related to the initialization signal line (e.g., ...) is set in the sub-pixel driving circuit. Figure 3 The first shielding component 404, coupled to VINT1 in the initialization signal, is given a fixed potential identical to that of the initialization signal. The orthographic projection of the first shielding component 404 onto the substrate 50 is positioned such that the orthographic projection of the first transistor T1 onto the substrate 50 coincides with the target data line pattern (e.g., VINT1). Figure 3 The first shielding component 404 can reduce the impact of signal changes transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the coupling effect between the gate (i.e., 203g) of the driving transistor and the target data line pattern, weakening the problem of vertical crosstalk, and enabling the display substrate to obtain better display effect when used for display.

[0184] In addition, the above-mentioned coupling of the first shielding component 404 with the initialization signal line pattern not only makes the first shielding component 404 have a fixed potential, but also strengthens the voltage of the initialization signal line pattern, making the voltage of the initialization signal transmitted on the initialization signal line pattern more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0185] It is worth noting that, in addition to coupling the first shielding component 404 to the initialization signal line pattern, the first shielding component 404 can also be coupled to the power signal line pattern VDD included in the sub-pixel, so that the first shielding component 404 has the same fixed potential as the power signal transmitted by the power signal line pattern VDD.

[0186] The above-described method of coupling the first shielding component 404 to the power signal line pattern VDD can ensure that the first shielding component 404 has a fixed potential, but it will increase the parasitic capacitance generated by the power signal line pattern VDD, making the RC load of the power signal line pattern VDD larger, which is not conducive to reducing vertical crosstalk.

[0187] like Figure 3 As shown, in some embodiments, the gate 201g of the first transistor T1 and the gate pattern GATE are an integral structure, and the gate 201g of the first transistor T1 is a portion of the integral structure that can form an overlapping region with the active film layer in a direction perpendicular to the substrate.

[0188] like Figure 3 As shown, in some embodiments, the plurality of sub-pixels includes multiple rows of sub-pixels, each row of sub-pixels includes a plurality of the sub-pixels arranged along the second direction, and the initialization signal line patterns located in the same row of sub-pixels are sequentially coupled to form the initialization signal line corresponding to that row of sub-pixels; the first shielding member 404 extends along the first direction and is coupled to at least one of the initialization signal lines.

[0189] Specifically, the plurality of sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and each column of sub-pixels includes multiple sub-pixels arranged along a first direction. The first direction intersects with the second direction. The initialization signal line patterns located in the same row of sub-pixels are coupled sequentially to form an initialization signal line corresponding to that row of sub-pixels.

[0190] The above-described configuration, in which the first shielding component 404 extends along the first direction and is coupled to at least one of the initialization signal lines, not only enables the first shielding component 404 to reduce the impact of signal variations transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the coupling effect between the gate (i.e., 203g) of the driving transistor and the target data line pattern, and weakening the problem of vertical crosstalk, thus enabling the display substrate to obtain a better display effect when used for display; but also strengthens the voltage of the initialization signal line, making the voltage of the initialization signal transmitted on the initialization signal line more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0191] likeFigure 9 As shown, in some embodiments, the first shielding component 404 is coupled to its two adjacent initialization signal lines.

[0192] Specifically, when the first shielding component 404 is coupled to the initialization signal line, the coupling method between the first shielding component 404 and the initialization signal line, as well as the specific structure and arrangement of the first shielding component 404, are varied. For example,... Figure 3 As shown, the first shielding component 404 can be coupled to its two adjacent initialization signal lines respectively. This arrangement ensures that the orthographic projection of the first shielding component 404 on the substrate 50 is not only located between the orthographic projection of the first transistor T1 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; it also ensures that the orthographic projection of the first shielding component 404 on the substrate 50 is located between the orthographic projection of the connecting line 401 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; and it also ensures that the orthographic projection of the first shielding component 404 on the substrate 50 is located between the orthographic projection of the driving transistor (i.e., the third transistor T3) on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50.

[0193] The above-described configuration effectively reduces the first crosstalk between the target signal line pattern and the first transistor T1, as well as the second crosstalk between the target signal line pattern and the connecting line 401, thereby reducing the indirect crosstalk to the driving transistor caused by the first and second crosstalk. Furthermore, the above-described configuration also reduces the direct crosstalk between the target signal line pattern and the driving transistor, thus better ensuring the operating performance of the display substrate.

[0194] Please continue reading. Figure 3 In some embodiments, the first shielding component 404 is connected to the initialization signal line pattern (e.g., Figure 3 In the VINT1) heterogeneous layer setting, the orthographic projection of the first shielding component 404 on the substrate 50 has a first overlapping area with the orthographic projection of the initialization signal line pattern on the substrate, and the first shielding component 404 is coupled to the initialization signal line pattern through a first via provided in the first overlapping area.

[0195] Specifically, the first shielding component 404 can be disposed on the same layer or on a different layer than the initialization signal line pattern. When the first shielding component 404 and the initialization signal line pattern are disposed on a different layer, the orthographic projection of the first shielding component 404 on the substrate 50 and the orthographic projection of the initialization signal line pattern on the substrate 50 can both have a first overlapping area. In this way, by setting a first via in the first overlapping area, the coupling between the first shielding component 404 and the initialization signal line can be achieved.

[0196] It should be noted that the above-mentioned "the first shielding component 404 can be disposed in the same layer as the initialization signal line pattern" includes at least one of the following: the first shielding component 404 and the initialization signal line pattern are located on the same horizontal plane; the first shielding component 404 and the initialization signal line pattern are located in the same film layer; the first shielding component 404 and the initialization signal line pattern are both disposed on the surface of the same insulating layer facing away from the substrate; and the first shielding component 404 and the initialization signal line pattern are formed by a single patterning process.

[0197] The aforementioned "the first shielding component 404 may be disposed in a different layer from the initialization signal line pattern" includes at least one of the following situations: the first shielding component 404 and the initialization signal line pattern are not located in the same film layer; the first shielding component 404 and the initialization signal line pattern cannot be formed by a single patterning process.

[0198] In some embodiments, the first shielding component 404 and the data cable pattern (e.g.) can be configured. Figure 3 DATA1 in the settings is the same as the material settings.

[0199] In some embodiments, the display substrate may include a first interlayer insulating layer, and the first shielding member 404 and the data line pattern (such as...) Figure 3 DATA1) are all located on the surface of the first interlayer insulation layer facing away from the substrate.

[0200] Specifically, by setting the first shielding component 404 in the manner described above, the first shielding component 404 and the data line pattern can be formed simultaneously on the surface of the first interlayer insulating layer facing away from the substrate through a single patterning process. This avoids the need for additional patterning processes to manufacture the first shielding component 404, thereby greatly simplifying the manufacturing process of the display substrate and saving manufacturing costs.

[0201] like Figure 3 As shown, in some embodiments, the sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, the second transistor T2 comprising:

[0202] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern respectively, wherein the conductivity of the third conductor pattern is better than that of the first semiconductor pattern and the second semiconductor pattern.

[0203] A first gate pattern and a second gate pattern are coupled together, wherein the orthographic projection of the first gate pattern on the substrate 50 overlaps with the orthographic projection of the first semiconductor pattern on the substrate 50, and the orthographic projection of the second gate pattern on the substrate 50 overlaps with the orthographic projection of the second semiconductor pattern on the substrate 50.

[0204] The orthographic projection of the third conductor pattern on the substrate 50 does not overlap with the orthographic projection of the first gate pattern on the substrate 50, nor with the orthographic projection of the second gate pattern on the substrate 50.

[0205] The orthographic projection of the third conductor pattern onto the substrate 50, and the initialization signal line pattern (e.g., ...). Figure 3 The orthographic projections of VINT1 on the substrate 50 at least partially overlap.

[0206] Specifically, such as Figure 7 As shown, the second transistor T2 has a dual-gate structure, and the first semiconductor pattern and the second semiconductor pattern therein form the channel region of the second transistor T2 (corresponding to...). Figure 7 The third conductor pattern 102px, which is marked at position 102pg, has better conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping. The first gate pattern and the second gate pattern of the second transistor T2 cover the first semiconductor pattern and the second semiconductor pattern respectively, and can be used together as the gate 202g of the second transistor T2.

[0207] In the second transistor T2 of the above structure, because the third conductor pattern 102px has good conductivity and is not covered by the gate pattern, it is prone to coupling with other nearby conductive patterns, resulting in crosstalk. In the technical solution provided by the above embodiment, by setting the orthogonal projection of the third conductor pattern on the substrate 50, and the initialization signal line pattern (such as...) Figure 3The VINT1 in the diagram at least partially overlaps with the orthographic projection on the substrate 50, so that the initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the coupling effect between the third conductor pattern 102px and other nearby conductive patterns is better reduced, thereby making the working performance of the display substrate more stable.

[0208] like Figure 4 As shown, in some embodiments, the sub-pixel driving circuit further includes a first extension extending from the first semiconductor pattern, the first extension having better conductivity than the first semiconductor pattern; the first extension includes a first portion 61, a second portion 62, and a third portion 63, the first portion 61 and the third portion 63 both extending along the first direction, the second portion 62 extending along the second direction, one end of the second portion 62 being coupled to the first portion 61, and the other end of the second portion 62 being coupled to the third portion 63; the end of the third portion 63 away from the second portion 62 is coupled to the first transistor T1.

[0209] Specifically, the first extension can be fabricated in a single patterning process with the first semiconductor pattern, and after the first semiconductor pattern is formed, the first extension is doped so that the conductivity of the first extension is better than that of the first semiconductor pattern.

[0210] After adding the first shielding component 404, the first extension is configured as described above. This makes it easier to reduce the impact of signal changes transmitted on the target data line pattern on the performance of the first transistor T1 and the second transistor T2 when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor respectively through the first extension. This reduces the coupling effect between the gate of the driving transistor (i.e., 203g) and the target data line pattern, weakens the vertical crosstalk problem, and enables the display substrate to obtain a better display effect when used for display.

[0211] like Figure 3 and Figure 4 As shown, in some embodiments, the first transistor T1 includes:

[0212] A fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern respectively, wherein the conductivity of the sixth conductor pattern is better than that of the fourth semiconductor pattern and the fifth semiconductor pattern;

[0213] A third gate pattern and a fourth gate pattern are coupled together, wherein the orthographic projection of the third gate pattern on the substrate 50 partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate 50, and the orthographic projection of the fourth gate pattern on the substrate 50 partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate 50.

[0214] The orthographic projection of the sixth conductor pattern on the substrate 50, the orthographic projection of the third gate pattern on the substrate 50, and the orthographic projection of the fourth gate pattern on the substrate 50 do not overlap.

[0215] Specifically, such as Figure 4 As shown, the first transistor has a dual-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included therein form the channel region of the first transistor (corresponding to...). Figure 4 The sixth conductor pattern 101px, which is marked 101pg, has better conductivity than the fourth and fifth semiconductor patterns due to doping. The third and fourth gate patterns of the first transistor cover the fourth and fifth semiconductor patterns respectively and can be used together as the gate 201g of the first transistor T1.

[0216] like Figure 10 As shown, in some embodiments, the orthographic projection of the first shielding member 404 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50.

[0217] Specifically, in the first transistor T1 of the above structure, since the sixth conductor pattern 101px has good conductivity and is not covered by the gate pattern, it is prone to coupling with other conductive patterns nearby, resulting in crosstalk. In the technical solution provided by the above embodiment, by setting the orthographic projection of the first shielding member 404 on the substrate 50 to at least partially overlap with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, the first shielding member 404 can cover the sixth conductor pattern 101px. Furthermore, since the first shielding member 404 has a fixed potential, the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby is better reduced, making the working performance of the display substrate more stable.

[0218] like Figure 11 , Figure 12 and Figure 13As shown, in some embodiments, the sub-pixel driving circuit further includes a second shielding component 301 coupled to the first shielding component 404, wherein the orthographic projection of the second shielding component 301 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50.

[0219] Specifically, the above-mentioned arrangement of the orthographic projection of the second shielding component 301 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px. Furthermore, since the second shielding component 301 is coupled to the first shielding component 404, the second shielding component 301 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns, making the working performance of the display substrate more stable.

[0220] Therefore, in the display substrate provided in the above embodiments, since both the first shielding component 404 and the second shielding component 301 have a fixed potential, the formation of parasitic capacitance between the first transistor T1 and the target data line pattern (such as DATA2) is better prevented or reduced, and vertical crosstalk defects are effectively prevented or reduced.

[0221] Furthermore, the orthographic projection of the second shielding component 301 on the substrate 50 may be configured to cover the entire orthographic projection of the sixth conductor pattern on the substrate 50.

[0222] Specifically, the orthographic projection of the second shielding component 301 on the substrate 50 covers the entire orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can completely cover the sixth conductor pattern 101px, thereby minimizing the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns, and better improving the working stability of the display substrate.

[0223] In some embodiments, the second shielding component 301 and the first shielding component 404 are disposed in different layers, and the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50 have a second overlapping area, and the second shielding component 301 and the first shielding component 404 are coupled through a second through-hole disposed in the second overlapping area.

[0224] Specifically, the second shielding component 301 can be disposed in the same layer as the first shielding component 404 or disposed in a different layer. When the second shielding component 301 and the first shielding component 404 are disposed in a different layer, a second overlapping area can be provided between the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50. In this way, by providing a second via in the second overlapping area, the second shielding component 301 and the first shielding component 404 can be coupled through the second via.

[0225] In some embodiments, the second shielding component 301 may be made of the same material as the initialization signal line pattern.

[0226] In some embodiments, the display substrate may further include a second interlayer insulating layer, wherein the second shielding member 301 and the initialization signal line pattern (such as...) Figure 3 The VINT1 in the second interlayer insulation layer is located on the surface of the second interlayer insulation layer facing away from the substrate.

[0227] Specifically, the second shielding component 301 and the initialization signal line pattern are made of the same material, and the second shielding component 301 and the initialization signal line pattern (such as...) are... Figure 3 The VINT1 in the second interlayer insulating layer is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second shielding component 301 can be formed simultaneously with the initialization signal line pattern in the same patterning process. This avoids the need for additional manufacturing processes specifically for the second shielding component 301, thereby greatly simplifying the manufacturing process of the display substrate and saving production costs.

[0228] like Figure 3 As shown, in some embodiments, the sub-pixel further includes a power signal line pattern VDD, the power signal line pattern VDD including a portion extending along the first direction, and the sub-pixel driving circuit further includes a storage capacitor Cst, the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the driving transistor, the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, and the second plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate.

[0229] Specifically, the sub-pixel driving circuit includes a storage capacitor Cst with a first plate Cst1 and a second plate Cst2. The first plate Cst1 and the second plate Cst2 are arranged opposite to each other, and the first plate Cst1 is coupled to the gate of the driving transistor, while the second plate Cst2 is coupled to the power signal line pattern VDD. When laying out the storage capacitor Cst, the first plate Cst1 can be directly reused as the gate of the driving transistor. This not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor but also reduces the space occupied by the sub-pixel driving circuit, which is more conducive to improving the resolution of the display substrate. Furthermore, the second plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate, allowing the second plate Cst2 of the storage capacitor Cst to be formed simultaneously with the second shielding component 301 and the initialization signal line pattern in the same patterning process. This greatly simplifies the manufacturing process of the display substrate and saves production costs.

[0230] like Figure 14 As shown, in some embodiments, the sub-pixel further includes: a reset signal line pattern extending along a second direction intersecting the first direction (e.g., Figure 3 The sub-pixel driving circuit further includes: (RST1 in the original text)

[0231] The first conductive connection portion 405, the orthographic projection of the first conductive connection portion 405 on the substrate 50 covers at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50;

[0232] The second transistor T2 has its first terminal (e.g., source S2) coupled to the initialization signal line pattern (e.g., VINT1) via the first conductive connection portion 405, its second terminal (e.g., drain D2) coupled to the gate of the driving transistor, and its gate 202g coupled to the reset signal line pattern (e.g., RST1).

[0233] Specifically, the first conductive connection portion 405 may be made of metal material and may be formed in the same patterning process as the data cable pattern.

[0234] The above-described configuration allows the orthographic projection of the first conductive connection portion 405 on the substrate 50 to cover at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50. This enables the first conductive connection portion 405 to cover the sixth conductor pattern 101px. Furthermore, since the first conductive connection portion 405 is coupled to the initialization signal line pattern, it has a fixed potential. This further reduces the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns, resulting in more stable performance of the display substrate.

[0235] like Figure 3 As shown, in some embodiments, the sub-pixel further includes: a gate pattern GATE, a light emission control signal line pattern EM, and a reset signal line pattern (such as...). Figure 3 The RST1) and power signal line pattern VDD; the gate line pattern GATE, the light emission control signal line pattern EM and the reset signal line pattern all extend along the second direction, and the power signal line pattern VDD includes a portion extending along the first direction;

[0236] The sub-pixel driving circuit further includes: a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7;

[0237] The gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second terminal of the first transistor T1, the first terminal of the driving transistor is coupled to the second terminal of the fifth transistor T5, and the second terminal of the driving transistor is coupled to the first terminal of the first transistor T1.

[0238] The gate 201g of the first transistor T1 is coupled to the gate pattern GATE;

[0239] The gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first terminal of the second transistor T2 is coupled to the initialization signal line pattern, and the second terminal of the second transistor T2 is coupled to the gate of the driving transistor.

[0240] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, and the first electrode of the fourth transistor T4 is coupled to the data line pattern (e.g., Figure 3 The second terminal of the fourth transistor T4 is coupled to the first terminal of the driving transistor;

[0241] The gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern EM, and the first terminal of the fifth transistor T5 is coupled to the power signal line pattern VDD.

[0242] The gate 206g of the sixth transistor T6 is coupled to the light-emitting control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor T6 is coupled to the light-emitting element in the sub-pixel.

[0243] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) of the next sub-pixel adjacent to the first direction, the first electrode of the seventh transistor T7 is coupled to the initialization signal line pattern (such as VINT2) of the next sub-pixel, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.

[0244] Specifically, in the above-mentioned display substrate, the multiple sub-pixels can be arranged in an array. The multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and each column of sub-pixels includes multiple sub-pixels arranged along a first direction. The first direction intersects with the second direction.

[0245] It should be noted that the next sub-pixel adjacent along the first direction is the next sub-pixel adjacent to the seventh transistor T7 in the same column.

[0246] By configuring the sub-pixel and its included sub-pixel driving circuit as described above, the layout space occupied by the sub-pixel driving circuit can be effectively reduced while ensuring the working performance of the sub-pixel driving circuit, which is beneficial to improving the resolution of the display substrate.

[0247] It should be noted that the gates of each transistor included in the sub-pixel driving circuit and the functional patterns coupled thereto can be formed into an integral structure. For example, the gates of the first transistor and the fourth transistor are both integral structures with the corresponding coupled gate line patterns, the gates of the fifth transistor and the sixth transistor are both integral structures with the corresponding coupled light emission control signal line patterns, and the gates of the second transistor and the seventh transistor are integral structures with the corresponding coupled reset signal line patterns.

[0248] Additionally, the first transistor T1 is used to perform threshold compensation on the driving transistor (such as the third transistor T3), the second transistor T2 is used to reset the gate of the driving transistor, the fourth transistor T4 is used to write the data signal transmitted by the data line pattern, the fifth transistor T5 is used to write the power signal transmitted by the power signal line pattern to the first terminal of the driving transistor, the sixth transistor T6 is used to control whether the corresponding light-emitting element emits light, and the seventh transistor T7 is used to reset the anode of the light-emitting element.

[0249] In some embodiments, the sub-pixel further includes: a gate pattern GATE, a light emission control signal line pattern EM, a reset signal line pattern RST, and a power signal line pattern VDD; the gate pattern GATE, the light emission control signal line pattern EM, and the reset signal line pattern RST all extend along the second direction, and the power signal line pattern VDD includes a portion extending along the first direction; the orthographic projection of the first shielding member 404 on the substrate 50 overlaps with the orthographic projections of the gate pattern GATE on the substrate 50 and the orthographic projections of the light emission control signal line pattern EM on the substrate 50, respectively.

[0250] Specifically, the first shielding component 404 is arranged in the manner described above, so that the first shielding component 404 can isolate the first transistor T1 and the driving transistor from the target data line pattern (such as DATA2), thereby making it more beneficial to reduce the crosstalk caused by changes in the data signal on the target data line pattern to the first transistor T1 and the driving transistor.

[0251] In some embodiments, the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel in various ways. For example, the orthographic projection of the anode of the light-emitting element on the substrate overlaps with the orthographic projection of the second electrode of the seventh transistor T7 on the substrate, and the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through a via disposed at the overlap. Alternatively, the orthographic projection of the anode of the light-emitting element on the substrate does not overlap with the orthographic projection of the second electrode of the seventh transistor T7 on the substrate. In this case, the sub-pixel driving circuit further includes a second conductive connection portion 406 and a third conductive connection portion 407, where the orthographic projection of the anode of the light-emitting element on the substrate overlaps with the orthographic projection of the first end of the third conductive connection portion 407 on the substrate. The anode of the light-emitting element is coupled to the first end of the third conductive connection 407 through a via at the overlapping point. The second end of the third conductive connection 407 overlaps with the first end of the second conductive connection 406. The second end of the third conductive connection 407 and the first end of the second conductive connection 406 are coupled through a via at the overlapping point. The orthographic projection of the second electrode of the seventh transistor T7 on the substrate overlaps with the orthographic projection of the second end of the second conductive connection 406 on the substrate. The second electrode of the seventh transistor T7 is coupled to the second end of the second conductive connection 406 through a via at the overlapping point. Thus, the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through the second conductive connection 406 and the third conductive connection 407.

[0252] When the anode of the light-emitting element is coupled to the second electrode of the seventh transistor T7 through the second conductive connection portion 406 and the third conductive connection portion 407, the second conductive connection portion 406 may include a portion extending along the first direction, the anode of the light-emitting element may be located above the light-emitting control signal line pattern in its corresponding sub-pixel, and the second electrode of the seventh transistor T7 may be located below the light-emitting control signal line pattern in its corresponding sub-pixel.

[0253] like Figure 15 and Figure 24 As shown in the figure, the structure of the sub-pixels of the three colors shown in the figure is explained.

[0254] The light-emitting element in the first color sub-pixel includes a first anode 601, a first organic light-emitting material layer, and a first cathode, which are sequentially stacked in a direction away from the substrate. The orthogonal projection of the first anode 601 on the substrate overlaps with the orthogonal projection of the second electrode of the corresponding seventh transistor T7 on the substrate. The first anode 601 is coupled to the second electrode of the corresponding seventh transistor T7 through a via at the overlap.

[0255] The light-emitting element in the second color sub-pixel includes a second anode 602, a second organic light-emitting material layer, and a second cathode, which are sequentially stacked in a direction away from the substrate. The orthogonal projection of the second anode 602 on the substrate does not overlap with the orthogonal projection of the second electrode of the corresponding seventh transistor T7 on the substrate. The sub-pixel driving circuit in the second color sub-pixel also includes a second conductive connection portion 406 and a third conductive connection portion 407. The second anode 602 is coupled to the second electrode of the corresponding seventh transistor T7 through the second conductive connection portion 406 and the third conductive connection portion 407.

[0256] The light-emitting element in the third color sub-pixel includes a third anode 603, a third organic light-emitting material layer, and a third cathode, which are stacked sequentially in a direction away from the substrate. The orthogonal projection of the third anode 603 on the substrate overlaps with the orthogonal projection of the second electrode of the corresponding seventh transistor T7 on the substrate. The third anode 603 is coupled to the second electrode of the corresponding seventh transistor T7 through a via at the overlap.

[0257] For example, such as Figure 15 As shown, the anode of the organic light-emitting element of each color sub-pixel includes a main electrode and a connecting electrode, and the shape of the main electrode is hexagonal.

[0258] like Figure 15As shown, the first anode 601 of the first color sub-pixel includes a first main electrode 6011 and a first connecting electrode 6012. The first main electrode 6011 and the first connecting electrode 6012 can be an integral structure, and the first connecting electrode 6012 is connected to the second electrode of the seventh transistor T7 of the first color sub-pixel through a connecting hole. The second anode 602 of the second color sub-pixel includes a second main electrode 6021 and a second connecting electrode 6022. The second main electrode 6021 and the second connecting electrode 6022 can be an integral structure, and the second connecting electrode 6022 is connected to the second electrode of the seventh transistor T7 of the second color sub-pixel through a second conductive connecting portion 406 and a third conductive connecting portion 407. The third anode 603 of the third color sub-pixel includes a third main electrode 6031 and a third connecting electrode 6032. The third main electrode 6031 and the third connecting electrode 6032 can be an integral structure, and the third connecting electrode 6032 is connected to the second electrode of the seventh transistor T7 of the third color sub-pixel through a connecting hole.

[0259] For example, the first connection electrode 6012 of the first color sub-pixel is located in the X direction on the side away from the data line pattern of the sub-pixel pixel circuit from the center of the first main electrode 6011, and in the Y direction on the side away from the light emission control signal line of the sub-pixel pixel circuit from the center of the first main electrode 6011. For example, the first connection electrode 6012 and the first main electrode 6011 of the first color sub-pixel are arranged in the Y direction, with the first connection electrode 6012 located at the lower right corner of the first main electrode 6011. For example, the second connection electrode 6022 of the second color sub-pixel is located in the X direction on the side away from the data line of the sub-pixel pixel circuit from the center of the second main electrode 6021, and in the Y direction on the side close to the light emission control signal line of the sub-pixel pixel circuit from the center of the second main electrode 6021. For example, the second connection electrode 6022 and the second main electrode 6021 of the second color sub-pixel are arranged in the Y direction, with the second connection electrode 6022 located at the lower right corner of the first main electrode 1231. For example, the third connecting electrode 6032 and the third main electrode 6031 of the third color sub-pixel are arranged in the X direction, and the third connecting electrode 6032 is located to the right of the third main electrode 6031, that is, close to the side of the sub-pixel pixel circuit that is close to the shielding line.

[0260] like Figure 15 As shown, the first main electrode 6011 of the first anode 601 of the first color sub-pixel covers the driving transistor of the first color sub-pixel, the second main electrode 6021 of the second anode 602 of the second color sub-pixel basically does not overlap with or partially overlaps with the driving transistor of the second color sub-pixel, and the third main electrode 6031 of the third anode 603 of the third color sub-pixel does not overlap with the driving transistor of the third color sub-pixel.

[0261] likeFigure 15 As shown, the first main electrode 6011 of the first color sub-pixel 601 (e.g., the blue sub-pixel) overlaps with the gate pattern and the light emission control signal line pattern; the second main electrode 6021 of the second color sub-pixel (e.g., the red sub-pixel) overlaps with the gate pattern and the reset signal line pattern; the third main electrode 6031 of the third color sub-pixel (e.g., the green sub-pixel) overlaps with the light emission control signal line pattern, the reset signal line pattern of the next row sub-pixel driving circuit, and the initialization signal line pattern of the next row sub-pixel driving circuit. For example, the third main electrode 6031 of the third color sub-pixel (e.g., the green sub-pixel) overlaps with the pixel driving circuit area of ​​the adjacent first color sub-pixel (e.g., the blue sub-pixel) in the next row.

[0262] For example, the first main electrode 6011 of the first color sub-pixel 601 partially overlaps with the driving transistor of the adjacent third color sub-pixel, and the first main electrode 6011 of the first color sub-pixel 601 also overlaps with the data line pattern in its sub-pixel driving circuit, the first shielding component 404, and the data line pattern in the sub-pixel driving circuit of the adjacent second color sub-pixel. The second main electrode 6021 of the second color sub-pixel does not overlap with the data line pattern in its sub-pixel driving circuit, but overlaps with the power signal line pattern in its sub-pixel driving circuit and the power signal line pattern and data line pattern in the sub-pixel driving circuit of the adjacent third color sub-pixel. The third main electrode 6031 of the third color sub-pixel overlaps with both the data line pattern and the power signal line pattern in its sub-pixel driving circuit, and also overlaps with the power signal line pattern in the sub-pixel driving circuit of the adjacent second color sub-pixel.

[0263] For example, such as Figure 15 As shown, the first main electrode 6011 of the first color sub-pixel 601 is provided with a first connection electrode 6012 connected to it on the side near the next row of reset signal line pattern; the second main electrode 6021 of the second color sub-pixel is provided with a second connection electrode 6022 connected to it on the side near the next row of reset signal line pattern; the third main electrode 6031 of the third color sub-pixel is provided with a third connection electrode 6032 connected to it on the side near its seventh transistor T7.

[0264] For example, such as Figure 15As shown, the first connection electrode 6012 of the first color sub-pixel 601 overlaps with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit. The second connection electrode 6022 of the second color sub-pixel does not overlap with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit, but the second electrode of the seventh transistor T7 of the second color sub-pixel overlaps with the third main electrode 6031 of the third color sub-pixel. The third connection electrode 6032 of the third color sub-pixel overlaps with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit.

[0265] like Figure 26 As shown, this disclosure also provides a display substrate, including: a substrate 50 and a plurality of sub-pixels arrayed on the substrate 50; the sub-pixels include:

[0266] A data line pattern extending along the first direction (e.g., DATA1);

[0267] An initialization signal line pattern (e.g., VINT1) is provided, which includes a portion extending along a second direction that intersects with the first direction. The initialization signal line pattern is used to transmit an initialization signal with a fixed potential.

[0268] A sub-pixel driving circuit includes: a driving transistor (e.g., a third transistor T3), a first transistor T1 coupled to the gate of the driving transistor, and a first shielding component 404 coupled to the initialization signal line pattern. The first shielding component 404 is used to form a coupling capacitance with the first terminal (i.e., the source S1) of the first transistor T1. The orthographic projection of the first shielding component 404 on the substrate 50 does not overlap with the orthographic projection of the target data line pattern (e.g., DATA2) on the substrate 50. The next sub-pixel adjacent to the sub-pixel along the second direction includes the target data line pattern.

[0269] Specifically, the aforementioned display substrate generally includes multiple sub-pixels arranged in an array, each sub-pixel including: a data line pattern extending along a first direction (such as...). Figure 3 DATA1 in the diagram), and the initialization signal line pattern extending at least partially along the second direction (such as...). Figure 3 The data line pattern is used to transmit data signals, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential. For example, the first direction includes the Y direction, and the second direction includes the X direction.

[0270] The target data line pattern is: the data line pattern included in the next sub-pixel adjacent to the current sub-pixel along the second direction.

[0271] Each sub-pixel also includes a sub-pixel driving circuit and a light-emitting element corresponding to the sub-pixel driving circuit. The light-emitting element includes an anode, an organic light-emitting material layer, and a cathode stacked together. The anode of the light-emitting element is coupled to the corresponding sub-pixel driving circuit. Under the drive signal provided by the sub-pixel driving circuit, the light-emitting element emits light.

[0272] More specifically, such as Figure 1 , Figure 3 and Figure 4 As shown, taking the sub-pixel driving circuit including the aforementioned 7T1C as an example, the gate 203g of the third transistor T3 (i.e., the driving transistor) is coupled to the drain D1 of the first transistor T1 via a connection line 401, and the drain D3 of the third transistor T3 is coupled to the source S1 of the first transistor T1. Along the X direction, the orthogonal projection of the first channel region 101pg of the first transistor T1 onto the substrate 50 coincides with the target data line pattern (e.g., ...). Figure 3 The minimum distance between the orthographic projections of DATA2) on the substrate 50 is less than the minimum distance between the orthographic projection of the third channel region 103pg of the third transistor T3 on the substrate 50 and the minimum distance between the orthographic projection of the target data line pattern on the substrate 50. It is noteworthy that the orthographic projections of the aforementioned channel regions (e.g., the first channel region 101pg and the third channel region 103pg) on ​​the substrate 50 and the minimum distance between the orthographic projections of the target data line pattern (e.g., the first channel region 101pg and the third channel region 103pg) on ​​the substrate 50 and the target data line pattern (e.g., the first channel region 101pg and the third channel region 103pg) on ​​the substrate 50 are less than the minimum distance between the orthographic projections of the third channel region 103pg of the third transistor T3 on the substrate Figure 3 The minimum distance between the orthographic projections of DATA2 on the substrate 50 refers to the boundary of the channel region closest to the target data line pattern in its orthographic projection on the substrate 50, and the boundary of the target data line pattern (e.g., DATA2). Figure 3 The minimum distance between the orthographic projections of DATA2 on the substrate 50.

[0273] In the sub-pixel driving circuit of the above structure, when the data signal transmitted by the target data line pattern changes, it will affect the performance of the first transistor T1. Since the first transistor T1 is coupled to the third transistor T3 through the connection line 401, it will affect the working performance of the third transistor T3.

[0274] In this embodiment of the disclosure, a pattern related to the initialization signal line (e.g., ...) is set in the sub-pixel driving circuit. Figure 3The first shielding component 404 is coupled to VINT1 in the first transistor T1, so that the first shielding component 404 has the same fixed potential as the initialization signal, and the first shielding component 404 is configured to form a coupling capacitance with the first terminal (i.e., the source S1) of the first transistor T1. This allows the first shielding component 404 to reduce the impact of signal changes transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the coupling effect between the gate (i.e., 203g) of the driving transistor and the target data line pattern, weakening the vertical crosstalk problem, and enabling the display substrate to obtain a better display effect when used for display.

[0275] In addition, the above-mentioned coupling of the first shielding component 404 with the initialization signal line pattern not only makes the first shielding component 404 have a fixed potential, but also strengthens the voltage of the initialization signal line pattern, making the voltage of the initialization signal transmitted on the initialization signal line pattern more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0276] It is worth noting that, in addition to coupling the first shielding component 404 to the initialization signal line pattern, the first shielding component 404 can also be coupled to the power signal line pattern VDD included in the sub-pixel, so that the first shielding component 404 has the same fixed potential as the power signal transmitted by the power signal line pattern VDD.

[0277] The above-described method of coupling the first shielding component 404 to the power signal line pattern VDD can ensure that the first shielding component 404 has a fixed potential, but it will increase the parasitic capacitance generated by the power signal line pattern VDD, making the RC load of the power signal line pattern VDD larger, which is not conducive to reducing vertical crosstalk.

[0278] like Figure 3 As shown, in some embodiments, the gate 201g of the first transistor T1 and the gate pattern GATE are an integral structure, and the gate 201g of the first transistor T1 is a portion of the integral structure that can form an overlapping region with the active film layer in a direction perpendicular to the substrate.

[0279] like Figure 3 As shown, in some embodiments, the plurality of sub-pixels includes multiple rows of sub-pixels, each row of sub-pixels includes a plurality of the sub-pixels arranged along the second direction, and the initialization signal line patterns located in the same row of sub-pixels are sequentially coupled to form the initialization signal line corresponding to that row of sub-pixels; the first shielding member 404 extends along the first direction and is coupled to at least one of the initialization signal lines.

[0280] Specifically, the plurality of sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and each column of sub-pixels includes multiple sub-pixels arranged along a first direction. The first direction intersects with the second direction. The initialization signal line patterns located in the same row of sub-pixels are coupled sequentially to form an initialization signal line corresponding to that row of sub-pixels.

[0281] The above-described configuration, in which the first shielding component 404 extends along the first direction and is coupled to at least one of the initialization signal lines, not only enables the first shielding component 404 to reduce the impact of signal variations transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the coupling effect between the gate (i.e., 203g) of the driving transistor and the target data line pattern, and weakening the problem of vertical crosstalk, thus enabling the display substrate to obtain a better display effect when used for display; but also strengthens the voltage of the initialization signal line, making the voltage of the initialization signal transmitted on the initialization signal line more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0282] like Figure 9 As shown, in some embodiments, the first shielding component 404 is coupled to its two adjacent initialization signal lines.

[0283] Specifically, when the first shielding component 404 is coupled to the initialization signal line, the coupling method between the first shielding component 404 and the initialization signal line, as well as the specific structure and arrangement of the first shielding component 404, are varied. For example,... Figure 3 As shown, the first shielding component 404 can be coupled to its two adjacent initialization signal lines respectively. This arrangement ensures that the orthographic projection of the first shielding component 404 on the substrate 50 is not only located between the orthographic projection of the first transistor T1 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; it also ensures that the orthographic projection of the first shielding component 404 on the substrate 50 is located between the orthographic projection of the connecting line 401 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; and it also ensures that the orthographic projection of the first shielding component 404 on the substrate 50 is located between the orthographic projection of the driving transistor (i.e., the third transistor T3) on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50.

[0284] The above-described configuration effectively reduces the first crosstalk between the target signal line pattern and the first transistor T1, as well as the second crosstalk between the target signal line pattern and the connecting line 401, thereby reducing the indirect crosstalk to the driving transistor caused by the first and second crosstalk. Furthermore, the above-described configuration also reduces the direct crosstalk between the target signal line pattern and the driving transistor, thus better ensuring the operating performance of the display substrate.

[0285] Please continue reading. Figure 3 In some embodiments, the first shielding component 404 is connected to the initialization signal line pattern (e.g., Figure 3 In the VINT1) heterogeneous layer setting, the orthographic projection of the first shielding component 404 on the substrate 50 has a first overlapping area with the orthographic projection of the initialization signal line pattern on the substrate, and the first shielding component 404 is coupled to the initialization signal line pattern through a first via provided in the first overlapping area.

[0286] Specifically, the first shielding component 404 can be disposed on the same layer or on a different layer than the initialization signal line pattern. When the first shielding component 404 and the initialization signal line pattern are disposed on a different layer, the orthographic projection of the first shielding component 404 on the substrate 50 and the orthographic projection of the initialization signal line pattern on the substrate 50 can both have a first overlapping area. In this way, by setting a first via in the first overlapping area, the coupling between the first shielding component 404 and the initialization signal line can be achieved.

[0287] It should be noted that the above-mentioned "the first shielding component 404 can be disposed in the same layer as the initialization signal line pattern" includes at least one of the following: the first shielding component 404 and the initialization signal line pattern are located on the same horizontal plane; the first shielding component 404 and the initialization signal line pattern are located in the same film layer; the first shielding component 404 and the initialization signal line pattern are both disposed on the surface of the same insulating layer facing away from the substrate; and the first shielding component 404 and the initialization signal line pattern are formed by a single patterning process.

[0288] The aforementioned "the first shielding component 404 may be disposed in a different layer from the initialization signal line pattern" includes at least one of the following situations: the first shielding component 404 and the initialization signal line pattern are not located in the same film layer; the first shielding component 404 and the initialization signal line pattern cannot be formed by a single patterning process.

[0289] In some embodiments, the first shielding component 404 and the data cable pattern (e.g.) can be configured. Figure 3 DATA1 in the settings is the same as the material settings.

[0290] In some embodiments, the display substrate may include a first interlayer insulating layer, and the first shielding member 404 and the data line pattern (such as...) Figure 3 DATA1) are all located on the surface of the first interlayer insulation layer facing away from the substrate.

[0291] Specifically, by setting the first shielding component 404 in the manner described above, the first shielding component 404 and the data line pattern can be formed simultaneously on the surface of the first interlayer insulating layer facing away from the substrate through a single patterning process. This avoids the need for additional patterning processes to manufacture the first shielding component 404, thereby greatly simplifying the manufacturing process of the display substrate and saving manufacturing costs.

[0292] like Figure 3 As shown, in some embodiments, the sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, the second transistor T2 comprising:

[0293] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern respectively, wherein the conductivity of the third conductor pattern is better than that of the first semiconductor pattern and the second semiconductor pattern.

[0294] A first gate pattern and a second gate pattern are coupled together, wherein the orthographic projection of the first gate pattern on the substrate 50 overlaps with the orthographic projection of the first semiconductor pattern on the substrate 50, and the orthographic projection of the second gate pattern on the substrate 50 overlaps with the orthographic projection of the second semiconductor pattern on the substrate 50.

[0295] The orthographic projection of the third conductor pattern on the substrate 50 does not overlap with the orthographic projection of the first gate pattern on the substrate 50, nor with the orthographic projection of the second gate pattern on the substrate 50.

[0296] The orthographic projection of the third conductor pattern onto the substrate 50, and the initialization signal line pattern (e.g., ...). Figure 3 The orthographic projections of VINT1 on the substrate 50 at least partially overlap.

[0297] Specifically, such as Figure 7 As shown, the second transistor T2 has a dual-gate structure, and the first semiconductor pattern and the second semiconductor pattern therein form the channel region of the second transistor T2 (corresponding to...). Figure 7The third conductor pattern 102px, which is marked at position 102pg, has better conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping. The first gate pattern and the second gate pattern of the second transistor T2 cover the first semiconductor pattern and the second semiconductor pattern respectively, and can be used together as the gate 202g of the second transistor T2.

[0298] In the second transistor T2 of the above structure, because the third conductor pattern 102px has good conductivity and is not covered by the gate pattern, it is prone to coupling with other nearby conductive patterns, resulting in crosstalk. In the technical solution provided by the above embodiment, by setting the orthogonal projection of the third conductor pattern on the substrate 50, and the initialization signal line pattern (such as...) Figure 3 The VINT1 in the diagram at least partially overlaps with the orthographic projection on the substrate 50, so that the initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the coupling effect between the third conductor pattern 102px and other nearby conductive patterns is better reduced, thereby making the working performance of the display substrate more stable.

[0299] like Figure 4 As shown, in some embodiments, the sub-pixel driving circuit further includes a first extension extending from the first semiconductor pattern, the first extension having better conductivity than the first semiconductor pattern; the first extension includes a first portion 61, a second portion 62, and a third portion 63, the first portion 61 and the third portion 63 both extending along the first direction, the second portion 62 extending along the second direction, one end of the second portion 62 being coupled to the first portion 61, and the other end of the second portion 62 being coupled to the third portion 63; the end of the third portion 63 away from the second portion 62 is coupled to the first transistor T1.

[0300] Specifically, the first extension can be fabricated in a single patterning process with the first semiconductor pattern, and after the first semiconductor pattern is formed, the first extension is doped so that the conductivity of the first extension is better than that of the first semiconductor pattern.

[0301] After adding the first shielding component 404, the first extension is configured as described above. This makes it easier to reduce the impact of signal changes transmitted on the target data line pattern on the performance of the first transistor T1 and the second transistor T2 when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor respectively through the first extension. This reduces the coupling effect between the gate of the driving transistor (i.e., 203g) and the target data line pattern, weakens the vertical crosstalk problem, and enables the display substrate to obtain a better display effect when used for display.

[0302] like Figure 3 and Figure 4 As shown, in some embodiments, the first transistor T1 includes:

[0303] A fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern respectively, wherein the conductivity of the sixth conductor pattern is better than that of the fourth semiconductor pattern and the fifth semiconductor pattern;

[0304] A third gate pattern and a fourth gate pattern are coupled together, wherein the orthographic projection of the third gate pattern on the substrate 50 partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate 50, and the orthographic projection of the fourth gate pattern on the substrate 50 partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate 50.

[0305] The orthographic projection of the sixth conductor pattern on the substrate 50, the orthographic projection of the third gate pattern on the substrate 50, and the orthographic projection of the fourth gate pattern on the substrate 50 do not overlap.

[0306] Specifically, such as Figure 4 As shown, the first transistor has a dual-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included therein form the channel region of the first transistor (corresponding to...). Figure 4 The sixth conductor pattern 101px, which is marked 101pg, has better conductivity than the fourth and fifth semiconductor patterns due to doping. The third and fourth gate patterns of the first transistor cover the fourth and fifth semiconductor patterns respectively and can be used together as the gate 201g of the first transistor T1.

[0307] like Figure 10 As shown, in some embodiments, the orthographic projection of the first shielding member 404 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50.

[0308] Specifically, in the first transistor T1 of the above structure, since the sixth conductor pattern 101px has good conductivity and is not covered by the gate pattern, it is prone to coupling with other conductive patterns nearby, resulting in crosstalk. In the technical solution provided by the above embodiment, by setting the orthographic projection of the first shielding member 404 on the substrate 50 to at least partially overlap with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, the first shielding member 404 can cover the sixth conductor pattern 101px. Furthermore, since the first shielding member 404 has a fixed potential, the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby is better reduced, making the working performance of the display substrate more stable.

[0309] like Figure 11 , Figure 12 and Figure 13 As shown, in some embodiments, the sub-pixel driving circuit further includes a second shielding component 301 coupled to the first shielding component 404, wherein the orthographic projection of the second shielding component 301 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50.

[0310] Specifically, the above-mentioned arrangement of the orthographic projection of the second shielding component 301 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px. Furthermore, since the second shielding component 301 is coupled to the first shielding component 404, the second shielding component 301 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns, making the working performance of the display substrate more stable.

[0311] Therefore, in the display substrate provided in the above embodiments, since both the first shielding component 404 and the second shielding component 301 have a fixed potential, the formation of parasitic capacitance between the first transistor T1 and the target data line pattern (such as DATA2) is better prevented or reduced, and vertical crosstalk defects are effectively prevented or reduced.

[0312] Furthermore, the orthographic projection of the second shielding component 301 on the substrate 50 may be configured to cover the entire orthographic projection of the sixth conductor pattern on the substrate 50.

[0313] Specifically, the orthographic projection of the second shielding component 301 on the substrate 50 covers the entire orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can completely cover the sixth conductor pattern 101px, thereby minimizing the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns, and better improving the working stability of the display substrate.

[0314] In some embodiments, the second shielding component 301 and the first shielding component 404 are disposed in different layers, and the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50 have a second overlapping area, and the second shielding component 301 and the first shielding component 404 are coupled through a second through-hole disposed in the second overlapping area.

[0315] Specifically, the second shielding component 301 can be disposed in the same layer as the first shielding component 404 or disposed in a different layer. When the second shielding component 301 and the first shielding component 404 are disposed in a different layer, a second overlapping area can be provided between the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50. In this way, by providing a second via in the second overlapping area, the second shielding component 301 and the first shielding component 404 can be coupled through the second via.

[0316] In some embodiments, the second shielding component 301 may be made of the same material as the initialization signal line pattern.

[0317] In some embodiments, the display substrate may further include a second interlayer insulating layer, wherein the second shielding member 301 and the initialization signal line pattern (such as...) Figure 3 The VINT1 in the second interlayer insulation layer is located on the surface of the second interlayer insulation layer facing away from the substrate.

[0318] Specifically, the second shielding component 301 and the initialization signal line pattern are made of the same material, and the second shielding component 301 and the initialization signal line pattern (such as...) are... Figure 3 The VINT1 in the second interlayer insulating layer is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second shielding component 301 can be formed simultaneously with the initialization signal line pattern in the same patterning process. This avoids the need for additional manufacturing processes specifically for the second shielding component 301, thereby greatly simplifying the manufacturing process of the display substrate and saving production costs.

[0319] like Figure 3As shown, in some embodiments, the sub-pixel further includes a power signal line pattern VDD, the power signal line pattern VDD including a portion extending along the first direction, and the sub-pixel driving circuit further includes a storage capacitor Cst, the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the driving transistor, the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, and the second plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate.

[0320] Specifically, the sub-pixel driving circuit includes a storage capacitor Cst with a first plate Cst1 and a second plate Cst2. The first plate Cst1 and the second plate Cst2 are arranged opposite to each other, and the first plate Cst1 is coupled to the gate of the driving transistor, while the second plate Cst2 is coupled to the power signal line pattern VDD. When laying out the storage capacitor Cst, the first plate Cst1 can be directly reused as the gate of the driving transistor. This not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor but also reduces the space occupied by the sub-pixel driving circuit, which is more conducive to improving the resolution of the display substrate. Furthermore, the second plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate, allowing the second plate Cst2 of the storage capacitor Cst to be formed simultaneously with the second shielding component 301 and the initialization signal line pattern in the same patterning process. This greatly simplifies the manufacturing process of the display substrate and saves production costs.

[0321] like Figure 14 As shown, in some embodiments, the sub-pixel further includes: a reset signal line pattern extending along a second direction intersecting the first direction (e.g., Figure 3 The sub-pixel driving circuit further includes: (RST1 in the original text)

[0322] The first conductive connection portion 405, the orthographic projection of the first conductive connection portion 405 on the substrate 50 covers at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50;

[0323] The second transistor T2 has its first terminal (e.g., source S2) coupled to the initialization signal line pattern (e.g., VINT1) via the first conductive connection portion 405, its second terminal (e.g., drain D2) coupled to the gate of the driving transistor, and its gate 202g coupled to the reset signal line pattern (e.g., RST1).

[0324] Specifically, the first conductive connection portion 405 may be made of metal material and may be formed in the same patterning process as the data cable pattern.

[0325] The above-described configuration allows the orthographic projection of the first conductive connection portion 405 on the substrate 50 to cover at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50. This enables the first conductive connection portion 405 to cover the sixth conductor pattern 101px. Furthermore, since the first conductive connection portion 405 is coupled to the initialization signal line pattern, it has a fixed potential. This further reduces the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns, resulting in more stable performance of the display substrate.

[0326] like Figure 3 As shown, in some embodiments, the sub-pixel further includes: a gate pattern GATE, a light emission control signal line pattern EM, and a reset signal line pattern (such as...). Figure 3 The RST1) and power signal line pattern VDD; the gate line pattern GATE, the light emission control signal line pattern EM and the reset signal line pattern all extend along the second direction, and the power signal line pattern VDD includes a portion extending along the first direction;

[0327] The sub-pixel driving circuit further includes: a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7;

[0328] The gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second terminal of the first transistor T1, the first terminal of the driving transistor is coupled to the second terminal of the fifth transistor T5, and the second terminal of the driving transistor is coupled to the first terminal of the first transistor T1.

[0329] The gate 201g of the first transistor T1 is coupled to the gate pattern GATE;

[0330] The gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first terminal of the second transistor T2 is coupled to the initialization signal line pattern, and the second terminal of the second transistor T2 is coupled to the gate of the driving transistor.

[0331] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, and the first electrode of the fourth transistor T4 is coupled to the data line pattern (e.g., Figure 3 The second terminal of the fourth transistor T4 is coupled to the first terminal of the driving transistor;

[0332] The gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern EM, and the first terminal of the fifth transistor T5 is coupled to the power signal line pattern VDD.

[0333] The gate 206g of the sixth transistor T6 is coupled to the light-emitting control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor T6 is coupled to the light-emitting element in the sub-pixel.

[0334] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) of the next sub-pixel adjacent to the first direction, the first electrode of the seventh transistor T7 is coupled to the initialization signal line pattern (such as VINT2) of the next sub-pixel, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.

[0335] Specifically, in the above-mentioned display substrate, the multiple sub-pixels can be arranged in an array. The multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and each column of sub-pixels includes multiple sub-pixels arranged along a first direction. The first direction intersects with the second direction.

[0336] It should be noted that the next sub-pixel adjacent along the first direction is the next sub-pixel adjacent to the seventh transistor T7 in the same column.

[0337] By configuring the sub-pixel and its included sub-pixel driving circuit as described above, the layout space occupied by the sub-pixel driving circuit can be effectively reduced while ensuring the working performance of the sub-pixel driving circuit, which is beneficial to improving the resolution of the display substrate.

[0338] It should be noted that the gates of each transistor included in the sub-pixel driving circuit and the functional patterns coupled thereto can be formed into an integral structure. For example, the gates of the first transistor and the fourth transistor are both integral structures with the corresponding coupled gate line patterns, the gates of the fifth transistor and the sixth transistor are both integral structures with the corresponding coupled light emission control signal line patterns, and the gates of the second transistor and the seventh transistor are integral structures with the corresponding coupled reset signal line patterns.

[0339] Additionally, the first transistor T1 is used to perform threshold compensation on the driving transistor (such as the third transistor T3), the second transistor T2 is used to reset the gate of the driving transistor, the fourth transistor T4 is used to write the data signal transmitted by the data line pattern, the fifth transistor T5 is used to write the power signal transmitted by the power signal line pattern to the first terminal of the driving transistor, the sixth transistor T6 is used to control whether the corresponding light-emitting element emits light, and the seventh transistor T7 is used to reset the anode of the light-emitting element.

[0340] In some embodiments, the sub-pixel further includes: a gate pattern GATE, a light emission control signal line pattern EM, a reset signal line pattern RST, and a power signal line pattern VDD; the gate pattern GATE, the light emission control signal line pattern EM, and the reset signal line pattern RST all extend along the second direction, and the power signal line pattern VDD includes a portion extending along the first direction; the orthographic projection of the first shielding member 404 on the substrate 50 overlaps with the orthographic projections of the gate pattern GATE on the substrate 50 and the orthographic projections of the light emission control signal line pattern EM on the substrate 50, respectively.

[0341] Specifically, the first shielding component 404 is arranged in the manner described above, so that the first shielding component 404 can isolate the first transistor T1 and the driving transistor from the target data line pattern (such as DATA2), thereby making it more beneficial to reduce the crosstalk caused by changes in the data signal on the target data line pattern to the first transistor T1 and the driving transistor.

[0342] In some embodiments, the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel in various ways. For example, the orthographic projection of the anode of the light-emitting element on the substrate overlaps with the orthographic projection of the second electrode of the seventh transistor T7 on the substrate, and the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through a via disposed at the overlap. Alternatively, the orthographic projection of the anode of the light-emitting element on the substrate does not overlap with the orthographic projection of the second electrode of the seventh transistor T7 on the substrate. In this case, the sub-pixel driving circuit further includes a second conductive connection portion 406 and a third conductive connection portion 407, where the orthographic projection of the anode of the light-emitting element on the substrate overlaps with the orthographic projection of the first end of the third conductive connection portion 407 on the substrate. The anode of the light-emitting element is coupled to the first end of the third conductive connection 407 through a via at the overlapping point. The second end of the third conductive connection 407 overlaps with the first end of the second conductive connection 406. The second end of the third conductive connection 407 and the first end of the second conductive connection 406 are coupled through a via at the overlapping point. The orthographic projection of the second electrode of the seventh transistor T7 on the substrate overlaps with the orthographic projection of the second end of the second conductive connection 406 on the substrate. The second electrode of the seventh transistor T7 is coupled to the second end of the second conductive connection 406 through a via at the overlapping point. Thus, the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through the second conductive connection 406 and the third conductive connection 407.

[0343] When the anode of the light-emitting element is coupled to the second electrode of the seventh transistor T7 through the second conductive connection portion 406 and the third conductive connection portion 407, the second conductive connection portion 406 may include a portion extending along the first direction, the anode of the light-emitting element may be located above the light-emitting control signal line pattern in its corresponding sub-pixel, and the second electrode of the seventh transistor T7 may be located below the light-emitting control signal line pattern in its corresponding sub-pixel.

[0344] like Figure 15 As shown in the figure, the structure of the sub-pixels of the three colors shown in the figure is explained.

[0345] The light-emitting element in the first color sub-pixel includes a first anode 601, a first organic light-emitting material layer, and a first cathode, which are sequentially stacked in a direction away from the substrate. The orthogonal projection of the first anode 601 on the substrate overlaps with the orthogonal projection of the second electrode of the corresponding seventh transistor T7 on the substrate. The first anode 601 is coupled to the second electrode of the corresponding seventh transistor T7 through a via at the overlap.

[0346] The light-emitting element in the second color sub-pixel includes a second anode 602, a second organic light-emitting material layer, and a second cathode, which are sequentially stacked in a direction away from the substrate. The orthogonal projection of the second anode 602 on the substrate does not overlap with the orthogonal projection of the second electrode of the corresponding seventh transistor T7 on the substrate. The sub-pixel driving circuit in the second color sub-pixel also includes a second conductive connection portion 406 and a third conductive connection portion 407. The second anode 602 is coupled to the second electrode of the corresponding seventh transistor T7 through the second conductive connection portion 406 and the third conductive connection portion 407.

[0347] The light-emitting element in the third color sub-pixel includes a third anode 603, a third organic light-emitting material layer, and a third cathode, which are stacked sequentially in a direction away from the substrate. The orthogonal projection of the third anode 603 on the substrate overlaps with the orthogonal projection of the second electrode of the corresponding seventh transistor T7 on the substrate. The third anode 603 is coupled to the second electrode of the corresponding seventh transistor T7 through a via at the overlap.

[0348] For example, such as Figure 15 As shown, the anode of the organic light-emitting element of each color sub-pixel includes a main electrode and a connecting electrode, and the shape of the main electrode is hexagonal.

[0349] like Figure 15 As shown, the first anode 601 of the first color sub-pixel includes a first main electrode 6011 and a first connecting electrode 6012. The first main electrode 6011 and the first connecting electrode 6012 can be an integral structure, and the first connecting electrode 6012 is connected to the second electrode of the seventh transistor T7 of the first color sub-pixel through a connecting hole. The second anode 602 of the second color sub-pixel includes a second main electrode 6021 and a second connecting electrode 6022. The second main electrode 6021 and the second connecting electrode 6022 can be an integral structure, and the second connecting electrode 6022 is connected to the second electrode of the seventh transistor T7 of the second color sub-pixel through a second conductive connecting portion 406 and a third conductive connecting portion 407. The third anode 603 of the third color sub-pixel includes a third main electrode 6031 and a third connecting electrode 6032. The third main electrode 6031 and the third connecting electrode 6032 can be an integral structure, and the third connecting electrode 6032 is connected to the second electrode of the seventh transistor T7 of the third color sub-pixel through a connecting hole.

[0350] For example, the first connection electrode 6012 of the first color sub-pixel is located in the X direction on the side away from the data line pattern of the sub-pixel pixel circuit from the center of the first main electrode 6011, and in the Y direction on the side away from the light emission control signal line of the sub-pixel pixel circuit from the center of the first main electrode 6011. For example, the first connection electrode 6012 and the first main electrode 6011 of the first color sub-pixel are arranged in the Y direction, with the first connection electrode 6012 located at the lower right corner of the first main electrode 6011. For example, the second connection electrode 6022 of the second color sub-pixel is located in the X direction on the side away from the data line of the sub-pixel pixel circuit from the center of the second main electrode 6021, and in the Y direction on the side close to the light emission control signal line of the sub-pixel pixel circuit from the center of the second main electrode 6021. For example, the second connection electrode 6022 and the second main electrode 6021 of the second color sub-pixel are arranged in the Y direction, with the second connection electrode 6022 located at the lower right corner of the first main electrode 1231. For example, the third connecting electrode 6032 and the third main electrode 6031 of the third color sub-pixel are arranged in the X direction, and the third connecting electrode 6032 is located to the right of the third main electrode 6031, that is, close to the side of the sub-pixel pixel circuit that is close to the shielding line.

[0351] like Figure 15 As shown, the first main electrode 6011 of the first anode 601 of the first color sub-pixel covers the driving transistor of the first color sub-pixel, the second main electrode 6021 of the second anode 602 of the second color sub-pixel basically does not overlap with or partially overlaps with the driving transistor of the second color sub-pixel, and the third main electrode 6031 of the third anode 603 of the third color sub-pixel does not overlap with the driving transistor of the third color sub-pixel.

[0352] like Figure 15 As shown, the first main electrode 6011 of the first color sub-pixel 601 (e.g., the blue sub-pixel) overlaps with the gate pattern and the light emission control signal line pattern; the second main electrode 6021 of the second color sub-pixel (e.g., the red sub-pixel) overlaps with the gate pattern and the reset signal line pattern; the third main electrode 6031 of the third color sub-pixel (e.g., the green sub-pixel) overlaps with the light emission control signal line pattern, the reset signal line pattern of the next row sub-pixel driving circuit, and the initialization signal line pattern of the next row sub-pixel driving circuit. For example, the third main electrode 6031 of the third color sub-pixel (e.g., the green sub-pixel) overlaps with the pixel driving circuit area of ​​the adjacent first color sub-pixel (e.g., the blue sub-pixel) in the next row.

[0353] For example, the first main electrode 6011 of the first color sub-pixel 601 partially overlaps with the driving transistor of the adjacent third color sub-pixel, and the first main electrode 6011 of the first color sub-pixel 601 also overlaps with the data line pattern in its sub-pixel driving circuit, the first shielding component 404, and the data line pattern in the sub-pixel driving circuit of the adjacent second color sub-pixel. The second main electrode 6021 of the second color sub-pixel does not overlap with the data line pattern in its sub-pixel driving circuit, but overlaps with the power signal line pattern in its sub-pixel driving circuit and the power signal line pattern and data line pattern in the sub-pixel driving circuit of the adjacent third color sub-pixel. The third main electrode 6031 of the third color sub-pixel overlaps with both the data line pattern and the power signal line pattern in its sub-pixel driving circuit, and also overlaps with the power signal line pattern in the sub-pixel driving circuit of the adjacent second color sub-pixel.

[0354] For example, such as Figure 15 As shown, the first main electrode 6011 of the first color sub-pixel 601 is provided with a first connection electrode 6012 connected to it on the side near the next row of reset signal line pattern; the second main electrode 6021 of the second color sub-pixel is provided with a second connection electrode 6022 connected to it on the side near the next row of reset signal line pattern; the third main electrode 6031 of the third color sub-pixel is provided with a third connection electrode 6032 connected to it on the side near its seventh transistor T7.

[0355] For example, such as Figure 15 As shown, the first connection electrode 6012 of the first color sub-pixel 601 overlaps with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit. The second connection electrode 6022 of the second color sub-pixel does not overlap with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit, but the second electrode of the seventh transistor T7 of the second color sub-pixel overlaps with the third main electrode 6031 of the third color sub-pixel. The third connection electrode 6032 of the third color sub-pixel overlaps with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit.

[0356] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0357] In the display substrate provided in the above embodiments, by providing the first shielding member 404, the impact of signal changes transmitted on the target data line pattern on the performance of the first transistor T1 can be reduced, thereby reducing the coupling effect between the gate (i.e., 203g) of the driving transistor and the target data line pattern, weakening the vertical crosstalk problem, and enabling the display substrate to obtain a better display effect when used for display. In addition, in the display substrate provided in the above embodiments, coupling the first shielding member 404 to the initialization signal line pattern not only makes the first shielding member 404 have a fixed potential, but also strengthens the voltage of the initialization signal line pattern, making the voltage of the initialization signal transmitted on the initialization signal line pattern more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0358] Therefore, the display device provided in this embodiment of the present disclosure, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0359] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer.

[0360] This disclosure also provides a method for manufacturing a display substrate, used to manufacture the display substrate provided in the above embodiments, the method comprising:

[0361] A plurality of sub-pixels are fabricated in an array on a substrate 50; the sub-pixels include:

[0362] Data line pattern extending along the first direction (e.g.) Figure 3 (DATA1 in the middle);

[0363] Initialize signal line pattern (e.g.) Figure 3 VINT1 in the original text), the initialization signal line pattern includes a portion extending along a second direction, which intersects with the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;

[0364] Sub-pixel driving circuit, the sub-pixel driving circuit including: driving transistor (e.g. Figure 3 T3), a first transistor T1 coupled to the gate of the driving transistor, and a first shielding member 404 coupled to the initialization signal line pattern, wherein the orthographic projection of the first shielding member 404 on the substrate 50 is located at the orthographic projection of the first transistor T1 on the substrate 50 and the target data line pattern (e.g., T3), the first transistor T1 coupled to the gate of the driving transistor, and the first shielding member 404 coupled to the initialization signal line pattern, wherein the first shielding member 404 is coupled to ... shielding member 404 is coupled to the gate of the driving transistor, and the first shielding member 404 is coupled to the initialization signal line pattern, wherein the first Figure 3 The target data line pattern is included in the next sub-pixel adjacent to the sub-pixel along the second direction between the orthographic projections of DATA2 on the substrate 50.

[0365] When fabricating the above-mentioned display substrate using the manufacturing method provided in this embodiment, a pattern corresponding to the initialization signal line (such as...) is provided in the sub-pixel driving circuit. Figure 3 The first shielding component 404, coupled to VINT1 in the initialization signal, is given a fixed potential identical to that of the initialization signal. The orthographic projection of the first shielding component 404 onto the substrate 50 is positioned such that the orthographic projection of the first transistor T1 onto the substrate 50 coincides with the target data line pattern (e.g., VINT1). Figure 3 The first shielding component 404 can reduce the impact of signal changes transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the coupling effect between the gate (i.e., 203g) of the driving transistor and the target data line pattern, weakening the problem of vertical crosstalk, and enabling the display substrate to obtain better display effect when used for display.

[0366] In addition, when the above-mentioned display substrate is manufactured using the manufacturing method provided in the embodiments of this disclosure, the first shielding component 404 is coupled to the initialization signal line pattern. In addition to making the first shielding component 404 have a fixed potential, the voltage of the initialization signal line pattern is also strengthened, making the voltage of the initialization signal transmitted on the initialization signal line pattern more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0367] like Figure 16 As shown, this disclosure also provides a display substrate, including: a substrate 50 and a plurality of sub-pixels arrayed on the substrate 50; the sub-pixels include:

[0368] A data line pattern extending along the first direction (e.g., DATA1);

[0369] A power signal line pattern VDD, wherein the power signal line pattern VDD includes a portion extending along the first direction;

[0370] A sub-pixel driving circuit includes: two switching transistors (such as a fourth transistor T4 and a fifth transistor T5), a driving transistor (such as a third transistor T3), and a storage capacitor Cst; the first plate Cst1 of the storage capacitor Cst is coupled to the gate of the driving transistor (such as the gate 203g of the third transistor T3), and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD; the second terminals of the two switching transistors (such as the drain D4 of the fourth transistor T4 and the drain D5 of the fifth transistor T5) are both coupled to the first terminal of the driving transistor (such as the source S3 of the third transistor T3); the orthographic projection of the second terminal of at least one of the two switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and at least partially overlaps with the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50.

[0371] Specifically, the aforementioned display substrate generally includes a plurality of sub-pixels distributed in an array, each sub-pixel including: a data line pattern (such as DATA1) extending along a first direction, and a power signal line pattern VDD extending at least partially along the first direction; for example, the first direction includes the Y direction, and the second direction includes the X direction.

[0372] It is worth noting that the specific structure of the power signal line pattern VDD varies. For example, the power signal line pattern VDD is a grid structure, and the grid structure of the power signal line pattern VDD includes a portion extending along the first direction.

[0373] Each sub-pixel also includes a sub-pixel driving circuit and a light-emitting element corresponding to the sub-pixel driving circuit. The light-emitting element includes an anode, an organic light-emitting material layer, and a cathode stacked together. The anode of the light-emitting element is coupled to the corresponding sub-pixel driving circuit. Under the drive signal provided by the sub-pixel driving circuit, the light-emitting element emits light.

[0374] More specifically, such as Figure 16As shown, taking the sub-pixel driving circuit including the above-mentioned 7T1C as an example, the gate 203g of the third transistor T3 (i.e. the driving transistor) is multiplexed as the first plate Cst1 of the storage capacitor Cst. The second plate Cst2 of the storage capacitor Cst is located on the side of the first plate Cst1 facing away from the substrate. The orthographic projection of the first plate Cst1 on the substrate at least partially overlaps with the orthographic projection of the second plate Cst2 on the substrate. The orthographic projection of the second plate Cst2 on the substrate at least partially overlaps with the orthographic projection of the second electrode of at least one of the switching transistors, the fourth transistor T4 and the fifth transistor T5, on the substrate 50, and with the orthographic projection of the power signal line pattern VDD on the substrate 50.

[0375] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, the second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, such that the second electrode Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted on the power signal line pattern VDD; at the same time, the second electrodes of the two switching transistors are both coupled to the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and at least partially overlaps with the orthographic projection of the second electrode Cst2 of the storage capacitor Cst on the substrate 50, so that the second electrode Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both block the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon generated by signals on other conductive patterns (such as signal line patterns) around at least one of the two switching transistors on the second electrode of at least one of the two switching transistors, and further reducing the crosstalk phenomenon generated on the first electrode of the driving transistor.

[0376] like Figure 16 As shown, in some embodiments, the second terminals of the two switching transistors (such as the fourth transistor T4 and the fifth transistor T5) are integrally structured with the first terminal of the driving transistor (such as the third transistor T3). This integral structure includes a first conductive portion 108 extending along the first direction. The orthographic projection of the first conductive portion 108 on the substrate has a first overlapping region with the orthographic projection of the power signal line pattern VDD on the substrate and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50. The first overlapping region does not overlap with the orthographic projection of the data line pattern (such as DATA1) on the substrate 50.

[0377] Specifically, the second terminals of the two switching transistors and the first terminal of the driving transistor are formed into an integral structure, so that the second terminals of the two switching transistors and the first terminal of the driving transistor can be formed in a single patterning process.

[0378] In the display substrate provided in the above embodiments, the integrated structure includes a first conductive portion 108 extending along the first direction. The orthographic projection of the data line pattern on the substrate is located on the side of the orthographic projection of the first conductive portion 108 on the substrate away from the orthographic projection of the driving transistor on the substrate. The orthographic projection of the first conductive portion 108 on the substrate, the orthographic projection of the power signal line pattern VDD on the substrate, and the orthographic projection of the second electrode Cst2 of the storage capacitor Cst on the substrate 50 have a first overlapping area. This allows the second electrode Cst2 of the storage capacitor Cst and the power signal line pattern VDD to both block the first conductive portion 108, reducing the signal transmitted on the data line pattern and causing crosstalk to the first conductive portion 108, thereby reducing the crosstalk phenomenon generated to the first electrode of the driving transistor.

[0379] like Figure 16 As shown, in some embodiments, the orthogonal projection of the first electrode of the driving transistor on the substrate 50 may be located inside the orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst on the substrate.

[0380] The above configuration allows the second plate Cst2 of the storage capacitor Cst to completely cover the first electrode of the driving transistor, thereby more effectively reducing the crosstalk phenomenon generated by the signal transmitted on the data line pattern on the first electrode of the driving transistor.

[0381] like Figure 16 and Figure 17 As shown, in some embodiments, the sub-pixel further includes: a gate pattern GATE and a light emission control signal line pattern EM, both extending along a second direction, the second direction intersecting the first direction;

[0382] The sub-pixel driving circuit further includes: a first transistor T1 and a sixth transistor T6; the two switching transistors include a fourth transistor T4 and a fifth transistor T5;

[0383] The gate 204g of the fourth transistor T4 is coupled to the gate pattern GATE, the first terminal of the fourth transistor T4 is coupled to the data line pattern (e.g., DATA1), the second terminal of the fourth transistor T4 is coupled to the second terminal of the fifth transistor T5, the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and the first terminal of the fifth transistor T5 is coupled to the power supply signal line pattern VDD.

[0384] The gate 201g of the first transistor T1 is coupled to the gate pattern GATE, the second terminal of the first transistor T1 is coupled to the gate of the driving transistor, the first terminal of the first transistor T1, the first terminal of the sixth transistor T6 and the second terminal of the driving transistor are formed into an integral structure, the integral structure includes a second conductive portion 109 extending along the first direction, the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern EM, and the second terminal of the sixth transistor T6 is coupled to the light emission element in the sub-pixel;

[0385] The channel region of the driving transistor (e.g.) Figure 18 The orthographic projection of the 103pg of the driving transistor onto the substrate is located between the orthographic projection of the first conductive portion 108 onto the substrate 50 and the orthographic projection of the second conductive portion 109 onto the substrate 50; and along the second direction, the minimum distance between the orthographic projection of the channel region of the driving transistor onto the substrate and the orthographic projection of the first conductive portion 108 onto the substrate is less than the minimum distance between the orthographic projection of the channel region onto the substrate 50 and the orthographic projection of the second conductive portion 109 onto the substrate.

[0386] Specifically, in the aforementioned display substrate, the multiple sub-pixels can be arranged in an array. These multiple sub-pixels can be divided into multiple rows and multiple columns of sub-pixels. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and each column of sub-pixels includes multiple sub-pixels arranged along a first direction, which intersects with the second direction. The sub-pixel driving circuits included in each column of sub-pixels are located between the data line patterns included in that column of sub-pixels and the data line patterns included in the next column of sub-pixels adjacent to that column.

[0387] It should be noted that, along the second direction, the minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive portion 108 on the substrate refers to the distance between the boundary of the orthographic projection of the channel region of the driving transistor on the substrate closest to the orthographic projection of the first conductive portion 108 on the substrate and the orthographic projection of the first conductive portion 108 on the substrate; the minimum distance between the orthographic projection of the channel region on the substrate 50 and the orthographic projection of the second conductive portion 109 on the substrate refers to the distance between the boundary of the orthographic projection of the channel region of the driving transistor on the substrate closest to the orthographic projection of the second conductive portion 109 on the substrate and the orthographic projection of the second conductive portion 109 on the substrate.

[0388] More specifically, each sub-pixel includes a sub-pixel driving circuit located between two adjacent data line patterns (e.g., DATA1 and DATA2). Since the data transmitted on these two data line patterns can change, and when this data changes, crosstalk can easily occur to the gate of the driving transistor in the sub-pixel driving circuit. Specifically, as shown... Figure 25 As shown, this affects the operational stability of the driving transistor.

[0389] In the technical solution provided by the above embodiments, the fourth transistor T4, the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all disposed in the peripheral area of ​​the driving transistor. One of the two data line patterns (e.g., DATA1) is located on the side of the fourth transistor T4 and the fifth transistor T5 away from the driving transistor, and the other of the two data line patterns (e.g., DATA2) is located on the side of the first transistor T1 and the sixth transistor T6 away from the driving transistor. Simultaneously, by setting the channel region of the driving transistor (e.g., ... Figure 18 The orthographic projection of the 103pg of the first conductive part 108 on the substrate 50 and the orthographic projection of the second conductive part 109 on the substrate 50 are located between them. The minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive part 108 on the substrate is less than the minimum distance between the orthographic projection of the channel region on the substrate and the orthographic projection of the second conductive part 109 on the substrate. This allows the channel region of the driving transistor to maximize the distance between the channel region of the driving transistor and DATA2 while ensuring a suitable distance from DATA1, thereby better reducing the crosstalk generated by DATA2 on the driving transistor.

[0390] Furthermore, since the portion of the channel region of the driving transistor close to DATA1 can be covered by the power signal line pattern VDD, the crosstalk generated by DATA1 on the channel region of the driving transistor can be effectively reduced. Therefore, in the technical solution provided by the above embodiment, even if the channel region of the driving transistor is close to DATA, the crosstalk effect is relatively small.

[0391] Furthermore, since the second plate Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted on the power signal line pattern VDD, and the orthographic projection of the first conductive part 108 on the substrate, the orthographic projection of the power signal line pattern VDD on the substrate, and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 have a first overlapping area, the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both block the first conductive part 108, reducing the signal transmitted on DATA1 and causing crosstalk to the first conductive part 108, thereby reducing the crosstalk phenomenon generated to the first electrode and channel region of the driving transistor.

[0392] like Figure 16 As shown, in some embodiments, the sub-pixel further includes: a gate pattern GATE and a light emission control signal line pattern EM, both extending along a second direction, the second direction intersecting the first direction;

[0393] The sub-pixel driving circuit further includes: a first transistor T1 and a sixth transistor T6; the two switching transistors include a fourth transistor T4 and a fifth transistor T5;

[0394] The gate 204g of the fourth transistor T4 is coupled to the gate pattern GATE, the first terminal of the fourth transistor T4 is coupled to the data line pattern (e.g., DATA1), the second terminal of the fourth transistor T4 is coupled to the second terminal of the fifth transistor T5, the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and the first terminal of the fifth transistor T5 is coupled to the power supply signal line pattern VDD.

[0395] The gate 201g of the first transistor T1 is coupled to the gate pattern GATE, the second terminal of the first transistor T1 is coupled to the gate of the driving transistor, the first terminal of the first transistor T1, the first terminal of the sixth transistor T6 and the second terminal of the driving transistor are formed into an integral structure, the integral structure includes a second conductive portion 109 extending along the first direction, the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern EM, and the second terminal of the sixth transistor T6 is coupled to the light emission element in the sub-pixel;

[0396] The channel region of the driving transistor (e.g.) Figure 18 The orthographic projection of 103pg in the first conductive part 108 on the substrate is located between the orthographic projection of the first conductive part 108 on the substrate and the orthographic projection of the second conductive part 109 on the substrate; the first and second poles of the driving transistor each include a first portion extending along the second direction, and the length of the first portion of the first pole along the second direction is different from the length of the first portion of the second pole extending along the second direction.

[0397] Specifically, the first and second electrodes of the driving transistor described above both include a first portion extending along the second direction. The length of the first portion of the first electrode extending along the second direction is different from the length of the first portion of the second electrode extending along the second direction, specifically including the following two cases:

[0398] In the first case, the length H1 of the first portion of the first electrode along the second direction is less than the length H2 of the first portion of the second electrode extending along the second direction, thus the channel region of the driving transistor (e.g.) Figure 18 The 103pg data line pattern (e.g., DATA1) is located close to the data line pattern of its sub-pixel and far away from the data line pattern of the next sub-pixel adjacent to its sub-pixel along the second direction (e.g., DATA2). This allows the channel region of the driving transistor to maximize the distance between the channel region of the driving transistor and DATA2 while ensuring a suitable distance from DATA1, thereby better reducing the crosstalk caused by DATA2 to the driving transistor. Simultaneously, since the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both shield the first conductive part 108, the signal transmitted on DATA1 is reduced, reducing crosstalk to the first conductive part 108, and further reducing the crosstalk phenomenon to the first electrode and channel region of the driving transistor.

[0399] In the second scenario, the length of the first portion of the first electrode along the second direction is greater than the length of the first portion of the second electrode extending along the second direction, thus the channel region of the driving transistor (e.g.) Figure 18The 103pg of the driving transistor is positioned far from the data line pattern (e.g., DATA1) of its sub-pixel and close to the data line pattern (e.g., DATA2) of the next sub-pixel adjacent to its sub-pixel along the second direction. This maximizes the distance between the channel region of the driving transistor and DATA1 while ensuring a suitable distance from DATA2, thereby better reducing the crosstalk generated by DATA1 on the driving transistor. Furthermore, when the display substrate includes a first shielding component that can completely block DATA2 from the second conductive portion 109, it can reduce the crosstalk generated by the signal transmitted on DATA2 on the second conductive portion 109, thereby reducing the crosstalk phenomenon generated on the second electrode and channel region of the driving transistor.

[0400] like Figure 16 As shown, in some embodiments, the sub-pixel further includes an initialization signal line pattern (such as VINT1), the initialization signal line pattern including a portion extending along a second direction that intersects with the first direction, the initialization signal line pattern being used to transmit an initialization signal having a fixed potential;

[0401] The sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, the second transistor T2 comprising:

[0402] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern respectively, wherein the conductivity of the third conductor pattern is better than that of the first semiconductor pattern and the second semiconductor pattern.

[0403] A first gate pattern and a second gate pattern are coupled together, wherein the orthographic projection of the first gate pattern on the substrate at least partially overlaps with the orthographic projection of the first semiconductor pattern on the substrate, and the orthographic projection of the second gate pattern on the substrate at least partially overlaps with the orthographic projection of the second semiconductor pattern on the substrate;

[0404] The orthographic projection of the third conductor pattern on the substrate does not overlap with the orthographic projection of the first gate pattern on the substrate, nor with the orthographic projection of the second gate pattern on the substrate;

[0405] The orthographic projection of the third conductor pattern onto the substrate at least partially overlaps with the orthographic projection of the initialization signal line pattern onto the substrate.

[0406] Specifically, such as Figure 16As shown, the second transistor T2 has a dual-gate structure, and the first semiconductor pattern and the second semiconductor pattern therein form the channel region of the second transistor T2 (corresponding to...). Figure 18 The third conductor pattern 102px, which is marked at position 102pg, has better conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping. The first gate pattern and the second gate pattern of the second transistor T2 cover the first semiconductor pattern and the second semiconductor pattern respectively, and can be used together as the gate 202g of the second transistor T2.

[0407] In the second transistor T2 of the above structure, since the third conductor pattern 102px has good conductivity and is not covered by the gate pattern, it is prone to coupling with other conductive patterns nearby, resulting in crosstalk. In the technical solution provided by the above embodiment, by setting the orthographic projection of the third conductor pattern on the substrate 50 to at least partially overlap with the orthographic projection of the initialization signal line pattern on the substrate 50, the initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the coupling effect between the third conductor pattern 102px and other conductive patterns nearby is better reduced, thereby making the working performance of the display substrate more stable.

[0408] like Figure 16 and Figure 18 As shown, in some embodiments, the sub-pixel driving circuit further includes a first extension extending from the first semiconductor pattern, the first extension having better conductivity than the first semiconductor pattern; the first extension includes a first portion 61, a second portion 62, and a third portion 63, the first portion 61 and the third portion 63 both extending along the first direction, the second portion 62 extending along the second direction, one end of the second portion 62 being coupled to the first portion 61, and the other end of the second portion 62 being coupled to the third portion 63; the end of the third portion 63 away from the second portion 62 is coupled to the first transistor T1.

[0409] Specifically, the first extension can be fabricated in a single patterning process with the first semiconductor pattern, and after the first semiconductor pattern is formed, the first extension is doped so that the conductivity of the first extension is better than that of the first semiconductor pattern.

[0410] After adding the first shielding component 404, the first extension is configured as described above. This makes it easier to reduce the impact of signal changes transmitted on the target data line pattern on the performance of the first transistor T1 and the second transistor T2 when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor respectively through the first extension. This reduces the coupling effect between the gate of the driving transistor (i.e., 203g) and the target data line pattern, weakens the vertical crosstalk problem, and enables the display substrate to obtain a better display effect when used for display.

[0411] In some embodiments, the first transistor includes:

[0412] A fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern respectively, wherein the conductivity of the sixth conductor pattern is better than that of the fourth semiconductor pattern and the fifth semiconductor pattern;

[0413] A third gate pattern and a fourth gate pattern are coupled together, wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate;

[0414] The orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate, nor with the orthographic projection of the fourth gate pattern on the substrate.

[0415] Specifically, such as Figure 16 As shown, the first transistor has a dual-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included therein form the channel region of the first transistor (corresponding to...). Figure 18 The sixth conductor pattern 101px, which is marked 101pg, has better conductivity than the fourth and fifth semiconductor patterns due to doping. The third and fourth gate patterns of the first transistor cover the fourth and fifth semiconductor patterns respectively and can be used together as the gate 201g of the first transistor T1.

[0416] like Figure 19 As shown, in some embodiments, the sub-pixel further includes an initialization signal line pattern (such as VINT1), the initialization signal line pattern including a portion extending along a second direction that intersects with the first direction, the initialization signal line pattern being used to transmit an initialization signal having a fixed potential;

[0417] The sub-pixel driving circuit further includes a first shielding component 404 coupled to the initialization signal line pattern, wherein the orthographic projection of the first shielding component 404 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50.

[0418] In the technical solution provided by the above embodiments, by setting the orthographic projection of the first shielding component 404 on the substrate 50 to at least partially overlap with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, the first shielding component 404 can cover the sixth conductor pattern 101px. Furthermore, since the first shielding component 404 has a fixed potential, the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns is better reduced, making the working performance of the display substrate more stable.

[0419] like Figure 20 As shown, in some embodiments, the sub-pixel further includes an initialization signal line pattern (such as VINT1), the initialization signal line pattern including a portion extending along a second direction that intersects with the first direction, the initialization signal line pattern being used to transmit an initialization signal having a fixed potential;

[0420] The sub-pixel driving circuit further includes: a first shielding component 404 coupled to the initialization signal line pattern, and a second shielding component 301 coupled to the first shielding component 404, wherein the orthographic projection of the second shielding component 301 on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate.

[0421] Specifically, the above-mentioned arrangement of the orthographic projection of the second shielding component 301 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px. Furthermore, since the second shielding component 301 is coupled to the first shielding component 404, the second shielding component 301 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns, making the working performance of the display substrate more stable.

[0422] Therefore, in the display substrate provided in the above embodiments, since both the first shielding component 404 and the second shielding component 301 have a fixed potential, the formation of parasitic capacitance between the first transistor T1 and the target data line pattern (such as DATA2) is better prevented or reduced, and vertical crosstalk defects are effectively prevented or reduced.

[0423] like Figure 21 and Figure 22As shown, in some embodiments, the plurality of sub-pixels includes multiple rows of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels arranged along the second direction, and the initialization signal line patterns located in the same row of sub-pixels are sequentially coupled to form the initialization signal line corresponding to that row of sub-pixels; the first shielding member 404 extends along the first direction, and the first shielding member 404 is coupled to its two adjacent initialization signal lines.

[0424] In some embodiments, the shape of the power signal line pattern can be arranged as needed. For example, along the second direction, the width of the power signal line pattern near the channel region of the driving transistor is smaller than its width away from the channel region of the driving transistor, so that the influence of the power signal line pattern on the gate of the driving transistor can be reduced near the channel region of the driving transistor.

[0425] In some embodiments, such as Figure 23 As shown, a compensation pattern 408 can be provided in the display substrate, and the compensation pattern 408 can be connected in parallel with the power signal line pattern to improve the transmission performance of the power signal line pattern. It is worth noting that the compensation pattern 408 can be provided in the same layer and with the same material as the third conductive connection portion, so that the compensation pattern 408 and the third conductive connection portion can be formed in the same patterning process.

[0426] In some embodiments, in a sub-pixel, the orthographic projection of the power signal line pattern VDD onto the substrate completely covers the orthographic projection of the first conductive portion 108 onto the substrate.

[0427] In some embodiments, in a sub-pixel, the orthographic projection of the power signal line pattern VDD onto the substrate covers the orthographic projections of the first semiconductor pattern, the second semiconductor pattern, and the third conductor pattern of the second transistor T2 onto the substrate, and also covers at least a portion of the orthographic projection of the first electrode of the second transistor T2 onto the substrate, and at least a portion of the orthographic projection of the second electrode of the second transistor T2 onto the substrate.

[0428] In some embodiments, the first shielding component 404 is an extension structure extending from the initialization signal line pattern.

[0429] Specifically, the first shielding component 404 is configured as an extension structure extending from the initialization signal line pattern, so that the first shielding component 404 and the initialization signal line pattern can be formed in the same patterning process, thereby further simplifying the manufacturing process of the display substrate.

[0430] like Figure 20As shown, in some embodiments, the first shielding component 404 and the initialization signal line pattern are disposed on different layers. The orthographic projection of the first shielding component 404 on the substrate 50 and the orthographic projection of the initialization signal line pattern on the substrate 50 have a first overlapping area. The first shielding component is coupled to the initialization signal line pattern through a first via provided in the first overlapping area.

[0431] The second shielding component 301 and the first shielding component 404 are disposed in different layers. The orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50 have a second overlapping area. The second shielding component 301 and the first shielding component 404 are coupled through a second through hole disposed in the second overlapping area.

[0432] Specifically, the first shielding component 404 can be disposed on the same layer as the initialization signal line pattern or on a different layer. When the first shielding component 404 and the initialization signal line pattern are disposed on a different layer, the orthographic projection of the first shielding component 404 on the substrate 50 and the orthographic projection of the initialization signal line pattern on the substrate 50 can both have a first overlapping area. In this way, by setting a first via in the first overlapping area, the coupling between the first shielding component 404 and the initialization signal line can be achieved. Similarly, the second shielding component 301 can be disposed on the same layer as the first shielding component 404 or on a different layer. When the second shielding component 301 and the first shielding component 404 are disposed on a different layer, the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50 can both have a second overlapping area. In this way, by setting a second via in the second overlapping area, the second shielding component 301 and the first shielding component 404 can be coupled through the second via.

[0433] In some embodiments, the first shielding component 404 is made of the same material as the data cable pattern.

[0434] In some embodiments, the display substrate includes a first interlayer insulating layer, wherein the first shielding member 404 and the data line pattern are both located on the surface of the first interlayer insulating layer facing away from the substrate.

[0435] Specifically, by setting the first shielding component 404 in the manner described above, the first shielding component 404 and the data line pattern can be formed simultaneously on the surface of the first interlayer insulating layer facing away from the substrate through a single patterning process. This avoids the need for additional patterning processes to manufacture the first shielding component 404, thereby greatly simplifying the manufacturing process of the display substrate and saving manufacturing costs.

[0436] In some embodiments, the second shielding component 301 is made of the same material as the initialization signal line pattern.

[0437] In some embodiments, the display substrate further includes a second interlayer insulating layer, wherein the second shielding member 301 and the initialization signal line pattern are both located on the surface of the second interlayer insulating layer facing away from the substrate.

[0438] Specifically, the second shielding component 301 and the initialization signal line pattern are made of the same material, and the second shielding component 301 and the initialization signal line pattern (such as...) are... Figure 3 The VINT1 in the second interlayer insulating layer is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second shielding component 301 can be formed simultaneously with the initialization signal line pattern in the same patterning process. This avoids the need for additional manufacturing processes specifically for the second shielding component 301, thereby greatly simplifying the manufacturing process of the display substrate and saving production costs.

[0439] In some embodiments, the first plate Cst1 of the storage capacitor Cst is reused as the gate of the driving transistor, the second plate Cst2 of the storage capacitor Cst is made of the same material as the second shielding member 301, and the second plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate 50.

[0440] Specifically, the sub-pixel driving circuit includes a storage capacitor Cst with a first plate Cst1 and a second plate Cst2. The first plate Cst1 and the second plate Cst2 are arranged opposite to each other, and the first plate Cst1 is coupled to the gate of the driving transistor, while the second plate Cst2 is coupled to the power signal line pattern VDD. When laying out the storage capacitor Cst, the first plate Cst1 can be directly reused as the gate of the driving transistor. This not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor but also reduces the space occupied by the sub-pixel driving circuit, which is more conducive to improving the resolution of the display substrate. Furthermore, the second plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate, allowing the second plate Cst2 of the storage capacitor Cst to be formed simultaneously with the second shielding component 301 and the initialization signal line pattern in the same patterning process. This greatly simplifies the manufacturing process of the display substrate and saves production costs.

[0441] In some embodiments, the sub-pixel further includes: a reset signal line pattern (such as RST1) extending along a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:

[0442] The first conductive connection portion 405, the orthographic projection of the first conductive connection portion 405 on the substrate 50 covers at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50;

[0443] The second transistor T2 has its first terminal (e.g., source S2) coupled to the initialization signal line pattern (e.g., VINT1) via the first conductive connection portion 405, its second terminal (e.g., drain D2) coupled to the gate of the driving transistor, and its gate 202g coupled to the reset signal line pattern (e.g., RST1).

[0444] Specifically, the first conductive connection portion 405 may be made of metal material and may be formed in the same patterning process as the data cable pattern.

[0445] The above-described configuration allows the orthographic projection of the first conductive connection portion 405 on the substrate 50 to cover at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50. This enables the first conductive connection portion 405 to cover the sixth conductor pattern 101px. Furthermore, since the first conductive connection portion 405 is coupled to the initialization signal line pattern, it has a fixed potential. This further reduces the coupling effect between the sixth conductor pattern 101px and other nearby conductive patterns, resulting in more stable performance of the display substrate.

[0446] like Figure 16 As shown, in some embodiments, the sub-pixel further includes: a gate pattern GATE, a light emission control signal line pattern EM, a reset signal line pattern (such as RST1), and an initialization signal line pattern (such as VINT1); the gate pattern GATE, the light emission control signal line pattern EM, the reset signal line pattern, and the initialization signal line pattern all extend along a second direction, and the second direction intersects with the first direction;

[0447] The two switching transistors include a fourth transistor T4 and a fifth transistor T5;

[0448] The sub-pixel driving circuit further includes: a first transistor T1, a second transistor T2, a sixth transistor T6, and a seventh transistor T7;

[0449] The gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second terminal of the first transistor T1, the first terminal of the driving transistor is coupled to the second terminal of the fifth transistor T5, and the second terminal of the driving transistor is coupled to the first terminal of the first transistor T1.

[0450] The gate 201g of the first transistor T1 is coupled to the gate pattern GATE;

[0451] The gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first terminal of the second transistor T2 is coupled to the initialization signal line pattern, and the second terminal of the second transistor T2 is coupled to the gate of the driving transistor.

[0452] The gate 204g of the fourth transistor T4 is coupled to the gate pattern GATE, the first terminal of the fourth transistor T4 is coupled to the data line pattern (DATA1 in Figure ().), and the second terminal of the fourth transistor T4 is coupled to the first terminal of the driving transistor.

[0453] The gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern EM, and the first terminal of the fifth transistor T5 is coupled to the power signal line pattern VDD.

[0454] The gate 206g of the sixth transistor T6 is coupled to the light-emitting control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor T6 is coupled to the light-emitting element in the sub-pixel.

[0455] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) of the next sub-pixel adjacent to the first direction, the first electrode of the seventh transistor T7 is coupled to the initialization signal line pattern (such as VINT2) of the next sub-pixel, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.

[0456] Specifically, in the above-mentioned display substrate, the multiple sub-pixels can be arranged in an array. The multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels. Each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and each column of sub-pixels includes multiple sub-pixels arranged along a first direction. The first direction intersects with the second direction.

[0457] It should be noted that the next sub-pixel adjacent along the first direction is the next sub-pixel adjacent to the seventh transistor T7 in the same column.

[0458] By configuring the sub-pixel and its included sub-pixel driving circuit as described above, the layout space occupied by the sub-pixel driving circuit can be effectively reduced while ensuring the working performance of the sub-pixel driving circuit, which is beneficial to improving the resolution of the display substrate.

[0459] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0460] In the display substrate provided in the above embodiments, the second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, so that the second electrode Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted on the power signal line pattern VDD; at the same time, the second electrodes of the two switching transistors are both coupled to the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and at least partially overlaps with the orthographic projection of the second electrode Cst2 of the storage capacitor Cst on the substrate 50, so that the second electrode Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both block the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon generated by signals on other conductive patterns (such as signal line patterns) around at least one of the two switching transistors to the second electrode of at least one of the two switching transistors, and further reducing the crosstalk phenomenon generated to the first electrode of the driving transistor.

[0461] Therefore, the display device provided in this embodiment of the present disclosure, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0462] This disclosure also provides a method for fabricating a display substrate, the method comprising: fabricating a plurality of sub-pixels arranged in an array on a substrate; each sub-pixel comprising: a data line pattern extending along a first direction; a power signal line pattern, the power signal line pattern including a portion extending along the first direction; a sub-pixel driving circuit comprising: two switching transistors, a driving transistor, and a storage capacitor; a first electrode of the storage capacitor coupled to the gate of the driving transistor, and a second electrode of the storage capacitor coupled to the power signal line pattern; the second electrodes of both switching transistors coupled to the first electrodes of the driving transistors, wherein the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate at least partially overlaps with the orthographic projection of the power signal line pattern on the substrate, and at least partially overlaps with the orthographic projection of the second electrode of the storage capacitor on the substrate.

[0463] In the display substrate fabricated using the manufacturing method provided in this embodiment, the second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, such that the second electrode Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted on the power signal line pattern VDD; simultaneously, the second electrodes of both switching transistors are coupled to the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and at least partially overlaps with the orthographic projection of the second electrode Cst2 of the storage capacitor Cst on the substrate 50, so that the second electrode Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both block the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon generated by signals on other conductive patterns (such as signal line patterns) around at least one of the two switching transistors on the second electrode of at least one of the two switching transistors, and further reducing the crosstalk phenomenon generated on the first electrode of the driving transistor.

[0464] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0465] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0466] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0467] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0468] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized by, Comprise: a substrate and a plurality of sub-pixels arranged in an array on the substrate; the sub-pixel comprises: a data line pattern extending along a first direction; a first initialization signal line pattern extending along a second direction, the first initialization signal line pattern being used to transmit an initialization signal having a fixed potential; a power signal line pattern, the power signal line pattern comprising a portion extending along the first direction; a sub-pixel drive circuit, the sub-pixel drive circuit comprising: two switching transistors, a drive transistor, and a storage capacitor; a first plate of the storage capacitor is coupled to a gate of the drive transistor, a second plate of the storage capacitor is coupled to the power signal line pattern; a second electrode of each of the two switching transistors is coupled to a first electrode of the drive transistor, a second electrode of at least one of the two switching transistors has a normal projection on the substrate that at least partially overlaps a normal projection on the substrate of the power signal line pattern and at least partially overlaps a normal projection on the substrate of the second plate of the storage capacitor, wherein the sub-pixel drive circuit further comprises: a second transistor coupled to the gate of the drive transistor; one of the two switching transistors comprises a fourth transistor coupled to the first electrode of the drive transistor, a first electrode of the fourth transistor is coupled to the data line pattern; the sub-pixel drive circuit further comprises: a connection line for connecting the first initialization signal line pattern and the second transistor; a gate line pattern, a gate of the fourth transistor is coupled to the gate line pattern; a first shielding member coupled to the first initialization signal line pattern, the first shielding member extending along the second direction, a normal projection on the substrate of the first shielding member overlaps a normal projection on the substrate of the gate line pattern, and a normal projection on the substrate of the first shielding member does not overlap a normal projection on the substrate of the connection line.

2. The display substrate of claim 1, wherein, the second electrode of the two switching transistors and the first electrode of the drive transistor are in an integrated structure, the integrated structure comprises a first conductive portion extending along the first direction, the first conductive portion has a first overlapping area with a normal projection on the substrate of the power signal line pattern and a normal projection on the substrate of the second plate of the storage capacitor, the first overlapping area does not overlap a normal projection on the substrate of the data line pattern. 3.The display substrate of claim 1, wherein, a normal projection on the substrate of the first electrode of the drive transistor is inside a normal projection on the substrate of the second plate of the storage capacitor.

4. The display substrate of claim 2, wherein, the sub-pixel further comprises: a light-emitting control signal line pattern extending along the second direction; the sub-pixel drive circuit further comprises: a first transistor and a sixth transistor; the other of the two switching transistors comprises a fifth transistor; a second electrode of the fourth transistor is coupled to a second electrode of the fifth transistor, a gate of the fifth transistor is coupled to the light-emitting control signal line pattern, a first electrode of the fifth transistor is coupled to the power signal line pattern; A gate of the first transistor is coupled with the gate line pattern, a second electrode of the first transistor is coupled with the gate electrode of the driving transistor, a first electrode of the first transistor and a first electrode of the sixth transistor are formed as an integral structure, the integral structure includes a second conductive part extending along the first direction, a gate electrode of the sixth transistor is coupled with the light emitting control signal line pattern, and a second electrode of the sixth transistor is coupled with the light emitting element in the sub-pixel. A channel region of the driving transistor is located between a projection of the first conductive part on the substrate and a projection of the second conductive part on the substrate; and along the second direction, a minimum distance between a projection of the gate electrode of the driving transistor on the substrate and a projection of the first conductive part on the substrate is less than a minimum distance between the projection of the gate electrode of the driving transistor on the substrate and the projection of the second conductive part on the substrate.

5. The display substrate of claim 1, wherein The second transistor includes: a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled with the first semiconductor pattern and the second semiconductor pattern, respectively, the third conductor pattern having a conductivity better than that of the first semiconductor pattern and that of the second semiconductor pattern; a first gate pattern and a second gate pattern, a projection of the first gate pattern on the substrate at least partially overlaps with a projection of the first semiconductor pattern on the substrate, and a projection of the second gate pattern on the substrate at least partially overlaps with a projection of the second semiconductor pattern on the substrate; the projection of the third conductor pattern on the substrate does not overlap with the projection of the first gate pattern on the substrate and the projection of the second gate pattern on the substrate; and the projection of the third conductor pattern on the substrate at least partially overlaps with the projection of the first initialization signal line pattern on the substrate. 6.The display substrate of claim 1, wherein, The sub-pixel driving circuit further includes a first transistor and a sixth transistor; the first transistor includes: a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled with the fourth semiconductor pattern and the fifth semiconductor pattern, respectively, the sixth conductor pattern having a conductivity better than that of the fourth semiconductor pattern and that of the fifth semiconductor pattern; a third gate pattern and a fourth gate pattern coupled with each other, a projection of the third gate pattern on the substrate partially overlaps with a projection of the fourth semiconductor pattern on the substrate, and a projection of the fourth gate pattern on the substrate partially overlaps with a projection of the fifth semiconductor pattern on the substrate; the projection of the sixth conductor pattern on the substrate does not overlap with the projection of the third gate pattern on the substrate and the projection of the fourth gate pattern on the substrate.

7. The display substrate of claim 6, wherein, A normal projection of the first shielding component on the base at least partially overlaps with a normal projection of the sixth conductor pattern on the base. 8.The display substrate of claim 6, wherein, The sub-pixel driving circuit further comprises: A second shielding component for receiving a constant voltage signal; a normal projection of the second shielding component on the base at least partially overlaps with a normal projection of the sixth conductor pattern on the base. 9.The display substrate of claim 8, wherein, The sub-pixel further comprises a third initialization signal line pattern extending along a first direction, the third initialization signal line pattern is coupled with the first initialization signal line pattern, the second direction intersects with the first direction, and the third initialization signal line pattern is used for transmitting an initialization signal with a fixed potential. The first shielding component and the third initialization signal line pattern are in an integrated structure. 10.The display substrate of claim 9, wherein, The third initialization signal line pattern and the first initialization signal line pattern are arranged in different layers, a normal projection of the third initialization signal line pattern on the base has a first overlapping area with a normal projection of the first initialization signal line pattern on the base, and the third initialization signal line pattern is coupled with the first initialization signal line pattern through a first via arranged in the first overlapping area. The second shielding component and the third initialization signal line pattern are arranged in different layers, and a normal projection of the second shielding component on the base has a second overlapping area with a normal projection of the first shielding component on the base. 11.The display substrate of claim 10, wherein, The second shielding component does not overlap with the data line pattern. 12.The display substrate of claim 7, wherein, The sub-pixel further comprises a third initialization signal line pattern extending along a first direction, the third initialization signal line pattern is coupled with the first initialization signal line pattern, the second direction intersects with the first direction, and the third initialization signal line pattern is used for transmitting an initialization signal with a fixed potential. The third initialization signal line pattern and the data line pattern are arranged in the same material. 13.The display substrate of claim 12, wherein, The third initialization signal line pattern and the power signal line pattern are arranged in the same layer. The third initialization signal line pattern and the power signal line pattern are located on two sides of the driving transistor. 14.The display substrate of claim 7, wherein, The sub-pixel further comprises a third initialization signal line pattern extending along a first direction, the third initialization signal line pattern is coupled with the first initialization signal line pattern, the second direction intersects with the first direction, and the third initialization signal line pattern is used for transmitting an initialization signal with a fixed potential. The display substrate comprises a first interlayer insulating layer, and the third initialization signal line pattern and the data line pattern are located on a surface of the first interlayer insulating layer away from the base. 15.The display substrate of claim 8, wherein, The second shielding component and the first initialization signal line pattern are arranged in the same material. 16.The display substrate of claim 15, wherein, The second shielding component and the first initialization signal line pattern are arranged in the same layer as a second plate of the storage capacitor. 17.The display substrate of claim 8, wherein, The sub-pixel further comprises a third initialization signal line pattern extending along a first direction, the third initialization signal line pattern is coupled with the first initialization signal line pattern, the second direction intersects with the first direction, and the third initialization signal line pattern is used for transmitting an initialization signal with a fixed potential. The display substrate further comprises a second interlayer insulating layer, and the second shielding component is located on a surface of the second interlayer insulating layer away from the substrate together with the first initialization signal line pattern and the third initialization signal line pattern. 18.The display substrate of claim 17, wherein, The first plate of the storage capacitor is multiplexed as the gate of the drive transistor, the second plate of the storage capacitor is made of the same material as the second shielding component, and the second plate of the storage capacitor is located on a surface of the second interlayer insulating layer away from the substrate. 19.The display substrate of claim 1, wherein, The sub-pixel further comprises a gate line pattern, a light-emitting control signal line pattern, and a reset signal line pattern, and the gate line pattern, the light-emitting control signal line pattern, and the reset signal line pattern all extend along a second direction. The other of the two switching transistors comprises a fifth transistor. The sub-pixel driving circuit further comprises a first transistor, a sixth transistor, and a seventh transistor. The gate of the drive transistor is coupled to the second electrode of the first transistor, the first electrode of the drive transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the drive transistor is coupled to the first electrode of the first transistor. The gate of the first transistor is coupled to the gate line pattern. The gate of the second transistor is coupled to the reset signal line pattern, the first electrode of the second transistor is coupled to the first initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the drive transistor. The second electrode of the fourth transistor is coupled to the first electrode of the drive transistor. The gate of the fifth transistor is coupled to the light-emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern. The gate of the sixth transistor is coupled to the light-emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the drive transistor, and the second electrode of the sixth transistor is coupled to the light-emitting element in the sub-pixel. The gate of the seventh transistor is coupled to the reset signal line pattern included in a next sub-pixel adjacent to the sub-pixel along the first direction, the first electrode of the seventh transistor is coupled to the second initialization signal line pattern included in the next sub-pixel, and the second electrode of the seventh transistor is coupled to the light-emitting element in the sub-pixel.

20. A display device comprising: The display substrate as claimed in any one of claims 1-19.

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