Alternating-current coupling SiC low-gain detector chip, low-gain detector and preparation method

Abstract

The invention provides an alternating-current coupling SiC low-gain detector chip, a low-gain detector and a preparation method, the chip sequentially comprises an N-type electrode layer, an N-type substrate layer, an N-type active layer, an N + gain layer, a P + type electrode layer and an insulating layer from bottom to top, an alternating-current electrode layer and a direct-current electrode layer are arranged at the top of the insulating layer, the N-type electrode layer is a cathode, and the P + type electrode layer is an anode. The direct-current electrode layer is an anode, and the terminal layer is formed by combining junction termination extension with etching. Compared with a conventional coupling detector, the requirement of position resolution for the pixel size is low, the problems of detection dead zones and large leakage current caused by SiC in an etching mesa terminal are reduced, and meanwhile the excellent position resolution and time resolution characteristics are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor detectors, and in particular to an AC-coupled SiC low-gain detector chip, a low-gain detector and a preparation method thereof. Background Art

[0002] As a third-generation semiconductor, SiC has the characteristics of wide bandgap, high atomic displacement threshold energy, fast carrier saturation drift velocity and high thermal conductivity compared to Si. It is more suitable for the detection of minimum ionizing particles (MIPs) under high temperature and high irradiation.

[0003] The characteristic of low-gain detectors is that they realize low-gain avalanche multiplication inside them, which improves the detection efficiency and sensitivity while improving the signal-to-noise ratio of the device, thereby obtaining a higher time resolution. However, existing detectors have the problem of large leakage current caused by SiC in the etched table terminal, and their position resolution has low requirements for pixel size, which makes it impossible to accurately measure the time and position resolution of particles, and there is also a detection dead zone.

[0004] Therefore, there is an urgent need for an AC-coupled SiC low-gain detector chip, a low-gain detector and a preparation method to solve the above problems. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides an AC-coupled SiC low-gain detector chip, a low-gain detector and a preparation method thereof.

[0006] The present invention provides an AC-coupled SiC low-gain detector chip, which comprises, from bottom to top, an N-type electrode layer, an N-type substrate layer, an N-type active layer, an N+ gain layer, a P+ type electrode layer and an insulating layer, wherein: An AC electrode layer and a DC electrode layer are arranged on the top of the insulating layer, the N-type electrode layer is a cathode, and the DC electrode layer is an anode.

[0007] According to an AC-coupled SiC low-gain detector chip provided by the present invention, the substrate layer of the chip is a SiC substrate layer, wherein the SiC substrate layer is an N-type doped SiC semiconductor substrate layer.

[0008] According to an AC-coupled SiC low-gain detector chip provided by the present invention, the insulating layer, the P+ type electrode layer and the AC electrode layer constitute a coupling capacitor, and the AC electrode layer collects charge signals through the coupling capacitor.

[0009] According to an AC-coupled SiC low-gain detector chip provided by the present invention, the materials of the N-type electrode layer are Ni layer, Ti layer and Al layer from bottom to top, the thickness of the Ni layer is 50nm, the thickness of the Ti layer is 15nm, and the thickness of the Al layer is 80nm.

[0010] According to an AC-coupled SiC low-gain detector chip provided by the present invention, the N-type active layer is an N-type low-doped SiC material; the N+ gain layer is an N-type highly-doped SiC material; the P+ type electrode layer is a P-type highly-doped SiC material; the material of the insulating layer is SiO2, or the material of the insulating layer is HfO2 and Al2O3.

[0011] According to an AC-coupled SiC low-gain detector chip provided by the present invention, the DC electrode layer is used to guide carriers out of the chip.

[0012] According to an AC-coupled SiC low-gain detector chip provided by the present invention, the chip also includes a junction terminal extension terminal layer formed by junction terminal extension combined with mesa etching terminal technology, the junction terminal extension terminal layer is P-type doped, and the doping concentration of the junction terminal extension terminal layer is lower than the doping concentration of a P++ type doped contact layer in contact with the DC electrode layer.

[0013] According to an AC-coupled SiC low-gain detector chip provided by the present invention, the doping ions of the P++ type doped contact layer are Al 3+ , and its doping concentration is 5×10 18 cm -3 Up to 5×10 20 cm -3 .

[0014] The present invention also provides a low-gain detector based on the above-mentioned AC-coupled SiC low-gain detector chip, wherein the low-gain detector includes a microstrip type low-gain detector and a pixel type low-gain detector, wherein the AC current welding points in the microstrip type low-gain detector are uniformly distributed in a strip structure; and the AC current welding points in the pixel type low-gain detector are a pixel grid structure of a preset size, and are uniformly distributed in a polygonal pixel grid corresponding to a preset polygonal distribution form.

[0015] The present invention also provides a method for preparing the AC-coupled SiC low-gain detector chip, comprising: Cleaning and drying of SiC epitaxial wafers; Etching mesa terminals; Preparing an N+ gain layer; preparing a P-type doped junction terminal extension terminal layer; Preparing a P+ type electrode layer; preparing a P++ type doped contact layer; preparing an N-type electrode layer and a DC electrode layer; preparing an insulating layer; preparing an AC electrode layer; Slicing and packaging.

[0016] Compared with conventional coupled detectors, the AC-coupled SiC low-gain detector chip, low-gain detector and preparation method provided by the present invention have lower requirements on pixel size for position resolution, reduce the detection dead zone and the problem of large leakage current caused by SiC in the etched table terminal, and have excellent position resolution and time resolution characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of the AC-coupled SiC low-gain detector chip provided by the present invention; Figure 2 One of the top views of the pixel-type AC-coupled SiC low-gain detector structure provided by the present invention; Figure 3 The second top view of the pixel-type AC-coupled SiC low-gain detector structure provided by the present invention; Figure 4 A top view of the microstrip type AC-coupled SiC low-gain detector structure provided by the present invention; Figure 5 A schematic flow chart of a method for preparing an AC-coupled SiC low-gain detector chip provided by the present invention; Reference numerals: 101: N-type electrode layer; 102: N-type substrate layer; 103: N-type active layer; 104: N+ gain layer; 105: P+ type electrode layer; 106: insulation layer; 107: junction terminal extension terminal layer; 108: P++ type doped contact layer; 1061: AC electrode layer; 1062: DC electrode layer. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] AC-coupled low-gain avalanche diode (AC-LGAD) is a new type of detector designed based on low-gain avalanche diode. It not only has the high time resolution of low-gain avalanche diode, but also has high spatial resolution. It is a detector with great potential. In order to further enable the low-gain detector to better measure the time and position resolution of particles and reduce the detection dead zone, the present invention provides an AC-coupled SiC low-gain detector structure, which reduces the problem of large leakage current caused by SiC in the etched table terminal. It only needs to protect the terminal of the entire array, without protecting a single pixel, which simplifies the process requirements; at the same time, it has excellent position resolution and time resolution characteristics, and can be used to detect the time and position information of particles in extreme environments such as high radiation dose and high temperature.

[0021] Figure 1 The schematic diagram of the structure of the AC-coupled SiC low-gain detector chip provided by the present invention is as follows: Figure 1 As shown, the present invention provides an AC-coupled SiC low-gain detector chip, which includes, from bottom to top, an N-type electrode layer 101, an N-type substrate layer 102, an N-type active layer 103, an N+ gain layer 104, a P+ type electrode layer 105 and an insulating layer 106, wherein: An AC electrode layer 1061 and a DC electrode layer 1062 are disposed on the top of the insulating layer 106 . The N-type electrode layer 101 is a cathode, and the DC electrode layer 1062 is an anode.

[0022] In the present invention, the AC-coupled SiC low-gain detector chip comprises, from bottom to top, an N-type electrode layer 101, an N-type substrate layer 102, an N-type active layer 103, an N+ gain layer 104, a P+ type electrode layer 105 and an insulating layer 106, wherein the N+ gain layer 104 is distributed between the N-type active layer 103 and the P+ type electrode layer 105; an AC electrode layer 1061 and a DC electrode layer 1062 are provided on the top of the insulating layer 106, wherein the N-type electrode layer 101 is a cathode and the DC electrode layer 1062 is an anode.

[0023] On the basis of the above embodiment, the substrate layer of the chip is a SiC substrate layer, wherein the SiC substrate layer is an N-type doped SiC semiconductor substrate layer.

[0024] In semiconductor devices, the substrate layer is the basis for supporting the entire chip structure. It has a higher breakdown electric field, lower thermal conductivity, and higher saturated electron drift velocity than traditional Si materials, enabling SiC devices to operate at higher temperatures and higher power densities while maintaining lower energy losses and longer service life. In the present invention, additional free electrons are introduced into the SiC material by N-type doping, and the N-type doped SiC substrate layer provides a good current conduction path for the entire chip, which helps to reduce resistance losses and improve the working efficiency of the device.

[0025] Based on the above embodiment, the chip also includes a junction terminal extension terminal layer 107 formed by junction terminal extension combined with mesa etching terminal technology, the junction terminal extension terminal layer 107 is P-type doped, and the doping concentration of the junction terminal extension terminal layer 107 is lower than the doping concentration of the P++ type doped contact layer 108 in contact with the DC electrode layer 1062.

[0026] In the present invention, reference may be made to Figure 1 As shown, the junction termination extension (JTE) terminal layer 107 in the AC-coupled SiC low-gain detector chip is P-type doped, and the doping concentration is lower than the doping concentration of the P++-type doped contact layer 108 in contact with the DC electrode layer 1062 .

[0027] Based on the above embodiment, the materials of the N-type electrode layer are Ni layer, Ti layer and Al layer from bottom to top, the thickness of the Ni layer is 50nm, the thickness of the Ti layer is 15nm, and the thickness of the Al layer is 80nm.

[0028] Based on the above embodiments, the N-type active layer is an N-type low-doped SiC material; the N+ gain layer is an N-type highly-doped SiC material; the P+ type electrode layer is a P-type highly-doped SiC material; the material of the insulating layer is SiO2, or the material of the insulating layer is HfO2 and Al2O3.

[0029] Based on the above embodiment, the doping ions of the P++ type doped contact layer are Al 3+ , and its doping concentration is 5×10 18 cm -3 Up to 5×10 20 cm -3 .

[0030] In the present invention, the materials of the N-type electrode layer 101 are Ni, Ti, and Al from bottom to top, and the thicknesses of the materials of each layer are 50 nm, 15 nm, and 80 nm, respectively, to achieve ohmic contact and reduce voltage drop.

[0031] The N-type base layer 102 is a 4° beveled <11-20> oriented, double-sided polished low-resistance film. The doping ions of the N-type active layer 103 are N 3- , the corresponding doping concentration is about 5×10 13 cm -3 Up to 5×10 14 cm -3 , with a thickness of 50 μm. The N-type active layer 103 in the present invention is N-type low-doped SiC, thereby increasing its depletion depth.

[0032] The doping ions of the N+ gain layer 104 are N 3- , the corresponding doping concentration is 1×10 17 cm -3 Up to 4×10 17 cm -3 , with a thickness of about 1-0.5 μm. The N+ gain layer 104 in the present invention is N-type highly doped SiC, thereby forming a high electric field region to achieve avalanche multiplication.

[0033] The doping particles of the P+ type electrode layer 105 are Al 3+ , the corresponding doping concentration is about 1×10 16 cm -3 Up to 5×10 17 cm -3 The material of the insulating layer 106 is SiO2, or HfO2 plus Al2O3, which acts as a passivation layer. At the same time, the insulating layer 106 forms a coupling capacitor with the P+ type electrode layer 105 and the AC electrode layer 1061. The coupling capacitor provides a ground path for the fast signal and charges and discharges the coupling capacitor, serving as a coupled signal readout terminal.

[0034] The materials of the AC electrode layer 1062 are Ni, Ti, and Al, respectively, and their thicknesses are 50 nm, 15 nm, and 80 nm, respectively. The material of the AC electrode layer is Al, and the corresponding thickness is 100 nm. The doping ions of the junction terminal extension terminal layer 107 are Al. 3+ , corresponding to a doping concentration of 1×10 16 cm -3 Up to 1×10 17 cm -3 The thickness is about 0.7um to 1um. The doping ions of the P++ type doped contact layer 108 in contact with the DC electrode layer 1062 are Al 3+ , the corresponding doping concentration is 5×10 18 cm -3 Up to 5×10 20 cm -3 .

[0035] On the basis of the above embodiment, the insulating layer 106 , the P+ type electrode layer 105 and the AC electrode layer 1061 form a coupling capacitor, and the AC electrode layer 1061 collects charge signals through the coupling capacitor.

[0036] On the basis of the above-mentioned embodiment, the DC electrode layer 1062 is used to lead the carriers out of the chip.

[0037] In the present invention, the P+ type electrode layer 105 is used as a plate of the coupling capacitor, and is in close contact with the insulating layer 106, and together they form a part of the coupling capacitor. At the same time, the AC electrode layer 1061 is located on the other side of the insulating layer 106 (opposite to the P+ type electrode layer), thereby forming a capacitive coupling with the P+ type electrode layer 105 through the insulating layer 106.

[0038] In the present invention, the main function of the DC electrode layer 1062 is to conduct the carriers inside the chip (device) through grounding. In semiconductor devices, effective management of carriers is crucial to maintaining device performance and stability. In this structure, the DC electrode layer 1062 conducts the carriers generated inside the chip to the external circuit, thereby maintaining the stability of the collected charge inside the chip.

[0039] The AC-coupled SiC low-gain detector chip provided by the present invention has lower requirements on pixel size for position resolution compared to conventional coupled detectors, reduces the detection dead zone and the problem of large leakage current caused by SiC in the etched table terminal, and has excellent position resolution and time resolution characteristics.

[0040] The present invention also provides a low-gain detector based on the AC-coupled SiC low-gain detector chip described in the above embodiments, wherein the gain multiple of the low-gain detector is 10 to 100 times, and the low-gain detector includes a microstrip type low-gain detector and a pixel type low-gain detector, wherein the AC current welding points in the microstrip type low-gain detector are uniformly distributed in a strip structure; the AC current welding points in the pixel type low-gain detector are a pixel grid structure of a preset size, and are uniformly distributed in a polygonal pixel grid corresponding to a preset polygonal distribution form.

[0041] Figure 2 One of the top views of the pixel-type AC-coupled SiC low-gain detector structure provided by the present invention can be referred to Figure 2 As shown, in the present invention, as a pixel-type low-gain detector, its pixel unit is a 3×3 rectangular matrix. It should be noted that the present invention Figure 2 The pixel unit in the image is to use the AC pad as the pixel grid structure, and the polygon pixel grid corresponding to the preset polygon distribution form (such as Figure 2The 3×3 rectangular matrix in the figure is uniformly distributed and constructed. The distribution method is only used as an example, and the pixel unit is not limited to the 3×3 matrix. In the present invention, reference can be made to Figure 2 As shown, the pitch of the pixel unit can be 100 μm to 2000 μm, the size of the AC current solder joint can be 50 μm to 1000 μm, the AC current solder joint is used for coupling signal readout, and the outer ring is a DC electrode for signal derivation.

[0042] Figure 3 The second top view of the pixel-type AC-coupled SiC low-gain detector structure provided by the present invention can be referred to Figure 3 As shown, it is a low-gain detector with regular hexagonal pixels. Similarly, Figure 3 The pixel units formed by the polygonal pixel grid distribution corresponding to the preset polygonal distribution form of the AC current welding points are only used as an embodiment, and the present invention does not specifically limit the distribution form of the pixel units. Figure 3 In the example, the pixel unit pitch can be 100μm to 2000μm, and the size of the AC current solder joint is 50μm to 1000μm, where the AC current solder joint is used for coupling signal readout, and the outer ring is a DC electrode for signal derivation. Figure 3 As shown in the figure, taking the AC current welding point at the center of the regular hexagon as an example, the distance between the unit pixel and the AC current welding points in the form of pixel grids around it is equal, and the signal collected by the AC current welding point is related to the position where the detector is hit, and its intensity will change as the position of the hit moves. The closer the distance, the greater the intensity. The advantage of the regular hexagonal pixel type low-gain detector is that the distance from the hit point to the six surrounding AC current welding points is consistent, that is, the signal intensity sensed by the six surrounding AC current welding points is almost the same, so its position reconstruction and signal processing are simpler than the matrix pixel type low-gain detector.

[0043] Figure 4 The top view of the micro-strip AC-coupled SiC low-gain detector structure provided by the present invention can be referred to Figure 4 As shown, in addition to the pixel-type detector, the present invention also provides a microstrip type low-gain detector, the unit spacing of the microstrip can be 100μm to 2000μm, and the width of the microstrip formed by each AC current welding point is about 50μm, wherein the AC current welding point is used for coupling signal readout, and the outer ring is a DC electrode for signal export.

[0044] The low-gain detector provided by the present invention has lower requirements on pixel size for position resolution compared to conventional coupled detectors, reduces the detection dead zone and the problem of large leakage current caused by SiC in the etched table terminal, and has excellent position resolution and time resolution characteristics.

[0045] Figure 5 The schematic diagram of the process of preparing the AC-coupled SiC low-gain detector chip provided by the present invention is as follows: Figure 5 As shown, the present invention provides a method for preparing an AC-coupled SiC low-gain detector chip based on the above embodiments, comprising: Step 501: Clean and dry the SiC epitaxial wafer.

[0046] In the present invention, the SiC to be cleaned is cleaned according to the RCA standard, and after cleaning, the chip is blown dry with high-purity nitrogen protection, and after ensuring that it is clean, the epitaxial wafer to be processed is heated and dried for standby use.

[0047] Step 502, etching the mesa terminal.

[0048] Further, a photoresist is coated on the epitaxial wafer to be processed, a mesa to be etched is formed by photolithography and development, and the mesa terminal is formed by etching to the N-active area by a CIP process, and the photoresist is cleaned.

[0049] Step 503: prepare an N+ gain layer.

[0050] Photoresist is applied to the epitaxial wafer to be processed, and the N+ gain layer pattern to be injected is formed by photolithography and development. Then N ion implantation is performed with an injection energy of 280keV and an injection dose of 6.8e 12 ions / cm 2 , with a depth of 400nm and a concentration of up to 1×10 17 cm -3 Up to 4×10 17 cm -3 , clean the photoresist.

[0051] Step 504, preparing a P-type doped junction terminal extension terminal layer.

[0052] Photoresist is applied to the epitaxial wafer to be processed, and the P-type doped JTE terminal pattern to be injected is formed by photolithography and development. Then Al ion implantation is performed with an injection energy of 1MeV and an injection dose of 1.6e 12 ions / cm 2 , the depth is 0.7um to 1um, and the doping concentration can reach 1×10 16 cm -3 Up to 1×10 17 cm -3 , clean the photoresist.

[0053] Step 505, preparing a P+ type electrode layer.

[0054] The epitaxial wafer to be processed is coated with photoresist, and the P-type electrode layer pattern to be injected is formed by photolithography and development. Then Al ion implantation is performed with an injection energy of 280 KeV and an injection dose of 1.83e10 ions / cm 2 , and its doping concentration is about 1×10 16 cm -3 Up to 5×10 17 cm -3 , clean the photoresist.

[0055] Step 506: Prepare a P++ type doped contact layer.

[0056] The epitaxial wafer to be processed is coated with photoresist, and the P-type heavily doped contact layer to be implanted is formed by photolithography and development. Then Al ion implantation is performed with an implantation energy of 200 KeV and an implantation dose of 2.0 e 15 ions / cm 2 , the doping concentration can reach 1×10 16 cm -3 Up to 1×10 17 cm -3 , clean the photoresist.

[0057] Step 507: Prepare an N-type electrode layer and a DC electrode layer.

[0058] Ni, Ti and Al are magnetron sputtered at the bottom of the epitaxial wafer to be processed to form ohmic contacts with thicknesses of 50 nm, 15 nm and 80 nm respectively.

[0059] Furthermore, photoresist is coated on the epitaxial wafer to be processed, developed into a DC electrode pattern by photolithography, and magnetron sputtering Ni, Ti, and Al is used to form ohmic contacts with thicknesses of 50 nm, 15 nm, and 80 nm, respectively, and the photoresist is cleaned.

[0060] Step 508: preparing an insulating layer.

[0061] Deposit or sputter a certain thickness of SiO2, or HfO2 plus Al2O3 and other insulating materials as a passivation layer on the epitaxial wafer to be processed, photolithography and development to hollow out the DC electrode layer, corrode or etch the insulating layer to make a metal welding electrode.

[0062] Step 509: preparing an AC electrode layer.

[0063] Photoresist is applied on the epitaxial wafer to be processed, and an AC electrode pattern is formed by photolithography and development. Magnetron sputtering of Al with a thickness of 100 nm is used to clean the photoresist.

[0064] Step 510: dicing and packaging.

[0065] The manufactured chip is diced with a dicing machine, and the electrodes of the external power supply system and the welding points are welded by hot pressing welding and other methods, and the chip packaging is completed.

[0066] The present invention provides a method for preparing an AC-coupled SiC low-gain detector chip. The produced low-gain detector chip has a lower requirement for pixel size in position resolution, reduces the detection dead zone and the problem of large leakage current caused by SiC in the etched table terminal, and has excellent position resolution and time resolution characteristics.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An AC-coupled SiC low-gain detector chip, characterized in that: The chip includes, from bottom to top, an N-type electrode layer, an N-type substrate layer, an N-type active layer, an N+ gain layer, a P+ type electrode layer and an insulating layer, wherein: An AC electrode layer and a DC electrode layer are arranged on the top of the insulating layer, the N-type electrode layer is a cathode, and the DC electrode layer is an anode.

2. The AC-coupled SiC low-gain detector chip according to claim 1, characterized in that: The substrate layer of the chip is a SiC substrate layer, wherein the SiC substrate layer is an N-type doped SiC semiconductor substrate layer.

3. The AC-coupled SiC low-gain detector chip according to claim 1, characterized in that: The insulating layer, the P+ type electrode layer and the AC electrode layer form a coupling capacitor, and the AC electrode layer collects charge signals through the coupling capacitor.

4. The AC-coupled SiC low-gain detector chip according to claim 1, characterized in that: The materials of the N-type electrode layer are Ni layer, Ti layer and Al layer from bottom to top. The thickness of the Ni layer is 50 nm, the thickness of the Ti layer is 15 nm, and the thickness of the Al layer is 80 nm.

5. The AC-coupled SiC low-gain detector chip according to claim 1, characterized in that: The N-type active layer is made of N-type low-doped SiC material; the N+ gain layer is made of N-type high-doped SiC material; the P+ type electrode layer is made of P-type high-doped SiC material; the material of the insulating layer is SiO2, or the material of the insulating layer is HfO2 and Al2O3.

6. The AC-coupled SiC low-gain detector chip according to claim 1, characterized in that: The DC electrode layer is used to lead carriers out of the chip.

7. The AC-coupled SiC low-gain detector chip according to claim 1, characterized in that: The chip also includes a junction terminal extension terminal layer formed by junction terminal extension combined with mesa etching terminal technology, the junction terminal extension terminal layer is P-type doped, and the doping concentration of the junction terminal extension terminal layer is lower than the doping concentration of the P++ type doped contact layer in contact with the DC electrode layer.

8. The AC-coupled SiC low-gain detector chip according to claim 7, characterized in that: The doping ions of the P++ type doped contact layer are Al 3+ , and its doping concentration is 5×10 18 cm -3 Up to 5×10 20 cm -3 .

9. A low-gain detector based on the AC-coupled SiC low-gain detector chip according to any one of claims 1 to 8, characterized in that: The low-gain detector includes a microstrip type low-gain detector and a pixel type low-gain detector, wherein the AC current welding points in the microstrip type low-gain detector are uniformly distributed in a strip structure; the AC current welding points in the pixel type low-gain detector are a pixel grid structure of a preset size, and are uniformly distributed in a polygonal pixel grid corresponding to a preset polygonal distribution form.

10. A method for preparing an AC-coupled SiC low-gain detector chip according to any one of claims 1 to 8, characterized in that: include: Cleaning and drying of SiC epitaxial wafers; Etching mesa terminals; Preparing an N+ gain layer; preparing a P-type doped junction terminal extension terminal layer; Preparing a P+ type electrode layer; preparing a P++ type doped contact layer; preparing an N-type electrode layer and a DC electrode layer; preparing an insulating layer; preparing an AC electrode layer; Slicing and packaging.

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