Apparatus and method for providing sensor data of optical system, optical system and lithographic apparatus comprising optical system

Abstract

An apparatus (100) for providing sensor data from N sensors (301-30N) of an optical system (4, 10) of a lithographic apparatus (1), where N > = 1, comprises an analog-to-digital converter (500) configured to provide an analog signal sequence (AF) of N analog sensor signals (A1-AN) from said N sensors (301-30N) of the optical system (4, 10) via N channels (K1-KN), converting into a digital signal sequence (DF) comprising N digital sensor signals (D1-DN); and a digital filter device (600) connected downstream of the analog-to-digital converter (500) wherein the analog-to-digital converter (500) and the digital filter device (600) have the same frequency synchronization system clock, and the digital filter device (600) is configured to provide and store an individual filtered digital sensor signal (F1-FN) of each of the N channels (K1-KN), and to filter the N digital sensor signals (D1-DN) of the digital signal sequence (DF) in a specific channel manner.

Description

Technical Field

[0001] The invention relates to an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus. The invention further relates to an optical system having such an apparatus, and a lithographic apparatus having such an optical system. Furthermore, the invention relates to a method for providing sensor data from a sensor of an optical system of a lithographic apparatus.

[0002] The content of the priority application DE 10 2022 207 027.5 is hereby incorporated in its entirety by reference. Background Art

[0003] Microlithography is used to produce microstructured component parts, such as integrated circuits. The microlithography process is carried out using a lithography device having an illumination system and a projection system. The image of a mask (reticle) illuminated by means of the illumination system is projected by means of the projection system onto a substrate (e.g. a silicon wafer) coated with a photosensitive layer (photoresist) and arranged in the image plane of the projection system, in order to transfer the mask structure to the photosensitive coating of the substrate.

[0004] In the production of integrated circuits, driven by the need for ever smaller structures, EUV lithography devices using light with a wavelength in the range of 0.1 nm to 30 nm, in particular 13.5 nm, are currently being developed. Since most materials absorb light at this wavelength, it is necessary to use reflective optical components (i.e. mirrors) in such EUV lithography devices instead of (as previously) refractive optical components (i.e. lens elements).

[0005] The optical system of the lithography apparatus may have a vacuum housing. In the vacuum housing, various sensors such as negative temperature coefficient (NTC) sensors, photodiodes, or temperature measuring sensors such as capacitors are arranged. These sensors provide individual analog sensor signals on the output side. If multiple sensors are present, the analog sensor signals of the multiple sensors can be supplied to a multiplexer, which provides an analog signal sequence including multiplexed analog sensor signals from the sensors on the output side. Outside the vacuum housing, an analog filter coupled to the multiplexer and an analog-to-digital converter connected downstream of the analog filter are provided. The analog-to-digital converter converts the analog signal sequence filtered by the analog filter into a digital signal sequence and supplies it to a digital signal processing unit for further processing.

[0006] The use of conventional filter concepts is very limited, since conventional filters always require a certain settling time to switch between different channels of different signals from different sensors before their normal function is established. This is because after each channel change, it is necessary to wait again for the settling time of the filter to be completed, which can take many times longer than the sampling process. Therefore, the sampling of sensor values ​​has a time-limited sampling. However, if the filter is omitted due to these effects and a high sampling rate is used, the unwanted aliasing effects will significantly interfere with the used signal. However, if conventional filters are used, only very limited sampling rates can be used due to the long filter settling time, with a constant multiplexing of the sensor signals. The same applies to the sampling of individual sensor signals with accurate but slowly sampling analog-to-digital converters. Summary of the invention

[0007] Against this background, it is an object of the present invention to improve the supply of sensor data from a sensor of an optical system of a lithographic apparatus.

[0008] According to a first aspect, an apparatus for providing sensor data from N sensors (where N ≥ 1) of an optical system of a lithographic apparatus, wherein the apparatus comprises:

[0009] an analog-to-digital converter configured to convert an analog signal sequence provided via N channels and comprising N analog sensor signals from N sensors of the optical system into a digital signal sequence comprising N digital sensor signals; and

[0010] A digital filter device is connected downstream of the analog-to-digital converter, wherein the analog-to-digital converter and the digital filter device have the same frequency synchronized system clock, and the digital filter device is configured to filter the N digital sensor signals of the digital signal sequence in a channel-specific manner in order to provide and store a respective filtered digital sensor signal for each of the N channels.

[0011] The device of the present invention can omit the analog filter in order to avoid limiting the maximum sampling rate due to the stabilization process of the analog filter.

[0012] The digital filter device used here, which can internally buffer filter values ​​for different channels (i.e. filtered digital sensor signals for N channels), enables multiplexing of the channels to be measured (i.e. sensor channels) in synchronization with the individual filter values. In this way, it may be advantageous that the digital filter does not need to be stabilized again with each channel change.

[0013] According to a specific embodiment, the sampling frequency of the analog-to-digital converter and the properties of the digital filter device are matched to each other so that interfering frequency bands are suppressed. The method can be used in the case of one interfering frequency band as well as in the case of a plurality of interfering frequency bands. In particular, the sampling frequency of the analog-to-digital converter is selected so that known interfering frequencies are suppressed.

[0014] The digital filter device comprises one or more digital filters. Examples of this are mentioned below. During filtering, the used bandwidth of the individual digital sensor signals is not affected, or is substantially not affected.

[0015] According to one embodiment, filtering of undersampled interfering frequencies is also possible.

[0016] According to a specific embodiment, the apparatus comprises a control unit configured to perform clock synchronization control of the analog-to-digital converter and the digital filter device by means of a frequency-synchronized system clock.

[0017] In the present case, clock synchronization control means in particular control by means of a frequency-synchronized system clock. The system clock is preferably embodied in the form of a frequency-synchronized and phase-synchronized system clock.

[0018] In this case, the control unit advantageously provides a precise timing trigger. In particular, the control unit is embodied in the form of a state machine, for example in the form of a finite state machine. The state machine enables periodic precise control for switching the multiplexer unit, starting quantization by the analog-to-digital converter, and correctly switching the filter values ​​of the relevant channels of the digital filter device. This advantageously ensures that during the periodic actuation of the individual components, any time-of-flight deviations cannot appear in the form of jitter, which could have the effect of phase noise in the spectral representation of the individual sampled signals.

[0019] According to an alternative embodiment, the analog-to-digital converter is a unit providing a frequency-synchronous system clock. The digital filter device and the control unit are then controlled by means of the provided frequency-synchronous system clock.

[0020] According to a further embodiment, the device comprises a multiplexer unit configured to receive a plurality of N analog sensor signals from a plurality of N sensors of the optical system via a plurality of N channels (wherein N ≥ 2) and to provide an analog signal sequence comprising the N multiplexed analog sensor signals to the analog-to-digital converter on an output side.

[0021] According to a specific embodiment, the control unit is configured to perform clock synchronization control of the analog-to-digital converter, the digital filter device, and the multiplexer unit by means of a frequency synchronized system clock.

[0022] According to another embodiment, the device comprises:

[0023] a multiplexer unit configured to receive a plurality of N analog sensor signals from a plurality of N sensors of the optical system via a plurality of N channels and to provide an analog signal sequence comprising N multiplexed analog sensor signals on an output side, wherein N ≥ 2;

[0024] the analog-to-digital converter connected to the multiplexer unit and configured to convert the analog signal sequence provided by the multiplexer unit into a digital signal sequence comprising N multiplexed digital sensor signals; and

[0025] The digital filter device is connected downstream of the analog-to-digital converter and is configured to filter the multiplexed digital sensor signal of the digital signal sequence in a channel-specific manner in order to provide and store a respective filtered digital sensor signal for each of the N channels.

[0026] The multiplexer unit may also be referred to as a multiplexer. The analog-to-digital converter may also be referred to as an ADC.

[0027] In particular, a storage unit having N memory locations is provided, which is connected downstream of the digital filter device. Here, each of the N memory locations is assigned exactly one of the N channels. The individual memory locations are configured to store the individual filtered digital sensor signals of a corresponding one of the N channels. In addition, a control unit is preferably provided. The control unit is preferably used for centrally controlling and operating the digital filter device. It may in particular be a digital circuit, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) or a microprocessor.

[0028] In order to operate the multiplexing of a plurality of different sensor channels without requiring any new stabilization of the filter after each channel change, the invention provides for the filter values ​​of the different channels to be buffered. This can be done, for example, by multiple instantiations of the digital filter. Details of this will be mentioned below.

[0029] The optical system is preferably a projection optical unit of a lithography apparatus or a projection exposure apparatus. However, the optical system may also be an illumination system. The projection exposure apparatus may be an EUV lithography apparatus. EUV stands for "extreme ultraviolet" and denotes a wavelength of the working light between 0.1 nm and 30 nm. The projection exposure apparatus may also be a DUV lithography apparatus. DUV stands for "deep ultraviolet" and denotes a wavelength of the working light between 30 nm and 250 nm.

[0030] According to a specific embodiment, the multiplexer unit is embodied in the form of Nx1 multiplexer units. The Nx1 multiplexer units are configured to receive N analog sensor signals from N sensors of the optical system via N channels and to provide an analog signal sequence comprising N multiplexed analog sensor signals on an output side. In general, N ≥ 2. For example, N may be greater than 100 or greater than 1000.

[0031] According to yet another specific embodiment, the digital filter device comprises:

[0032] a plurality of N parallel digital filters, wherein each of the N digital filters is assigned exactly one of the N channels; and

[0033] A demultiplexer unit is connected between the analog-to-digital converter and the N digital filters and is configured to demultiplex the multiplexed digital sensor signal of the digital signal sequence to the N digital filters in a channel-specific manner for the N channels.

[0034] This embodiment utilizes the (already mentioned above) multiple instantiation of the digital filter, in the present case an N-fold instantiation of the digital filter. The individual digital filters in particular comprise memory locations for buffering individual filter values. Furthermore, multiple filter values ​​per channel can be buffered. A buffer can be used for this purpose. Thus, the digital filter device is suitable for parallel processing of multiple channels as a general-purpose arithmetic unit.

[0035] According to a further embodiment, the device comprises a storage unit connected downstream of the N digital filters, having N memory locations. Here, each of the N memory locations is assigned exactly one of the N channels. A respective memory location is configured to store a respective filtered digital sensor signal of a respective channel of the N channels.

[0036] According to another specific embodiment, the device includes a digital-to-analog converter connected between the control unit and the N sensors. Here, the control unit is configured to perform clock synchronization control on the multiplexer unit, the analog-to-digital converter, the digital filter device, the storage unit, and the N sensors by means of the digital-to-analog converter.

[0037] Due to the additional use of a digital-to-analog converter, the control unit can also use more components of the system to be able to perform clock-synchronous control on the N sensors.

[0038] According to a further embodiment, the digital filter device comprises a plurality of M delay units connected in series for receiving a sequence of digital signals including the digital sensor signal, wherein M ≥ 2. Here, each of the individual delay units has a memory location for each of the N channels. Each of the N memory locations is assigned exactly one of the N channels. The delay unit shifts the memory content of its memory location to the memory location of the respective delay unit connected downstream in a channel-specific manner for the N channels according to a system clock.

[0039] This embodiment has the advantage in particular that hardware resources in the form of memory and computing power can be saved. Here, the digital filter device according to the invention with the plurality of delay units is configured to multiplex between the filter values ​​of the different channels and to provide the respectively selected channels on the output side.

[0040] According to a further embodiment, a respective multiplier unit is connected downstream of each of the M delay units. Here, each multiplier unit is assigned a specific filter coefficient. The delay unit is configured to supply the memory content of a specific channel among the N channels to the M multiplier units in dependence on a system clock. The M multiplier units are configured to multiply the memory content supplied by the M delay units by the specific filter coefficient. An adding unit connected downstream of the M multiplier units adds the products of the multiplications provided by the M multiplier units in order to provide a filtered digital sensor signal for the specific channel.

[0041] According to yet another specific embodiment, the digital filter device forms a finite impulse response (FIR) filter, an infinite impulse response (IIR) filter, a biquad filter, or a CIC filter.

[0042] The multiplier unit thus always processes exactly one specific frequency channel at a specific time and is therefore configured to provide a filtered digital sensor signal of the specific frequency channel on the output side using the adding unit.

[0043] According to a further embodiment, the device comprises a storage unit having N memory locations and connected downstream of the adding unit. Each of the N memory locations is assigned exactly one of the N channels. Here, a respective memory location is configured to store a respective filtered digital sensor signal of a corresponding one of the N channels.

[0044] According to yet another embodiment, the apparatus comprises a control unit configured to perform clock synchronization control on the multiplexer unit, the analog-to-digital converter, the delay unit, and the storage unit by means of a frequency-synchronized system clock.

[0045] According to another embodiment, the device comprises a digital-to-analog converter connected between the control unit and the N sensors. The control unit is configured to perform clock synchronization control on the multiplexer unit, the analog-to-digital converter, the delay unit, the storage unit, and the N sensors by means of the digital-to-analog converter and by means of a frequency synchronization system clock.

[0046] By using the digital-analog converter, the current and / or voltage values ​​at the sensor can be controlled in a targeted manner in order to induce resonance, for example. Due to the use of the digital-analog converter, it is further possible to use further electronically controllable circuits (such as adjustable resistors, capacitors, coils, or heating wires) to influence the sensor behavior of the N sensors.

[0047] According to another embodiment, the digital filter device, the storage unit, and the control unit are provided (particularly integrated) in a processor device. Particularly, the processor device is a microprocessor, a digital signal processor (DSP), or an FPGA (field programmable gate array).

[0048] For example, if the processor device controls an electric motor (in which the speed is actively specified), the induced disturbance signal can be predicted (e.g. based on a model) as a function of the speed. Thus, as the speed of the motor is dynamically controlled, the filtering of the sensor values ​​can also be continuously adapted by the digital filter device.

[0049] Embodiments as processor devices or as digital circuits (such as FPGAs, ASICs, or digital logic modules) may enable cycle-accurate conversions, whereby phase noise may advantageously be further reduced.

[0050] According to a further embodiment, the processor device further comprises a signal analysis unit. The signal analysis unit is configured to analyze the digital sensor signal of the digital signal sequence and / or the filtered digital sensor signal and to adapt at least one property of the digital filter device accordingly, in particular a filter coefficient of the digital filter device and / or a sampling frequency of the analog-to-digital converter.

[0051] Due to the analysis of the digital signal sequence and / or the filtered digital signal sequence, the signal analysis unit is suitable for adaptive noise suppression. In this case, the signal analysis unit can adapt the noise suppression, in particular during operation, in particular by continuously analyzing the input signal or the transfer function of the input signal and the output signal. In particular, the adaptive noise suppression can be achieved by changing the sampling frequency of the analog-to-digital converter or by adapting the digital filter device. Depending on the embodiment, in addition to the filter coefficients, the structure of the digital filter device can also be adapted.

[0052] According to yet another specific embodiment, the N sensors and the multiplexer unit are arranged in a vacuum housing of the optical system. In this case, in particular, the analog-to-digital converter and the digital filter device are arranged outside the vacuum housing.

[0053] According to yet another specific embodiment, the N sensors are arranged in a vacuum housing of the optical system, and the multiplexer unit is arranged outside the vacuum housing.

[0054] According to a further embodiment, the sampling frequency of the analog-to-digital converter is selected such that the sampling frequency used for filtering the interference frequency is less than twice the interference frequency. As a result, it is also possible to suppress high frequency interference using an analog-to-digital converter that is tuned for high accuracy rather than speed.

[0055] Individual units (e.g. control units) may be implemented by hardware technology and / or software technology. In the case of hardware implementation, the unit may be in the form of a device or a part of a device, such as a computer or a microprocessor or a part of a control device. In the case of software implementation, the unit may be in the form of a computer program product, a function, a routine, a part of a program code, or an executable object.

[0056] According to a second aspect, an optical system for a lithographic apparatus is provided, wherein the optical system comprises an apparatus according to the first aspect or according to one of the specific embodiments of the first aspect.

[0057] Depending on the embodiment, the optical system is in the form of an illumination optical unit or in the form of a projection optical unit of a lithographic apparatus.

[0058] According to a third aspect, a lithographic apparatus is provided, which has an optical system according to the second aspect or according to one of the specific embodiments of the second aspect.

[0059] According to a fourth aspect, a method for providing sensor data from N sensors (where N ≥ 1) of an optical system of a lithographic apparatus is provided. The method comprises the following steps:

[0060] converting an analog signal sequence provided via N channels and comprising N analog sensor signals from the N sensors of the optical system into a digital signal sequence comprising N digital sensor signals; and

[0061] The N digital sensor signals of the digital signal sequence are filtered in a channel-specific manner by means of a digital filter device connected downstream of the analog-to-digital converter in order to provide and store individual filtered digital sensor signals for each of the N channels, wherein the analog-to-digital converter and the digital filter device have the same frequency synchronized system clock.

[0062] According to a specific embodiment, the method comprises the following steps:

[0063] receiving, at a multiplexer unit, a plurality of N analog sensor signals from a plurality of N sensors of the optical system via a plurality of N channels (where N ≥ 2),

[0064] providing an analog signal sequence comprising the N multiplexed analog sensor signals by means of the multiplexer unit,

[0065] transmitting the analog signal serially to an analog-to-digital converter connected to the multiplexer unit,

[0066] converting the analog signal sequence into a digital signal sequence comprising N multiplexed digital sensor signals by means of the analog-to-digital converter, and

[0067] The multiplexed digital sensor signal of the digital signal sequence is filtered in a channel-specific manner by means of a digital filter device connected downstream of the analog-to-digital converter in order to provide and store a respective filtered digital sensor signal for each of the N channels.

[0068] The specific embodiments described for the proposed device also apply to the proposed method, and vice versa. Furthermore, the definitions and explanations about the device also apply to the proposed method.

[0069] According to a fifth aspect, a design method for designing a device is provided, the device comprising an analog-to-digital converter for converting an analog sensor signal into a digital sensor signal; and a digital filter device connected downstream of the analog-to-digital converter for filtering the digital sensor signal, which includes a used signal component having a used signal frequency with a used signal bandwidth, and an interference signal component having at least one known interference frequency that is undersampled by the analog-to-digital converter. The design method comprises:

[0070] The sampling frequency of the analog-to-digital converter is selected so that at least one alias frequency of the under-sampled interference signal component is outside the used signal bandwidth and the sampling frequency is not a submultiple of the interference frequency; and

[0071] The sampling frequency of the analog-to-digital converter and the filter order of the digital filter device with low-pass behavior are selected such that the digital filter device allows signal components within the used signal bandwidth to pass and suppresses at least one aliasing frequency of the undersampled interfering signal components.

[0072] For the example of a moving average filter as a digital filter device, the sampling frequency of the analog-to-digital converter and the filter order may be selected such that a quotient of the sampling frequency and the filter order corresponds to a submultiple of the aliasing frequency and is larger than the used signal bandwidth.

[0073] In particular, the method according to the invention is used for under-sampled interference frequencies. The one or more interference frequencies and the one or more aliasing frequencies are determined and are therefore known a priori. Accordingly, in particular, the method according to the invention is used when the sampling rate of the analog-to-digital converter is too low to sample a specific interference frequency according to the Nyquist-Shannon sampling theorem, in particular due to very precise but slow analog-to-digital converters, and / or due to the necessary multiplexing of multiple signals from multiple channels to be processed in parallel. In the case of under-sampling of the interference frequency, aliasing effects occur, so that the interference frequency image appears in the low frequency band. This is called an image interference frequency or aliasing frequency.

[0074] According to the design method of the present invention, the sampling frequency of the analog-to-digital converter and the filter order of the digital filter device are selected so as to meet the following three conditions I, II, and III.

[0075] Condition I: The sampling frequency of the analog-to-digital converter is selected such that the at least one aliasing frequency is outside the used signal bandwidth of the digital sensor signal. Furthermore, the sampling frequency of the analog-to-digital converter is selected such that it is greater than twice the used signal bandwidth.

[0076] Condition II: The sampling frequency of the analog-to-digital converter is selected such that the sampling frequency is not a multiple of the interference frequency.

[0077] Condition III: The digital filter setting has a low-pass behavior that allows signal components within the used signal bandwidth to pass and suppresses aliasing frequencies of the undersampled interfering signal components.

[0078] For the example of a moving average filter as a digital filter device, the condition III can be formulated using the conditions IIIa and IIIb:

[0079] Condition IIIa: The sampling frequency of the analog-to-digital converter and the filter order of the digital filter device are selected such that the quotient of the sampling frequency and the filter order corresponds to a submultiple of the aliasing frequency.

[0080] Condition IIIb: The sampling frequency of the analog-to-digital converter and the filter order of the digital filter device are selected so that the quotient of the sampling frequency and the filter order is greater than the used signal bandwidth.

[0081] The filter order of the digital filter device specifically corresponds to a plurality of M delay units connected in series of the digital filter device.

[0082] The device designed using the design method of the present invention (the device includes an analog-to-digital converter and a digital filter device) is capable of filtering the aliased frequencies of under-sampled known interference frequencies without significantly affecting the used signal bandwidth of the used signal.

[0083] The aliasing frequency may also be called an image interference frequency or a mirror frequency.

[0084] The device designed using the design method of the present invention is configured to provide sensor data from N sensors (where N ≥ 1) of an optical system of a lithography device, and preferably comprises:

[0085] an analog-to-digital converter configured to convert an analog signal sequence provided via N channels and comprising N analog sensor signals from the N sensors of the optical system into a digital signal sequence comprising N digital sensor signals; and

[0086] a digital filter device connected downstream of the analog-to-digital converter, wherein the analog-to-digital converter and the digital filter device have the same frequency synchronized system clock, and the digital filter device is configured to filter the N digital sensor signals of the digital signal sequence in a channel-specific manner in order to provide and store a respective filtered digital sensor signal for each of the N channels,

[0087] The digital filter device comprises a plurality of M delay units connected in series, which are used to receive the digital signal sequence including the digital sensor signal, wherein M ≥ 2, wherein each individual delay unit has a memory location for each of the N channels, wherein each of the N memory locations is allocated exactly one of the N channels, and wherein the delay unit is configured to shift the memory content of its memory location to the memory location of the delay unit connected downstream in a channel-specific manner for the N channels according to a system clock.

[0088] According to a specific embodiment of the design method, the digital filter device is in the form of a notch filter.

[0089] According to yet another specific embodiment of the design method, the digital filter device is in the form of a moving average filter in a FIR filter structure.

[0090] The following example of a moving average filter shows an exemplary use of the design method described above:

[0091] Based on the above conditions I to III (IIIa, IIIb), the filter order M of the digital filter device is as follows at a sampling frequency f of 100 Hz: s , the used signal bandwidth f is 2 Hz N , interference frequency f of 60 Hz d , and the aliasing frequency f of 40 Hz a Next select:

[0092] 1. Aliasing frequency f of 40 Hz a (Image interference frequency) is a divisor of 10.

[0093] 2. For divisor 10: f s / M = 10 → M = 10. The divisor 10 and the resulting filter order M = 10 meet all conditions I to III, as well as IIIa and IIIb. Therefore, the filter order M = 10 is acceptable for the example of the present invention.

[0094] According to yet another embodiment, a plurality of digital filter devices are connected in series in order to improve the signal-to-noise ratio of the filtered digital sensor signal.

[0095] A plurality of digital filter devices, in particular in the form of individual FIR filter units, may advantageously be connected in series and / or combined with low-pass filters, high-pass filters, and / or band-pass filters.

[0096] According to the sixth aspect, a device is proposed, which includes an analog-to-digital converter for converting an analog sensor signal into a digital sensor signal; and a digital filter device, which is connected downstream of the analog-to-digital converter and has a low-pass behavior for filtering the digital sensor signal (which includes a used signal component having a used signal frequency with a used signal bandwidth, and an interference signal component having at least one determinable aliasing frequency of a known interference frequency in the analog sensor signal that is undersampled by the analog-to-digital converter), wherein the sampling frequency of the analog-to-digital converter and the filter order of the digital filter device are selected so that the at least one aliasing frequency is outside the used signal bandwidth, and the sampling frequency is not a multiple of the interference frequency, and so that the digital filter device allows the signal component within the used signal bandwidth to pass and suppresses at least one aliasing frequency of the undersampled interference signal component.

[0097] According to the seventh aspect, a method for operating the apparatus as described above is proposed, wherein the analog-to-digital converter and the digital filter device are controlled so that the analog-to-digital converter sequentially converts a series of sensor signal values ​​of the analog sensor signal from each of the N channels into digital sensor signals, and the digital filter device subsequently filters them.

[0098] The apparatus used according to the seventh aspect is configured to provide sensor data from N sensors (where N ≥ 1) of an optical system of a lithographic apparatus and preferably comprises:

[0099] an analog-to-digital converter configured to convert an analog signal sequence provided via N channels and comprising N analog sensor signals from the N sensors of the optical system into a digital signal sequence comprising N digital sensor signals; and

[0100] a digital filter device connected downstream of the analog-to-digital converter, wherein the analog-to-digital converter and the digital filter device have the same frequency synchronized system clock, and the digital filter device is configured to filter the N digital sensor signals of the digital signal sequence in a channel-specific manner in order to provide and store a respective filtered digital sensor signal for each of the N channels,

[0101] The digital filter device comprises:

[0102] a plurality of N parallel digital filters, wherein each of the N digital filters is assigned exactly one of the N channels; and

[0103] A demultiplexer unit is connected between the analog-to-digital converter and the N digital filters and is configured to demultiplex the multiplexed digital sensor signal of the digital signal sequence to the N digital filters in a channel-specific manner for the N channels.

[0104] According to one embodiment, the device comprises a storage unit having N memory locations connected downstream of the N digital filters. Here, each of the N memory locations is assigned exactly one of the N channels. A respective memory location is configured to store a respective filtered digital sensor signal of a respective channel of the N channels.

[0105] According to a specific embodiment, the digital filter device averages the raw values ​​of the digital sensor signals of the individual channels over a period of an integer number of known cycles of the interference signal component in order to provide the filtered digital sensor signal.

[0106] In this way, aliased frequencies of the interfering frequency which occur due to undersampling are filtered out.

[0107] In the context of the present invention, "one" or "an" should not necessarily be understood as being limited to exactly one element. Rather, a plurality of elements (e.g., two, three, or more) may also be provided. Any other number used herein should also not be understood as having the effect of being limited to exactly the number of elements stated. On the contrary, unless otherwise indicated, upward and downward numerical deviations are possible.

[0108] More possible implementations of the present invention also include combinations (not explicitly mentioned) of the features or specific embodiments described above or below with respect to the exemplary specific embodiments. In this case, those skilled in the art will also add individual aspects as improvements or supplements to individual basic forms of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] Further advantageous configurations and aspects of the invention are the subject matter of the dependent claims and exemplary embodiments of the invention which will be described below.The invention will be explained in detail below based on preferred embodiments with reference to the accompanying drawings.

[0110] Figure 1 A schematic meridional cross section showing a projection exposure apparatus for EUV projection lithography;

[0111] Figure 2 A schematic illustration of a first specific embodiment of an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus is shown;

[0112] Figure 3 A schematic illustration of a second specific embodiment of an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus;

[0113] Figure 4 A schematic illustration of a third specific embodiment of an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus;

[0114] Figure 5 A schematic illustration of a fourth specific embodiment of an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus;

[0115] Figure 6 A schematic illustration of a fifth specific embodiment of an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus;

[0116] Figure 7 A schematic illustration of a sixth specific embodiment of an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus;

[0117] Figure 8 A schematic diagram showing a specific embodiment of a method of providing sensor data from a sensor of an optical system of a lithographic apparatus;

[0118] Fig. 9 A schematic diagram showing yet another specific embodiment of a method of providing sensor data from a sensor of an optical system of a lithographic apparatus;

[0119] Fig.10 A schematic diagram showing a specific embodiment of a method for designing an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus;

[0120] Fig.11 Display is used to illustrate (by example) the basis Fig.10 A schematic diagram of the sampling frequency, interference frequency, aliasing frequency, and frequency profile of the designed device; and

[0121] Fig.12 A schematic diagram showing a specific embodiment of a method for operating an apparatus for providing sensor data from a sensor of an optical system of a lithographic apparatus. DETAILED DESCRIPTION

[0122] Unless otherwise indicated, identical or functionally equivalent elements have been provided with the same reference numerals in the drawings.It should also be noted that the illustrations in the drawings are not necessarily drawn to scale.

[0123] Figure 1A specific embodiment of a projection exposure apparatus 1 (lithography apparatus), in particular an EUV lithography apparatus, is shown. In addition to a light or radiation source 3, a specific embodiment of an illumination system 2 of the projection exposure apparatus 1 has an illumination optical unit 4 for illuminating an object field 5 in an object plane 6. In an alternative specific embodiment, the light source 3 might also be provided as a module separate from the rest of the illumination system 2. In this case, the illumination system 2 does not comprise the light source 3.

[0124] A reticle 7 arranged in the object field 5 is exposed. The reticle 7 is held by a reticle holder 8. The reticle holder 8 can be displaced by a reticle displacement drive 9, in particular in the scanning direction.

[0125] For illustrative purposes, Figure 1 A Cartesian coordinate system is shown with an x-direction x, a y-direction y, and a z-direction z. The x-direction x runs perpendicular to the plane of the figure. The y-direction y runs transversely, and the z-direction z runs longitudinally. Figure 1 In the embodiment of the present invention, the scanning direction runs in the y-direction y. The z-direction z runs perpendicular to the object plane 6.

[0126] The projection exposure apparatus 1 comprises a projection optical unit 10. The projection optical unit 10 serves to image the object field 5 into an image field 11 in an image plane 12. The image plane 12 extends parallel to the object plane 6. Alternatively, angles other than 0° are also possible between the object plane 6 and the image plane 12.

[0127] The structures on the reticle 7 are imaged onto a photosensitive layer of a wafer 13 which is arranged in the region of an image field 11 in an image plane 12. The wafer 13 is held by a wafer holder 14. The wafer holder 14 can be displaced, in particular in the y direction y, by a wafer displacement drive 15. The displacement of firstly the reticle 7 by the reticle displacement drive 9 and secondly the wafer 13 by the wafer displacement drive 15 can be carried out synchronously with one another.

[0128] The light source 3 is a EUV radiation source. The light source 3 emits in particular EUV radiation 16, also referred to below as used radiation, illumination radiation or illumination light. In particular, the used radiation 16 has a wavelength in the range between 5 nm and 30 nm. The light source 3 may be a plasma source, such as an LPP (acronym for laser produced plasma) source or a DPP (acronym for gas-discharge produced plasma) source. It may also be a synchrotron type radiation source. The light source 3 may be an FEL (acronym for free-electron laser).

[0129] The illumination radiation 16 emerging from the light source 3 is focused by a collector 17. The collector 17 may be a collector having one or more elliptical and / or hyperbolic reflecting surfaces. At least one reflecting surface of the collector 17 may be illuminated by the illumination radiation 16 at grazing incidence (abbreviation: GI), i.e. at an angle of incidence greater than 45°, or at normal incidence (abbreviation: NI), i.e. at an angle of incidence less than 45°. The collector 17 may be structured and / or coated firstly in order to optimize its reflectivity for the radiation used and secondly in order to suppress extraneous light.

[0130] Downstream of the collector 17, the illumination radiation 16 propagates through an intermediate focus in an intermediate focal plane 18. The intermediate focal plane 18 may represent a separation between the radiation source module with the light source 3 and the collector 17 and the illumination optical unit 4.

[0131] The illumination optical unit 4 comprises a deflection mirror 19; and a first facet mirror 20, which is arranged downstream of the deflection mirror in the beam path. The deflection mirror 19 may be a plane deflection mirror or a reflector having a beam influencing effect that is not merely a pure deflection effect. As an alternative or in addition, the deflection mirror 19 may be in the form of a spectral filter which separates the used light wavelength of the illumination radiation 16 from extraneous light of a wavelength deviating therefrom. If the first facet mirror 20 is arranged in a plane which is optically conjugated to the illumination optical unit 4 and the object plane 6 as a field plane, it is also referred to as a field facet mirror. The first facet mirror 20 comprises a plurality of individual first facets 21, which may also be referred to as field facets. Only some of these first facets 21 are shown by way of example in Figure 1 middle.

[0132] The first facets 21 may be embodied as macro facets, in particular rectangular facets or facets with an arched edge profile or an edge profile of a portion of a circle. The first facets 21 may be in the form of planar facets or as facets with a convex or concave curvature.

[0133] As is known, for example, from DE 10 2008 009 600 A1, the first facets 21 themselves can also each consist of a plurality of individual mirrors, in particular a plurality of micromirrors. The first facet mirrors 20 can in particular be in the form of a microelectromechanical system (MEMS system). For further information, please refer to DE 10 2008 009 600 A1.

[0134] Between the collector 17 and the deflection mirror 19 the illuminating radiation 16 travels transversely, ie in this y-direction y.

[0135] In the beam path of the illumination optical unit 4, the second facet mirror 22 is arranged downstream of the first facet mirror 20. If the second facet mirror 22 is arranged in the pupil plane of the illumination optical unit 4, it is also called a pupil facet mirror. The second facet mirror 22 can also be arranged at a distance from the pupil plane of the illumination optical unit 4. In this case, the combination of the first facet mirror 20 and the second facet mirror 22 is also called a specular reflector. Specular reflectors are known from US 2006 / 0132747 A1, EP 1 614 008 B1, and US 6,573,978.

[0136] The second facet mirror 22 comprises a plurality of second facets 23. In the case of a pupil facet mirror, the second facets 23 are also called pupil facets.

[0137] The second facets 23 may also be macroscopic facets, which may have, for example, circular, rectangular or hexagonal boundaries, or facets consisting of micromirrors. In this case, reference is also made to DE 10 2008 009 600 A1.

[0138] The second facet 23 may have a planar reflective surface, or a reflective surface with a convex or concave curvature.

[0139] Therefore, the illumination optical unit 4 forms a two-facet system. This basic principle is also called a fly's eye condenser (or integrator).

[0140] It may be advantageous that the second facet mirror 22 is not arranged exactly in a plane optically conjugate to the pupil plane of the projection optical unit 10. In particular, the second facet mirror 22 may be arranged tilted relative to the pupil plane of the projection optical unit 10, as described, for example, in DE 10 2017 220 586 A1.

[0141] By means of the second facet mirror 22 , the individual first facets 21 are imaged into the object field 5 . The second facet mirror 22 is the last beam shaping mirror or in fact the last mirror for the illumination radiation 16 in the beam path upstream of the object field 5 .

[0142] In a further specific embodiment (not illustrated) of the illumination optical unit 4, a transmission optical unit can be arranged in the beam path between the second facet mirror 22 and the object field 5, wherein the transmission optical unit in particular contributes to the imaging of the first facet 21 into the object field 5. The transmission optical unit can comprise exactly one mirror, but alternatively also two or more mirrors, which are arranged consecutively in the beam path of the illumination optical unit 4. The transmission optical unit can in particular comprise one or two normal incidence mirrors (NI mirrors) and / or one or two grazing incidence mirrors (GI mirrors).

[0143] exist Figure 1 In the specific embodiment shown in FIG. 1 , the illumination optical unit 4 has exactly three mirrors downstream of the collector 17 , specifically a deflection mirror 19 , a first facet mirror 20 , and a second facet mirror 22 .

[0144] In a further specific embodiment of the illumination optical unit 4 , the deflection mirror 19 can also be omitted and the illumination optical unit 4 can therefore then have exactly two mirrors downstream of the collector 17 , specifically a first facet mirror 20 and a second facet mirror 22 .

[0145] The imaging of the first facet 21 into the object plane 6 by means of the second facet 23 or using the second facet 23 and the transfer optical unit is often only approximately imaged.

[0146] The projection optical unit 10 comprises a plurality of mirrors Mi which are numbered according to the sequence of their arrangement in the beam path of the projection exposure apparatus 1 .

[0147] exist Figure 1 In the example shown, the projection optical unit 10 comprises six mirrors M1 to M6. Alternative examples with four, eight, ten, twelve, or any other number of mirrors Mi are also possible. The projection optical unit 10 is a twice-obscured optical unit. The penultimate mirror M5 and the last mirror M6 both have a passage opening for the illumination radiation 16. The projection optical unit 10 has an image-side numerical aperture of greater than 0.5 and possibly also greater than 0.6 and possibly, for example, 0.7 or 0.75.

[0148] The reflective surface of the reflector Mi can be embodied as a free-form surface without an axis of rotational symmetry. Alternatively, the reflective surface of the reflector Mi can be designed as an aspherical surface with exactly one axis of rotational symmetry of the shape of the reflective surface. Just like the reflectors of the illumination optical unit 4, the reflector Mi may have a highly reflective coating for the illumination radiation 16. These coatings can be designed as multilayer coatings, in particular with alternating layers of molybdenum and silicon.

[0149] The projection optical unit 10 has a large object-image offset in the y direction y between the y coordinate of the center of the object field 5 and the y coordinate of the center of the image field 11. This object-image offset in the y direction y may have approximately the same magnitude as the z distance between the object plane 6 and the image plane 12.

[0150] The projection optical unit 10 may in particular have a deformed form. It has in particular different imaging ratios βx, βy in the x and y directions x, y. The two imaging ratios βx, βy of the projection optical unit 10 are preferably (βx, βy)=(+ / -0.25, + / -0.125). A positive imaging ratio β means imaging without image reversal. A negative sign for the imaging ratio β means imaging with image reversal.

[0151] Therefore, the projection optical unit 10 results in a size reduction in the x-direction x, ie in a direction perpendicular to the scanning direction, by a ratio of 4:1.

[0152] The projection optical unit 10 results in a downsizing of 8:1 in the y-direction y, ie in the scanning direction.

[0153] Other imaging ratios are also possible. Imaging ratios with the same sign and the same absolute value in the x direction x and the y direction y are also possible, for example with an absolute value of 0.125 or 0.25.

[0154] In the beam path between the object field 5 and the image field 11, the number of intermediate image planes in the x-direction x and the y-direction y may be the same or may be different, depending on the specific embodiment of the projection optical unit 10. Examples of projection optical units with a different number of such intermediate images in the x- and y-directions x, y are known from US 2018 / 0074303 A1.

[0155] In each case, one of the second facets 23 is assigned to one of the first facets 21 in order to form an illumination channel for illuminating the object field 5. This makes it possible in particular to generate illumination according to the Köhler principle. The far field is decomposed into a plurality of object fields 5 by means of the first facets 21. The first facets 21 generate a plurality of images of the intermediate focus on the second facets 23 respectively assigned thereto.

[0156] The first facets 21 are imaged onto the reticle 7 in each case overlapping one another for the purpose of illuminating the object field 5 by means of the assigned second facets 23. In particular, the illumination of the object field 5 is as homogeneous as possible. It preferably has a homogeneity error of less than 2%. Field homogeneity can be achieved by overlapping different illumination channels.

[0157] The illumination of the entrance pupil of the projection optical unit 10 may be geometrically defined by the arrangement of the second facets 23. The intensity distribution in the entrance pupil of the projection optical unit 10 may be set by selecting the illumination channels, in particular the subset of the second facets 23 that guide the light. This intensity distribution is also referred to as illumination setting or illumination pupil filling.

[0158] An equally good pupil homogeneity in the region of the segments of the illumination pupil of the illumination optical unit 4 that are illuminated in a defined manner is possible by redistribution of the illumination channels.

[0159] Further aspects and details of the illumination of the object field 5 and in particular of the entrance pupil of the projection optical unit 10 are explained below.

[0160] The projection optical unit 10 may in particular have a concentric entrance pupil. The concentric entrance pupil may be accessible or inaccessible.

[0161] The entrance pupil of the projection optical unit 10 is often not fully illuminated by the second facet mirror 22. When imaging the center of the second facet mirror 22 telecentrically onto the projection optical unit 10 on the wafer 13, the aperture rays often do not intersect at a single point. However, it is possible to find a surface area in which the spacing of the aperture rays determined in pairs is minimal. This surface area represents the entrance pupil, or an area in real space conjugate therewith. In particular, this surface area has a finite curvature.

[0162] The projection optical unit 10 may have different positions of the entrance pupil for the tangential beam path and for the sagittal beam path. In this case, an imaging element, in particular an optical assembly component of the transmission optical unit, should be provided between the second facet mirror 22 and the reticle 7. With the help of this optical element, different poses of the tangential entrance pupil and the sagittal entrance pupil can be taken into account.

[0163] exist Figure 1 In the arrangement of the components of the illumination optical unit 4 shown in , the second facet mirror 22 is arranged in a region conjugate with the entrance pupil of the projection optical unit 10. The first facet mirror 20 is arranged tilted with respect to the object plane 6. The first facet mirror 20 is arranged tilted with respect to the arrangement plane defined by the deflection mirror 19. The first facet mirror 20 is arranged tilted with respect to the arrangement plane defined by the second facet mirror 22.

[0164] Figure 2A schematic illustration of a first specific embodiment of a display device 100 is shown. The device 100 is arranged in an optical system 4, 10 (e.g. an illumination optical unit 4 or a projection optical unit 10) of a lithographic apparatus 1 and is used to provide sensor data from N sensors 301 (where N ≥ 1) of the optical system 4, 10 of the lithographic apparatus 1. Without prejudice to generality, Figure 2 Where N = 1. The sensor 301 is disposed in the vacuum housing 110 of the lithography apparatus 1 .

[0165] Figure 2 The device 100 in FIG. 4 comprises an analog-to-digital converter 500 . The analog-to-digital converter 500 is connected to the sensor 301 via an electrical connection 410 . Figure 2 The device 100 further comprises a processor device 900, which is in particular in the form of a microprocessor, a DSP, or an FPGA. Figure 2 In the example of , the processor device 900 comprises a digital filter device 600 and a control unit 800. The analog-to-digital converter 500 and the processor device 900 are coupled via an interface 420. The interface 420 is in particular a digital interface, such as a peripheral bus (eg an SPI bus).

[0166] The analog-to-digital converter 500 converts an analog signal sequence AF including analog sensor signals from the sensor 301 into a digital signal sequence DF including digital sensor signals.

[0167] The analog-to-digital converter 500 and the digital filter device 600 connected downstream of the analog-to-digital converter 500 have the same frequency-synchronized system clock. In particular, the sensor 301 also has the same frequency-synchronized system clock. Figure 2 In the example of , the control unit 800 is configured to synchronize the system clock with the sequence, perform clock synchronization control on the sensor 301, the analog-to-digital converter 500, and the digital filter device 600, and thereby synchronize them with each other.

[0168] The digital filter device 600 is configured to filter the digital sensor signals of the digital signal sequence DF in a channel-specific manner in order to provide and store a respective filtered digital sensor signal for each of the N channels.

[0169] If a plurality of sensors 301 are provided (where N ≥ 2), a multiplexer unit 200 may be used (see e.g. Figure 3 ), or a multi-channel-ready analog-to-digital converter may be used. Preferably, an analog filter (not shown) may also be placed between the individual sensors 301 and the analog-to-digital converter 500 .

[0170] Figure 3 Schematic illustration of a second specific embodiment of the display apparatus 100. The apparatus 100 is arranged in an optical system 4, 10 (eg an illumination optics unit 4 or a projection optics unit 10) of a lithographic apparatus 1 and is used to provide sensor data from sensors 301-30N of the optical system 4, 10 of the lithographic apparatus 1.

[0171] exist Figure 3 In the embodiment, the device 100 comprises a vacuum housing 110, for example, an optical system 4. A plurality of N sensors 301-30N and a multiplexer unit 200 are arranged in the vacuum housing 110. The sensors 301-30N comprise, for example, temperature measuring sensors, such as NTC sensors, photodiodes, or capacitors. In particular, the sensors 301-30N have in common that they provide analog sensor signals A1-AN on the output side.

[0172] exist Figure 3 In the embodiment, the multiplexer unit 200 is disposed inside the vacuum housing 110. In various specific embodiments, the multiplexer unit 200 may also be disposed outside the vacuum housing 110.

[0173] The multiplexer unit 200 is configured to receive analog sensor signals A1-AN from a plurality of N sensors 301-30N of the optical system 4, 10 via a plurality of N frequency channels K1-KN and to provide an analog signal sequence AF comprising N multiplexed analog sensor signals A1-AN on the output side via an electrical connection 410. Each sensor 301-30N is assigned a frequency channel K1-KN via which an individual analog sensor signal A1-AN is supplied to the multiplexer unit 200.

[0174] Here, preferably, the multiplexer unit 200 is configured as Nx1 multiplexer units 200, which are configured to receive N analog sensor signals A1-AN from N sensors 301-30N of the optical system 4, 10 via N channels K1-KN, and provide an analog signal sequence AF including the N multiplexed analog sensor signals A1-AN on the output side via a single electrical connection 410.

[0175] also, Figure 3The device 100 comprises an analog-to-digital converter 500, which is connected to the multiplexer unit 200 via an electrical connection 410. The analog-to-digital converter 500 is configured to convert the analog signal sequence AF provided by the multiplexer unit 200 into a digital signal sequence DF comprising N multiplexed digital sensor signals D1-DN. In this case, the digital sensor signal D1 corresponds to a digital representation of the analog sensor signal A1. Both, i.e. the digital sensor signal D1 and the analog sensor signal A1, are assigned to the channel K1. Accordingly, the digital sensor signal D2 corresponds to a digital representation of the analog sensor signal A2, and both are assigned to the channel K2. The same applies to the other digital and analog signals accordingly. Accordingly, the digital signal DN is ultimately a digital representation of the analog signal AN, and both are assigned to the channel KN.

[0176] exist Figure 3 In the embodiment, the multiplexer unit 200 is disposed between the sensors 301-30N and the analog-to-digital converter 500. In various specific embodiments, the multiplexer unit 200 may also be disposed upstream of the sensors 301-30N (not shown).

[0177] Figure 3 The device 100 also includes a processor device 900, which is in the form of, for example, a microprocessor, a DSP, or an FPGA. The processor device 900 may also be referred to as a processing unit. Figure 3 In the example of , the processor device 900 includes a digital filter device 600 , a storage unit 700 , a control unit 800 , and an interface 910 .

[0178] The analog-to-digital converter 500 is coupled to the digital filter device 600 via the interface 420. The digital filter device 600 is configured to filter the multiplexed digital sensor signals D1-DN of the digital signal sequence DF in a channel-specific manner for the N channels K1-KN in order to provide and store the individual filtered digital sensor signals F1-FN for each of the channels K1-KN. For this purpose, Figure 3 The digital filter device 600 includes a plurality of N parallel digital filters 611 - 61N, wherein each of the N digital filters 611 - 61N is allocated exactly one of the channels K1 -KN. Figure 3The digital filter device 600 further includes a demultiplexer unit 620. The demultiplexer unit 620 is disposed between the analog-to-digital converter 500 and the N digital filters 611-61N. The demultiplexer unit 620 demultiplexes the multiplexed digital sensor signals D1-DN of the digital signal sequence DF to the N digital filters 611-61N in a specific channel manner for the N channels K1-KN, i.e., correctly distributes the multiplexed digital sensor signals D1-DN in a specific channel manner. The individual digital filters 611-61N filter the supplied sensor signals D1-DN and provide filtered digital sensor signals F1-FN on the output side.

[0179] Figure 3 The device 100 further comprises a storage unit 700. The storage unit 700 is connected downstream of the N digital filters 611-61N and comprises N memory locations 701-70N. Here, each of the N memory locations 701-70N is assigned exactly one of the N channels K1-KN. Here, a respective memory location 701-70N is configured to store a respective filtered digital sensor signal F1-FN for each of the N channels K1-KN. In addition, a buffer is preferably provided for the last X sensor signals of each channel K1-KN.

[0180] In particular, the control unit 800 is configured to perform clock synchronization control on the multiplexer unit 200 , the analog-to-digital converter 500 , and the digital filter device 600 .

[0181] Figure 4 A schematic illustration of a third specific embodiment of an apparatus 100 for providing sensor data from sensors 301 - 30N of an optical system 4 , 10 of a lithographic apparatus 1 is shown. Figure 4 A third specific embodiment of the device 100 comprises a method according to Figure 3 All the features of the second specific embodiment of the present invention. Moreover, Figure 4 The device 100 includes a digital-to-analog converter 510. The digital-to-analog converter 510 is arranged between the control unit 800 and the N sensors 301-30N. Figure 4 The control unit 800 is configured to perform clock synchronization control on the multiplexer unit 200 , the analog-to-digital converter 500 , the digital filter device 600 , the storage unit 700 , and the N sensors 301 - 30N by means of the digital-to-analog converter 510 .

[0182] Figure 5 A schematic illustration of a fourth specific embodiment of an apparatus 100 for providing sensor data from sensors 301 - 30N of an optical system 4 , 10 of a lithographic apparatus 1 is shown. Figure 5The device 100 may be based on Figure 3 or Figure 4 For drawing reasons, the control lines for the multiplexer unit 200 and the analog-to-digital converter 500 are shown in FIG. Figure 5 is shown as from processor device 900. In addition to Figure 3 or based on Figure 4 In addition to the device 100, according to Figure 5 The device 100 comprises a signal analysis unit 920. The signal analysis unit 920 is configured to analyze the digital sensor signals D1-DN and / or the filtered digital sensor signals F1-FN of the digital signal sequence DF and to adapt at least one property of the digital filter device 600, in particular the filter coefficients of the digital filter device 600 and / or the sampling frequency of the analog-to-digital converter 500, accordingly.

[0183] Figure 6 A schematic illustration of a fifth specific embodiment of an apparatus 100 for providing sensor data from sensors 301 - 30N of an optical system 4 , 10 of a lithographic apparatus 1 is shown.

[0184] exist Figure 6 In the embodiment of the present invention, the device 100 comprises, for example, a vacuum housing 110 of an optical system 4. A plurality of sensors 301-30N and a multiplexer unit 200 are arranged in the vacuum housing 110. The sensors 301-30N comprise, for example, temperature measuring sensors, such as NTC sensors, photodiodes, or capacitors. In particular, the sensors 301-30N have in common that they provide analog sensor signals A1-AN on the output side. The multiplexer unit 200 is configured to receive analog sensor signals A1-AN from a plurality of N sensors 301-30N of the optical system 4, 10 via a plurality of N channels K1-KN, and to provide an analog signal sequence AF comprising N multiplexed analog sensor signals A1-AN on the output side via an electrical connection 410.

[0185] Here, preferably, the multiplexer unit 200 is configured as Nx1 multiplexer units, which are configured to receive N analog sensor signals A1-AN from N sensors 301-30N of the optical system 4, 10 via N channels K1-KN, and provide an analog signal sequence AF including N multiplexed analog sensor signals A1-AN on the output side via electrical connection 410.

[0186] also, Figure 6The device 100 comprises an analogue-to-digital converter 500, which is connected to the multiplexer unit 200 via an electrical connection 410. The analogue-to-digital converter 500 is configured to convert an analogue signal sequence AF provided by the multiplexer unit 200 into a digital signal sequence DF comprising N multiplexed digital sensor signals D1-DN.

[0187] Figure 6 The device 100 further comprises a processor device 900, which is in the form of a microprocessor, a DSP, or an FPGA, for example. The processor device 900 may also be referred to as a processing unit. Figure 6 The processor device 900 includes a digital filter device 600; a storage unit 700; a control unit 800; an interface or output interface 910; an address encoder 930; and a configuration unit 940, which is used to store and manage settings or configurations. In particular, the interface 910 is coupled to the storage unit 700, the control unit 800, and the configuration unit 940. It is of course possible for the processor device 900 to include more components, which are coupled to the interface 910. The address encoder 930 is coupled between the control unit 800 and the storage unit 700, so that the control unit 800 can access the storage unit 700 with the help of the address encoder 930.

[0188] The digital filter device 600 is connected to Figure 6 The digital filter device 600 is configured to filter the multiplexed digital sensor signals D1-DN of the digital signal sequence DF in a channel-specific manner for the N channels K1-KN in order to provide and store a respective filtered digital sensor signal F1-FN for each of the channels K1-KN. For this purpose, Figure 6 The digital filter device 600 includes a plurality of M delay units 630 connected in series. The delay properties of the delay units 630 are determined by -1 Example in Figure 6 The delay unit 630 is configured to receive a digital signal sequence DF including multiplexed digital sensor signals D1-DN. In this case, the delay unit 630 comprises a memory location 631-63N for each of the N channels K1-KN. Therefore, the individual delay units 630 are configured to store the digital sensor signals D1-DN in the corresponding allocated individual memory locations 631-63N in a channel-specific manner for the N channels K1-KN. Here, each of the N memory locations 631-63N is allocated exactly one of the channels K1-KN. In particular, this allocation of the memory locations 631-63N to the channels K1-K is bijective.

[0189] Figure 6The delay unit 630 is configured to shift the memory contents of its memory locations 631-63N to the memory locations 631-63N of the corresponding delay unit 630 connected downstream in a channel-specific manner for the N channels K1-KN according to the system clock.

[0190] Furthermore, a respective multiplier unit 640 is connected downstream of each of the M delay units 630. Each multiplier unit 640 is assigned a specific filter coefficient b1-b M Here, the delay unit 630 is configured to supply the memory content of a specific channel of the N channels K1-KN to the M multiplier units 640 according to the system clock. The M multiplier units 640 are configured to multiply the memory content supplied by the M delay units 630 by the specific filter coefficients b1-b M The adding unit 650, which may have a plurality of adding positions and is connected downstream of the M multiplier units 640, is configured to add the products of the multiplications provided by the M multiplier units 640 in order to provide the filtered digital sensor signal F1 of the specific channel K1. Figure 6 In the example of , channel K1 is a specific channel, and so the adding unit 650 provides the filtered digital sensor signal F1 of the channel K1 on the output side at this point in time. Then, this filtered digital sensor signal F1 is stored in the memory location 701 of the storage unit 700 assigned to the channel K1.

[0191] As in Figure 6 It is further shown in Figure 6 The control unit 800 is configured to perform clock synchronization control on the multiplexer unit 200, the analog-to-digital converter 500, the delay unit 630, and the storage unit 700.

[0192] Figure 7 A schematic illustration of a sixth specific embodiment of an apparatus 100 for providing sensor data from sensors 301 - 30N of an optical system 4 , 10 of a lithographic apparatus 1 is shown. Figure 7 The sixth specific embodiment is based on Figure 6 The fifth embodiment of and including all of its features. And, in addition, Figure 7 The device 100 additionally has a digital-to-analog converter 510 connected between the control unit 800 and the N sensors 301-30N. Here, the control unit 800 is configured to perform clock synchronization control on the multiplexer unit 200, the analog-to-digital converter 500, the delay unit 630, the storage unit 700, and the N sensors 301-30N by means of the digital-to-analog converter 510.

[0193] Figure 8A schematic diagram showing a specific embodiment of a method for providing sensor data from N sensors 301 - 30N of an optical system 4 , 10 of a lithographic apparatus 1 . Figure 8 The method can be used based on Figures 2 to 7 Any device 100. Figure 8 In the method, the method comprises steps S81 and S82:

[0194] In step S81, an analog signal sequence AF is provided via N channels K1-KN, which includes N analog sensor signals A1-AN from N sensors 301-30N of the optical system 4, 10, and is converted into a digital signal sequence DF, which includes N digital sensor signals D1-DN.

[0195] In step S82, the N digital sensor signals D1-DN of the digital signal sequence DF are filtered in a specific channel manner in order to provide and store individual filtered digital sensor signals F1-FN for each of the N channels K1-KN with the help of a digital filter device 600 connected downstream of the analog-to-digital converter 500, wherein the analog-to-digital converter 500 and the digital filter device 600 have the same frequency synchronized system clock.

[0196] Fig. 9 A schematic diagram showing a further specific embodiment of a method for providing sensor data from sensors 301 - 30N of an optical system 4 , 10 of a lithographic apparatus 1 . Fig. 9 The method can be used based on Figures 2 to 7 Any device 1. Fig. 9 In the method, the method comprises steps S91-S95:

[0197] In step S91 , a plurality of N analog sensor signals A1 -AN from a plurality of N sensors 301 - 30N of the optical system 4 , 10 are received via a plurality of N channels K1 -KN at the multiplexer unit 200 .

[0198] In step S92 , an analog signal sequence AF is provided by means of the multiplexer unit 200 , which analog signal sequence AF includes N multiplexed analog sensor signals A1 -AN.

[0199] In step S93 , the analog signal sequence AF is transmitted to the analog-to-digital converter 500 which is connected to the multiplexer unit 200 via the electrical connection 410 .

[0200] In step S94 , the analog signal sequence AF is converted into a digital signal sequence DF by means of the analog-to-digital converter 500 . The digital signal sequence DF includes N multiplexed digital sensor signals D1 -DN.

[0201] In step S95, the multiplexed digital sensor signals D1-DN of the digital signal sequence DF are filtered in a specific channel manner for the N channels K1-KN in order to provide and store individual filtered digital sensor signals F1-FN for each of the N channels K1-KN with the help of a digital filter device 600 connected downstream of the analog-to-digital converter 500.

[0202] Fig.10 A schematic diagram showing a specific embodiment of a method for designing an apparatus 100 for providing sensor data from sensors 301 - 30N of an optical system 4 , 10 of a lithographic apparatus 1 .

[0203] In particular, examples of such devices 100 are described above with reference to Figures 2 to 7 The device 100 comprises at least one analog-to-digital converter 500 for converting analog sensor signals A1-AN into digital sensor signals D1-DN; and a digital filter device 600 connected downstream of the analog-to-digital converter 500 for filtering the digital sensor signals D1-DN.

[0204] The digital sensor signal D1-DN contains the used signal bandwidth f N The interference signal component undersampled by the analog-to-digital converter 500 has an interference frequency f d and an interfering signal component having at least one specific aliasing frequency f caused by undersampling a .in this regard, Fig.11 The sampling frequency (f s = 100), 60 Hz interference frequency (f d = 60 Hz), and an associated aliasing frequency of 40 Hz (f a = 40 Hz). Fig.11 In the example, the signal bandwidth f N 2 Hz (f N = 2 Hz).

[0205] in accordance with Fig.10 The method comprises steps S101 and S102:

[0206] In step S101, the sampling frequency f of the analog-to-digital converter 500 is s is chosen so that the interference frequency f d and the aliasing frequency f a Located in the signal bandwidth f used N External, and the sampling frequency f sNot the interference frequency f d The divisor of .

[0207] In step S102, the sampling frequency f of the analog-to-digital converter 500 is s and the filter order M of the digital filter device 600 is selected so that the digital filter device 600 allows the used signal bandwidth f N The aliasing frequency f of the signal components within the range is passed and the aliasing frequency f of the interference signal components with insufficient sampling is suppressed. a .

[0208] For the example of a moving average filter as the digital filter device 600, the sampling frequency and the filter order of the analog-to-digital converter 500 may be selected so that the sampling frequency f s The quotient of the filter order corresponds to the aliasing frequency f a A divisor of and greater than the signal bandwidth f used N .

[0209] In particular, the digital filter device 600 is in the form of a notch filter. An exemplary frequency profile for such a notch filter is also illustrated in Fig.11 In. Based on Fig.11 The frequency distribution of the notch filter is shown in Figure 4. The aliasing frequency f is 40 Hz. a Filtered out, but with f N = 2 Hz signal was used without filtering.

[0210] In particular, based on Fig.11 The design method of the present invention is used to sample the under-sampled interference frequency f d . One or more interference frequencies f d and one or more aliasing frequencies f a Based on this, in particular, the design method of the present invention is used when the sampling rate of the analog-to-digital converter 500 is too low to sample the specific interference frequency f according to the Nyquist sampling theorem. d , in particular due to a very precise but slow analog-to-digital converter 500, and / or due to the necessary multiplexing of a plurality of signals from a plurality of channels K1-KN to be processed in parallel. d In the case of such undersampling, aliasing effects appear, thus interfering with the frequency f d The image appears in the low frequency band. This is called (as mentioned above) the image interference frequency or aliasing frequency f a .

[0211] According to the design method of the present invention, the sampling frequency f of the analog-to-digital converter 500 is sAnd the filter order M of the digital filter device 600 is selected so as to meet the following three conditions I, II, and III:

[0212] Condition I: Sampling frequency f of analog-to-digital converter 500 s is chosen so that at least one aliasing frequency f a The used signal bandwidth f of the digital sensor signal D1-DN N In addition, the sampling frequency f of the analog-to-digital converter 500 s is chosen so that it is larger than the used signal bandwidth f N twice as much.

[0213] Condition II: Sampling frequency f of the analog-to-digital converter 500 s is chosen so that the sampling frequency f s Not the interference frequency f d The divisor of .

[0214] Condition III: The digital filter device 600 has a signal bandwidth f that allows the use N The aliasing frequency f of the signal components within the range is passed and the aliasing frequency f of the interference signal components with insufficient sampling is suppressed. a low-pass behavior.

[0215] For the example of a moving average filter as the digital filter device 600, the condition III can be formulated using conditions IIIa and IIIb:

[0216] Condition IIIa: Sampling frequency f of analog-to-digital converter 500 s and the filter order m of the digital filter device 600 is selected so that the sampling frequency f s The quotient of the filter order M corresponds to the aliasing frequency f a The divisor of .

[0217] Condition IIIb: Sampling frequency f of analog-to-digital converter 500 s and the filter order M of the digital filter device 600 is selected so that the sampling frequency f s The quotient of the filter order m is greater than the signal bandwidth f used N .

[0218] The filter order m of the digital filter device 600 corresponds in particular to a plurality of M serially connected delay units 630 of the digital filter device (see in this respect Figure 6 ).

[0219] The device 100 designed using the design method of the present invention (the device 100 includes an analog-to-digital converter 500 and a digital filter device 600) is capable of filtering the under-sampled known interference frequency fd The aliasing frequency f a , without affecting the used signal bandwidth f of the used signal N .

[0220] Based on the above conditions I to III, the filter order M of the digital filter device 600 is as follows at a sampling frequency f of 100 Hz: s , the used signal bandwidth f is 2 Hz N , interference frequency f of 60 Hz d , and the aliasing frequency f of 40 Hz a The following is selected:

[0221] 1. Image interference frequency f of 40 Hz a The divisor of is 10.

[0222] 2. For divisor 10: f s / M = 10 → M = 10. The divisor 10 and the resulting filter order M = 10 meet all conditions I to III (IIIa and IIIb). Therefore, the filter order M = 10 is acceptable for the present example.

[0223] Fig.12 A schematic diagram showing a specific embodiment of a method for operating an apparatus 100 for providing sensor data from sensors 301 - 30N of an optical system 4 , 10 of a lithographic apparatus 1 .

[0224] In particular, based on Fig.12 The device 100 is operated according to Figures 3 to 5 According to the device 100 of one of Fig.12 The method includes controlling the analog-to-digital converter 500 and the digital filter device 600, and includes steps S121 and S122.

[0225] In step S121 , the analog-to-digital converter 500 is controlled such that it sequentially converts a series of sensor signal values ​​of the analog sensor signals A1 -AN from each of the N channels K1 -KN into digital sensor signals D1 -DN.

[0226] In step S122 , the digital filter device 600 is subsequently controlled such that it filters the digital sensor signals D1 -DN provided by the analog-to-digital converter 500 .

[0227] In particular, the digital filter device 600 averages the raw values ​​of the digital sensor signals D1-DN of the individual channels K1-KN over a period of an integer number of known cycles of the interference signal component in order to provide the digital sensor signals F1-FN. dThis averaging can be used to filter out aliased frequencies of interfering frequencies that occur due to undersampling.

[0228] Although the invention has been described with reference to exemplary embodiments, it can be modified in various ways.

[0229] Reference numerals list

[0230] 1Projection exposure device

[0231] 2 Lighting System

[0232] 3 Light Source

[0233] 4 Illumination optical unit

[0234] 5. Physical Field

[0235] 6 Object Plane

[0236] 7. Mask Master

[0237] 8 Mask Master Holder

[0238] 9Mask displacement driver

[0239] 10 Projection optics unit

[0240] 11 Image Field

[0241] 12 Image plane

[0242] 13 Chip

[0243] 14 Wafer Holder

[0244] 15 Chip displacement driver

[0245] 16 Lighting Radiation

[0246] 17 Collector

[0247] 18 Intermediate focal plane

[0248] 19 Deflecting mirror

[0249] 20 First Facet Mirror

[0250] 21 First facet

[0251] 22 Second facet mirror

[0252] 23 Second facet

[0253] 100 devices

[0254] 110 Vacuum housing

[0255] 200 multiplexer units

[0256] 301-30N sensor

[0257] 410 electrical connection

[0258] 420 interface

[0259] 500 analog-to-digital converter

[0260] 510 Digital to Analog Converter

[0261] 600 digital filter devices

[0262] 611-61N Digital Filter

[0263] 620 Demultiplexer Unit

[0264] 630 Delay Unit

[0265] 631-63N memory location

[0266] 640 multiplier units

[0267] 650 Addition Unit

[0268] 700 storage units

[0269] 701-70N memory location

[0270] 800 control unit

[0271] 900 processor devices

[0272] 910 interface

[0273] 920 Signal Analysis Unit

[0274] 930 address encoder

[0275] 940 Hive

[0276] AF analog signal sequence

[0277] A1-AN Analog sensor signal

[0278] b1-b M Filter coefficients

[0279] K1-KN Channel

[0280] D1-DN digital sensor signal

[0281] DF digital signal sequence

[0282] fFrequency

[0283] f a Aliasing frequency

[0284] fd Interference frequency

[0285] f s Sampling frequency

[0286] f N Signal bandwidth used

[0287] F1-FN Filtered digital sensor signal

[0288] M1 Reflector

[0289] M2 Reflector

[0290] M3 Reflector

[0291] M4 Reflector

[0292] M5 Reflector

[0293] M6 Reflector

[0294] S81-S82 Method Steps

[0295] S91-S95 Method Steps

[0296] S101-S102 Method Steps

[0297] S121-S122 Method Steps

Claims

1. An apparatus (100) for providing sensor data from N sensors (301-30N) of an optical system (4, 10) of a lithographic apparatus (1), wherein N ≥ 1, the apparatus comprising: an analog-to-digital converter (500) configured to convert an analog signal sequence (AF) provided via N channels (K1-KN) into a digital signal sequence (DF), the analog signal sequence (AF) comprising N analog sensor signals (A1-AN) from the N sensors (301-30N) of the optical system (4, 10), and the digital signal sequence (DF) comprising N digital sensor signals (D1-DN); a digital filter device (600) connected downstream of the analog-to-digital converter (500), wherein the analog-to-digital converter (500) and the digital filter device (600) have the same frequency synchronized system clock, and the digital filter device (600) is configured to filter the N digital sensor signals (D1-DN) of the digital signal sequence (DF) in a channel-specific manner in order to provide and store a respective filtered digital sensor signal (F1-FN) for each of the N channels (K1-KN); and A multiplexer unit (200) is configured to receive a plurality of N analog sensor signals (A1-AN) from a plurality of N sensors (301-30N) of the optical system (4, 10) via a plurality of N channels (K1-KN), wherein N ≥ 2, and to provide an analog signal sequence (AF) on the output side to the analog-to-digital converter (500), the analog signal sequence (AF) comprising the N multiplexed analog sensor signals (A1-AN).

2. The device of claim 1, further comprising: A control unit (800) is configured to perform clock synchronization control on the analog-to-digital converter (500) and the digital filter device (600) by means of the frequency synchronization system clock.

3. The device as claimed in claim 1, The digital filter device (600) comprises: a plurality of N digital filters (611-61N), wherein each of the N digital filters (611-61N) is assigned exactly one of the N channels (K1-KN); and A demultiplexer unit (620) is connected between the analog-to-digital converter (500) and the N digital filters (611-61N) and is configured to demultiplex the multiplexed digital sensor signals (D1-DN) of the digital signal sequence (DF) to the N digital filters (611-61N) in a specific channel manner for the N channels (K1-KN).

4. The device of claim 3, further comprising: A storage unit (700) having N memory locations (701-70N) and connected downstream of the N digital filters (611-61N), wherein each of the N memory locations (701-70N) is assigned exactly one of the N channels (K1-KN), wherein a respective memory location (701-70N) is configured to store a respective filtered digital sensor signal (F1-FN) of a respective one of the N channels (K1-KN).

5. The device according to any one of claims 1 to 4, further comprising: A digital-to-analog converter (510) is connected between the control unit (800) and the N sensors (301-30N), wherein the control unit (800) is configured to perform clock synchronization control on the multiplexer unit (200), the analog-to-digital converter (500), the digital filter device (600), the storage unit (700), and / or the N sensors (301-30N) by means of the digital-to-analog converter (510).

6. The device according to any one of claims 1 to 3, The digital filter device (600) comprises: A plurality of M delay units (630) connected in series are used to receive the digital signal sequence (DF) including the digital sensor signal (D1-DN), wherein each of the delay units (630) has a memory location (631-63N) for each of the N channels (K1-KN), wherein each of the N memory locations (631-63N) is allocated exactly one of the N channels (K1-KN), and the delay unit (630) is configured to shift the memory content of its memory location (631-63N) to the memory location (631-63N) of the corresponding delay unit (630) connected downstream in a channel-specific manner for the N channels (K1-KN) according to a system clock.

7. The device as claimed in claim 6, wherein a corresponding multiplier unit (640) is connected downstream of each of the M delay units (630), wherein each multiplier unit (640) is assigned a specific filter coefficient (b1-b M ), wherein the delay unit (630) is configured to supply the memory content of a specific channel (K1) among the N channels (K1-KN) to the M multiplier units (640) according to the system clock, wherein the M multiplier units (640) are configured to multiply the memory content supplied by the M delay units (630) by the specific filter coefficient (b1-b M ), wherein the adding unit (650) connected downstream of the M multiplier units (640) is configured to add the products of the multiplications provided by the M multiplier units (640) in order to provide the filtered digital sensor signal (F1) of the specific channel (K1), A storage unit (700) having N memory locations (701-70N) is connected downstream of the adding unit (650), wherein each of the N memory locations (701-70N) is assigned exactly one of the N channels (K1-KN), wherein the corresponding memory location (701-70N) is configured to store a respective filtered digital sensor signal (F1) of a corresponding one of the N channels (K1-KN).

8. The device as claimed in claim 7, The control unit (800) is configured to perform clock synchronization control on the multiplexer unit (200), the analog-to-digital converter (500), the delay unit (630), and the storage unit (700) by means of the frequency synchronization system clock.

9. The apparatus of claim 8, further comprising: A digital-to-analog converter (510) is connected between the control unit (800) and the N sensors (301-30N), wherein the control unit (800) is configured to perform clock synchronization control on the multiplexer unit (200), the analog-to-digital converter (500), the delay unit (630), the storage unit (700), and the N sensors (301-30N) by means of the digital-to-analog converter (510) and the frequency synchronization system clock.

10. The device of claim 8 or claim 9, The digital filter device (600), the storage unit (700), and the control unit (800) are provided in a processor device (900), in particular, in a microprocessor, a digital signal processor, or an FPGA.

11. The device as claimed in claim 10, The processor device (900) further comprises a signal analysis unit (920) configured to analyze the digital sensor signal (D1-DN) of the digital signal sequence (DF) and / or the filtered digital sensor signal (F1-FN), and to adapt at least one property of the digital filter device (600), in particular the filter coefficients (b1-b2) of the digital filter device (600) accordingly. M ), and / or the sampling frequency of the analog-to-digital converter (500).

12. The device according to any one of claims 1 to 11, The N sensors (301-30N) and the multiplexer unit (200) are arranged in a vacuum housing (110) of the optical system (4, 10), and the analog-to-digital converter (500) and the digital filter device (600) are arranged outside the vacuum housing (110).

13. An optical system (4, 10) for a lithographic apparatus (1), comprising the apparatus (100) according to any one of claims 1 to 12.

14. A lithographic apparatus (1) comprising an optical system (4, 10) as claimed in claim 13.

15. A method for providing sensor data from N sensors (301-30N) of an optical system (4, 10) of a lithographic apparatus (1), wherein N ≥ 1, the method comprising Converting (S81) an analog signal sequence (AF) provided via N channels (K1-KN), the analog signal sequence (AF) comprising N analog sensor signals (A1-AN) from the N sensors (301-30N) of the optical system (4, 10) into a digital signal sequence (DF); and By means of a digital filter device (600) connected downstream of the analog-to-digital converter (500), wherein the analog-to-digital converter (500) and the digital filter device (600) have the same frequency synchronized system clock, filtering (S82) the N digital sensor signals (D1-DN) of the digital signal sequence (DF) in a channel-specific manner in order to provide and store a respective filtered digital sensor signal (F1-FN) for each of the N channels (K1-KN), A plurality of N analog sensor signals (A1-AN) from a plurality of N sensors (301-30N) of the optical system (4, 10) are received via a plurality of N channels (K1-KN) by means of a multiplexer unit (200), wherein N ≥ 2, and an analog signal sequence (AF) comprising the N multiplexed analog sensor signals (A1-AN) is provided to the analog-to-digital converter (500) on the output side of the multiplexer unit (200).

16. A design method for designing a device (100), the device comprising an analog-to-digital converter (500) for converting an analog sensor signal (A1-AN) into a digital sensor signal (D1-DN); and a digital filter device (600) connected downstream of the analog-to-digital converter (500) for filtering the digital sensor signal (D1-DN), comprising a signal bandwidth (f N ) and a known interference frequency (f ) in the analog sensor signal that is undersampled by the analog-to-digital converter (500) d ) of at least one determinable aliasing frequency (f a ), the design method includes: a) selecting (S101) a sampling frequency (f s ), so that at least one aliasing frequency (f a ) is located within the used signal bandwidth (f N ) external, and the sampling frequency (f s ) is not the interference frequency (f d ); and b) selecting ( S102 ) the sampling frequency (f s ) and the filter order of the digital filter device (600) with low-pass behavior, so that: the digital filter device (600) allows the used signal bandwidth (f N ) and suppress at least one aliasing frequency (f a ).

17. The design method according to claim 16, The digital filter device (600) is in the form of a notch filter.

18. The design method according to claim 16 or claim 17, The digital filter device (600) is in the form of a moving average filter in a FIR filter structure.

19. The design method according to any one of claims 16 to 18, A plurality of digital filter devices (600) are connected in series to improve the signal-to-noise ratio of the filtered digital sensor signals (F1-FN).

20. A device (100) comprising an analog-to-digital converter (500) for converting an analog sensor signal (A1-AN) into a digital sensor signal (D1-DN); and a digital filter device (600) connected downstream of the analog-to-digital converter (500) and having a low-pass behavior for filtering the digital sensor signal (D1-DN), the digital sensor signal (D1-DN) comprising a signal having a used signal bandwidth (f N ) and a known interference frequency (f ) in the analog sensor signal that is undersampled by the analog-to-digital converter (500) d ) of at least one determinable aliasing frequency (f a ) of the interference signal component, wherein the sampling frequency (f s ) and the filter order of the digital filter device (600) is selected so that the at least one aliasing frequency (f a ) is located within the used signal bandwidth (f N ) external, and the sampling frequency (f s ) is not the interference frequency (f d ), and the digital filter device (600) allows the used signal bandwidth (f N ) and suppress at least one aliasing frequency (f a ).

21. A method for operating an apparatus (100) as claimed in any one of claims 3 to 4, wherein the analog-to-digital converter (500) and the digital filter device (600) are controlled so that the analog-to-digital converter (500) sequentially converts (S121) a series of sensor signal values ​​of the analog sensor signal (A1-AN) from each of the N channels into a digital sensor signal (D1-DN), and the digital filter device (600) subsequently filters (S122) the digital sensor signal (D1-DN).

22. The method of claim 21, The digital filter device (600) averages the original values ​​of the digital sensor signals (D1-DN) of the individual channels (K1-KN) within a period of an integer known period of the interference signal component in order to provide the filtered digital sensor signals (F1-FN).

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