Gate trench power semiconductor device with trench shield pattern formed during well implantation and related methods

Abstract

A wide bandgap semiconductor layer structure is provided that includes a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide bandgap semiconductor layer structure. A second conductivity type dopant is implanted into the wide bandgap semiconductor layer structure to simultaneously form a well region below the source region and a trench shielding region below the trench, the well region and the trench shielding region each having the second conductivity type.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial No. 17 / 845,120 filed on June 21, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to power semiconductor devices, and more particularly, to power semiconductor devices having gate trenches and methods of manufacturing such devices. Background Art

[0004] Metal insulator semiconductor field effect transistor ("MISFET") is a well-known semiconductor transistor that can be used as a switching device. MISFET is a three-terminal device having a gate, drain and source terminals and a semiconductor body. The source region and the drain region are formed in the semiconductor body, separated by a channel region, and a gate electrode (which can act as a gate terminal or be electrically connected to the gate terminal) is disposed adjacent to the channel region. The MISFET can be turned on or off by setting the bias voltage applied to the gate electrode to be higher or lower than a threshold value. When the MISFET is turned on (i.e., in the "on state"), current is conducted through the channel region between the source region and the drain region of the MISFET. When the bias voltage drops below the threshold level, the current stops conducting through the channel region.

[0005] The n-type MISFET has an n-type source and drain region and a p-type channel. Therefore, the n-type MISFET has an "npn" design. When a gate bias voltage sufficient to create a conductive n-type inversion layer in the p-type channel region electrically connecting the n-type source region and the drain region is applied to the gate electrode, the n-type MISFET is turned on, thereby allowing majority carrier conduction therebetween. The p-type MISFET has a "pnp" design and is turned on when a gate bias voltage sufficient to create a conductive p-type inversion layer in the n-type channel region electrically connecting the p-type source and drain regions is applied to the gate electrode. In this article, the terms "first conductivity type" and "second conductivity type" are used to indicate n-type or p-type, where the first and second conductivity types are different. Therefore, if the first region of the device has the first conductivity type and the second region of the device has the second conductivity type, then this means that the first region has n-type conductivity and the second region has p-type conductivity, or the first region has p-type conductivity and the second region has n-type conductivity.

[0006] The gate electrode of the MISFET is separated from the channel region by a thin dielectric layer, which is called a gate dielectric layer. Typically, a power MISFET uses an oxide layer (such as a silicon oxide layer) to implement a thin gate dielectric layer. A power MISFET including an oxide gate dielectric layer is called a metal oxide semiconductor field effect transistor ("MOSFET"), and the gate dielectric layer is called a gate oxide layer. Since the oxide gate dielectric layer is almost always used due to its excellent properties, the discussion herein will focus on MOSFETs rather than MISFETs, but it should be understood that the techniques described herein according to embodiments of the present invention are equally applicable to devices having a gate dielectric layer formed of materials other than oxides.

[0007] Because the gate electrode of the MOSFET is insulated from the channel region by the gate oxide layer, a minimum gate current is required to maintain the MOSFET in the on state or to switch the MOSFET between the on state and the off state. Because the gate forms a capacitor with the channel region, the gate current remains small during switching. Therefore, only a minimum charging and discharging current is required during switching, thereby allowing a simpler gate drive circuit system and a faster switching speed. MOSFET can be a stand-alone device, or it can be combined with other circuit devices. For example, an insulated gate bipolar transistor ("IGBT") is a semiconductor device that includes both a MOSFET and a bipolar junction transistor ("BJT"), which combines the high impedance gate electrode of the MOSFET with the small on-state conduction loss that the BJT can provide. The IGBT can be implemented as, for example, a Darlington pair including a high voltage n-channel MOSFET at the input terminal and a BJT at the output terminal. The base current of the BJT is supplied through the channel of the MOSFET, thereby allowing a simplified external drive circuit (because the drive circuit only charges and discharges the gate electrode of the MOSFET).

[0008] In some applications, MOSFETs may need to carry large currents and / or be able to block high voltages. Such MOSFETs are often referred to as "power" MOSFETs. Power MOSFETs are often made of wide bandgap semiconductor materials (in this article, the term "wide bandgap semiconductor" covers any semiconductor with a bandgap of at least 1.4 eV), such as, for example, silicon carbide ("SiC"), which has a number of advantageous characteristics, such as high electric field breakdown strength, high electron mobility, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity.

[0009] Power semiconductor devices (such as power MOSFETs) can have a lateral structure or a vertical structure. In a device with a lateral structure, the terminals of the device (e.g., the drain, gate, and source terminals of a power MOSFET) are located on the same main surface (i.e., top or bottom) of a semiconductor layer structure. In contrast, in a device with a vertical structure, at least one terminal is provided on each main surface of the semiconductor layer structure (e.g., in a vertical MOSFET, the source can be located on the top surface of the semiconductor layer structure, and the drain can be located on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate, such as a growth substrate. In this article, the term "semiconductor layer structure" refers to a structure including one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0010] The semiconductor layer structure of a power semiconductor device generally includes an "active region" having one or more functional semiconductor devices with a junction (such as a pn junction). The active region acts as a main junction for blocking voltage during reverse bias operation and providing current flow during forward bias operation. The power semiconductor device may also have an edge termination in a termination region of the semiconductor layer structure adjacent to the active region. Typically, a plurality of power semiconductor devices are formed in / on a common semiconductor layer structure, and each power semiconductor device will generally have its own edge termination. After the semiconductor layer structure is fully processed, the resulting structure may be cut (dice) to separate the power semiconductor devices of the individual edge terminations. Each power semiconductor device may have a unit cell structure, wherein the active region of each power semiconductor device includes a plurality of separate "unit cell" devices, which are electrically connected in parallel and used together as a single power semiconductor device.

[0011] A vertical power semiconductor device including a MOSFET transistor can have a standard gate electrode design, where the gate electrode of the transistor is formed on top of a semiconductor layer structure, or, alternatively, the gate electrode can be buried in a trench within the semiconductor layer structure. A MOSFET with a buried gate electrode is often referred to as a gate trench MOSFET. In the case of a standard gate electrode design, the channel region of each unit cell transistor is horizontally disposed below the gate electrode. In contrast, in a gate trench MOSFET design, the channel is vertically disposed. A gate trench MOSFET can provide enhanced performance, but typically requires a more complex manufacturing process.

[0012] One failure mechanism of power MOSFETs is the so-called "breakdown" of the gate oxide layer. When the power MOSFET is in the conducting or "on" state, the gate oxide layer is subjected to high electric fields. The stress caused by these electric fields on the gate oxide layer creates defects in the oxide material, which accumulate over time. When the concentration of defects reaches a critical value, a so-called "percolation path" is generated through the gate oxide layer, which electrically connects the gate electrode to the source or drain region, thereby creating a short circuit that destroys the device. The "lifetime" of the gate oxide layer (i.e., how long the device can operate before breakdown occurs) is, among other things, a function of the magnitude of the electric field to which the gate oxide layer is subjected and the length of time for which the electric field is applied. FIG. 1 is a schematic diagram illustrating the relationship between the operating time until breakdown occurs ("gate oxide lifetime") and the level of the electric field applied to the gate oxide layer. This figure assumes that the same electric field is always applied (which is not necessarily the case) and that the gate oxide layer has a certain thickness. As shown in FIG. 1, when the gate oxide lifetime is plotted on a logarithmic scale, in some cases, the relationship can be generally linear. An important point to take away from Figure 1 is that the lifetime of the gate oxide decreases exponentially as the electric field level increases. The lifetime of the gate oxide can be increased by increasing the thickness of the gate oxide, but various performance parameters of the MOSFET can be a function of the thickness of the gate oxide, so increasing the thickness of the gate oxide is generally not an acceptable way to increase the lifetime of the gate oxide. Summary of the invention

[0013] According to some embodiments of the present invention, methods for manufacturing semiconductor devices are provided. According to these methods, a wide bandgap semiconductor layer structure is provided, the wide bandgap semiconductor layer structure including a drift region having a first conductivity type and a source region having the first conductivity type on the drift region, the wide bandgap semiconductor layer structure including a trench. A second conductivity type dopant is implanted into the wide bandgap semiconductor layer structure to simultaneously form a well region under the source region and a trench shielding region under the trench, the well region and the trench shielding region each having a second conductivity type.

[0014] In some embodiments, the trench may extend through the source region and into the drift region.

[0015] In some embodiments, the second conductivity type dopant may be implanted into the drift region through the source region.

[0016] In some embodiments, the well region may be formed by converting a portion of a drift region having a first conductivity type into a well region having a second conductivity type.

[0017] In some embodiments, a well region may separate the source region from the drift region.

[0018] In some embodiments, the source region may form upper portions of first and second sidewalls of the trench, and the drift region may form lower portions of the first and second sidewalls, wherein the first sidewall faces the second sidewall.

[0019] In some embodiments, when the second conductive type dopant is implanted into the wide bandgap semiconductor layer structure, the first sidewall of the trench may be exposed.

[0020] In some embodiments, the method may further include performing an oxidation process to convert at least first and second sidewalls and a bottom of the trench into an oxide material, and removing the oxide material to convert the trench into an enlarged trench.

[0021] In some embodiments, the wide bandgap semiconductor layer structure may extend in a length direction, a width direction, and a depth direction that are perpendicular to each other, and a lower surface of the wide bandgap semiconductor layer structure may extend in the length and width directions.

[0022] In some embodiments, the source region may extend a first distance in the depth direction, and the shield region may extend a second distance in the depth direction, wherein the second distance exceeds the first distance.

[0023] In some embodiments, the second distance may be at least 1.5 times or at least twice the first distance.

[0024] In some embodiments, a portion of the well region extending to the upper surface of the wide bandgap semiconductor layer structure may extend a third distance in the depth direction, and the third distance may be substantially the same as the second distance.

[0025] In some embodiments, the concentration of the second conductivity type dopant in the source region may be at least 5×10 15 / cm 3 .

[0026] In some embodiments, a doping profile of the second conductivity type dopant in a portion of the well region below the source region differs by less than 15% from a doping profile of the second conductivity type dopant in a lower portion of the shielding region extending longitudinally below the center of the trench bottom.

[0027] In some embodiments, the method may further include implanting additional second conductivity type dopants into the wide bandgap semiconductor layer structure below the trench.

[0028] In some embodiments, the second conductivity type dopant and the additional second conductivity type dopant may be implanted using the same ion implantation mask. In some embodiments, the additional second conductivity type dopant may be implanted before the second conductivity type dopant is implanted.

[0029] In some embodiments, the method may further include forming a mask on sidewalls of the trench before implanting the additional second conductivity type dopant into the wide bandgap semiconductor layer structure.

[0030] In some embodiments, when additional second conductivity type dopants are implanted into the wide bandgap semiconductor layer structure, an upper surface of the source region may be exposed.

[0031] In some embodiments, the method further comprises implanting additional second conductivity type dopants into the wide bandgap semiconductor layer structure below the trench. In some embodiments, the additional second conductivity type dopants may be implanted before performing an oxidation process to convert at least the first and second sidewalls and the bottom of the trench into an oxide material.

[0032] In some embodiments, when the second conductive type dopant is implanted into the wide bandgap semiconductor layer structure, the upper surface of the source region may be exposed.

[0033] In some embodiments, providing a wide bandgap semiconductor layer structure includes forming a drift region on an upper surface of a wide bandgap semiconductor substrate having a first conductivity type, implanting first conductivity type dopant ions into the upper surface of the drift region to form a source region having a higher first conductivity type dopant concentration than the drift region, and forming a trench in the upper surface of the wide bandgap semiconductor layer structure.

[0034] In some embodiments, the method may further include implanting a second conductivity type dopant into the semiconductor layer structure to form a first support shield and a second support shield in the semiconductor layer structure on respective first and second sides of the trench.

[0035] In some embodiments, the method may further include sequentially forming a gate oxide layer and a gate electrode in the trench.

[0036] In some embodiments, the method may further include forming a trench shield region connection region that electrically connects the trench shield region to the well region.

[0037] According to a further embodiment of the present invention, a semiconductor device including a wide bandgap semiconductor layer structure is provided, which wide bandgap semiconductor layer structure includes: a drift region having a first conductivity type; a well region having a second conductivity type located on the drift region; a source region having the first conductivity type located on the well region; a gate electrode located within a trench; and a shielding region having the second conductivity type located below the gate trench, wherein the doping distribution of the second conductivity type dopant in a portion of the well region located below the source region differs by less than 15% from the doping distribution of the second conductivity type dopant in a lower portion of the shielding region extending longitudinally below the center of the bottom of the trench.

[0038] In some embodiments, the well region may be located between the drift region and the source region, and the trench may extend through the source region and the well region and into the drift region.

[0039] In some embodiments, the semiconductor layer structure may extend in a length direction, a width direction, and a depth direction that are perpendicular to each other, and a lower surface of the semiconductor layer structure may extend in the length and width directions.

[0040] In some embodiments, the source region may extend a first distance in the depth direction, and the shield region may extend a second distance in the depth direction, wherein the second distance exceeds the first distance.

[0041] In some embodiments, the second distance may be at least 1.5 times or at least twice the first distance.

[0042] In some embodiments, the semiconductor device may also include a first support shield and a second support shield having a second conductivity type located in the wide bandgap semiconductor layer structure on the respective first and second sides of the trench, wherein the first support shield and the second support shield extend closer to the bottom surface of the wide bandgap semiconductor layer structure than the shielding area.

[0043] In some embodiments, a concentration of the second conductivity type dopant in the upper portion of the shielding region may exceed a concentration of the second conductivity type dopant in the source region.

[0044] In some embodiments, an average concentration of the second conductivity type dopant in the upper half of the shielding region may exceed an average concentration of the second conductivity type dopant in the lower half of the shielding region.

[0045] In some embodiments, the drift region, the well region, the source region, and the shield region include silicon carbide.

[0046] According to a further embodiment of the present invention, a semiconductor device including a wide bandgap semiconductor layer structure is provided, which wide bandgap semiconductor layer structure includes: a drift region having a first conductivity type; a well region having a second conductivity located on the drift region; a source region having the first conductivity type located on the well region; a gate electrode located within a trench; and a shielding region having the second conductivity type located below the trench, wherein the shielding region extends downward from the bottom of the trench to a first distance in the semiconductor layer structure, and the well region extends downward from the top surface of the semiconductor layer structure to a second distance in the semiconductor layer structure, wherein the first distance is within + / -10% of the second distance.

[0047] In some embodiments, the well region may be located between the drift region and the source region, and the trench may extend through the source region and the well region and into the drift region.

[0048] In some embodiments, the source region may extend from the top surface of the semiconductor layer structure down to a third distance into the semiconductor layer structure, and the first distance exceeds the third distance.

[0049] In some embodiments, the first distance is at least 1.5 times or at least twice the third distance.

[0050] In some embodiments, the semiconductor device may also include a first support shield and a second support shield having a second conductivity type located in the wide bandgap semiconductor layer structure on the respective first and second sides of the trench, wherein the first support shield and the second support shield extend closer to the bottom surface of the wide bandgap semiconductor layer structure than the shielding area.

[0051] In some embodiments, a concentration of the second conductivity type dopant in the upper portion of the shielding region may exceed a concentration of the second conductivity type dopant in the source region.

[0052] In some embodiments, the drift region, the well region, the source region, and the shield region may include silicon carbide. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIG. 1 is a diagram illustrating a relationship between an operation time until breakdown and an electric field level applied to a gate oxide layer of a power semiconductor device.

[0054] 2A-2G and 2I are schematic vertical cross-sectional views, and FIG. 2H is a schematic horizontal cross-sectional view, illustrating a method of manufacturing a conventional gate trench power MOSFET.

[0055] Figures 3A-3J and 3L are schematic vertical cross-sectional views, and Figure 3K is a schematic horizontal cross-sectional view illustrating a method of manufacturing a gate trench MOSFET according to an embodiment of the present invention.

[0056] Figure 4A and 4B It is a graphic Figures 3A-3L Schematic vertical cross-sectional view of a modified version of a gate trench MOSFET.

[0057] Figure 5 is a flow chart illustrating a method of manufacturing a gate trench semiconductor device according to an embodiment of the present invention.

[0058] Figure 6 is a schematic diagram illustrating how the change between two doping profiles can be determined. DETAILED DESCRIPTION

[0059] Power semiconductor devices based on vertical silicon carbide with gate trenches (such as vertical power MOSFETs and IGBTs) are attractive for many applications because of their inherently lower specific on-resistance, which results in more efficient operation of power switching operations. The gate trench vertical power device exhibits a lower specific resistance during on-state operation because the channel is formed in the sidewall of the gate trench. Moreover, the carrier mobility in the sidewall channel of the gate trench power device can be 2-4 times higher than the corresponding carrier mobility in the horizontal channel of the standard (i.e., non-gate trench) vertical power device. This increased channel mobility leads to an increased current concentration during on-state operation, thereby allowing higher switching speeds. In addition, the trench design reduces the overall pitch of the device, thereby allowing for increased integration. Lower conduction losses (due to reduced on-state resistance) and improved switching speeds make gate trench power devices very suitable for high-frequency power applications with low to medium voltage blocking requirements (e.g., 600-1200 volts). These devices can have reduced requirements for associated passive components, low cost, light weight, and require relatively simple cooling solutions. Since MOSFET is the most widely used silicon carbide based trench power semiconductor gate device, the following discussion focuses on MOSFET embodiments. However, it should be appreciated that each of the embodiments described can alternatively be implemented using a non-oxide gate dielectric layer (e.g., nitride, high dielectric constant material, etc.), and the same techniques can be used to form other gate trench power semiconductor devices, such as IGBTs, gate-controlled thyristors, etc.

[0060] Gate trench power MOSFETs are susceptible to oxide reliability issues due to the presence of high electric fields in the gate oxide layer arranged at the bottom and sidewalls of the gate trench. Over time, the high electric fields degrade the gate oxide layer and can eventually cause device failure. The highest electric fields occur in the corner regions of the gate oxide layer, where the electric field crowding effect can significantly increase the electric field level in the gate oxide layer. When the gate trench MOSFET is operated in reverse blocking operation (i.e., when the MOSFET is in its off state), the source terminal of the MOSFET is typically grounded, the gate terminal is typically grounded or at a negative bias voltage, and the drain terminal is typically at a high positive voltage. Under this reverse blocking operation, the high electric field extends upward from the drain terminal (located on the bottom surface of the semiconductor layer structure) to the top surface of the semiconductor layer structure. Therefore, under reverse blocking operation, the bottom portion of the gate dielectric layer experiences the highest electric field level. Due to the electric field crowding effect, the electric field level at the lower corner of the gate oxide layer at the bottom edge of the gate trench can be particularly high. Moreover, due to the difference in dielectric constant between silicon carbide and silicon oxide, the electric field in the silicon oxide gate dielectric layer can be about 2.6 times higher than the electric field in the adjacent silicon carbide. When the electric field reaches a critical level Ecr, the silicon oxide breaks down. Therefore, during reverse blocking operation, the MOSFET can be operated with the drain voltage at a lower level to ensure that the electric field does not reach a level that will cause breakdown.

[0061] So-called "trench shielding regions" are often provided below the gate trench of conventional gate trench power MOSFETs to reduce the electric field level in the gate oxide layer during reverse blocking operation. These trench shielding regions include a highly doped semiconductor layer having the same conductivity type as the channel region of the device. The trench shielding region can, for example, extend downward from the bottom surface of the gate trench by 0.5 to 1.0 microns or more into the semiconductor layer structure of the device. The protection provided by these trench shielding regions for the gate oxide layer increases as the depth of the trench shielding region increases. The trench shielding region can also extend laterally farther than the sidewall of the trench and / or can extend along the lower side of the trench in some cases. The trench shielding region is electrically connected to the source terminal of the MOSFET through the trench shielding region connection pattern. The trench shielding region is usually formed into the bottom surface of the gate trench via an ion implantation process. However, if the channel region in the sidewall of the gate trench is not masked during this ion implantation process, the doping concentration of the channel region will be negatively affected by the implantation process, thereby reducing device performance. As will be discussed below, according to embodiments of the present invention, the same implant may be used to form both the channel region and the trench shield region, which allows for forgoing any masking steps (which increase manufacturing costs) while also allowing for deeper trench shield regions.

[0062] 2A-2G and 2I are schematic vertical cross-sectional views illustrating a method of manufacturing a conventional silicon carbide-based gate trench vertical power MOSFET 1. FIG. 2H is a schematic horizontal cross-sectional view of a gate trench vertical power MOSFET 1. In this article, a vertical cross-sectional view of a power semiconductor device refers to a view of a cross section taken through the device along a plane perpendicular to the main surface of the semiconductor layer structure of the device. Similarly, a horizontal cross-sectional view of a power semiconductor device refers to a cross-sectional view taken through the device along a plane parallel to the main surface of the semiconductor layer structure of the device.

[0063] As shown in FIG2A, in the heavily doped (n + )n-type silicon carbide substrate 10 is formed by epitaxial growth of lightly doped (n - ) silicon carbide drift region 20. A moderately doped (p) p-type silicon carbide well layer 30 is formed on the upper surface of the n-type drift region 20 either by epitaxial growth or more commonly by implanting p-type dopant ions into the upper portion of the n-type drift region 20.

[0064] 2B, a heavily doped n-type silicon carbide well layer is formed in the upper portion of the p-type silicon carbide well layer 30 by, for example, ion implantation. + Silicon carbide source layer 40. The silicon carbide substrate 10, the drift region 20, the well layer 30, and the source layer 40 together with various regions formed therein constitute a semiconductor layer structure 50 of the power MOSFET 1.

[0065] 2C, by implanting p-type dopant ions into the semiconductor layer structure 50 to form a heavily doped p + Silicon carbide trench support shield 60. In order to form the trench support shield 60, an ion implantation mask 62 is formed on the upper surface of the semiconductor layer structure 50. As shown in FIG. 2C, the ion implantation mask 62 is patterned to form an opening above the region where the trench support shield 60 is to be formed in the semiconductor layer structure 50. The trench support shield 60 is then formed by ion implantation, and the ion implantation mask 62 is subsequently removed. The trench support shield 60 can extend between 0.5 and 10 microns in the semiconductor layer structure 50 in the depth direction (z direction). The trench support shield 60 can alternatively be formed before forming the source layer 40. The trench support shield 60 helps to reduce the electric field level in the gate oxide layer (described below) of the MOSFET 1, which helps to prevent premature breakdown of the gate oxide layer. If the MOSFET undergoes avalanche breakdown, the trench support shield 60 also provides a low resistance current path between the source and drain terminals of the MOSFET 1. This low resistance current path helps reduce device heating during an avalanche breakdown event, thereby increasing the likelihood that the MOSFET will survive such an event without damage.

[0066] Referring to FIG. 2D , an etching process may then be performed to form a plurality of gate trenches 70 in the upper surface of the semiconductor layer structure 50. Each gate trench 70 may extend laterally in a first direction (i.e., parallel to the main surface of the semiconductor layer structure 50), spanning the length (or width) of the power MOSFET 1. In FIGS. 2A-2G and 2I , the first direction is into the page and is indicated as the x-direction. The gate trenches 70 may extend vertically through the source layer 40 and the well layer 30 in a third direction (i.e., perpendicular to the main surface of the semiconductor layer structure, indicated as the z-direction), and into the drift region 20, as shown, and the gate trenches 70 may be spaced apart from each other in a second direction (here, the y-direction, which is perpendicular to the first and third directions). The gate trenches 70 convert the medium-doped p-type silicon carbide well layer 30 into a plurality of medium-doped p-wells 32, and convert the heavily doped n-type silicon carbide source layer 40 into a plurality of heavily doped n-type source regions 42. The portion of each p-well 32 adjacent to the gate trench 70 serves as a transistor channel 34 , as will be discussed below.

[0067] 2E , spacers 78 such as oxide spacers are formed on the sidewalls of the gate trenches 70. The spacers 78 may be formed by thermal oxidation of silicon carbide or by depositing oxide followed by blanket etching (which will remove the oxide at the top surface of the semiconductor layer structure and the bottom of the trench while leaving most of the oxide spacers because horizontal surfaces will be etched faster than vertical surfaces). Then, a heavily doped (p-type) semiconductor layer structure 50 is formed in each gate trench 70 by ion implantation by blanket implanting p-type ions into the upper surface of the semiconductor layer structure 50. + ) p-type silicon carbide trench shielding region 80. Typically, the sidewalls of the gate trenches 70 will not be completely vertical, so the upper portion of each gate trench 70 is slightly wider than its lower portion. For example, the sidewalls can be at an angle of 95-105° or more relative to the bottom surface of the trench. Therefore, if the spacer 78 is not formed, some of the p-type ions will be directly injected into the sidewalls of the gate trenches 70. Additional p-type ions can be scattered from the bottom surface of the gate trenches 70, and some of these ions will also be injected into the sidewalls of the gate trenches 70. The spacer 78 can substantially prevent p-type ions from being injected into the sidewalls of the gate trenches 70, thereby preventing the p-type ions injected to form the trench shielding region 80 from changing the doping concentration of the channel region 34 and / or converting the lower portion of the sidewalls (which is part of the n-type drift region 20) into p-type material.

[0068] Since the upper surface of the semiconductor layer structure 50 is exposed, a relatively low ion implantation energy is used in the ion implantation step for forming the trench shielding region 80, so that the p-type dopant is implanted only to a distance in the depth direction (z direction) that is less than or equal to the depth of the source region 42 from the top surface of the semiconductor layer structure 50. This ensures that the implantation step for forming the trench shielding region 80 does not significantly change the doping concentration of the well region 32. The trench shielding region 80 may extend the entire length of the corresponding gate trench 70 (e.g., along the x direction).

[0069] 2F , the sidewall spacers 78 may then be removed using an oxide etch.

[0070] Referring to FIG. 2G , a gate insulating layer 72 is formed on the bottom surface and sidewalls of each gate trench 70. Typically, the gate insulating layer 72 is an oxide layer and will therefore be referred to herein as a gate oxide layer 72. A gate electrode 74 is formed on each gate oxide layer 72 to fill the corresponding gate trench 70. An intermetallic dielectric layer 76 is formed on the exposed portion of the gate electrode 74, and a source contact 90 is formed on the upper portion of the device. The source contact 90 is physically and electrically connected to the n-type source region 42. The p-well extension 36 physically and electrically connects the p-well 32 to the source contact 90 in selected areas of the device (see the plan view of FIG. 2H ), which are not visible in the cross-section of FIG. 2G . The source contact 90 may include a source terminal of the MOSFET 1, or may be electrically connected to the source terminal. A drain contact 92 is formed on the lower surface of the substrate 10. A gate contact (not shown) is also provided that is connected to the gate electrode 74 outside of the cross-sectional view of FIG. 2D , typically via one or more gate busses (not shown).

[0071] FIG2H is a horizontal cross-sectional view of the device shown in FIG2G taken along line 2H-2H (i.e., the cross-section is taken along the top surface of the semiconductor layer structure 50). FIG2H shows how the p-well extension 36 includes a series of islands that extend upward through the source region 42 to the upper surface of the semiconductor layer structure 50. FIG2I is a vertical cross-sectional view taken along line 2I-2I of FIG2H, which illustrates the p-well extension 36 and the trench shielding area connection pattern 38 that electrically connects the trench shielding area 80 shown to the p-well extension 36. The trench shielding area connection pattern 38 and the p-well extension 36 can be highly doped (p + )p-type region.

[0072] Trench shielding region 80 helps protect the corners of gate oxide layer 72 from high electric fields during reverse blocking operation. However, the conventional process for manufacturing power MOSFET 1 described above has at least two potential disadvantages.

[0073] First, the doping concentration in the channel region 34 of the silicon carbide power MOSFET 1 is usually very carefully controlled to ensure optimal device performance. Therefore, steps are usually taken to ensure that the ion implantation step performed to form the trench shielding region 80 does not change the doping concentration of the channel region 34. In some cases, this can be achieved by forming an ion implantation mask (which prevents p-type dopant ions from reaching the n-type source region 42) above the source region 42 during the ion implantation step for forming the trench shielding region 80. However, forming and removing this ion implantation mask increases the time and cost of manufacturing the device. As described above, in other cases, the masking step can be omitted, but instead the trench shielding region 80 can be formed to extend in the depth direction by a distance less than the depth of the source region 42 (which also ensures that the doping concentration of the channel region 34 does not increase). However, the shallow trench shielding region 80 formed when the ion implantation mask is not used provides less protection to the gate oxide layer 72 during the reverse blocking operation, so when such a shallow trench shielding region 80 is used, the reliability of the MOSFET 1 is affected. Although the support shielding regions 60 can improve the protection level (thereby improving reliability), the formation of these support shielding regions 60 requires additional processing steps, which increases manufacturing time and cost, and still cannot provide the same protection level as that provided by the deep trench shielding region. The increase of the support shielding regions 60 will also reduce the integration density of the MOSFET 1.

[0074] Second, as described above, in order to prevent p-type ions from being implanted into the sidewalls of the gate trenches 70 during the ion implantation process used to form the trench shielding regions 80, spacers 78 are formed on the sidewalls of the gate trenches 70. Forming these spacers 78 requires additional processing steps because the spacer material must either be selectively deposited on the sidewalls, or blanket deposited and then selectively removed from areas other than the sidewalls of the gate trenches 70. These additional steps increase processing time and cost.

[0075] According to an embodiment of the present invention, an improved technique for forming a trench shielding region in a gate trench power semiconductor device is disclosed. In particular, the trench shielding region can be formed at least partially during an ion implantation process for forming a well region, and can be formed before forming any source layer / region. In other words, the trench shielding region and the p-well can be formed simultaneously by a single ion implantation process. Since the p-well is generally a relatively deep structure, the process according to an embodiment of the present invention allows the formation of a relatively deep trench shielding region. In some embodiments, the source layer is doped with a first conductive dopant, and the doping degree is significantly heavier than the well region and the trench shielding region, so that the second (opposite) conductive type dopant injected into the source layer during the ion implantation step for forming the well region and the trench shielding region does not have a substantial effect on the doping concentration of the source layer. In other embodiments, the source layer can be doped heavier than desired, so that there is an additional first conductive type dopant to offset the second (opposite) conductive type dopant injected into the source layer during the ion implantation step for forming the well region and the trench shielding region.

[0076] Since the ion implantation step is used to form the well region and the trench shielding region, there is no need to mask the semiconductor layer structure during the ion implantation step, while still having the ability to form a deeper trench shielding region. Moreover, since the trench shielding region can extend to a deeper position in the semiconductor layer structure below the gate trench, in some embodiments, the ion implantation step for forming the well region and the trench shielding region can be performed without forming a spacer on the sidewall of the gate trench. Alternatively, the ion implantation can be performed with the sidewall of the gate trench exposed, and then the device can be subjected to an oxidation step of oxidizing its exposed surface (thereby oxidizing the portion of the sidewall that was inadvertently implanted during the ion implantation step), and then the oxide formed by this process can be removed using oxide etching. Although this oxide etching will reduce the distance that each trench shielding pattern extends in the depth direction (because the upper portion of the trench shielding pattern will be oxidized and then removed), this reduction is acceptable because these regions can initially be formed to extend farther in the depth direction. Therefore, the above-mentioned technology for manufacturing the trench shielding region can greatly simplify the device manufacturing process.

[0077] According to some embodiments of the present invention, a method for manufacturing a semiconductor device (such as a power semiconductor device) is provided. According to these methods, a wide bandgap semiconductor layer structure is provided, the structure including a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of grooves are provided in the upper surface of the wide bandgap semiconductor layer structure. The grooves may extend through the source region and into the drift region. A second conductivity type dopant is injected into the wide bandgap semiconductor layer structure to simultaneously form a well region below the source region and a trench shielding region below the trench, the well region and the trench shielding region each having a second conductivity type.

[0078] A second conductivity type dopant can be injected into the drift region through the source region so as to convert a portion of the drift region having the first conductivity type into a well region having the second conductivity type. In some cases, when the second conductivity type dopant is injected into the wide bandgap semiconductor layer structure, the sidewalls of the trench can be exposed. In such embodiments, an oxidation process can be performed after forming the well region and the trench shielding region to convert the sidewalls and bottom of the trench into an oxide material. The oxide material can then be removed to convert the trench into an enlarged trench. This oxidation and removal process can be used to eliminate portions of the sidewalls of the trench that were inadvertently injected during the formation of the well region and the trench shielding region.

[0079] In some embodiments, the source region may extend a first distance in the depth direction, and the shielding region may extend a second distance in the depth direction, wherein the second distance is greater than the first distance. For example, the second distance may be at least 1.5 times the first distance, or at least two times or even three times the first distance. In some embodiments, the portion of the well region extending to the upper surface of the wide bandgap semiconductor layer structure extends a third distance in the depth direction, and the third distance may be substantially the same as the second distance.

[0080] In some embodiments, a doping profile of a lower portion of the trench shield region taken along a first axis extending through the center of the bottom of the gate trench in the depth direction differs by less than 15% from a doping profile of the well region taken along a second axis parallel to the first axis and extending through the well region.

[0081] According to a further embodiment of the present invention, there is provided a semiconductor device including a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, a source region including the first conductivity type on the well region, a gate electrode structure in a trench, and a shielding region including the second conductivity type below the gate trench. In some embodiments, the shielding region extends downward from the bottom of the trench to a first distance in the semiconductor layer structure, and the well region extends downward from the top surface of the semiconductor layer structure to a second distance in the semiconductor layer structure, wherein the first distance is within + / -10% of the second distance (or within + / -5% of the second distance in other embodiments). In other embodiments, the doping distribution of the second conductivity type dopant in the portion of the well region below the source region differs by less than 15% from the doping distribution of the second conductivity type dopant in the lower portion of the shielding region extending longitudinally below the center of the bottom of the trench.

[0082] Now refer to Figure 3A-5 Embodiments of the present invention are described in more detail. It should be appreciated that the features of the different embodiments disclosed herein can be combined in any manner to provide many additional embodiments. Therefore, it should be appreciated that various features of the present invention are described below with respect to specific examples, but these features can be added to other embodiments and / or used to replace the example features of other embodiments to provide many additional embodiments. Therefore, the present invention should be understood to cover these different combinations. In addition, although the example embodiments focus on MOSFET implementations, it should be appreciated that the same technology can be used in other gate trench power semiconductor devices, such as insulated gate bipolar transistors (IGBTs), gate-controlled thyristors, etc.

[0083] Figures 3A-3L 1 is a schematic cross-sectional view illustrating a gate trench power MOSFET 100 according to an embodiment of the present invention. More specifically, Figures 3A-3I is a schematic vertical cross-sectional view illustrating a method of manufacturing a semiconductor layer structure of a gate trench power MOSFET 100 . Figure 3K is a schematic horizontal cross-sectional view of MOSFET 100 after metallization is added, Figure 3J and Figure 3L Along the Figure 3K Schematic vertical cross-sectional views taken along lines 3J-3J and 3L-3L.

[0084] refer to Figure 3A, providing an n-type silicon carbide substrate 110. The substrate 110 may include, for example, a 4H-silicon carbide or 6H-silicon carbide substrate. In other embodiments, the substrate 110 may be or include a different semiconductor material (e.g., a III-nitride-based material, silicon, gallium arsenide, zinc oxide, etc.) or a non-semiconductor material (e.g., sapphire). The substrate 110 may be heavily doped (n + ) has n-type impurities (i.e., n + The impurities may include, for example, nitrogen or phosphorus. The doping concentration of the substrate 110 may be, for example, 1×10 18 Atom / cm 3 and 1x10 21 Atom / cm 3 , but other doping concentrations may be used. In some embodiments, substrate 110 may be relatively thick (e.g., 20-100 microns or more). It should be noted that although the substrate is shown as a relatively thin layer in the figures, this is done to allow for the thickness of other layers and regions in the figures to be expanded, and it should be appreciated that the substrate is typically much thicker than shown. The thickness of various other layers of the MOSFET according to embodiments of the present invention may also not be shown to scale in order to allow for other parts of the device to be magnified in the figures.

[0085] Lightly doped (n - ) The silicon carbide drift region 120 may be provided on the substrate 110. The n-type drift region 120 may be formed on the substrate 110 by, for example, epitaxial growth. The n-type drift region 120 may have, for example, 5×10 15 Up to 5x10 17 Dopant / cm 3 The n-type drift region 120 may be a thick region having a vertical height of, for example, 3-50 microns above the substrate 110. In some embodiments, an upper portion of the n-type drift region 120 may include an n-type current diffusion layer (not shown) that is more heavily doped than a lower portion of the n-type drift region 120.

[0086] Heavily doped (n + )n-type silicon carbide source layer 140 is formed on the lightly doped (n - ) in the upper region of the silicon carbide drift region 120. The heavily doped n-type silicon carbide source layer 140 is typically formed via ion implantation, as this provides a more consistent doping concentration, but may alternatively be formed by epitaxial growth on the silicon carbide drift region 120. The doping concentration of the heavily doped n-type silicon carbide source layer 140 may be, for example, between 1×10 19 Atom / cm 3 Up to 5×10 21 Atom / cm 3The silicon carbide substrate 110 , the drift region 120 , and the source layer 140 , together with various regions / patterns formed therein (such as a well region and various shielding regions (discussed below)), constitute a semiconductor layer structure 150 of the power MOSFET 100 .

[0087] refer to Figure 3B , a mask 162 is formed on the upper surface of the source layer 140. The mask 162 is patterned to form an opening that exposes a selected portion of the semiconductor layer structure 150. Then, an ion implantation process is performed to implant a p-type dopant into the exposed portion of the semiconductor layer structure 150 to form a trench support shield 160. The trench support shield 160 is a p-type region. The trench support shield 160 may have a thickness of approximately 1×10 20 The maximum doping concentration of the semiconductor layer structure 150 can be extended to a depth of between 0.5 and 10 microns from the upper surface of the semiconductor layer structure 150. If the trench support shield 160 is not provided, it is usually necessary to significantly increase the doping concentration of the trench shielding region formed in subsequent processing steps, and even if the doping concentration is increased, the electric field on the gate oxide layer (discussed below) of the device will be higher. After the trench support shield 160 is formed, the ion implantation mask 162 is removed.

[0088] refer to Figure 3C , a plurality of gate trenches 170 are formed in the upper surface of the semiconductor layer structure 150 by etching. Figure 3C Only one complete gate trench 170 and a portion of a second gate trench 170 are shown in the figure, but it should be appreciated that a large number of gate trenches 170 are generally provided, wherein each gate trench 170 extends in a first direction above the substrate 110 (here the gate trench 170 extends in the x-direction), and the gate trenches 170 are spaced apart from each other in a second direction (here the y-direction) so that the gate trenches 170 extend longitudinally parallel to each other. Each gate trench 170 has a length (corresponding to the distance in the x-direction), a width (corresponding to the distance in the y-direction), and a depth (corresponding to the distance in the z-direction). The length direction is the longest direction, so the longitudinal axis of each gate trench 170 refers to the axis extending downward along the middle of the gate trench 170 in the length direction. Each gate trench 170 has first and second opposing sidewalls and a bottom surface, each of which extends in the x-direction and therefore extends parallel to the longitudinal axis.

[0089] Although Figure 3CA device having multiple gate trenches is illustrated, all of which extend parallel to each other in a first direction, but it should be appreciated that embodiments of the present invention are not limited thereto. Power MOSFETs with various gate trench designs are known in the art. For example, some power MOSFETs have both a first set of gate trenches extending through a semiconductor layer structure in a first direction and a second set of gate trenches extending through a semiconductor layer structure in a second (usually vertical) direction, such that the trenches in the two groups intersect with each other. As another example, some MOSFETs have gate trenches formed as rectangles, hexagons, octagons, or circles (when viewed from above), wherein the trenches surround a well region (wherein a source region is present). It should be appreciated that the techniques disclosed herein can be used on MOSFETs with any gate trench design, including the example additional designs discussed above.

[0090] Each gate trench 170 extends through the heavily doped n-type silicon carbide layer 140 in the z-direction (depth direction) to convert the source layer 140 into a plurality of spaced-apart heavily doped n-type silicon carbide regions 142 that serve as source regions of the power MOSFET 100. Each gate trench 170 also extends into the upper surface of the n-type drift region 120. The sidewalls of each gate trench 170 are exposed surfaces of the layers / regions of the semiconductor layer structure 150 that are located on either side of each gate trench 170.

[0091] refer to Figure 3D, an ion implantation process is performed to implant p-type dopant ions into the semiconductor layer structure 150. This ion implantation step can be performed without an ion implantation mask. The p-type dopant is implanted and passes through the heavily doped n-type source region 142 and is implanted into the drift region 120 below to form a plurality of p-wells 132 in the upper portion of the drift region 120 below the source region 142. The portion of each p-well 132 adjacent to the gate trench 170 acts as a transistor channel 134, as will be discussed below. The p-type dopant is also implanted into the portion of the drift region 120 located below the bottom surface of the gate trench 170 to form a plurality of trench shielding regions 180 extending below the corresponding gate trenches 170. This ion implantation step is performed using a higher ion implantation energy than in the conventional process described above with reference to FIG. 2E because the p-type dopant is implanted through the n-type source region 142 to form the p-well 132 below it. Thus, the trench shielding region 180 can be formed to extend deeper into the semiconductor layer structure 150 than the trench shielding region 80 formed in the conventional process described above. Note that, herein, the distance that a layer or region of a semiconductor layer structure extends in the depth direction refers to how far the layer or region extends in a direction perpendicular to the main surface of the semiconductor layer structure (i.e., how far the layer region extends in the vertical or "z" direction). The bottom of a region defined by doping with a particular conductive type dopant (such as a p-well 132 or a trench shielding region 180) refers to the point where the doping concentration drops by two orders of magnitude from the peak doping concentration of the region. In an example embodiment, the trench shielding region 180 can extend 1.5 to 10 times farther in the depth direction than the trench shielding region 80 of the MOSFET 1. The trench shielding region 180 can extend 1.2 to 5 times more in the depth direction than the p-well 132. Herein, the depth of a layer or region of a semiconductor layer structure refers to how far the layer or region extends in a direction perpendicular to the main surface of the semiconductor layer structure from a plane defined by the top surface of the semiconductor layer structure. The depth of the trench shielding region 180 may be greater or less than the depth of the trench support shield 160, such as Figure 3D In an example embodiment, the trench shield region 180 may have a depth between 0.75 and 0.95 times the depth of the trench support shield 160 .

[0092] The p-well 132 and at least the lower portion of the trench shielding region 180 may be moderately doped p-type regions. The doping concentration of the p-type well region 132 may be selected based on the desired doping concentration of the transistor channel of the MOSFET 100. In some embodiments, the moderately doped p-type well layer 130 and the lower portion of the trench shielding region 180 may each have a doping concentration of, for example, 1×10 16 Atom / cm 3 and 1×10 19 Atom / cm 3In some embodiments, the medium-doped p-type well layer 130 may have a graded doping profile.

[0093] Since the p-well 132 and the trench shielding region 180 are formed together (i.e., simultaneously) by the same ion implantation process, the doping profile of the p-type dopant in the p-well 132 will substantially match (i.e., match within 15%) the doping profile of the p-type dopant in the lower portion of the trench shielding region 180. As used herein, the doping profile of a region of a semiconductor layer structure (e.g., the doping profile of a p-well or trench shielding region) refers to the variation in the concentration of a certain type of conductive type dopant with depth. Thus, the doping profile can be graphically depicted using a two-dimensional graph having a curve showing the concentration of a specified conductive type dopant as a function of the distance in the depth direction from a reference plane (such as, for example, the top surface of the semiconductor layer structure). It should be appreciated that the doping profile of a region is taken through a central portion of a region that is not adjacent to another region, rather than an edge portion of a region, because edge effects can cause unexpected variations in the doping profile that are not representative of the doping profile of the region.

[0094] The "variation" between two doping profiles refers to the variation between corresponding points on the two profiles. If there is no variation in the two doping profiles, then if the graphical representations of the two doping profiles overlap, then the two curves will completely overlap and appear to be a single curve. This condition rarely exists. In this article, the reference to the first doping profile being less than X% different from the second doping profile means that the average difference between the two doping concentrations at each equivalent depth is less than X%. It should be noted that this article refers to the variation between the doping profile of the p-type dopant (or second conductivity type dopant) of the p-well 132 and the doping profile of the p-type dopant (or second conductivity type dopant) of the lower portion of the trench shielding region 180 formed in the same process for forming the p-well 132. Here, since the trench shielding region is formed below the gate trench 170, the p-well 132 and the trench shielding region 180 are at different depths within the semiconductor layer structure 150. Therefore, when comparing the variation between the two doping profiles, the depth of one of the curves is adjusted to account for the depth offset so that the two curves overlap approximately.

[0095] It is foreseeable that due to the effect that the gate trench 170 may have on the ion implantation process, the doping profiles of the p-type dopant in the p-well 132 and the trench shielding region 180 will vary slightly, which is why the doping profiles discussed above may not be completely matched. Since the p-well 132 is formed by implanting p-type dopant ions through the n-type source region 142, the doping profile of the p-type dopant in the n-type source region 142 will also substantially match (i.e., match within 15%) the doping profile of the p-type dopant in the upper portion of the trench shielding region 180. In some embodiments, the variation between the two doping profiles may be less than 10% or even less than 5%.

[0096] Figure 6 Schematic diagram illustrating how a semiconductor device according to an embodiment of the present invention may have a p-well, wherein a portion of the p-well located below the source region has a doping profile of a p-type dopant that differs by less than 15% from a doping profile of a p-type dopant in a lower portion of a trench shielding region (where the doping profile of the trench shielding region is obtained by a portion of the trench shielding region extending longitudinally below the center of the bottom of the gate trench). Figure 6 As shown in , the depth of the lower portion of the trench shielding region is adjusted by a constant offset to properly align the two curves. The change in the two doping profiles is then determined by averaging the change in doping concentration values ​​at each point (e.g., 100 equidistant points) along the horizontal axis. Figure 6 The average values ​​taken at three points are shown by way of example, wherein the values ​​of the p-well doping profile are marked as x1, x2, x3, and the values ​​of the trench shield region doping concentration are marked as y1, y2, y3.

[0097] The upper portion of each trench shielding region 180 (which corresponds to a portion extending from the bottom of the gate trench 170 into the drift region 120 by a distance equal to the depth of the source region 142 in the z-direction) can have a higher p-type doping concentration than the remaining portion of each trench shielding region 180. The upper portion of each trench shielding region 180 can have a higher doping concentration because a higher concentration of p-type dopant can be implanted into the source region 142 (and simultaneously into the portion of the drift region that is converted into the upper portion of the trench shielding region 180) without affecting the doping concentration of the well region 132. In some cases, the dose of the n-type dopant implanted to form the source region (see above) is Figure 3A13 and 180. The trench shielding regions 180 may extend the entire length of the corresponding gate trenches 170.

[0098] As discussed above, the sidewalls of the gate trenches 170 are typically not completely vertical, but rather slope outward as the distance from the bottom of each gate trench 170 increases. Therefore, during the above-described ion implantation process performed to form the p-well 132 and the trench shielding region 180, a certain level of dopant ions will be implanted directly into the sidewalls of each gate trench 170. In addition, a certain amount of dopant ions will bounce off the exposed portion of the drift region 120 below each gate trench 170, and some of these "reflected" dopant ions will subsequently be implanted into the sidewalls of the gate trenches 170. Implanting p-type dopant ions into the sidewalls of the gate trenches by these two mechanisms during the ion implantation process performed to form the p-well 132 and the trench shielding region 180 can be problematic for two reasons.

[0099] First, as discussed above, the p-type doping concentration of the p-well 132 can be carefully selected so that the channel region 134 has a doping concentration for optimized device performance. If additional p-type dopant ions are implanted into the channel region 134 during the ion implantation process performed to form the p-well 132 and the trench shielding region 180, the performance of the MOSFET 100 will be reduced. Second, the lightly doped n-type drift region 120 forms the lower portion of each sidewall of each gate trench 170. If enough p-type dopant ions are implanted into these n-type regions of the sidewalls of the gate trenches 170, the lower sidewalls can become effectively undoped or even doped p-type. If this happens, the p-well 132 can be shorted to the p-type trench shielding region 180, and the unit cell will no longer operate as a transistor. As described above, oxide spacers 78 are formed on the sidewalls of gate trench 70 to prevent dopant ions from being implanted into the sidewalls during the ion implantation process performed to form trench shielding region 80 during the manufacturing process for forming conventional MOSFET 1. Although this technique is effective, it complicates the manufacturing process.

[0100] Figure 3E and Figure 3F The processing steps performed to remove dopant ions implanted into the sidewalls of the gate trench 170 during the ion implantation process performed to form the p-well 132 and the trench shielding region 180 are illustrated. Figure 3E, an oxidation process is performed on MOSFET 100. The oxidation process oxidizes the exposed surfaces of semiconductor layer structure 150, including the top surface of semiconductor layer structure 150 and the sidewalls and bottom surface of gate trench 170. In some embodiments (e.g., in embodiments formed using a 4H silicon carbide substrate), the sidewalls of gate trench 170 may be oxidized faster than the upper surface of semiconductor layer structure 150 and the upper portion of trench shielding region 180 because different faces of the silicon carbide crystal structure will oxidize at different rates. The oxidation process may be performed to oxidize portions of the sidewalls of gate trench 170 whose doping concentrations have been significantly changed by the ion implantation process performed to form p-well 132 and trench shielding region 180.

[0101] Next, refer to Figure 3F , an etching process is performed to remove the oxidized silicon carbide. This etching process is used to remove a portion of the sidewall of the gate trench 170 that was implanted during the ion implantation process performed to form the p-well 132 and the trench shielding region 180. The etching process also removes the oxidized top surface of the semiconductor layer structure 150 and the top portion of each trench shielding pattern 180.

[0102] Note that the above reference Figure 3E and Figure 3F The oxidation and oxide removal steps described serve to widen the gate trench 170. Thus, the gate trench 170 may initially be formed to have a width in the y-direction that is less than the desired final width of the gate trench 170.

[0103] In some cases, it may be desirable to further increase the doping concentration of the upper portion 182 of each trench shielding region 180. In some embodiments, a second ion implantation process may be performed in which a p-type dopant is implanted into the upper surface of the semiconductor layer structure and into the bottom surface of the gate trench 170. This ion implantation process may be a relatively low energy but high dose ion implantation process. Therefore, the p-type dopant is not deeply implanted and is implanted at a high dose level. The implantation energy may be set so that the dopant ions implanted into the upper surface of the semiconductor layer structure 150 do not completely pass through the n-type source region 142, thereby ensuring that the doping concentration of the p-well 132 is not substantially affected by this ion implantation step. Simultaneously, the p-type dopant ions are implanted into the upper portion 182 of each trench shielding region 180, which helps to reduce the magnitude of the electric field formed in the lower portion of the gate oxide layer of the device during the reverse blocking operation (discussed below). Since the implantation energy is set so that the dopant ions do not have a substantial effect on the doping concentration of the p-well 132, it is not necessary to form an ion implantation mask covering the source region 142. When the dopant concentration of the upper portion 182 of the trench shield region 180 is increased in the above manner, it can be referred to above. Figure 3E and Figure 3F The oxidation and removal steps are described as being preceded by a second ion implantation process so that the oxidation and removal steps can remove the p-type dopants implanted into the sidewalls of the gate trench 170 during the two ion implantation steps.

[0104] In other cases, the sidewalls of the gate trench 170 may be capped before performing the ion implantation step, which increases the doping concentration of the upper portion of the trench shielding region 180. Figure 3G-3I In particular, Figure 3G As shown in FIG. 1 , spacers 178 such as oxide spacers are formed on the sidewalls of the gate trench 170. The spacers 178 may be formed in the same manner as the oxide spacers 78 discussed above with reference to FIG. 2E , and thus further description thereof will be omitted herein. A supplemental ion implantation may then be performed to increase the dopant concentration in the upper portion 182 of the silicon carbide trench shield region 180, such as Figure 3H As discussed above, this supplemental ion implantation may be a high-dose, relatively low-energy implantation to ensure that the supplemental ion implantation does not substantially change the doping concentration of the p-well 132 .

[0105] refer to Fig. 3I , the sidewall spacers 178 may then be removed via an etching process. It should be noted that the vertical doping profile of the well region 132 taken along a first axis extending through the well region 132 in a direction perpendicular to a plane parallel to the top surface of the semiconductor layer structure 150 may differ by less than 10% from the vertical doping profile of the lower portion of the trench shield region 180 taken along a second axis parallel to the first axis and extending through the center of the bottom of the trench 170. As discussed above, this occurs because the p-well 132 and the trench shield region 180 are formed together (i.e., simultaneously) by the same ion implantation process. Here, the lower portion of the trench shield region 180 refers to a portion of the trench shield region 180 that extends in the depth direction from the bottom of the trench shield region 180 by the same distance as the p-well 132 extends in the depth direction. Here, "vertical" refers to a direction perpendicular to a plane parallel to the top surface of the semiconductor layer structure 150.

[0106] refer to Figure 3J , a gate oxide layer 172 is conformally formed on the bottom surface and sidewalls of each gate trench 170. The conformal gate oxide layer 172 can be formed by oxidizing the exposed silicon carbide via annealing in an oxygen-containing environment. Alternatively, the conformal gate oxide layer 172 can be formed by an oxide deposition step. Portions of the conformal gate oxide layer can be removed to form an opening, source contact 190 (see Figure 3J) can be connected to the source region 142 and the p-well extension 136 (discussed below) at the opening. After removing these portions of the conformal gate oxide layer, a gate oxide layer 172 is left in each gate trench 170.

[0107] A gate electrode 174 is formed on each gate oxide layer 172. In some embodiments, the gate electrode 174 can substantially fill the corresponding gate trench 170. The gate electrode 174 can include a conductive material such as, for example, polysilicon, a silicate, or a metal. An intermetallic dielectric layer 176 is formed on the gate oxide layer 172 and the exposed portions of the gate electrode 174. A source contact 190 is then formed on the upper portion of the device. The source contact 190 can include one or more metals and is physically and electrically connected to the p-well 132 (see reference 170 below). Figure 3L 10) and an n-type source region 142. Source contact 190 may include a source terminal of MOSFET 100, or may be electrically connected to the source terminal. Drain contact 192 is formed on the lower surface of substrate 110. A gate contact (not shown) connected to gate electrode 174 is also provided.

[0108] As discussed above, since the p-well 132 and the trench shield region 180 are formed together (ie, simultaneously) by the same ion implantation process (see Figure 3D ), the trench shielding region 180 will extend downward from the bottom of the corresponding gate trench 170 into the semiconductor layer structure 150, extending a first distance in the depth direction, which is substantially the same as a second distance that the p-well 132 extends downward from the top surface of the semiconductor layer structure 150 into the semiconductor layer structure 150. For example, in some embodiments, the first distance can be within + / -10% of the second distance. In other embodiments, the first distance can be within + / -5% of the second distance. Here, the first and second distances refer to the maximum depths of the p-well 132 and the trench shielding region 180, respectively.

[0109] Figure 3K is taken along line 3K-3K. Figure 3J 0 is a horizontal cross-section of the device shown in (ie, the cross-section is taken along the top surface of the semiconductor layer structure 150 ). Figure 3K1. It is shown how to form a p-well extension 136 extending between the p-well 132 and the upper surface of the semiconductor layer structure 150. In the depicted embodiment, a series of p-well extensions 136 are provided between each pair of gate trenches 170, wherein the p-well extensions 136 are spaced apart from each other in the x-direction. The p-well extensions 136 can be formed by, for example, additional ion implantation steps not discussed above. The p-well extensions 136 can be highly doped p-type regions and can have, for example, a doping concentration that equals or exceeds the doping concentration of the n-type source region 142. The p-well extensions 136 provide an electrical connection between the source contact 190 and the p-well 132.

[0110] Figure 3L It is along Figure 3K The cross-sectional view taken along line 3L-3L of FIG. 1 illustrates the p-well extension 136 and the trench shield region connection pattern 138 that electrically connects the trench shield region 180 to one of the p-well extensions 136. The trench shield region connection pattern 138 may be a highly doped (p + ) a p-type region formed in a portion of one of the sidewalls of the illustrated gate trench 170. The trench shielding region connection pattern 138 may be formed by, for example, an additional ion implantation step not discussed above.

[0111] As discussed above, including p-type trench support shields 160 in MOSFET 100 can be advantageous because they can help reduce the electric field in gate oxide layer 172 during reverse blocking operation and because they provide a more favorable (lower resistance) avalanche current path in the event of avalanche breakdown. However, forming trench support shields 160 requires additional processing steps and thus increases manufacturing costs, and in some applications, the additional expense may outweigh the advantages of trench support shields 160. Figure 4A-4B A MOSFET 100' according to a further embodiment of the present invention is illustrated, which does not include any trench support shield 160. In addition to omitting the above reference 160 when manufacturing the MOSFET 100', Figure 3B In addition to the processing steps described above, you can use the Figures 3A-3L The same processing steps discussed above are used to form MOSFET 100'. Figure 4A and Figure 4B Respectively Figure 3J and Figure 3L Correspondingly, wherein similar elements are numbered using the same reference numerals in these Figures, since MOSFET 100' is identical to MOSFET 100 except that trench support shield 160 is omitted, further description of MOSFET 100' will be omitted.

[0112] Figure 5is a flow chart illustrating a method for fabricating a gate trench semiconductor device, such as, for example, a power wide bandgap gate trench semiconductor device, according to an embodiment of the present invention.

[0113] like Figure 5 As shown in , an operation can form a semiconductor drift region on a substrate (box 200). The drift region can have a first conductivity type and can be relatively lightly doped. The drift region can be formed, for example, by epitaxial growth. Next, a source layer having a first conductivity type is formed in the upper surface of the drift region (box 205). The source layer can be heavily doped and can be formed, for example, by ion implantation. A trench support shield is also formed (box 210). The trench support shield can have a second conductivity type and can be heavily doped. The trench support shield can be formed, for example, by ion implantation using an ion implantation mask. The trench support shield can be formed before or after the source layer.

[0114] The gate trench is formed to pass through the source layer and enter the drift region (box 215). The gate trench can be formed by masking the device and then performing an etching process. The formation of the gate trench can subdivide the source layer into multiple source regions. Each gate trench can have a depth less than the depth of the trench support shield. Next, an ion implantation process can be performed to blanket implant the p-type dopant into the active region of the device (box 220). This ion implantation process simultaneously forms multiple second conductivity type well regions below the source region and multiple second conductivity type trench shield regions below the corresponding trenches. The well region and the trench shield region can be moderately doped with the second conductivity type dopant.

[0115] In some embodiments, a second ion implantation process (block 225) may be performed immediately after the ion implantation process of block 220. The second ion implantation may be a low energy, high dose ion implantation process that implants the second conductivity type dopant into the first conductivity type source region and into the upper portion of the corresponding trench shielding region. Since the low energy implantation process is performed, the second conductivity type dopant ions will not substantially pass through the source region into the well region, and thus will not change the doping concentration of the well region. Moreover, since the source region may have, for example, a first conductivity dopant concentration that is one order of magnitude greater than the second conductivity type dopant implanted into the source region, the second ion implantation process will not substantially change the effective doping concentration of the source region. For example, the second ion implantation process may be used to convert the upper portion of the trench shielding region into a heavily doped region in order to improve the electric field blocking capability of the trench shielding region.

[0116] After performing the above-described ion implantation steps, an oxidation process (block 230) may be performed to oxidize the exposed surfaces of the device. The oxidation process may involve pumping an oxygen-containing gas into a chamber containing the device at an elevated temperature. The oxidation process may be carefully controlled to oxidize the sidewalls of the gate trench to a desired amount. Next, an etching process may be performed to remove the oxidized semiconductor material (block 235). As described above, the oxidation and removal processes of blocks 230 and 235 remove portions of the sidewalls of the gate trench that were inadvertently doped during the ion implantation process discussed above.

[0117] In some embodiments, the second ion implantation process discussed above with reference to block 225 may be omitted. In such embodiments, the processes of blocks 240, 245, and 250 may be performed. In particular, sidewall spacers such as oxide spacers may be selectively formed on the sidewalls of the gate trench (block 240). Then, a low energy, high dose ion implantation process is performed, which implants the second conductivity type dopant into the first conductivity type source region and the upper portion of the corresponding trench shielding region (block 245). Since the low energy implantation process is performed, the second conductivity type dopant ions will not substantially pass through the source region into the well region, and thus will not change the doping concentration of the well region. Moreover, since the source region may have, for example, a first conductivity dopant concentration that is one order of magnitude greater than the second conductivity type dopant implanted into the source region, the second ion implantation process will not substantially change the effective doping concentration of the source region. The second ion implantation process may be used, for example, to convert the upper portion of the trench shielding region into a heavily doped region in order to improve the electric field blocking capability of the trench shielding region. The sidewall spacers protect the sidewalls of the gate trench during the ion implantation process. After the ion implantation process is completed, the sidewall spacers are removed (block 250 ).

[0118] Next, a gate oxide layer and a gate electrode may be sequentially formed in the gate trench (block 255). An intermetallic dielectric layer may be formed over the gate trench, and then source and drain metallization may be formed (block 260).

[0119] In the above description, each example embodiment has a specific conductivity type. It should be appreciated that by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments, devices of opposite conductivity types can be formed. Therefore, it should be appreciated that the present invention covers n-channel and p-channel devices for each different device structure (e.g., MOSFET, IGBT, etc.). In this article, when a contact can be either a source contact or a drain contact, it can be referred to as a "source / drain contact".

[0120] Although the present invention is described above with respect to power MOSFET and power IGBT embodiments, it should be appreciated that the techniques described herein are equally applicable to other similar vertical power devices with gate trenches. Therefore, embodiments of the present invention are not limited to MOSFET and IGBT, and the techniques disclosed herein can be used for any suitable gate trench device.

[0121] The present invention is discussed above primarily with respect to power semiconductor devices based on silicon carbide. However, it should be appreciated that silicon carbide is used herein as an example, and the devices discussed herein may be formed in any suitable wide bandgap semiconductor material system. As an example, in any of the above embodiments, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used instead of silicon carbide.

[0122] Embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the present invention are shown. However, it should be appreciated that the present invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth above. Rather, these embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. Throughout the text, similar reference numerals refer to similar elements.

[0123] In this context, the term "plurality" means two or more. In this context, "substantially" means within + / - 10%.

[0124] It should be understood that, although the terms first, second, etc. are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more associated listed items.

[0125] The terms used herein are used only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprises", "comprising", "includes", and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0126] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto another element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly" "on" another element, there are no intervening elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0127] Relative terms such as "below" or "above" or "up" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0128] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments (and intermediate structures) of the invention. For clarity, the thickness of layers and regions in the drawings may be exaggerated. In addition, due to reasons such as manufacturing techniques and / or tolerances, it is expected that the shapes of the drawings may be different. Embodiments of the invention are also described with reference to flow charts. It should be appreciated that the steps shown in the flow charts need not be performed in the order shown.

[0129] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions that are characterized as having conductivity types such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Therefore, n-type materials have a majority equilibrium concentration of negatively charged electrons, while p-type materials have a majority equilibrium concentration of positively charged holes. A material may be marked with "+" or "-" (such as n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a relatively larger ("+") or smaller ("-") majority carrier concentration compared to another layer or region. However, such a symbol does not mean that there is a particular concentration of majority or minority carriers in a layer or region.

[0130] In the drawings and specification, typical embodiments of the invention have been disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Providing a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure comprising a drift region having a first conductivity type and a source region having the first conductivity type on the drift region, the wide bandgap semiconductor layer structure comprising a trench therein; as well as A second conductivity type dopant is implanted into the wide bandgap semiconductor layer structure to simultaneously form a well region under the source region and a trench shield region under the trench, the well region and the trench shield region each having the second conductivity type.

2. The method of claim 1, wherein the trench extends through the source region and into the drift region.

3. The method of claim 1 or 2, wherein implanting the second conductivity type dopant into the wide bandgap semiconductor layer structure comprises: A second conductivity type dopant is implanted into the drift region through the source region. 4 . The method of claim 1 , wherein the well region is formed by converting a portion of a drift region having a first conductivity type into a well region having a second conductivity type.

5. The method of claim 1 or 2, wherein a well region separates a source region from a drift region.

6. The method of claim 1 or 2, wherein the source region forms upper portions of both a first sidewall and a second sidewall of the trench, and the drift region forms lower portions of the first sidewall and the second sidewall, wherein the first sidewall faces the second sidewall. 7 . The method of claim 6 , wherein when the second conductive type dopant is implanted into the wide bandgap semiconductor layer structure, the first sidewall of the trench is exposed.

8. The method of claim 7, further comprising: performing an oxidation process to convert at least the first and second sidewalls and the bottom of the trench into an oxide material; as well as The oxide material is removed to convert the trench into an enlarged trench.

9. The method of claim 1 or 2, wherein the wide bandgap semiconductor layer structure extends in a length direction, a width direction, and a depth direction that are perpendicular to each other, and a lower surface of the wide bandgap semiconductor layer structure extends in the length direction and the width direction.

10. The method of claim 9, wherein the source region extends a first distance in the depth direction and the shield region extends a second distance in the depth direction, wherein the second distance exceeds the first distance. The method of claim 10 , wherein the second distance is at least 1.5 times the first distance.

12. The method of claim 10, wherein the second distance is at least twice the first distance. 13 . The method of claim 10 , wherein the portion of the well region extending to the upper surface of the wide bandgap semiconductor layer structure extends a third distance in the depth direction, and the third distance is substantially the same as the second distance.

14. The method of any one of claims 1 to 13, wherein the concentration of the second conductivity type dopant in the source region is at least 5×10 15 / cm 3 .

15. The method of any one of claims 1-14, wherein a doping profile of a lower portion of the trench shielding region taken along a first axis extending in a depth direction through a center of a bottom portion of the gate trench differs by less than 15% from a doping profile of the well region taken along a second axis parallel to the first axis and extending through the well region.

16. The method according to claim 1 or 2, further comprising: Additional second conductivity type dopants are implanted into the wide bandgap semiconductor layer structure below the trench. 17 . The method of claim 16 , wherein the second conductivity type dopant and the additional second conductivity type dopant are implanted using the same ion implantation mask.

18. The method of claim 16, wherein the additional second conductivity type dopant is implanted before the implantation of the second conductivity type dopant.

19. The method of claim 16, further comprising: A mask is formed on the sidewalls of the trench before additional second conductivity type dopants are implanted into the wide bandgap semiconductor layer structure.

20. The method of claim 16, wherein when the additional second conductivity type dopant is implanted into the wide bandgap semiconductor layer structure, an upper surface of the source region is exposed.

21. The method of claim 8, further comprising: Additional second conductivity type dopants are implanted into the wide bandgap semiconductor layer structure below the trench.

22. The method of claim 16, wherein the additional second conductivity type dopant is implanted before performing an oxidation process to convert at least the first and second sidewalls and the bottom of the trench into an oxide material.

23. The method of any one of claims 1 to 22, wherein when the second conductivity type dopant is implanted into the wide bandgap semiconductor layer structure, an upper surface of the source region is exposed.

24. The method of any one of claims 1 to 23, wherein providing a wide bandgap semiconductor layer structure comprises: forming a drift region on an upper surface of a wide bandgap semiconductor substrate having a first conductivity type; Implanting first conductivity type dopant ions into the upper surface of the drift region to form a source region, the source region having a higher first conductivity type dopant concentration than the drift region; as well as A trench is formed in an upper surface of the wide bandgap semiconductor layer structure.

25. The method of any one of claims 1 to 24, further comprising: A second conductivity type dopant is implanted into the semiconductor layer structure to form a first support shield and a second support shield in the semiconductor layer structure on respective first and second sides of the trench.

26. The method of any one of claims 1 to 25, further comprising: A gate oxide layer and a gate electrode are sequentially formed in the trench.

27. The method of any one of claims 1 to 26, further comprising: A trench shield region connection region is formed that electrically connects the trench shield region to the well region.

28. A semiconductor device, comprising a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure comprising: a drift region having a first conductivity type; a well region, the well region being located on the drift region and having a second conductivity type; a source region, the source region being located on the well region and having a first conductivity type; a gate electrode, located in the trench; as well as a shielding region, the shielding region being located below the gate trench and having a second conductivity type, The doping profile of the second conductivity type dopant in the portion of the well region below the source region differs by less than 15% from the doping profile of the second conductivity type dopant in the lower portion of the shield region extending longitudinally below the center of the trench bottom.

29. The semiconductor device of claim 28, wherein the well region is located between the drift region and the source region, and wherein the trench extends through the source region and the well region and into the drift region.

30. The semiconductor device of claim 28 or 29, wherein the semiconductor layer structure extends in a length direction, a width direction, and a depth direction perpendicular to each other, and wherein a lower surface of the semiconductor layer structure extends in the length direction and the width direction.

31. The semiconductor device of claim 29, wherein the source region extends a first distance in the depth direction, and the shield region extends a second distance in the depth direction, wherein the second distance exceeds the first distance.

32. The semiconductor device of claim 30, wherein the second distance is at least 1.5 times the first distance.

33. The semiconductor device of claim 30, wherein the second distance is at least twice the first distance.

34. The semiconductor device of any one of claims 28-33 further comprises a first support shield and a second support shield having a second conductivity type in a wide bandgap semiconductor layer structure located on the respective first and second sides of the groove, wherein the first support shield and the second support shield extend closer to the bottom surface of the wide bandgap semiconductor layer structure than the shielding area.

35. The semiconductor device of any one of claims 28 to 34, wherein a concentration of the second conductivity type dopant in the upper portion of the shielding region exceeds a concentration of the second conductivity type dopant in the source region.

36. The semiconductor device of any one of claims 28-35, wherein an average concentration of the second conductivity type dopant in an upper portion of the shielding region exceeds an average concentration of the second conductivity type dopant in a lower portion of the shielding region.

37. A semiconductor device as claimed in any one of claims 28 to 36, wherein the drift region, the well region, the source region and the shield region comprise silicon carbide.

38. A semiconductor device, comprising a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure comprising: a drift region having a first conductivity type; a well region, the well region being located on the drift region and having a second conductivity; a source region, the source region being located on the well region and having a first conductivity type; a gate electrode, located in the trench; as well as a shielding region, located below the trench, having a second conductivity type, Wherein the shielding region extends from a bottom of the trench down to a first distance into the semiconductor layer structure, and the well region extends from a top surface of the semiconductor layer structure down to a second distance into the semiconductor layer structure, wherein the first distance is within + / -10% of the second distance.

39. The semiconductor device of claim 38, wherein the well region is located between the drift region and the source region, and wherein the trench extends through the source region and the well region and into the drift region.

40. The semiconductor device of claim 39, wherein the source region extends from a top surface of the semiconductor layer structure down into the semiconductor layer structure a third distance, and the first distance exceeds the third distance.

41. The semiconductor device of claim 40, wherein the first distance is at least 1.5 times the third distance.

42. The semiconductor device of claim 40, wherein the first distance is at least twice the third distance.

43. A semiconductor device as described in any one of claims 38-42, further comprising a first support shield and a second support shield having a second conductivity type in a wide bandgap semiconductor layer structure located on the respective first and second sides of the groove, wherein the first support shield and the second support shield extend closer to the bottom surface of the wide bandgap semiconductor layer structure than the shielding area.

44. The semiconductor device of any one of claims 38-43, wherein a concentration of the second conductivity type dopant in the upper portion of the shielding region exceeds a concentration of the second conductivity type dopant in the source region.

45. A semiconductor device as claimed in any one of claims 38 to 44, wherein the drift region, the well region, the source region and the shield region comprise silicon carbide.

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