Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device (10) including a miniature transistor is provided. The semiconductor device includes a first transistor (100) and a second transistor (200). The first transistor includes a first conductive layer (112a), a first insulating layer (110) on the first conductive layer, a second insulating layer (120) on the first insulating layer, a second conductive layer (112b) on the second insulating layer, a first semiconductor layer (108), a third insulating layer (106), and a third conductive layer (104). The first insulating layer, the second insulating layer, and the second conductive layer include openings (143) to the first conductive layer. The first semiconductor layer is in contact with a top surface and a side surface of the second conductive layer, a side surface of the first insulating layer, the second insulating layer and a top surface of the first conductive layer. The third insulating layer is disposed on the first semiconductor layer. The third conductive layer is disposed on the third insulating layer. The second transistor includes a second semiconductor layer (208) on the second insulating layer, a third insulating layer on the second semiconductor layer, and a fourth conductive layer (204) including a region overlapping the second semiconductor layer via the third insulating layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing a display device.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical field. Examples of the technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and methods for driving or manufacturing such devices. Background Art

[0003] Semiconductor devices including transistors are widely used in display devices and electronic devices, and they require high integration and high speed. For example, when semiconductor devices are used in high-definition display devices, highly integrated semiconductor devices are required. As one of the methods to increase the integration density of transistors, the development of micro-transistors is underway.

[0004] In recent years, there has been a high demand for display devices that can be used for virtual reality (VR), augmented reality (AR), substitute reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). In order to enhance the sense of reality and immersion, XR display devices are required to have high clarity and high color reproducibility. Examples of the above-mentioned display devices include liquid crystal display devices, light-emitting devices having light-emitting devices (also called light-emitting elements) such as organic EL (Electro Luminescence) devices or light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR using an organic EL device (also referred to as an organic EL element). [Prior technical literature] [Patent Document]

[0006] [Patent Document 1] International Patent Application Publication No. 2018 / 087625 Summary of the Invention Technical problem to be solved by the invention

[0007] One of the objects of one embodiment of the present invention is to provide a semiconductor device including a micro transistor and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a small semiconductor device and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with a large on-state current and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a high-performance semiconductor device and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a method for manufacturing the same.

[0008] Note that the inclusion of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not necessarily achieve all of the above objectives. Note that objectives other than those listed above can be extracted from the description of the specification, drawings, claims, etc. Means of solving technical problems

[0009] One embodiment of the present invention is a semiconductor device comprising: a first transistor; and a second transistor. The first transistor comprises a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a second conductive layer on the second insulating layer, a first semiconductor layer, a third insulating layer, and a third conductive layer. The first insulating layer, the second insulating layer, and the second conductive layer include an opening that reaches the first conductive layer. The first semiconductor layer contacts the top surface and side surfaces of the second conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second insulating layer, and the top surface of the first conductive layer. The third insulating layer is disposed on the first semiconductor layer. The third conductive layer is disposed on the third insulating layer. The second transistor comprises a second semiconductor layer on the second insulating layer, a third insulating layer on the second semiconductor layer, and a fourth conductive layer including a region overlapping the second semiconductor layer via the third insulating layer.

[0010] One embodiment of the present invention is a semiconductor device comprising: a first transistor; a second transistor; and a substrate. The first transistor comprises a first conductive layer on the substrate, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a second conductive layer on the second insulating layer, a first semiconductor layer, a third insulating layer, and a third conductive layer. The first insulating layer, the second insulating layer, and the second conductive layer include an opening reaching the first conductive layer. The first semiconductor layer contacts the top surface and side surfaces of the second conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second insulating layer, and the top surface of the first conductive layer. The third insulating layer is provided on the first semiconductor layer. The third conductive layer is provided on the third insulating layer. The second transistor comprises a second semiconductor layer on the second insulating layer, a third insulating layer on the second semiconductor layer, a fourth conductive layer including a region overlapping with the second semiconductor layer via the third insulating layer, and a fifth conductive layer on the substrate. The fifth conductive layer includes a region overlapping with the fourth conductive layer via the second semiconductor layer.

[0011] One embodiment of the present invention is a semiconductor device comprising: a first transistor; and a second transistor. The first transistor comprises a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a second conductive layer on the second insulating layer, a first semiconductor layer, a third insulating layer, and a third conductive layer. The first insulating layer, the second insulating layer, and the second conductive layer include an opening reaching the first conductive layer. The first semiconductor layer is in contact with the top surface and side surfaces of the second conductive layer, the side surfaces of the first insulating layer, the second insulating layer, and the top surface of the first conductive layer. The third insulating layer is provided on the first semiconductor layer. The third conductive layer is provided on the third insulating layer. The second transistor comprises the second semiconductor layer on the second insulating layer, the third insulating layer on the second semiconductor layer, a fourth conductive layer including a region overlapping with the second semiconductor layer via the third insulating layer, and a fifth conductive layer on the first insulating layer. The fifth conductive layer includes a region overlapping with the fourth conductive layer via the second semiconductor layer.

[0012] In the above semiconductor device, it is preferred that both the first semiconductor layer and the second semiconductor layer include a metal oxide.

[0013] In the above semiconductor device, the first semiconductor layer and the second semiconductor layer preferably include the same material.

[0014] In the above semiconductor device, the third conductive layer and the fourth conductive layer preferably include the same material.

[0015] In the above semiconductor device, the first insulating layer preferably includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. The fourth insulating layer preferably includes a region having a higher film density than the fifth insulating layer. The sixth insulating layer preferably includes a region having a higher film density than the fifth insulating layer.

[0016] In the above semiconductor device, the first insulating layer preferably includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. The fourth insulating layer preferably includes a region having a higher nitrogen content than the fifth insulating layer. The sixth insulating layer preferably includes a region having a higher nitrogen content than the fifth insulating layer.

[0017] In the semiconductor device described above, the second insulating layer preferably includes a seventh insulating layer and an eighth insulating layer on the seventh insulating layer. The seventh insulating layer preferably includes a region having a higher film density than the eighth insulating layer.

[0018] In the semiconductor device described above, the second insulating layer preferably includes a seventh insulating layer and an eighth insulating layer on the seventh insulating layer. The seventh insulating layer preferably includes a region containing a higher nitrogen content than the eighth insulating layer.

[0019] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive film; processing the first conductive film to form a first conductive layer and a second conductive layer; forming a first insulating film on the first conductive layer and the second conductive layer; forming a second conductive film on the first insulating film; processing the first insulating film and the second conductive film to form a first insulating layer and a third conductive layer including an opening in a region overlapping with the first conductive layer; forming a first semiconductor layer in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, and the top surface and side surface of the third conductive layer, and a second semiconductor layer in contact with the top surface of the first insulating layer; forming a second insulating layer on the first semiconductor layer and the second semiconductor layer; and forming a fourth conductive layer including a region overlapping with the first semiconductor layer and a fifth conductive layer including a region overlapping with the second semiconductor layer on the second insulating layer. Effects of the Invention

[0020] According to one embodiment of the present invention, a semiconductor device including a micro transistor and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a small semiconductor device and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a semiconductor device including a transistor with a large on-state current and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a high-performance semiconductor device and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a highly reliable semiconductor device and a method for manufacturing the same can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device and a method for manufacturing the same can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above effects can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A is a plan view showing an example of a semiconductor device. Figure 1B and Figure 1C is a cross-sectional view showing an example of a semiconductor device. Figures 2A to 2C It is a perspective view showing an example of a semiconductor device. Figure 3A and Figure 3B It is a perspective view showing an example of a semiconductor device. Figure 4A is a plan view showing an example of a semiconductor device. Figure 4B is a cross-sectional view showing an example of a semiconductor device. Figure 5A is a plan view showing an example of a semiconductor device. Figure 5B and Figure 5C is a cross-sectional view showing an example of a semiconductor device. Figure 6A and Figure 6B is a cross-sectional view showing an example of a semiconductor device. Figure 7A is a plan view showing an example of a semiconductor device. Figure 7B and Figure 7C is a cross-sectional view showing an example of a semiconductor device. Figures 8A to 8C It is a perspective view showing an example of a semiconductor device. Figure 9A and Figure 9B It is a perspective view showing an example of a semiconductor device. Figure 10A is a plan view showing an example of a semiconductor device. Figure 10B is a cross-sectional view showing an example of a semiconductor device. Figure 11A and Figure 11B is a cross-sectional view showing an example of a semiconductor device. Figure 12A and Figure 12B is a cross-sectional view showing an example of a semiconductor device. Figure 13A is a plan view showing an example of a semiconductor device. Figure 13B is a cross-sectional view showing an example of a semiconductor device. Figure 14 is a cross-sectional view showing an example of a semiconductor device. Figure 15A is a plan view showing an example of a semiconductor device. Figure 15B is a cross-sectional view showing an example of a semiconductor device. Figure 16A and Figure 16B is a cross-sectional view showing an example of a semiconductor device. Figure 17A is a plan view showing an example of a semiconductor device. Figure 17B is a cross-sectional view showing an example of a semiconductor device. Figure 18A It is a perspective view showing an example of a semiconductor device. Figure 18B and Figure 18C It is the equivalent circuit diagram of the transistor group. Figure 19A and Figure 19B It is a perspective view showing an example of a semiconductor device. Figure 20A and Figure 20B It is a perspective view showing an example of a semiconductor device. Figure 21A is a plan view showing an example of a semiconductor device. Figure 21B is a cross-sectional view showing an example of a semiconductor device. Figure 22A It is a perspective view showing an example of a semiconductor device. Figure 22B and Figure 22C It is the equivalent circuit diagram of the transistor group. Figure 23A and Figure 23B It is a perspective view showing an example of a semiconductor device. Figure 24A and Figure 24B It is a perspective view showing an example of a semiconductor device. Figures 25A to 25E This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. 26A to 26D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 27A to 27C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 28A to 28C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 29A and Figure 29B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 30A and Figure 30B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 31A and Figure 31B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 32A and Figure 32B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 33A and Figure 33B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 34A and Figure 34B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 35A It is a perspective view of a display device. Figure 35B is a block diagram of a display device. Figure 36A This is the circuit diagram of a latch circuit. Figure 36B It is the circuit diagram of the inverter circuit. Figure 37A and Figure 37B This is a circuit diagram of a pixel circuit. Figure 37C is a cross-sectional view showing an example of a pixel circuit. Figure 38A and Figure 38B is a cross-sectional view showing an example of a pixel circuit. Figure 39 is a cross-sectional view showing a structural example of a display device. Figure 40 is a cross-sectional view showing a structural example of a display device. Figures 41A to 41C is a cross-sectional view showing a structural example of a display device. Figure 42 is a cross-sectional view showing a structural example of a display device. Figures 43A to 43G is a diagram showing an example of a pixel. Figures 44A to 44K is a diagram showing an example of a pixel. Figures 45A to 45F is a diagram showing a structural example of a light emitting device. Figures 46A to 46C is a diagram showing a structural example of a light emitting device. Figure 47A and Figure 47B is a diagram showing a structural example of a display device. Figures 48A to 48D is a diagram showing a structural example of a display device. Figures 49A to 49C is a diagram showing a structural example of a display device. Figures 50A to 50D is a diagram showing a structural example of a display device. Figures 51A to 51F is a diagram showing a structural example of a display device. Figures 52A to 52F is a diagram showing a structural example of a display device. Figures 53A to 53F is a diagram illustrating an example of an electronic device. Figures 54A to 54F is a diagram illustrating an example of an electronic device. Modes for Carrying Out the Invention

[0023] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily appreciate that the embodiments and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the embodiments described below.

[0024] Note that in the invention structure described below, the same symbols are used to show the same parts or parts with the same function in different drawings, and repeated descriptions are omitted. In addition, when parts with the same function are represented, the same hatching is sometimes used without adding a special reference numeral.

[0025] For ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not necessarily represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0026] In addition, depending on the situation or state, the terms "film" and "layer" can be interchanged. For example, "conductive layer" can be replaced with "conductive film." Also, "insulating film" can be replaced with "insulating layer."

[0027] In this specification, devices manufactured using a metal mask or FMM (Fine Metal Mask) are sometimes referred to as devices having an MM (Metal Mask) structure. Furthermore, in this specification, devices manufactured without using a metal mask or FMM are sometimes referred to as devices having an MML (Metal Mask Less) structure.

[0028] In this specification and other documents, a structure in which at least the light-emitting layers of light-emitting devices (also called light-emitting elements) with different emission wavelengths are manufactured separately is sometimes referred to as an SBS (Side-by-Side) structure. The SBS structure allows for optimization of materials and structures for each light-emitting device, increasing the freedom of material and structure selection and facilitating improvements in brightness and reliability.

[0029] In this specification, holes or electrons are sometimes referred to as "carriers." Specifically, a hole injection layer or electron injection layer is sometimes referred to as a "carrier injection layer," a hole transport layer or electron transport layer is sometimes referred to as a "carrier transport layer," and a hole blocking layer or electron blocking layer is sometimes referred to as a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not be clearly distinguished based on their cross-sectional shape or characteristics. Furthermore, a single layer may sometimes perform the functions of two or all three of these layers.

[0030] In this specification, etc., a light-emitting device includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier blocking layer (a hole blocking layer and an electron blocking layer).

[0031] In this specification and the like, a light-receiving device (also referred to as a light-receiving element) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes.

[0032] In this specification, "island-shaped" refers to a state in which two or more layers formed in the same process and using the same material are physically separated. For example, an island-shaped light-emitting layer means that the light-emitting layer is physically separated from the adjacent light-emitting layer.

[0033] In this specification, etc., a tapered shape refers to a shape in which at least a portion of a side surface of a component is inclined relative to a substrate surface or a formed surface. For example, a region where the angle formed between the inclined side surface and the substrate surface or the formed surface (also known as a taper angle) is less than 90 degrees is preferably present. Here, the side surface, substrate surface, and formed surface of a component do not necessarily need to be completely flat; they may be approximately planar with slight curvature or have fine irregularities.

[0034] In this specification, etc., a mask layer (also called a sacrificial layer) is located at least above the light-emitting layer (more specifically, a layer processed into an island shape among the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0035] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is disconnected due to the shape of the surface on which it is formed (for example, a step, etc.).

[0036] In this specification, etc., the phrase "top surface shapes are substantially identical" means that at least a portion of the edges of each layer in the stack overlap. This includes, for example, cases where the upper and lower layers are processed using the same mask pattern, or a portion of the mask pattern is identical. However, in practice, there are cases where the edges do not overlap, and sometimes the upper layer is located inside or outside the lower layer. In these cases, the term "top surface shapes are substantially identical" can also be used.

[0037] (Implementation 1) In this embodiment, a semiconductor device according to one embodiment of the present invention, a method for manufacturing the same, and the like are described with reference to FIG. 1 to FIG. 34 .

[0038] <Structure Example 1> A semiconductor device according to one embodiment of the present invention will be described. Figure 1A 1 is a top view (also called a plan view) of the semiconductor device 10 . Figure 1B Shown along Figure 1A The cross-sectional view of the section along the dot-dash line A1-A2 is shown. Figure 1C Cross-sectional views along the dashed-dotted line B1 - B2 and the dashed-dotted line B3 - B4 are shown. Figure 2A is a perspective view of the semiconductor device 10. Note that Figure 1A and Figure 2A In the figure, a part of the components of the semiconductor device 10 (such as the insulating layer) is omitted. Figure 1A and Figure 2A Similarly, some components are omitted in the following drawings.

[0039] The semiconductor device 10 includes a transistor 100 and a transistor 200 .

[0040] Transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. Conductive layer 104 serves as a gate electrode. A portion of insulating layer 106 serves as a gate insulating layer. Conductive layer 112a serves as one of a source electrode and a drain electrode, and conductive layer 112b serves as the other of the source and drain electrodes. In semiconductor layer 108, the entire region overlapping the gate electrode with the gate insulating layer between the source and drain electrodes serves as a channel formation region. Furthermore, in semiconductor layer 108, the region in contact with the source electrode serves as a source region, and the region in contact with the drain electrode serves as a drain region.

[0041] A conductive layer 112a is provided on substrate 102. An insulating layer 110 is provided on conductive layer 112a. An insulating layer 120 is provided on insulating layer 110. A conductive layer 112b is provided on insulating layer 120. Insulating layers 110 and 120 include a region sandwiched between conductive layers 112a and 112b. Conductive layer 112a includes a region overlapping conductive layer 112b across insulating layers 110 and 120. Insulating layers 110 and 120 include openings 141 in the regions overlapping conductive layer 112a. Conductive layer 112a is exposed in openings 141. Conductive layer 112b includes openings 143 in the regions overlapping conductive layer 112a. Openings 143 are provided in the regions overlapping openings 141.

[0042] Semiconductor layer 108 is provided to cover openings 141 and 143. Semiconductor layer 108 includes regions in contact with the top and side surfaces of conductive layer 112b, the side surfaces of insulating layer 110, and the top surface of conductive layer 112a. Semiconductor layer 108 is electrically connected to conductive layer 112a via openings 141 and 143. Semiconductor layer 108 has a shape that conforms to the top and side surfaces of conductive layer 112b, the side surfaces of insulating layer 110, and the top surface of conductive layer 112a.

[0043] The insulating layer 106, which serves as a gate insulating layer for the transistor 100, is provided to cover the openings 141 and 143. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112 b, and the insulating layer 110. The insulating layer 106 includes a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112 b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shape of the top surface of the insulating layer 110, the top surface and side surfaces of the conductive layer 112 b, the top surface and side surfaces of the semiconductor layer 108, and the top surface of the conductive layer 112 a.

[0044] The conductive layer 104 serving as the gate electrode of the transistor 100 is provided over the insulating layer 106 and includes a region in contact with the top surface of the insulating layer 106. The conductive layer 104 includes a region overlapping with the semiconductor layer 108 via the insulating layer 106. The conductive layer 104 has a shape that follows the shape of the top surface of the insulating layer 106.

[0045] Transistor 100 is a so-called top-gate transistor, including a gate electrode above semiconductor layer 108. Furthermore, since the bottom surface of semiconductor layer 108 is in contact with the source and drain electrodes, it can be considered a TGBC (Top Gate Bottom Contact) transistor. Furthermore, in transistor 100, drain current flows in a direction perpendicular or approximately perpendicular to the surface of substrate 102, the substrate on which it is formed. Alternatively, the drain current in transistor 100 flows in a vertical direction or a substantially vertical direction, making transistor 100 a "vertical channel transistor."

[0046] The channel length of transistor 100 can be controlled by the thickness of the insulating layer provided between conductive layer 112a and conductive layer 112b. Therefore, a transistor having a channel length smaller than the limiting resolution of the exposure device used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic non-uniformity between multiple transistors 100 can be reduced. Therefore, the operation of the semiconductor device including transistor 100 is stable and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the circuit design freedom is improved, and the operating voltage of the semiconductor device can also be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0047] Transistor 200 includes conductive layer 204, insulating layer 106, semiconductor layer 208, insulating layer 195, conductive layer 212a, and conductive layer 212b. Conductive layer 204 serves as a gate electrode. A portion of insulating layer 106 serves as a gate insulating layer. Conductive layer 212a serves as one of a source electrode and a drain electrode, and conductive layer 212b serves as the other of the source electrode and the drain electrode.

[0048] In semiconductor layer 208, the entire region overlapping the gate electrode with the gate insulating layer between the source and drain electrodes serves as a channel formation region. Semiconductor layer 208 includes a pair of regions 208D sandwiching the channel formation region. One of the pair of regions 208D serves as a source region, and the other serves as a drain region. Region 208D can also be described as a region with a higher carrier concentration than the channel formation region, or a low-resistance region.

[0049] A semiconductor layer 208 is provided over the insulating layer 120. The semiconductor layer 208 can be formed using the same process as the semiconductor layer 108. An insulating layer 106 is provided over the semiconductor layer 208. The insulating layer 106 is provided in contact with the top and side surfaces of the semiconductor layer 208. A portion of the insulating layer 106 serves as the gate insulating layer of the transistor 100, while the remaining portion of the insulating layer 106 serves as the gate insulating layer of the transistor 200. A conductive layer 204 is provided over the insulating layer 106. The conductive layer 204 can be formed using the same process as the conductive layer 104.

[0050] An insulating layer 195 is provided to cover the conductive layer 104, the conductive layer 204, and the insulating layer 106. The insulating layer 195 serves as a protective layer for the transistors 100 and 200. A material that does not readily diffuse impurities is preferably used for the insulating layer 195. Providing the insulating layer 195 effectively suppresses the diffusion of impurities from the outside into the transistor, thereby improving the reliability of the display device. Examples of impurities include water and hydrogen. The insulating layer 195 may be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as an oxide, an oxynitride, a nitride oxide, or a nitride may be used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate may be used. For example, one or more of an acrylic resin and a polyimide resin may be used as the organic material. A photosensitive material may also be used as the organic material. Furthermore, two or more of the above insulating films may be stacked. The insulating layer 195 may have a stacked-layer structure of an insulating layer including an inorganic material and an insulating layer including an organic material.

[0051] Insulating layer 195 and insulating layer 106 include openings 147a and 147b that reach region 208D. Conductive layers 212a and 212b are provided to cover openings 147a and 147b. Conductive layer 212a is electrically connected to one of the pair of regions 208D, and conductive layer 212b is electrically connected to the other of the pair of regions 208D.

[0052] Transistor 200 is a so-called top-gate transistor that includes a gate electrode above semiconductor layer 208. For example, by adding an impurity element to semiconductor layer 208 using conductive layer 204, which serves as a gate electrode, as a mask, regions 208D serving as source and drain regions can be formed in a self-aligned manner. Transistor 200 can be considered a TGSA (Top Gate Self-Aligned) transistor.

[0053] The channel length of transistor 200 can be controlled by the length of conductive layer 204. Thus, the channel length of transistor 200 is greater than the resolution limit of the exposure equipment used in transistor manufacturing. By increasing the channel length, a transistor with high saturation can be realized.

[0054] Note that in this specification and other documents, a situation in which a current change in a saturation region of the Id-Vd characteristics of a transistor is small may be expressed as “high saturation”.

[0055] As described above, the transistor 100 with a short channel length and the transistor 200 with a long channel length can be formed on the same substrate by sharing some of the process steps. For example, by using the transistor 100 for a transistor requiring a large on-state current and the transistor 200 for a transistor requiring high saturation, a high-performance semiconductor device can be realized.

[0056] Figure 1A The top surface shapes of openings 147a and 147b are shown as being identical or substantially identical to the top surface shapes of openings 141 and 143, but one embodiment of the present invention is not limited thereto. The top surface shapes of openings 147a and 147b may also be different from the top surface shapes of openings 141 and 143. In addition, the top surface shapes of openings 147a and 147b may both be circular or elliptical, for example. The top surface shapes of openings 147a and 147b may both be polygonal, such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), or a pentagon, or these polygons may have rounded corners.

[0057] The detailed structures of the transistor 100 and the transistor 200 will be described.

[0058] The conductive layer 112a and the conductive layer 112b included in the transistor 100 may both have a stacked-layer structure. Figure 1B FIG. 1 shows a structure in which the conductive layer 112a has a stacked structure of a conductive layer 112a_1 and a conductive layer 112a_2 on the conductive layer 112a_1. Figure 1B As shown, the conductive layer 112a_2 includes an opening 145, in which the conductive layer 112a_1 is exposed. In the opening 145, the conductive layer 112a_1 includes a region in contact with the semiconductor layer 108. The conductive layer 112a_2 preferably does not include a region in contact with the semiconductor layer 108.

[0059] Figure 2B 14 is a perspective view schematically showing the conductive layer 112a. The conductive layer 112a_2 includes an opening 145 in a region overlapping with the conductive layer 112a_1. The conductive layer 112a_1 is exposed in the opening 145.

[0060] Figure 2C 1 is a perspective view schematically showing the conductive layer 112a, the conductive layer 112b, the opening 141, and the opening 143. Note that the opening 141 provided in the insulating layer 110 and the insulating layer 120 is shown by a dotted line. Figure 2C As shown, conductive layer 112b includes openings 143 in areas overlapping conductive layer 112a.

[0061] The top surface shapes of the openings 141 and 143 can be circular or elliptical. The top surface shapes of the openings 141 and 143 can also be polygonal shapes such as triangles, quadrangles (including rectangles, rhombuses, squares), pentagons, or the corners of these polygons are rounded. Figure 1A As shown, the top surfaces of openings 141 and 143 are preferably circular. By making the top surfaces of openings 141 and 143 circular, the processing accuracy when forming openings 141 and 143 can be improved, and fine openings 141 and 143 can be formed. Note that in this specification, circular is not limited to a perfect circle.

[0062] The end of the conductive layer 112b on the side of the opening 143 is preferably identical or approximately identical to the end of the insulating layer 120 on the side of the opening 141. The top surface shape of the opening 143 can also be said to be identical or approximately identical to the top surface shape of the opening 141. Note that in this specification, etc., the end of the conductive layer 112b on the side of the opening 143 refers to the end of the bottom surface of the conductive layer 112b on the side of the opening 143. The bottom surface of the conductive layer 112b refers to the surface on the side of the insulating layer 120. The end of the insulating layer 120 on the side of the opening 141 refers to the end of the top surface of the insulating layer 120 on the side of the opening 141. The top surface of the insulating layer 120 refers to the surface on the side of the conductive layer 112b. In addition, the top surface shape of the opening 143 refers to the shape of the end of the bottom surface of the conductive layer 112b on the side of the opening 143. The top surface shape of the opening 141 refers to the shape of the end of the top surface of the insulating layer 120 on the side of the opening 141.

[0063] The ends are consistent or roughly consistent, which can also be said to be aligned or roughly aligned. In the case where the ends are aligned or roughly aligned and the top surface shapes are consistent or roughly consistent, it can be said that at least a portion of their edges overlap each other between the stacked layers when viewed from above (also called from a plane). For example, this includes the case where the upper layer and the lower layer are processed by the same mask pattern or a portion of the same mask pattern. However, in reality, there are cases where the edges do not overlap, and sometimes the upper layer is located on the inner side of the lower layer or the upper layer is located on the outer side of the lower layer. In this case, it can also be said that "the ends are roughly aligned" or "the top surface shapes are roughly consistent."

[0064] The opening 141 can be formed using, for example, a resist mask for forming the opening 143. Specifically, a first insulating film to become the insulating layer 110, a second insulating film to become the insulating layer 120 on the first insulating film, a conductive film to become the conductive layer 112b on the second insulating film, and a resist mask on the conductive film are formed. After the opening 143 is formed in the conductive film using the resist mask, the opening 141 is formed in the first and second insulating films using the same resist mask. This allows the ends of the opening 141 to be aligned or substantially aligned with the ends of the opening 143. This structure simplifies the process.

[0065] The opening 141 may be formed after the opening 143 is formed, using a process different from that of the opening 143. There is no particular limitation on the order in which the openings 141 and 143 are formed. For example, after the opening 141 is formed in the first insulating film and the second insulating film, a conductive film to become the conductive layer 112 b may be formed, and the opening 143 may be formed in the conductive film.

[0066] The end of the conductive layer 112b on the side of the opening 143 may not coincide with the end of the insulating layer 120 on the side of the opening 141. That is, the top surface shape of the opening 143 may not coincide with the top surface shape of the opening 141. When viewed from above, the opening 143 preferably includes the opening 141. The end of the conductive layer 112b on the side of the opening 143 may be located outside the end of the insulating layer 120 on the side of the opening 141. The semiconductor layer 108 includes a region in contact with the top and side surfaces of the conductive layer 112b, the top and side surfaces of the insulating layer 120, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a. By adopting such a structure, the stage of the formed surface of the layer (for example, the semiconductor layer 108) formed on the conductive layer 112a, the conductive layer 112b, and the insulating layer 120 becomes smaller. Therefore, coverage of a layer formed over the conductive layer 112a, the conductive layer 112b, the insulating layer 110, and the insulating layer 120 can be improved, thereby suppressing occurrence of defects such as disconnection or voids in the layer.

[0067] Note that in this embodiment, openings 141 and 143 are provided in the insulating layer 110, the insulating layer 120, and the conductive layer 112b, and the semiconductor layer 108 is provided so as to cover the openings 141 and 143. However, one embodiment of the present invention is not limited to this. A semiconductor device according to one embodiment of the present invention may include a first region in which the insulating layer 110 and the insulating layer 120 are provided on the conductive layer 112a, and a second region in which the insulating layer 110 and the insulating layer 120 are not provided on the conductive layer 112a. In the transistor 100, the semiconductor layer 108 may be provided in a step formed by the first region and the second region. The insulating layer 106 may be provided on the semiconductor layer 108, and the conductive layer 104 may be provided so as to overlap the semiconductor layer 108 between the conductive layer 112a and the conductive layer 112b, with the insulating layer 106 interposed therebetween.

[0068] The semiconductor layer 108 preferably covers the end portion of the conductive layer 112 b on the opening 143 side. Figure 1B, etc., show a structure in which the end of semiconductor layer 108 is located on conductive layer 112b. The end of semiconductor layer 108 can also be said to be in contact with the top surface of conductive layer 112b. Alternatively, semiconductor layer 108 may extend to cover the end of conductive layer 112b that does not face opening 143. The end of semiconductor layer 108 may also be in contact with the top surface of insulating layer 120.

[0069] Figure 3A 1 is a perspective view schematically showing the conductive layer 112a and the semiconductor layer 108 included in the transistor 100 and the semiconductor layer 208 included in the transistor 200. Figure 3A As shown, the semiconductor layer 108 is provided in a manner covering the opening 141 and the opening 143. Figure 1B As shown in FIG. 1 , in the opening 141, the semiconductor layer 108 includes a region in contact with the top surface of the conductive layer 112a. Specifically, in the opening 141, the semiconductor layer 108 preferably includes a region in contact with the top surface of the conductive layer 112a_1. The semiconductor layer 208 can be formed by the same process as the semiconductor layer 108. Figure 1B As shown in FIG. 1 , the semiconductor layer 208 is provided on the insulating layer 120. In addition, the semiconductor layer 108 and the semiconductor layer 208 may be formed by different processes. The semiconductor layer 108 and the semiconductor layer 208 may also be formed using different materials.

[0070] exist Figure 1B Although the semiconductor layer 108 and the semiconductor layer 208 both have a single-layer structure, one embodiment of the present invention is not limited thereto. The semiconductor layer 108 and the semiconductor layer 208 may both have a stacked-layer structure of two or more layers.

[0071] Figure 3B 1 is a perspective view schematically showing the conductive layer 112a and the conductive layer 104 included in the transistor 100 and the conductive layer 204 included in the transistor 200. Figure 3B As shown, the conductive layer 104 is provided in a manner covering the opening 141 and the opening 143. The conductive layer 204 can be formed by the same process as the conductive layer 104. Figure 1B As shown in FIG. 1 and FIG. 2 , the conductive layer 104 and the conductive layer 204 are disposed on the insulating layer 106 .

[0072] like Figure 1BAs shown in Figures 1 and 2, in the openings 141 and 143 of the transistor 100, the conductive layer 104 includes a region that overlaps with the semiconductor layer 108 via the insulating layer 106. Furthermore, the conductive layer 104 includes a region that overlaps with the conductive layer 112a via the insulating layer 106 and the semiconductor layer 108, and a region that overlaps with the conductive layer 112b via the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 preferably covers the end portion of the conductive layer 112b on the side of the opening 143. By adopting this structure, the entire region of the semiconductor layer 108 that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode can be used as a channel formation region. Alternatively, the conductive layer 104 may extend to cover the end portion of the conductive layer 112b that does not face the opening 143. Alternatively, the conductive layer 104 may extend to cover the end portion of the semiconductor layer 108.

[0073] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can all be used as wiring. The transistor 100 can be arranged in an area where these wirings overlap, thereby reducing the area occupied by the transistor 100 and the wiring in the transistor 100 and the circuit including the wiring. Therefore, the area occupied by the circuit can be reduced to realize a small semiconductor device. For example, when a semiconductor device of one embodiment of the present invention is used in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be realized. In addition, when used in a driving circuit (for example, a gate line driving circuit and a source line driving circuit) of a display device, the area occupied by the driving circuit can be reduced, so that a display device with a narrow frame can be realized.

[0074] In the semiconductor device of one embodiment of the present invention, the conductive layers 112a, 112b, 104, and 204 used as wiring are provided in different layers. This allows wiring to be arranged in each layer, improves layout flexibility, and reduces the circuit footprint.

[0075] Here, refer to Figure 4A and Figure 4B The channel length and channel width of the transistor 100 will be described. Figure 4A is a top view of transistor 100 . Figure 4B yes Figure 1B An enlarged view of transistor 100 is shown.

[0076] In the semiconductor layer 108, the region in contact with the conductive layer 112a is used as one of the source region and the drain region, the region in contact with the conductive layer 112b is used as the other of the source region and the drain region, and the region between the source region and the drain region is used as a channel formation region.

[0077] The channel length of transistor 100 is the distance between the source region and the drain region. Figure 4BThe dotted double arrow in FIG. 1 represents a channel length L100 of the transistor 100. The channel length L100 is the distance between the end of the region where the semiconductor layer 108 contacts the conductive layer 112a and the end of the region where the semiconductor layer 108 contacts the conductive layer 112b in the cross section.

[0078] Here, the channel length L100 of transistor 100 corresponds to the sum of the length of the side surface of insulating layer 110 on the side of opening 141 and the length of the side surface of insulating layer 120 on the side of opening 141 in a cross section. Specifically, channel length L100 is determined by the thickness T110 of insulating layer 110, the thickness T120 of insulating layer 120, and the angle θ110 formed between the side surface of insulating layer 110 on the side of opening 141 and the surface on which insulating layer 110 is formed (here, the top surface of conductive layer 112a). It is not affected by the performance of the exposure equipment used to manufacture the transistor. Therefore, channel length L100 can be set to a value smaller than the limiting resolution of the exposure equipment, enabling the realization of a very fine transistor. For example, the channel length L100 is preferably 0.01 μm or more and less than 3 μm, more preferably 0.05 μm or more and less than 3 μm, more preferably 0.1 μm or more and less than 3 μm, more preferably 0.15 μm or more and less than 3 μm, more preferably 0.2 μm or more and less than 3 μm, more preferably 0.2 μm or more and 2.5 μm or less, more preferably 0.2 μm or more and 2 μm or less, more preferably 0.2 μm or more and 1.5 μm or less, more preferably 0.3 μm or more and 1.5 μm or less, more preferably 0.3 μm or more and 1.2 μm or less, more preferably 0.4 μm or more and 1.2 μm or less, more preferably 0.4 μm or more and 1 μm or less, more preferably 0.5 μm or more and 1 μm or less. Figure 4B In FIG. 1 , a double-dash arrow indicates a thickness T110 of the insulating layer 110 , and a double-dash arrow indicates a thickness T120 of the insulating layer 120 .

[0079] By reducing the channel length L100, the on-state current of transistor 100 can be increased. By using transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small semiconductor device can be realized. For example, when a semiconductor device according to one embodiment of the present invention is used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced when the number of wirings increases, thereby suppressing display unevenness. In addition, since the area occupied by the circuit can be reduced, the frame of the display device can be reduced.

[0080] By adjusting the thickness T110 of the insulating layer 110 , the thickness T120 of the insulating layer 120 , and the angle θ110 , the channel length L100 can be controlled.

[0081] The sum of the thickness T110 of the insulating layer 110 and the thickness T120 of the insulating layer 120 is preferably greater than or equal to 0.01 μm and less than 3 μm, more preferably greater than or equal to 0.05 μm and less than 3 μm, more preferably greater than or equal to 0.1 μm and less than 3 μm, more preferably greater than or equal to 0.15 μm and less than 3 μm, more preferably greater than or equal to 0.2 μm and less than 3 μm, more preferably greater than or equal to 0.2 μm and less than 2.5 μm, more preferably greater than or equal to 0.2 μm and less than 1.5 μm, more preferably greater than or equal to 0.3 μm and less than 1.5 μm, more preferably greater than or equal to 0.3 μm and less than 1.2 μm, more preferably greater than or equal to 0.4 μm and less than 1.2 μm, more preferably greater than or equal to 0.4 μm and less than 1 μm, more preferably greater than or equal to 0.5 μm and less than 1 μm.

[0082] The side surfaces of the insulating layer 110 and the insulating layer 120 on the side of the opening 141 preferably have a tapered shape. The angle θ110 formed by the side surface of the insulating layer 110 on the side of the opening 141 and the formed surface of the insulating layer 110 (here, the top surface of the conductive layer 112a) is preferably less than 90 degrees. By reducing the angle θ110, the coverage of the layer provided on the insulating layer 110 (for example, the semiconductor layer 108) can be improved. However, reducing the angle θ110 may reduce the contact area between the semiconductor layer 108 and the conductive layer 112a, thereby increasing the contact resistance between the semiconductor layer 108 and the conductive layer 112a. The angle θ110 is preferably 45 degrees or greater and less than 90 degrees, more preferably 50 degrees or greater and less than 90 degrees, more preferably 55 degrees or greater and less than 90 degrees, more preferably 60 degrees or greater and less than 90 degrees, more preferably 60 degrees or greater and less than 85 degrees, more preferably 65 degrees or greater and less than 85 degrees, more preferably 65 degrees or greater and less than 80 degrees, and more preferably 70 degrees or greater and less than 80 degrees. By setting the angle θ110 within the above range, the coverage of the layer (e.g., semiconductor layer 108) formed on the conductive layer 112a and the insulating layer 110 can be improved, thereby suppressing the occurrence of defects such as disconnection or voids in the layer. In addition, the contact resistance between the semiconductor layer 108 and the conductive layer 112a can be reduced.

[0083] Note that in Figure 4B , etc., show a configuration in which the side surfaces of the insulating layers 110 and 120 on the side of the opening 141 in cross section are straight lines, but one embodiment of the present invention is not limited thereto. The side surfaces of the insulating layers 110 and 120 on the side of the opening 141 in cross section may also be curved lines, or may include both straight and curved line areas.

[0084] Conductive layer 112b is preferably not provided inside opening 141. Specifically, conductive layer 112b preferably does not include a region in contact with the side surface of insulating layer 110 on the side of opening 141 and does not include a region in contact with the side surface of insulating layer 120 on the side of opening 141. If conductive layer 112b is also provided inside opening 141, channel length L100 of transistor 100 becomes shorter than the length of the side surfaces of insulating layer 110 and insulating layer 120, and thus control of channel length L100 may become difficult. Therefore, it is preferable that the top surface shape of opening 143 matches the top surface shape of opening 141, or that opening 143 includes opening 141 when viewed from above.

[0085] The channel width of transistor 100 is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction. In other words, the channel width is the width of the region where the semiconductor layer 108 contacts the conductive layer 112a or the width of the region where the semiconductor layer 108 contacts the conductive layer 112b in a direction perpendicular to the channel length direction. Here, the width of the region where the semiconductor layer 108 contacts the conductive layer 112b in a direction perpendicular to the channel length direction is used as the channel width of transistor 100. Figure 4A and Figure 4B The solid double arrow in FIG. 1 represents the channel width W100 of the transistor 100. The channel width W100 is the length of the circumference of the opening 143 in a plan view. Specifically, the channel width W100 is the length of the bottom end of the conductive layer 112b on the opening 143 side in a plan view.

[0086] The channel width W100 is determined by the top surface shape of the opening 143 . Figure 4A and Figure 4BThe double-dot chain arrow in FIG. 1 indicates the width D143 of the opening 143. The width D143 is the short side of the smallest rectangle circumscribing the opening 143 in a plan view. When the opening 143 is formed by photolithography, the width D143 of the opening 143 is greater than the limiting resolution of the exposure apparatus. The width D143 is, for example, preferably greater than or equal to 0.2 μm and less than 5 μm, more preferably greater than or equal to 0.2 μm and less than 4.5 μm, more preferably greater than or equal to 0.2 μm and less than 4 μm, more preferably greater than or equal to 0.2 μm and less than 3.5 μm, more preferably greater than or equal to 0.2 μm and less than 3 μm, more preferably greater than or equal to 0.2 μm and less than 2.5 μm, more preferably greater than or equal to 0.2 μm and less than 2 μm, more preferably greater than or equal to 0.2 μm and less than 1.5 μm, more preferably greater than or equal to 0.3 μm and less than 1.5 μm, more preferably greater than or equal to 0.3 μm and less than 1.2 μm, more preferably greater than or equal to 0.4 μm and less than 1.2 μm, more preferably greater than or equal to 0.4 μm and less than 1 μm, more preferably greater than or equal to 0.5 μm and less than 1 μm. Note that when the top surface of the opening 143 is circular, the width D143 corresponds to the diameter of the opening 143 , and the channel width W100 can be calculated as “D143×π”.

[0087] Next, refer to Figure 5A and Figure 5B The channel length and channel width of the transistor 200 will be described. Figure 5A is a top view of transistor 200 . Figure 5B yes Figure 1B An enlarged view of transistor 200 is shown.

[0088] In the semiconductor layer 208 , a pair of regions 208D serve as a source region and a drain region, and a region between the source region and the drain region serves as a channel formation region. The channel formation region includes a region overlapping with the conductive layer 204 via the insulating layer 106 .

[0089] The channel length of the transistor 200 is the length of the region where the semiconductor layer 208 and the conductive layer 204 overlap between the pair of regions 208D. Figure 5A and Figure 5B In the figure, the dotted double-headed arrow indicates the channel length L200 of transistor 200. The channel length L200 of transistor 200 is determined by the length of conductive layer 204 and is a value that exceeds the resolution limit of the exposure equipment used in transistor manufacturing. For example, channel length L200 can be 1.5 μm or greater. By increasing the channel length, a transistor with high saturation performance can be realized.

[0090] The channel width of the transistor 200 is the width of the region where the semiconductor layer 208 and the conductive layer 204 are in contact with each other in a direction perpendicular to the channel length direction. Figure 5A and Figure 5CIn FIG. 1 , the channel width W200 of the transistor 200 is indicated by a solid double arrow.

[0091] As described above, the channel length L100 of transistor 100 can be set to a value smaller than the limiting resolution of the exposure device, and the channel length L200 of transistor 200 can be set to a value greater than the limiting resolution of the exposure device. For example, by using transistor 100 as a transistor requiring a large on-state current and transistor 200 as a transistor requiring a high saturation characteristic, a high-performance semiconductor device 10 can be realized that utilizes the advantages of each transistor.

[0092] In the semiconductor device 10 according to one embodiment of the present invention, the transistor 100 and the transistor 200 having different structures and channel lengths can be formed on the substrate 102 using the same process. Specifically, the semiconductor layer 108 and the semiconductor layer 208 can be formed using the same process. A portion of the insulating layer 106 can be used as the gate insulating layer of the transistor 100, while the remaining portion of the insulating layer 106 can be used as the gate insulating layer of the transistor 200. The conductive layer 104 and the conductive layer 204 can be formed using the same process. Therefore, the manufacturing cost of the semiconductor device 10 can be reduced.

[0093] The components included in the semiconductor device of this embodiment will be described below.

[0094] <Components of Semiconductor Devices> [Semiconductor layer 108, semiconductor layer 208] There are no particular limitations on the semiconductor materials that can be used for the semiconductor layers 108 and 208. For example, a single-material semiconductor or a compound semiconductor can be used. For example, silicon or germanium can be used as a single-material semiconductor. For example, gallium arsenide and silicon germanium can be used as compound semiconductors. Organic substances having semiconductor properties or metal oxides having semiconductor properties (also called oxide semiconductors) can be used as compound semiconductors. Note that these semiconductor materials may also contain impurities as dopants.

[0095] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layers 108 and 208. An amorphous semiconductor or a crystalline semiconductor (a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a partial crystalline region thereof) can be used. The use of a crystalline semiconductor is preferred because it can suppress degradation of transistor characteristics.

[0096] Silicon can be used for both the semiconductor layer 108 and the semiconductor layer 208. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polycrystalline silicon (LTPS).

[0097] Transistors using amorphous silicon as their semiconductor layer can be formed on large glass substrates, enabling low-cost manufacturing. Transistors using polycrystalline silicon as their semiconductor layer have high field-effect mobility and are capable of high-speed operation. Furthermore, transistors using microcrystalline silicon as their semiconductor layer have higher field-effect mobility than transistors using amorphous silicon, enabling high-speed operation.

[0098] The semiconductor layer 108 and the semiconductor layer 208 preferably both contain a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is a metal element or a semi-metal element having a high bonding energy with oxygen, for example, a metal element or a semi-metal element having a higher bonding energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0099] The semiconductor layer 108 and the semiconductor layer 208 can use, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0100] Here, the composition of the metal oxide included in the semiconductor layer 108 and the semiconductor layer 208 has a significant influence on the electrical characteristics and reliability of the transistor 100 and the transistor 200 .

[0101] For example, by increasing the ratio of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, a transistor with high on-state current or high field-effect mobility can be realized. By using this transistor in a transistor requiring a large on-state current, a semiconductor device with excellent electrical characteristics can be realized.

[0102] Metal oxides can also replace In or contain one or more metal elements with large periodic numbers in the periodic table in addition to In. The greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large periodic number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large periodic number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0103] The metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field-effect mobility of the transistor. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0104] When using an In-Zn oxide as the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of the metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1, or a metal oxide in the vicinity thereof can be used.

[0105] When using an In-Sn oxide as the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of the metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1, or a ratio close thereto can be used.

[0106] When using In-Sn-Zn oxide as a semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin can be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin is preferably used. For example, the atomic ratios of the metal elements can be In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=5:1:9, In:Sn:Zn=5:1:10, In:Sn:Zn=5:1:11, In:Sn:Zn=5:1:12, In:Sn:Zn=5:1:13, In:Sn:Zn=5:1:14, In:Sn:Zn=5:1:15, In:Sn:Zn=5:1:16, In:Sn:Zn=5:1:17, In:Sn:Zn=5:1:18, In:Sn:Zn=5:1 ... n=6:1:6、In:Sn:Zn=10:1:3、In:Sn:Zn=10:1:6、In:Sn:Zn=10:1:7、In:Sn:Zn=10:1:8、In :Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10 or metal oxides near them.

[0107] When using In-Al-Zn oxide as a semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum can be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of aluminum is preferably used. For example, the atomic ratios of the metal elements can be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=5:1:9, In:Al:Zn=5:1:10, In:Al:Zn=5:1:11, In:Al:Zn=5:1:12, In:Al:Zn=5:1:13, In:Al:Zn=5:1:14, In:Al:Zn=5:1:15, In:Al:Zn=5:1:16, In:Al:Zn=5:1:17, In:Al:Zn=5:1:18, In:Al:Zn=5:1:19, In:Al:Zn=5:1:1 n=6:1:6, In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10 or metal oxides thereof.

[0108] When using In-Ga-Zn oxide as a semiconductor layer, a metal oxide in which the atomic number ratio of indium to the sum of the atomic numbers of all metal elements is higher than the atomic number ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic number ratio of zinc is higher than the atomic number ratio of gallium. For example, the semiconductor layer can use a metal element atomic number ratio of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=5:1:9, In:Ga:Zn=5:1:10, In:Ga:Zn=5:1:11, In:Ga:Zn=5:1:12, In:Ga:Zn=5:1:13, In:Ga:Zn=5:1:14, In:Ga:Zn=5:1:15, In:Ga:Zn=5:1:16, In:Ga:Zn=5:1:17, In:Ga:Zn=5:1:18, In:Ga:Zn=5:1:19, In:Ga:Zn=5:1:19, In:Ga:Zn=5:1:11 :Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereof.

[0109] When an In-M-Zn oxide is used as a semiconductor layer, a metal oxide can be used in which the atomic number ratio of indium relative to the sum of the atomic numbers of all metal elements contained is higher than the atomic number ratio of element M. Furthermore, it is more preferable to use a metal oxide in which the atomic number ratio of zinc is higher than the atomic number ratio of element M. For example, the semiconductor layer can use metal element atomic ratios of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M: Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10 or metal oxides thereabouts.

[0110] Note that when multiple metal elements are included as the element M, the sum of the atomic number ratios of the metal elements may be the atomic number ratio of the element M. For example, when an In-Ga-Al-Zn oxide containing gallium and aluminum as the element M is used, the sum of the atomic number ratio of gallium and the atomic number ratio of aluminum may be the atomic number ratio of the element M. Furthermore, the atomic number ratio of indium, the element M, and zinc is preferably within the above-mentioned range. For example, when an In-Ga-Sn-Zn oxide containing gallium and tin as the element M is used, the sum of the atomic number ratio of gallium and the atomic number ratio of tin may be the atomic number ratio of the element M. Furthermore, the atomic number ratio of indium, the element M, and zinc is preferably within the above-mentioned range.

[0111] It is preferred to use a metal oxide in which the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In-Ga-Zn oxide is used as the semiconductor layer, the ratio of the number of indium atoms to the sum of the number of atoms of indium, element M, and zinc is preferably within the above range.

[0112] In this specification, etc., the ratio of the number of indium atoms to the total number of atoms of all contained metal elements may be described as the indium content. The same applies to other metal elements.

[0113] The composition of the metal oxide can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of the above methods can be used for analysis. Note that the actual content of elements with low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0114] In this specification, etc., the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, a composition having an atomic ratio of In:M:Zn = 4:2:3 or a composition thereof includes the following: when the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Furthermore, a composition having an atomic ratio of In:M:Zn = 5:1:6 or a composition thereof includes the following: when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, a composition having an atomic ratio of In:M:Zn = 1:1:1 or a composition thereof includes the following: when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is greater than 0.1 and 2 or less.

[0115] The metal oxide can be formed using sputtering or atomic layer deposition (ALD) as appropriate. Note that when forming the metal oxide using sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of zinc in the target. Specifically, the atomic ratio of zinc may be between approximately 40% and 90% of the atomic ratio of zinc in the target.

[0116] Here, we will explain the reliability of transistors. One of the indicators for evaluating the reliability of transistors is the GBT (Gate Bias Temperature) stress test, which involves maintaining an electric field applied to the gate. The PBTS (Positive Bias Temperature Stress) test involves maintaining the gate at a high temperature while applying a positive potential (positive bias) relative to the source and drain potentials, while maintaining the gate at a high temperature. The NBTS (Negative Bias Temperature Stress) test involves maintaining the gate at a high temperature while applying a negative potential (negative bias) relative to the source and drain potentials. Furthermore, the PBTS test and the NBTS test, performed under light irradiation, are referred to as the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0117] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on (current flowing). Therefore, the fluctuation of the threshold voltage in the PBTS test is one of the important factors to be considered as an indicator of transistor reliability.

[0118] By using a metal oxide that contains no gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability in response to forward bias can be realized. In other words, a transistor with minimal fluctuation in threshold voltage during PBTS testing can be realized. Furthermore, when using a metal oxide containing gallium, the gallium content is preferably lower than the indium content. This allows for the realization of a highly reliable transistor.

[0119] One of the factors that causes threshold voltage fluctuations during PBTS testing is defect states at or near the interface between the semiconductor layer and the gate insulating layer. The greater the density of defect states, the more pronounced the degradation during PBTS testing. Reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer can suppress the generation of these defect states.

[0120] The reason why the threshold voltage fluctuation in the PBTS test can be suppressed by using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer is, for example, as follows. Gallium contained in the metal oxide is more likely to absorb oxygen than other metal elements (such as indium or zinc). Therefore, it can be inferred that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, carrier (here, electron) trap sites are easily generated by bonding between gallium and excess oxygen in the gate insulating layer. Therefore, when a positive potential is applied to the gate, carriers are captured at the interface between the semiconductor layer and the gate insulating layer, and the threshold voltage fluctuates.

[0121] More specifically, when using an In-Ga-Zn oxide as the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer. More preferably, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium is used. In other words, a metal oxide in which the atomic ratio of the metal elements satisfies In>Ga and Zn>Ga is preferably used for the semiconductor layer.

[0122] The semiconductor layer preferably uses a metal oxide in which the ratio of the number of atoms of gallium relative to the sum of the number of atoms of all metal elements is higher than 0 atomic % and less than 50 atomic %, preferably greater than 0.1 atomic % and less than 40 atomic %, more preferably greater than 0.1 atomic % and less than 35 atomic %, more preferably greater than 0.1 atomic % and less than 30 atomic %, more preferably greater than 0.1 atomic % and less than 25 atomic %, more preferably greater than 0.1 atomic % and less than 20 atomic %, more preferably greater than 0.1 atomic % and less than 15 atomic %, more preferably greater than 0.1 atomic % and less than 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be realized. Note that by containing gallium in the metal oxide, it is less likely to generate oxygen vacancies (V O : Oxygen Vacancy) effect.

[0123] As a semiconductor layer, a metal oxide that does not contain gallium can also be used. For example, In-Zn oxide can be used for the semiconductor layer. In this case, when the ratio of the number of atoms of indium relative to the sum of the number of atoms of all metal elements in the metal oxide is increased, the field effect mobility of the transistor can be improved. On the other hand, when the ratio of the number of atoms of zinc relative to the sum of the number of atoms of all metal elements in the metal oxide is increased, the metal oxide has high crystallinity, so the variation of the electrical characteristics of the transistor is suppressed, and the reliability can be improved. In addition, as a semiconductor layer, a metal oxide that does not contain gallium and zinc, such as indium oxide, can also be used. By using a metal oxide that does not contain gallium, the variation of the threshold voltage in the PBTS test can be made extremely small, in particular.

[0124] For example, an oxide containing indium and zinc can be used as the semiconductor layer. In this case, for example, a metal oxide having an atomic ratio of the metal elements of In:Zn=2:3, In:Zn=4:1, or a ratio thereof can be used.

[0125] Note that although gallium is used as an example in the description, the present invention can also be applied to the case where element M is used instead of gallium. A metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M is preferably used as the semiconductor layer. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M is preferably used.

[0126] By using a metal oxide with a low content of element M as a semiconductor layer, a transistor with high reliability under forward bias can be realized. By using this transistor as a transistor that needs to have high reliability under forward bias, a highly reliable semiconductor device can be realized.

[0127] Next, the reliability of transistors with respect to light will be described.

[0128] Light incident on a transistor can sometimes cause changes in its electrical characteristics. It is particularly desirable that transistors used in areas where light is likely to enter exhibit minimal changes in their electrical characteristics under light irradiation and exhibit high reliability against light. Reliability against light can be evaluated, for example, by measuring the fluctuation in threshold voltage during NBTIS testing.

[0129] By increasing the content of the element M in the metal oxide, a transistor with high reliability against light can be realized. In other words, a transistor with a small fluctuation in threshold voltage during NBTIS testing can be realized. Specifically, a metal oxide in which the atomic number ratio of the element M is greater than or equal to the atomic number ratio of indium has a larger band gap, which can reduce the fluctuation in threshold voltage during NBTIS testing of the transistor. The band gap of the metal oxide included in the semiconductor layer is preferably 2.0 eV or greater, more preferably 2.5 eV or greater, more preferably 3.0 eV or greater, more preferably 3.2 eV or greater, more preferably 3.3 eV or greater, more preferably 3.4 eV or greater, and more preferably 3.5 eV or greater.

[0130] For example, the semiconductor layer can use a metal oxide having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4 or thereabouts.

[0131] The semiconductor layer can particularly appropriately use the following metal oxides: the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements is greater than 20 atomic % and less than 70 atomic %, preferably greater than 30 atomic % and less than 70 atomic %, more preferably greater than 30 atomic % and less than 60 atomic %, more preferably greater than 40 atomic % and less than 60 atomic %, and more preferably greater than 50 atomic % and less than 60 atomic %.

[0132] When an In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the atomic ratio of indium to the total atomic number of all metal elements contained is less than or equal to the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal elements is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a metal oxide in the vicinity thereof can be used.

[0133] The semiconductor layer particularly preferably uses the following metal oxide: the ratio of the number of gallium atoms to the sum of the number of atoms of all metal elements is greater than 20 atomic % and less than 60 atomic %, preferably greater than 20 atomic % and less than 50 atomic %, more preferably greater than 30 atomic % and less than 50 atomic %, more preferably greater than 40 atomic % and less than 60 atomic %, and more preferably greater than 50% atomic % and less than 60 atomic %.

[0134] A transistor with high reliability against light can be realized by using a metal oxide with a high content of element M for the semiconductor layer. A highly reliable semiconductor device can be realized by using this transistor as a transistor that needs to have high reliability against light.

[0135] By increasing the content of element M, the oxygen vacancies (V O ) is formed. Therefore, by using a metal oxide with a high content of element M as a semiconductor layer, oxygen vacancies (V O ) is suppressed, thereby realizing a transistor with low off-state current. In addition, the variation in the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0136] Furthermore, increasing the zinc content results in a highly crystalline metal oxide, which can suppress the diffusion of impurities in the metal oxide. Therefore, using a metal oxide with a high zinc content as a semiconductor layer can suppress variations in the transistor's electrical characteristics, thereby improving reliability.

[0137] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device with both excellent electrical characteristics and high reliability can be realized.

[0138] The semiconductor layer may also have a stacked structure comprising two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer may also have the same or substantially the same composition. By employing a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0139] The two or more metal oxide layers included in the semiconductor layer may also have different compositions. For example, a stacked structure may suitably include a first metal oxide layer having an atomic ratio of In:M:Zn = 1:3:4 or a composition thereof, and a second metal oxide layer having an atomic ratio of In:M:Zn = 1:1:1 or a composition thereof disposed on the first metal oxide layer. Furthermore, gallium or aluminum is particularly preferably used as the element M. For example, a stacked structure may include any one selected from indium oxide, indium gallium oxide, and IGZO, and any one selected from IAZO, IAGZO, and ITZO (registered trademark).

[0140] A crystalline metal oxide layer is preferably used as the semiconductor layer. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nanocrystalline (nc) structure can be used. Using a crystalline metal oxide layer as the semiconductor layer can reduce the defect state density in the semiconductor layer, thereby achieving a highly reliable semiconductor device.

[0141] The higher the crystallinity of the metal oxide layer used for the semiconductor layer, the lower the defect state density in the semiconductor layer can be. On the other hand, using a metal oxide layer with low crystallinity can realize a transistor capable of passing a large current.

[0142] When forming a metal oxide layer using a sputtering method, the higher the substrate temperature during formation, the more crystalline the metal oxide layer can be formed. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. In addition, the higher the flow rate ratio of the oxygen gas relative to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio) or the oxygen partial pressure within the processing chamber, the more crystalline the metal oxide layer can be formed.

[0143] The semiconductor layer may also have a stacked structure of two or more metal oxide layers having different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may include a region having higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may include a region having lower crystallinity than the first metal oxide layer. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. For example, by using the same sputtering target and making the oxygen flow ratio or oxygen partial pressure different, a stacked structure of two or more metal oxide layers having different crystallinity can be formed. Note that the compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other.

[0144] The thickness of the semiconductor layer 108 and the semiconductor layer 208 is preferably greater than 3 nm and less than 100 nm, more preferably greater than 5 nm and less than 100 nm, more preferably greater than 10 nm and less than 100 nm, more preferably greater than 10 nm and less than 70 nm, more preferably greater than 15 nm and less than 70 nm, more preferably greater than 15 nm and less than 50 nm, more preferably greater than 20 nm and less than 50 nm, more preferably greater than 20 nm and less than 40 nm, more preferably greater than 25 nm and less than 40 nm.

[0145] The substrate temperature during formation of the semiconductor layers 108 and 208 is preferably room temperature (25° C.) or higher and 200° C. or lower, more preferably room temperature or higher and 130° C. or lower. By adopting a substrate temperature within this range, warping or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0146] Here, oxygen vacancies that may be formed in the semiconductor layer will be described.

[0147] When an oxide semiconductor is used as a semiconductor layer, hydrogen in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, thereby forming oxygen vacancies (V O ). In addition, sometimes hydrogen enters the defect in the oxygen vacancy (hereinafter referred to as V O H) is used as a donor to generate electrons as carriers. In addition, sometimes due to the bonding of a portion of hydrogen to the oxygen bonded to the metal atom, electrons as carriers are generated. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have a normally-on characteristic. In addition, because the hydrogen in the oxide semiconductor is easily moved due to heat, electric field, etc., when the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0148] VO H can be used as a donor in oxide semiconductors. However, it is difficult to quantitatively evaluate this defect. Therefore, in oxide semiconductors, evaluation is sometimes performed based on carrier concentration rather than donor concentration. Therefore, in this specification, etc., as a parameter of an oxide semiconductor, instead of donor concentration, the carrier concentration in a state where no electric field is applied is sometimes used. In other words, the "carrier concentration" described in this specification, etc. may sometimes be referred to as the "donor concentration."

[0149] Therefore, when an oxide semiconductor is used as a semiconductor layer, it is preferable to minimize the V O H to make it high purity intrinsic or substantially high purity intrinsic. In order to obtain this V O For an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities (e.g., water and hydrogen) in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to repair oxygen vacancies (V O ). By placing oxygen vacancies (V O ), V O Oxide semiconductors with sufficiently reduced H and impurities are used in the channel formation region of transistors to provide stable electrical characteristics. Note that oxygen is sometimes supplied to the oxide semiconductor to repair oxygen vacancies (V O ) is recorded as oxidation treatment.

[0150] When an oxide semiconductor is used as the semiconductor layer, the carrier concentration of the oxide semiconductor in the region serving as the channel formation region is preferably 1×10 18 cm -3 Below, more preferably less than 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , more preferably less than 1×10 12 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the region serving as the channel formation region is not particularly limited, and can be set to, for example, 1×10 -9 cm -3 .

[0151] The region 208D used as the source region or the drain region can be considered to be a region with lower resistance than the channel formation region, a region with higher carrier concentration, a region with higher oxygen vacancy density, a region with higher hydrogen concentration, or a region with higher impurity concentration. The carrier concentration in the region 208D can be, for example, 5×10 18 cm -3More than, preferably 1×10 19 cm -3 More than 5×10 19 cm -3 The upper limit of the carrier concentration in the region 208D is not particularly limited, but can be, for example, 5×10 21 cm -3 or 1×10 22 cm -3 .

[0152] The higher the resistance of the channel formation region in the state where no channel is formed, the better. For example, the sheet resistance value of the channel formation region is preferably 1×10 9 Ω / □ or more, more preferably 5×10 9 Ω / □ or more, more preferably 1×10 10 Ω / □ or more.

[0153] Since the resistance of the channel formation region in the state where no channel is formed is as high as possible, there is no need to set an upper limit. However, if an upper limit is set, for example, the sheet resistance of the channel formation region is preferably 1×10 9 Ω / □ or more and 1×10 12 Ω / □ or less, more preferably 5×10 9 Ω / □ or more and 1×10 12 Ω / □ or less, more preferably 1×10 10 Ω / □ or more and 1×10 12 Ω / □ or less.

[0154] The lower the resistance of the region 208D, the better. For example, the sheet resistance of the region 208D is preferably greater than 1Ω / □ and less than 1×10 3 Ω / □, more preferably 1Ω / □ or more and 8×10 2 Ω / □ or less.

[0155] The resistance of the channel formation region in a state where no channel is formed may be 1×10 6 times or more and 1×10 12 times or less, preferably 1×10 6 times or more and 1×10 11 times or less, more preferably 1×10 6 times or more and 1×10 10 times or less.

[0156] Region 208D is a region containing an impurity element. As the impurity element, one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or a noble gas can be used. As the impurity element, one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or a noble gas can be used. Particularly preferably, one or more of boron, phosphorus, aluminum, magnesium, and silicon are used.

[0157] The region 208D is formed by, for example, using the conductive layer 204 as a mask and supplying the impurity element to the semiconductor layer 208 through the insulating layer 106 .

[0158] The semiconductor layer 108 and the semiconductor layer 208 can be formed using the same process. In other words, the semiconductor layer 108 and the semiconductor layer 208 can be formed using the same material. For example, the semiconductor layer 108 and the semiconductor layer 208 can be formed using the same sputtering target, thereby reducing manufacturing costs.

[0159] Alternatively, when forming the region 208D, the conductive layer 104 may be used as a mask, and the impurity element may be supplied to the semiconductor layer 108 through the insulating layer 106. Consequently, the region 108D is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Note that in the transistor 100, a region of the semiconductor layer 108 that is in contact with the conductive layer 112b serves as a source region or a drain region. The region 108D is formed in a portion of this source region or drain region. Alternatively, the region 108D may not be formed. For example, if the conductive layer 104 extends to cover an end portion of the semiconductor layer 108, the entire semiconductor layer 108 is covered by the conductive layer 104, and thus, the impurity element is not supplied to the semiconductor layer 108, and the region 108D is not formed.

[0160] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a very high field-effect mobility. In addition, the leakage current between the source and drain of the OS transistor in the off state (hereinafter also referred to as the off-state current) is extremely small, which can maintain the charge stored in the capacitor connected in series with the transistor for a long time. In addition, by using OS transistors, the power consumption of semiconductor devices can be reduced.

[0161] A semiconductor device according to one embodiment of the present invention can be applied to a display device, for example. When increasing the brightness of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To this end, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because the source-drain withstand voltage of an OS transistor is higher than that of a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be increased, thereby improving the brightness of the light-emitting device.

[0162] When operating in the saturation region, OS transistors can make changes in the source-drain current smaller than those of Si transistors in response to changes in the gate-source voltage. Therefore, by using OS transistors as driver transistors in pixel circuits, the current flowing between the source and drain can be precisely determined based on changes in the gate-source voltage, allowing the amount of current flowing through the light-emitting device to be controlled. This increases the number of grayscales in the pixel circuit.

[0163] Regarding the saturation of the current flowing through the transistor when operating in the saturation region, compared to Si transistors, OS transistors can allow a stable current (saturation current) to flow even when the source-drain voltage is gradually increased. Therefore, by using OS transistors as drive transistors, a stable current can flow through the light-emitting device even if, for example, the current-voltage characteristics of the light-emitting device are uneven. In other words, when the OS transistor operates in the saturation region, even if the source-drain voltage is increased, the source-drain current remains almost unchanged, thereby stabilizing the light emission brightness of the light-emitting device.

[0164] As described above, by using an OS transistor as a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black blur," "increase in emission brightness," "multi-gradation," "suppression of unevenness in light-emitting devices," and the like.

[0165] OS transistors have little change in electrical characteristics due to exposure to radiation, that is, they have high tolerance to radiation, so they can be appropriately used in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be appropriately used as pixel circuits for flat-panel detectors of X-rays. In addition, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0166] [Insulation layer 110, insulation layer 120] The insulating layer 110 may be made of an inorganic insulating material or an organic insulating material, or may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0167] Inorganic insulating materials can be used as appropriate for the insulating layer 110. As the inorganic insulating material, one or more of oxides, oxynitrides, oxynitrides, and nitrides can be used. For example, the insulating layer 110 can be made of one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon oxynitride, and aluminum nitride.

[0168] Note that in this specification and other documents, "oxynitride" refers to a material containing more oxygen than nitrogen. "Oxynitride" refers to a material containing more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon oxynitride" refers to a material containing more nitrogen than oxygen.

[0169] For example, oxygen and nitrogen content can be analyzed using analytical techniques such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When the target element content is high (e.g., 0.5 atomic% or greater, or 1 atomic% or greater), XPS analysis is preferred. On the other hand, when the target element content is low (e.g., less than 0.5 atomic% or less than 1 atomic%), SIMS analysis is preferred. When comparing elemental contents, a combined analysis using both SIMS and XPS is more preferred.

[0170] The insulating layer 110 may also have a stacked structure of two or more layers. Figure 1B , etc., shows a structure in which the insulating layer 110 has a stacked structure of an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layers 110a, 110b, and 110c can all use the materials that can be used for the insulating layer 110 described above. Note that the insulating layers 110a, 110b, and 110c can be made of the same material or different materials. Note that the insulating layers 110a, 110b, and 110c can also have a stacked structure of two or more layers.

[0171] The thickness of insulating layer 110b can be greater than that of insulating layer 110a. The thickness of insulating layer 110b can be greater than that of insulating layer 110c. The deposition rate of insulating layer 110b is preferably fast. In particular, when the thickness of insulating layer 110b is large, the deposition rate of insulating layer 110b is preferably fast. By increasing the deposition rate of insulating layer 110b, productivity can be improved. For example, increasing the power used during the formation of insulating layer 110b can increase the deposition rate.

[0172] The insulating layer 110b may also have a stacked structure of two or more layers. For example, when the insulating layer 110b is thick, the stress in the insulating layer 110b is high, sometimes causing the substrate to warp. By forming the insulating layer 110b in multiple layers, it is sometimes possible to suppress process problems caused by stress. Note that in cross-sectional transmission electron microscopy (TEM) images, etc., the boundaries between the layers constituting the insulating layer 110b are sometimes unclear.

[0173] The stress of the insulating layer 110b is preferably low. When the insulating layer 110b is thick, the stress of the insulating layer 110b is high, which may cause the substrate to warp. By reducing the stress of the insulating layer 110b, the occurrence of process problems caused by stress such as substrate warping can be suppressed.

[0174] The insulating layer 110a and the insulating layer 110c are used as barrier films to suppress gas from escaping from the insulating layer 110b. The insulating layer 110a and the insulating layer 110c are preferably made of a material that does not easily diffuse gas. The insulating layer 110a and the insulating layer 110c preferably include a region with a higher film density than the insulating layer 110b. By increasing the film density of the insulating layer 110a and the insulating layer 110c, the barrier properties can be improved. The film densities of the insulating layer 110a and the insulating layer 110c can also be different. For example, the insulating layer 110a and the insulating layer 110c can be made of a material that contains more nitrogen than the insulating layer 110b. By increasing the nitrogen content of the insulating layer 110a and the insulating layer 110c, the barrier properties can be improved. The nitrogen content of the insulating layer 110a and the insulating layer 110c can also be different.

[0175] The insulating layer 110a and the insulating layer 110c only need to have a thickness sufficient to function as a barrier film to suppress gas from escaping from the insulating layer 110b, and may be thinner than the insulating layer 110b. The insulating layer 110a and the insulating layer 110c may also have different thicknesses. The deposition rate of the insulating layer 110a and the insulating layer 110c is preferably slower than the deposition rate of the insulating layer 110b. Note that by slowing down the deposition rate of the insulating layer 110a and the insulating layer 110c, the film density is increased, thereby improving the barrier properties. Similarly, by increasing the substrate temperature during the deposition of the insulating layer 110a and the insulating layer 110c, the film density is increased, thereby improving the barrier properties.

[0176] The film density can be evaluated, for example, using Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR). In addition, the difference in film density can sometimes be evaluated by a cross-sectional transmission electron microscope (TEM) image. In TEM observation, the transmission electron (TE) image is darker (darker) when the film density is high, and the transmission electron (TE) image is lighter (brighter) when the film density is low. Therefore, in the transmission electron (TE) image, the insulating layer 110a and the insulating layer 110c sometimes appear as darker (darker) images compared to the insulating layer 110b. Note that even if the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c use the same material, the film density is different, so sometimes these boundaries can be observed as different contrasts in the cross-sectional TEM image.

[0177] The difference in nitrogen content among the insulating layers 110a, 110b, and 110c can be confirmed using, for example, EDX. For example, when silicon nitride is used for the insulating layer 110a and silicon oxynitride is used for the insulating layer 110b, the ratio of the peak height of nitrogen relative to the peak height of silicon in the insulating layer 110a is higher than the ratio of the peak height of nitrogen relative to the peak height of silicon in the insulating layer 110b. When silicon nitride is used for the insulating layer 110c and silicon oxynitride is used for the insulating layer 110b, the ratio of the peak height of nitrogen relative to the peak height of silicon in the insulating layer 110c is higher than the ratio of the peak height of nitrogen relative to the peak height of silicon in the insulating layer 110b. Note that in EDX, the peak of a certain element refers to the point at which the count of the element reaches a maximum value in a spectrum in which the horizontal axis represents the energy of the characteristic X-ray and the vertical axis represents the count (detection value) of the characteristic X-ray. Alternatively, the difference in nitrogen content can be confirmed using the count at the energy of the characteristic X-ray inherent to the element as the ratio of the nitrogen count to the silicon count. For example, silicon can be counted at 1.739 keV (Si-Kα), and nitrogen can be counted at 0.392 keV (N-Kα). The ratio of nitrogen counts to silicon counts in insulating layer 110a is higher than the ratio of nitrogen counts to silicon counts in insulating layer 110b. The ratio of nitrogen counts to silicon counts in insulating layer 110c is higher than the ratio of nitrogen counts to silicon counts in insulating layer 110b.

[0178] Insulating layer 110a and insulating layer 110c may include regions where the hydrogen concentration in the films is lower than that in insulating layer 110b. The difference in hydrogen concentration among insulating layer 110a, insulating layer 110b, and insulating layer 110c can be evaluated using, for example, secondary ion mass spectrometry (SIMS).

[0179] Here, the insulating layer 110 will be described in detail by taking a structure in which the semiconductor layer 108 is made of metal oxide as an example.

[0180] When an oxide semiconductor is used for the semiconductor layer 108 , an inorganic insulating material can be appropriately used for the insulating layers 110 a , 110 b , and 110 c .

[0181] The insulating layer 110b is preferably made of oxide or oxynitride. The insulating layer 110b is preferably made of a film that releases oxygen by heating. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulating layer 110b.

[0182] Oxygen is released through the insulating layer 110b, and oxygen can be supplied from the insulating layer 110b to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, especially to the channel formation region of the semiconductor layer 108, oxygen vacancies (V O ) and V O H, a transistor with excellent electrical characteristics and high reliability can be realized. The insulating layer 110 b preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient of the insulating layer 110 b, oxygen can be easily diffused into the insulating layer 110 b, and oxygen can be efficiently supplied from the insulating layer 110 b to the semiconductor layer 108. Note that as a treatment for supplying oxygen to the semiconductor layer 108, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere can be used.

[0183] Oxygen vacancies (V O ) and V O H is preferably small. In particular, when the channel length L100 is small, the oxygen vacancies (V O ) and V O H has a great impact on electrical characteristics and reliability. For example, in V O When H diffuses from the source region or the drain region into the channel formation region, the carrier concentration in the channel formation region may increase, causing a change in the threshold voltage of the transistor 100 or a decrease in reliability. O The greater the effect of H diffusion on electrical characteristics and reliability, the greater the effect of H diffusion on electrical characteristics and reliability. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, especially the channel formation region of the semiconductor layer 108, oxygen vacancies (V O ) and V O H. Therefore, a transistor with a small channel length having good electrical characteristics and high reliability can be realized.

[0184] It is preferable that the amount of impurities (eg, water and hydrogen) released from the insulating layer 110b itself is small. Since the amount of impurities released from the insulating layer 110b is small, diffusion of the impurities into the semiconductor layer 108 can be suppressed, thereby realizing a transistor having good electrical characteristics and high reliability.

[0185] The insulating layer 110b can be appropriately made of, for example, silicon oxide or silicon oxynitride using a PECVD method. In this case, it is preferable to use a mixed gas of a silicon-containing gas and an oxygen-containing gas as the source gas. As the silicon-containing gas, for example, any one or more of silane, disilane, trisilane, and fluorinated silane can be used. As the oxygen-containing gas, for example, any one or more of oxygen (O2), ozone (O3), nitrous oxide (N2O), nitric oxide (NO), and nitrogen dioxide (NO2) can be used. Note that by increasing the power when forming the insulating layer 110b, the amount of impurities (for example, water and hydrogen) released from the insulating layer 110b can be reduced.

[0186] The insulating layers 110a and 110c are preferably not easily permeable to oxygen. The insulating layers 110a and 110c function as barrier films that prevent oxygen from escaping from the insulating layer 110b. Furthermore, the insulating layers 110a and 110c are preferably not easily permeable to hydrogen. The insulating layers 110a and 110c function as barrier films that prevent hydrogen from diffusing from the outside of the transistor through the insulating layer 110 into the semiconductor layer 108. The insulating layers 110a and 110c preferably have a high film density. Increasing the film density of the insulating layers 110a and 110c improves the barrier properties to oxygen and hydrogen. The film density of the insulating layers 110a and 110c is preferably higher than that of the insulating layer 110b. When silicon oxide or silicon oxynitride is used as the insulating layer 110b, silicon nitride, silicon oxynitride, or aluminum oxide can be used, for example, as appropriate, for the insulating layers 110a and 110c. The insulating layers 110a and 110c preferably include regions containing a higher nitrogen content than the insulating layer 110b. The insulating layers 110a and 110c can be made of, for example, a material containing a higher nitrogen content than the insulating layer 110b. The insulating layers 110a and 110c are preferably made of a nitride or nitride oxide. Silicon nitride or silicon oxynitride can be used as appropriate for the insulating layers 110a and 110c, for example.

[0187] When oxygen contained in the insulating layer 110b diffuses upward from a region of the insulating layer 110b that is not in contact with the semiconductor layer 108 (for example, the top surface of the insulating layer 110b), the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 may decrease. By providing the insulating layer 110c on the insulating layer 110b, it is possible to suppress the diffusion of oxygen contained in the insulating layer 110b from the region of the insulating layer 110 that is not in contact with the semiconductor layer 108. Similarly, by providing the insulating layer 110a below the insulating layer 110b, it is possible to suppress the diffusion of oxygen from the region of the insulating layer 110 that is not in contact with the semiconductor layer 108 to the bottom. Therefore, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is increased, and thus the oxygen vacancies (V O ) and V O H. Therefore, a transistor having good electrical characteristics and high reliability can be realized.

[0188] Sometimes, due to the oxygen contained in the insulating layer 110b, the conductive layer 112a and the conductive layer 112b are oxidized, thereby increasing the resistance. In addition, due to the oxygen contained in the insulating layer 110b, the conductive layer 112a and the conductive layer 112b are oxidized, and sometimes the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is reduced. By providing the insulating layer 110a between the insulating layer 110b and the conductive layer 112a, it is possible to suppress the conductive layer 112a from being oxidized and the resistance from being increased. Similarly, by providing the insulating layer 110c between the insulating layer 110b and the conductive layer 112b, it is possible to suppress the conductive layer 112b from being oxidized and the resistance from being increased. At the same time, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is increased, and the oxygen vacancies (V O ) and V O H, thereby achieving a transistor that exhibits good electrical characteristics and high reliability.

[0189] When hydrogen diffuses into the semiconductor layer 108, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V O ). Furthermore, V O H, sometimes the carrier concentration becomes high. By providing the insulating layer 110a and the insulating layer 110c, the oxygen vacancies (V O ) and V O H, thereby achieving a transistor that exhibits good electrical characteristics and high reliability.

[0190] The insulating layers 110a and 110c preferably have a thickness sufficient to function as barrier films for oxygen and hydrogen. If the thickness of the insulating layers 110a and 110c is small, their barrier function may be reduced. On the other hand, if the thickness of the insulating layers 110a and 110c is large, the region of the semiconductor layer 108 in contact with the insulating layer 110b becomes narrower, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 may decrease. The thickness of the insulating layers 110a and 110c may be smaller than that of the insulating layer 110b. The thickness of the insulating layers 110a and 110c is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 70 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 10 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less, and more preferably 20 nm or more and 40 nm or less. By setting the thickness of the insulating layer 110a and the insulating layer 110c within the above range, the oxygen vacancies (V O ) and V O H, and thus a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0191] Preferably, the amount of impurities (e.g., water and hydrogen) released from the insulating layers 110a and 110c themselves is small. Since the amount of impurities released from the insulating layers 110a and 110c is small, diffusion of the impurities into the semiconductor layer 108 can be suppressed, thereby achieving a transistor with good electrical characteristics and high reliability.

[0192] By reducing the release of impurities (e.g., water and hydrogen) from the insulating layers 110a and 110c, the regions of the semiconductor layer 108 in contact with the insulating layer 110a and the regions of the semiconductor layer 108 in contact with the insulating layer 110c can also be used as channel formation regions. Furthermore, when a material that releases impurities (e.g., water and hydrogen) is used for the insulating layer 110a, the regions of the semiconductor layer 108 in contact with the insulating layer 110a can be used as source regions or drain regions. The same applies to the insulating layer 110c.

[0193] In the transistor 100, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V O ) and V O H is reduced. Therefore, a transistor having good electrical characteristics and high reliability can be realized.

[0194] Oxygen may be released from the semiconductor layer 108 due to heat applied in a process after forming the semiconductor layer 108. However, since oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, oxygen vacancies (V O ) and V OH increases. Furthermore, the degree of freedom in the process temperature can be increased in the steps after forming the semiconductor layer 108. Specifically, the process temperature can be increased in the steps after forming the semiconductor layer 108. Consequently, a transistor 100 exhibiting excellent electrical characteristics and high reliability can be realized.

[0195] Furthermore, one or more of the insulating layer 110a and the insulating layer 110c may not be provided. Furthermore, both the insulating layer 110a and the insulating layer 110c may not be provided.

[0196] The insulating layer 120 may use the same material as that used for the insulating layer 110. Figure 1B The insulating layer 120 is shown as having a single-layer structure in FIG. 1 , but one embodiment of the present invention is not limited thereto. The insulating layer 120 may have a stacked-layer structure of two or more layers.

[0197] When a metal oxide is used as the semiconductor layer 108 or the semiconductor layer 208, an insulating layer containing oxygen is preferably used as the insulating layer 120 that is in contact with the semiconductor layer 108 or the semiconductor layer 208. An oxide or an oxynitride is preferably used as the insulating layer 120. A film that releases oxygen upon heating is preferably used as the insulating layer 120. For example, silicon oxide or silicon oxynitride can be suitably used as the insulating layer 120.

[0198] In addition, the insulating layer 120 may not be provided.

[0199] [Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 212a, conductive layer 212b, conductive layer 204] The conductive layers 112a, 112b, 104, 212a, 212b, and 204, which serve as source, drain, or gate electrodes, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or alloys containing one or more of the foregoing metals. The conductive layers 112a, 112b, 104, 212a, 212b, and 204 can each be formed using a low-resistivity conductive material containing one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because it is advantageous in terms of mass production.

[0200] A metal oxide film (also referred to as an oxide conductor) can be used for the conductive layers 112a, 112b, 104, 212a, 212b, and 204. Examples of the oxide conductor (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0201] Here, we will explain oxide conductors (OCs). For example, oxygen vacancies form in a metal oxide with semiconductor properties. Hydrogen is added to these oxygen vacancies, forming donor levels near the conduction band. As a result, the conductivity of the metal oxide increases, making it a conductor. Metal oxides that can function as conductors are referred to as oxide conductors.

[0202] A stacked-layer structure of a conductive film containing the above-mentioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy may be employed as the conductive layers 112a, 112b, 104, 212a, 212b, and 204. The use of a conductive film containing a metal or alloy can reduce wiring resistance.

[0203] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive layers 112a, 112b, 104, 212a, 212b, and 204. The use of a Cu-X alloy film allows processing by wet etching, thereby reducing manufacturing costs.

[0204] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can use the same material or different materials.

[0205] Here, the conductive layer 112 a and the conductive layer 112 b are specifically described by taking a structure in which metal oxide is used as the semiconductor layer 108 and the semiconductor layer 208 as an example.

[0206] When an oxide semiconductor is used as the semiconductor layer 108, the conductive layers 112a and 112b may be oxidized by oxygen contained in the semiconductor layer 108, thereby increasing the resistance. The conductive layers 112a and 112b may be oxidized by oxygen contained in the insulating layer 110b, thereby increasing the resistance. The conductive layers 112a and 112b may be oxidized by oxygen contained in the semiconductor layer 108, thereby increasing the resistance. OThe conductive layer 112a and the conductive layer 112b are oxidized by oxygen contained in the insulating layer 110b, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 may decrease.

[0207] Since the channel length L100 of transistor 100 is shorter than that of transistor 200, oxygen vacancies (V O ) and V O The electrical characteristics and reliability of H are greatly affected. For example, sometimes V O H diffuses from the source region or the drain region into the channel formation region, increasing the carrier concentration in the channel formation region, thereby causing the threshold voltage of the transistor 100 to fluctuate or the reliability to decrease. O The greater the impact of H diffusion on electrical characteristics and reliability. Therefore, the conductive layer 112a and the conductive layer 112b, including the area in contact with the semiconductor layer 108, are preferably made of a material that is not easily oxidized. The conductive layer 112a and the conductive layer 112b are preferably both made of an oxide conductor. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) can be appropriately used. Nitride conductors can also be used for the conductive layer 112a and the conductive layer 112b. As nitride conductors, tantalum nitride and titanium nitride can be cited. The conductive layer 112a and the conductive layer 112b can also have a stacked structure of the above materials. Note that the conductive layer 112a and the conductive layer 112b can be made of the same material or different materials.

[0208] By using a material that is not easily oxidized for the conductive layer 112a and the conductive layer 112b, an increase in resistance due to oxidation of oxygen contained in the semiconductor layer 108 or oxygen contained in the insulating layer 110b can be suppressed. O ) is suppressed while the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 is increased. Therefore, the oxygen vacancies (V O ) and V O H, thereby achieving the transistor 100 having good electrical characteristics and high reliability.

[0209] The conductive layers 212a and 212b can also be made of a material that is not easily oxidized. The conductive layers 212a and 212b can be made of the same material that can be used for the conductive layers 112a and 112b.

[0210] As described above, the conductive layer 112a and the conductive layer 112b in contact with the semiconductor layer 108 preferably use a material that is not easily oxidized. However, when a material that is not easily oxidized is used, the resistance sometimes becomes high. Since the conductive layer 112a and the conductive layer 112b are used as wiring, the resistance is preferably low. Therefore, when the conductive layer 112a_1 including the area in contact with the semiconductor layer 108 uses a material that is not easily oxidized and the conductive layer 112a_2 not including the area in contact with the semiconductor layer 108 uses a material with a low resistivity, the resistance of the conductive layer 112a can be reduced. In addition, the oxygen vacancies (V O ) and V O H, a transistor with good electrical characteristics and high reliability can be realized.

[0211] As described above, especially when the channel length L100 is small, the oxygen vacancies (V O ) and V O H has a great influence on electrical characteristics and reliability. When the conductive layer 112a_1 is made of a material that is not easily oxidized, oxygen vacancies (V O ) and V O Increase of H. Therefore, a transistor with a small channel length having good electrical characteristics and high reliability can be realized.

[0212] Conductive layer 112a_1 can be made of one or more of an oxide conductor and a nitride conductor. Conductive layer 112a_2 preferably uses a material with a lower resistivity than conductive layer 112a_1. Conductive layer 112a_2 can be made of, for example, one or more of copper, aluminum, titanium, tungsten, and molybdenum, or an alloy containing one or more of the above metals. Specifically, conductive layer 112a_1 can be made of In-Sn-Si oxide (ITSO), and conductive layer 112a_2 can be made of tungsten.

[0213] Note that the structure of the conductive layer 112a can be determined based on the required wiring resistance of the conductive layer 112a. For example, when the wiring (conductive layer 112a) is short and a high wiring resistance is required, the conductive layer 112a may have a single-layer structure using a material that is not easily oxidized. On the other hand, when the wiring (conductive layer 112a) is long and a low wiring resistance is required, a stacked structure of a material that is not easily oxidized and a low-resistivity material is preferably used as the conductive layer 112a.

[0214] Note that the structure of the conductive layer 112a can be used for other conductive layers. For example, the conductive layer 112b may have a stacked-layer structure of a first conductive layer and a second conductive layer on the first conductive layer, with a region where a portion of the second conductive layer is removed to expose the first conductive layer. In this region, the first conductive layer may be in contact with the semiconductor layer 108.

[0215] [Insulation layer 106] The insulating layer 106 serving as the gate insulating layer of the transistor 100 and the transistor 200 preferably has a low defect density. When the defect density of the insulating layer 106 is low, the transistor 100 and the transistor 200 can exhibit good electrical characteristics. Furthermore, the insulating layer 106 preferably has a high dielectric strength voltage. The high dielectric strength voltage of the insulating layer 106 allows the transistor 100 and the transistor 200 to be highly reliable.

[0216] The insulating layer 106 can be made of, for example, one or more of an insulating oxide, oxynitride, oxynitride, and nitride. The insulating layer 106 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 106 can be a single layer or a stacked layer. For example, the insulating layer 106 can have a stacked structure of oxides and nitrides.

[0217] Note that in a micro transistor, when the thickness of the gate insulating layer is small, leakage current sometimes increases. By using a material with a high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to achieve a lower voltage when the transistor is operating while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0218] It is preferable that a small amount of impurities (for example, water and hydrogen) be released from the insulating layer 106 itself. Since a small amount of impurities is released from the insulating layer 106, diffusion of impurities into the semiconductor layer 108 and the semiconductor layer 208 can be suppressed, thereby realizing a transistor having good electrical characteristics and high reliability.

[0219] Since the insulating layer 106 is formed on the semiconductor layer 108 and the semiconductor layer 208, it is preferably formed under conditions that minimize damage to the semiconductor layers 108 and 208. For example, it is preferably formed under conditions with a sufficiently low deposition rate. For example, when forming the insulating layer 106 using a plasma CVD method, forming it under low power conditions can minimize damage to the semiconductor layers 108 and 208.

[0220] Here, the insulating layer 106 will be specifically described by taking a structure in which the semiconductor layer 108 and the semiconductor layer 208 are formed of metal oxide as an example.

[0221] In order to improve the interface properties between the insulating layer 106 and the semiconductor layer 108, and between the insulating layer 106 and the semiconductor layer 208, an oxide or an oxynitride is preferably used for at least the side of the insulating layer 106 that is in contact with the semiconductor layer 108 and the semiconductor layer 208. For example, one or more of silicon oxide and silicon oxynitride can be used as appropriate for the insulating layer 106. Furthermore, a film that releases oxygen upon heating is more preferably used for the insulating layer 106.

[0222] Note that the insulating layer 106 may have a stacked-layer structure. The insulating layer 106 may have a stacked-layer structure of an oxide film in contact with the semiconductor layers 108 and 208, and a nitride film in contact with the conductive layers 104 and 204. For example, one or more of silicon oxide and silicon oxynitride can be suitably used as the oxide film. For example, silicon nitride can be suitably used as the nitride film.

[0223] [Substrate 102] While the material of the substrate 102 is not particularly limited, it must at least have heat resistance sufficient to withstand subsequent heat treatment. For example, the substrate 102 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate. Alternatively, a substrate having a semiconductor element provided thereon may be used as the substrate 102. Note that the semiconductor substrate and the insulating substrate may have a circular or angular shape.

[0224] A flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistor 100 and the like. The release layer may be used when a portion or all of a semiconductor device is fabricated on the release layer, which is then separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like may also be transferred to a substrate with low heat resistance or a flexible substrate.

[0225] Note that in Figure 1B In the embodiment of the present invention, the thickness of the region in contact with the semiconductor layer 108 and the thickness of the region not in contact with the semiconductor layer 108 in the conductive layer 112a (specifically, the conductive layer 112a_1) of the transistor 100 are equal or substantially equal, but one embodiment of the present invention is not limited to this. The thickness of the region in contact with the semiconductor layer 108 and the thickness of the region not in contact with the semiconductor layer 108 in the conductive layer 112a_1 may be different. Figure 6A As shown, the thickness of the conductive layer 112 a_1 in a region in contact with the semiconductor layer 108 is preferably smaller than the thickness of a region not in contact with the semiconductor layer 108 .

[0226] Figure 6A The height H104 from the formed surface of the conductive layer 112a_1 (here, the top surface of the substrate 102) to the lowest position of the bottom surface of the conductive layer 104 is shown. In addition, the height H112a from the formed surface of the conductive layer 112a_1 (here, the top surface of the substrate 102) to the highest position of the region where the conductive layer 112a_1 and the semiconductor layer 108 are in contact is shown. Figure 6A As shown, the height H104 from the lowest position of the bottom surface of the conductive layer 104 is preferably equal to or substantially equal to the height H112a from the highest position of the region where the conductive layer 112a_1 contacts the semiconductor layer 108. Alternatively, as shown in FIG. Figure 6B As shown, height H104 is preferably lower than height H112a. By setting height H104 from the lowest point of the bottom surface of conductive layer 104 to be equal to or lower than height H112a from the highest point of the region where conductive layer 112a_1 contacts semiconductor layer 108, the gate electrode electric field applied to the channel formation region near conductive layer 112a can be enhanced, thereby increasing the on-state current of transistor 100.

[0227] By setting the height H104 from the lowest point of the bottom surface of the conductive layer 104 to be equal to or lower than the height H112a from the highest point of the region where the conductive layer 112a_1 contacts the semiconductor layer 108, the gate electrode electric field applied to the channel formation region can be made more uniform. Here, when the gate electrode electric field applied to the channel formation region is non-uniform, the electrical characteristics when the conductive layer 112a is used as the source electrode and the conductive layer 112b is used as the drain electrode may differ from the electrical characteristics when the conductive layer 112a is used as the drain electrode and the conductive layer 112b is used as the source electrode. When the gate electrode electric field applied to the channel formation region of the transistor 100 is more uniform, the electrical characteristics can be made equal. Therefore, the transistor 100 can be suitably used in a circuit structure in which the source and drain electrodes are swapped.

[0228] The thickness of the conductive layer 112a (specifically, the conductive layer 112a_1) may be appropriately adjusted so that the height H104 is equal to or lower than the height H112a.

[0229] The above is the description of the components.

[0230] The following describes a configuration example of a semiconductor device having a partially different configuration from that of Configuration Example 1. The description of portions overlapping with Configuration Example 1 may be omitted. In the following drawings, portions having the same functions as those of Configuration Example 1 are hatched with the same hatching, and may not be assigned reference numerals.

[0231] <Structure Example 2> Figure 7A A top view of the semiconductor device 10A is shown. Figure 7B Shown along Figure 7A The cross-sectional view of the section along the dot-dash line A1-A2 is shown. Figure 7C Cross-sectional views along the dashed-dotted line B1 - B2 and the dashed-dotted line B3 - B4 are shown. Figure 8A A perspective view of a semiconductor device 10A is shown.

[0232] The semiconductor device 10A includes the transistor 100 and the transistor 200A. The transistor 200A differs from the transistor 200 included in the semiconductor device 10 shown in the structural example 1 mainly in that the transistor 200A includes a conductive layer 202.

[0233] Conductive layer 202 is provided between substrate 102 and insulating layer 110. In transistor 200A, conductive layer 204 serves as a first gate electrode (also referred to as a top gate electrode), and conductive layer 202 serves as a second gate electrode (also referred to as a bottom gate electrode or back gate electrode). Furthermore, a portion of insulating layer 106 serves as a first gate insulating layer, and portions of insulating layer 110 and insulating layer 120 serve as a second gate insulating layer.

[0234] The portion of semiconductor layer 208 that overlaps with at least one of conductive layer 204 and conductive layer 202 is used as a channel formation region. Below, for convenience of description, the portion of semiconductor layer 208 that overlaps with conductive layer 204 is sometimes referred to as a channel formation region. However, in practice, a channel may also be formed in a portion that does not overlap with conductive layer 204 but overlaps with conductive layer 202 (including region 208D).

[0235] Figure 8B is a perspective view schematically showing the conductive layer 112 a included in the transistor 100 and the conductive layer 202 included in the transistor 200A. Figure 8CThe figure summarizes the conductive layer 112a and the conductive layer 112b included in the transistor 100, and the conductive layer 202 included in the transistor 200A. The conductive layer 202 can use the same material as the conductive layer 112a. The conductive layer 202 can be formed by the same process as the conductive layer 112a. Alternatively, the conductive layer 202 can have a stacked-layer structure including a conductive layer 202_1 and a conductive layer 202_2 on the conductive layer 202_1. The conductive layer 202_1 can be formed by the same process as the conductive layer 112a_1, and the conductive layer 202_2 can be formed by the same process as the conductive layer 112a_2. Note that the conductive layer 202 does not include a region in contact with the semiconductor layer 208. Therefore, an opening corresponding to the opening 145 of the conductive layer 112a_2 may not be provided in the conductive layer 202_2.

[0236] Figure 9A 1 is a perspective view schematically illustrating the conductive layer 112a and the semiconductor layer 108 included in the transistor 100, and the conductive layer 202 and the semiconductor layer 208 included in the transistor 200A. The semiconductor layer 208 is provided on the conductive layer 202. The semiconductor layer 208 includes a region overlapping with the conductive layer 202.

[0237] like Figure 7A and Figure 7C As shown, the conductive layer 204 can also be electrically connected to the conductive layer 202 through the opening 149 provided in the insulating layer 106, the insulating layer 110, and the insulating layer 120. Thus, the same potential can be supplied to the conductive layer 204 and the conductive layer 202. By supplying the same potential to the conductive layer 204 and the conductive layer 202, the current that can flow when the transistor 200A is in the on state can be increased. Figure 9B 14 is a perspective view schematically showing the conductive layer 112a and the conductive layer 104 included in the transistor 100 and the conductive layer 202 and the conductive layer 204 included in the transistor 200A. The conductive layer 204 is provided to cover the opening 149 and includes a region in contact with the conductive layer 202.

[0238] Note that in Figure 7A , the top surface shape of opening 149 is identical or substantially identical to the top surface shapes of openings 141 and 143, but one embodiment of the present invention is not limited thereto. The top surface shape of opening 149 may also be different from the top surface shapes of openings 141 and 143. In addition, the top surface shape of opening 149 may be, for example, circular or elliptical. The top surface shape of opening 149 may also be a polygon such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), or a pentagon, or these polygons may have rounded corners.

[0239] like Figure 7A and Figure 7CAs shown in FIG. 2 , it is preferable that the conductive layer 204 and the conductive layer 202 protrude outside the end portion of the semiconductor layer 208 in the channel width direction of the transistor 200A. Figure 7C As shown, the entire semiconductor layer 208 in the channel width direction is covered by the conductive layer 204 and the conductive layer 202 via the insulating layer 106, the insulating layer 110, and the insulating layer 120. By adopting such a structure, the semiconductor layer 208 can be electrically surrounded by the electric field generated by the pair of gate electrodes. In this case, it is particularly preferable to supply the same potential to the conductive layer 204 and the conductive layer 202. This effectively applies the electric field for inducing a channel to the semiconductor layer 208, thereby increasing the on-state current of the transistor 200A. Consequently, a miniaturized transistor 200A can be realized.

[0240] Alternatively, the conductive layer 204 may not be connected to the conductive layer 202. In this case, a fixed potential may be supplied to one of the pair of gate electrodes, and a signal for driving the transistor 200A may be supplied to the other. In this case, the potential supplied to one electrode can be used to control the threshold voltage of the transistor 200A when the other electrode is used to drive the transistor 200A.

[0241] Conductive layer 202 may be electrically connected to conductive layer 212a or conductive layer 212b. In this case, conductive layer 212a or conductive layer 212b may be electrically connected to conductive layer 202 through openings provided in insulating layer 195, insulating layer 106, insulating layer 120, and insulating layer 110.

[0242] An insulating layer 110 is disposed on the conductive layer 202 . Figure 7B and Figure 7C The structure shown here is one in which insulating layer 110a is provided in contact with the top and side surfaces of conductive layer 202. Insulating layer 110a in contact with conductive layer 202 is preferably an insulating layer that does not readily diffuse the metal elements contained in conductive layer 202. Insulating layer 110a preferably functions as a barrier film to suppress gas escape from insulating layer 110b and to suppress diffusion of metal elements from conductive layer 202. The aforementioned materials can be used as appropriate for insulating layer 110a.

[0243] Notice, Figure 7B The conductive layer 202 shown in FIG. 1 may also be used in other structural examples.

[0244] Since the transistor 100 can refer to the description of Structural Example 1, detailed description is omitted.

[0245] <Structure Example 3> Figure 10A A top view of the semiconductor device 10B is shown. Figure 10B Shown along Figure 10AThe cross-sectional view of the cross section along the dot-dash line A1-A2 shown in FIG. 1 and the cross-sectional view along the dot-dash line B1-B2 and the dot-dash line B3-B4 can be referred to. Figure 7C .

[0246] The semiconductor device 10B includes the transistor 100 and the transistor 200B. The transistor 200B differs from the transistor 200A included in the semiconductor device 10A shown in the second structural example in that the end of the conductive layer 202 is located outside the end of the semiconductor layer 208 in the transistor 200B.

[0247] By adopting a structure in which the end of the conductive layer 202 is located outside the end of the semiconductor layer 208, the coverage of the layer formed on the conductive layer 202 (for example, the semiconductor layer 208 and the insulating layer 106) can be improved, thereby suppressing the occurrence of defects such as disconnection or voids in the layer. In addition, the conductive layer 202 can be used as a light shielding layer to block light incident from the outside of the semiconductor device 10B. Therefore, a semiconductor device with high light reliability can be realized. In addition, by increasing the area of ​​the region overlapping with the conductive layer 202 and the semiconductor layer 208 used as the back gate electrode, the electric field of the back gate electrode can be further enhanced.

[0248] Notice, Figure 10B The conductive layer 202 shown in FIG. 1 may also be used in other structural examples.

[0249] Since the transistor 100 can refer to the description of Structural Example 1, detailed description is omitted.

[0250] <Structure Example 4> For a top view of the semiconductor device 10C, refer to Figure 7A . Figure 11A Shown along Figure 7A The cross-sectional view of the section along the dot-dash line A1-A2 is shown. Figure 11B Cross-sectional views along the dashed-dotted line B1 - B2 and the dashed-dotted line B3 - B4 are shown.

[0251] The semiconductor device 10C includes a transistor 100A and a transistor 200C. The transistor 100A includes an insulating layer 106A instead of the insulating layer 106, and the transistor 200C includes an insulating layer 106B instead of the insulating layer 106. These are mainly different from the transistors 100 and 200A included in the semiconductor device 10A shown in the second structural example.

[0252] The insulating layer 106A is processed to have a top surface shape that substantially matches that of the conductive layer 104. The insulating layer 106B is processed to have a top surface shape that substantially matches that of the conductive layer 204. The insulating layers 106A and 106B can be formed, for example, by forming insulating films to become the insulating layers 106A and 106B and processing the insulating films using the same resist mask used to process the conductive layers 104 and 204.

[0253] Insulating layer 195 includes regions that contact the top and side surfaces of conductive layer 104, the side surfaces of insulating layer 106A, the top and side surfaces of semiconductor layer 108, the top and side surfaces of conductive layer 112b, the top and side surfaces of conductive layer 204, the side surfaces of insulating layer 106B, the top and side surfaces of semiconductor layer 208, and the top surface of insulating layer 120. Insulating layer 195 includes openings 147a and 147b in a region overlapping with region 208D.

[0254] Notice, Figure 11A The insulating layer 106A and the insulating layer 106B shown in FIG. 1 can also be used in other structural examples.

[0255] <Structure Example 5> For a top view of the semiconductor device 10D, refer to Figure 7A . Figure 12A Shown along Figure 7A The cross-sectional view of the section along the dot-dash line A1-A2 is shown. Figure 12B Cross-sectional views along the dashed-dotted line B1 - B2 and the dashed-dotted line B3 - B4 are shown.

[0256] The semiconductor device 10D includes a transistor 100B and a transistor 200D. The transistors 100B and 200D differ from the transistors 100A and 200C included in the semiconductor device 10C shown in the structural example 4 mainly in the structures of the insulating layers 106A and 106B.

[0257] The end portion of the conductive layer 204 is located inside the end portion of the insulating layer 106B. In other words, the insulating layer 106B has a portion that protrudes outside the end portion of the conductive layer 204 at least on the semiconductor layer 208.

[0258] The semiconductor layer 208 includes a pair of regions 208L sandwiching a channel formation region and a pair of regions 208D outside the region 208L. The regions 208L are regions of the semiconductor layer 208 that overlap with the insulating layer 106B and do not overlap with the conductive layer 204.

[0259] Region 208L functions as a buffer region to mitigate the drain electric field. Because region 208L does not overlap with conductive layer 204, a channel is rarely formed even when a gate voltage is applied to conductive layer 204. The carrier concentration in region 208L is preferably higher than that in the channel formation region. This allows region 208L to function as an LDD (Lightly Doped Drain) region.

[0260] The region 208L can be said to be a region having equal or lower resistance, equal or higher carrier concentration, equal or higher oxygen vacancy density, or equal or higher impurity concentration than the channel formation region.

[0261] The region 208L can be said to have the same or higher resistance, the same or lower carrier concentration, the same or lower oxygen vacancy density, or the same or lower impurity concentration than the region 208D.

[0262] In this manner, by providing the region 208L serving as the LDD region between the channel formation region and the region 208D serving as the source region or the drain region, a transistor 200D having both a high drain breakdown voltage and a large on-state current and high reliability can be realized.

[0263] Region 208D serves as a source region or a drain region and has lower resistance than other regions of semiconductor layer 208. Alternatively, region 208D can be said to have the highest carrier concentration, the highest oxygen vacancy density, or the highest impurity concentration compared to other regions of semiconductor layer 208.

[0264] The lower the resistance of the region 208D, the better. For example, the sheet resistance of the region 208D is preferably greater than 1Ω / □ and less than 1×10 3 Ω / □, more preferably 1Ω / □ or more and 8×10 2 Ω / □ or less.

[0265] The higher the resistance of the channel formation region in the state where no channel is formed, the better. For example, the sheet resistance value of the channel formation region is preferably 1×10 9 Ω / □ or more, more preferably 5×10 9 Ω / □ or more, more preferably 1×10 10 Ω / □ or more.

[0266] Since the resistance of the channel formation region in the state where no channel is formed is as high as possible, there is no need to set an upper limit. However, when setting an upper limit, for example, the sheet resistance of the channel formation region is preferably 1×10 9 Ω / □ or more and 1×10 12 Ω / □ or less, more preferably 5×10 9 Ω / □ or more and 1×1012 Ω / □ or less, more preferably 1×10 10 Ω / □ or more and 1×10 12 Ω / □ or less.

[0267] The sheet resistance value of the region 208L may be, for example, 1×10 3 Ω / □ or more and 1×10 9 Ω / □ or less, preferably 1×10 3 Ω / □ or more and 1×10 8 Ω / □ or less, more preferably 1×10 3 Ω / □ or more and 1×10 7 Ω / □ or less. By setting the sheet resistance value within the above range, a transistor with good electrical characteristics and high reliability can be realized. In addition, the sheet resistance can be calculated from the resistance value. By providing such a region 208L between the region 208D and the channel formation region, the source-drain withstand voltage of the transistor 200D can be increased.

[0268] The resistance of the channel formation region in a state where no channel is formed may be 1×10 6 times or more and 1×10 12 times or less, preferably 1×10 6 times or more and 1×10 11 times or less, more preferably 1×10 6 times or more and 1×10 10 times or less.

[0269] The resistance of the channel formation region in a state where no channel is formed may be 1×10 of the resistance of the region 208L. 0 times or more and 1×10 9 times or less, preferably 1×10 1 times or more and 1×10 8 times or less, more preferably 1×10 2 times or more and 1×10 7 times or less.

[0270] The resistance of region 208L may be 1×10 of the resistance of region 208D. 0 times or more and 1×10 9 times or less, preferably 1×10 1 times or more and 1×10 8 times or less, more preferably 1×10 1 times or more and 1×10 7 times or less.

[0271] The carrier concentration of semiconductor layer 208 preferably has a distribution in which the carrier concentration is lowest in the channel formation region and increases in the order of region 208L and region 208D. Providing region 208L between the channel formation region and region 208D allows the carrier concentration in the channel formation region to be kept extremely low, even if, for example, impurities such as hydrogen diffuse from region 208D during the manufacturing process.

[0272] The carrier concentration in the channel formation region should be as low as possible, preferably 1×10 18 cm -3 Below, more preferably 1×10 17 cm -3 Below, more preferably 1×10 16 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 12 cm -3 Note that there is no particular limitation on the lower limit of the carrier concentration in the channel formation region, and it can be set to 1×10 -9 cm -3 .

[0273] On the other hand, the carrier concentration in the region 208D may be, for example, 5×10 18 cm -3 More than, preferably 1×10 19 cm -3 More than 5×10 19 cm -3 The upper limit of the carrier concentration in the region 208D is not particularly limited, but can be, for example, 5×10 21 cm -3 or 1×10 22 cm -3 .

[0274] The carrier concentration in the region 208L may be between the values ​​of the channel formation region and the region 208D. For example, it may be 1×10 14 cm -3 Above and below 1×10 20 cm -3 The range of values.

[0275] Note that the carrier concentration in region 208L may not be uniform, and may have a gradient where the carrier concentration decreases from the region 208D side toward the channel formation region. For example, one or both of the hydrogen concentration and the oxygen vacancy concentration in region 208L may have a gradient where the carrier concentration decreases from the region 208D side toward the channel formation region.

[0276] Part of an end portion of the insulating layer 106B is located over the semiconductor layer 208. The insulating layer 106B overlaps with the conductive layer 204 and includes a region functioning as a gate insulating layer and a region not overlapping with the conductive layer 104 (ie, a region overlapping with the region 208L).

[0277] The end of the conductive layer 104 is located inside the end of the insulating layer 106A. In other words, the insulating layer 106A has a portion that protrudes outside the end of the conductive layer 104 at least on the semiconductor layer 108.

[0278] The semiconductor layer 108 includes a region 108L inside the region 108D. The region 108L is a region of the semiconductor layer 108 that overlaps with the insulating layer 106A and does not overlap with the conductive layer 104. The region 108L is formed when the region 208L is formed. Note that in the transistor 100B, the region of the semiconductor layer 108 that contacts the conductive layer 112b serves as a source region or a drain region. The region 108L and the region 108D are formed in part of this source region or drain region.

[0279] Notice, Figure 12A The insulating layer 106A and the insulating layer 106B shown in FIG. 1 can also be used in other structural examples.

[0280] <Structure Example 6> Figure 13A A top view of the semiconductor device 10E is shown. Figure 13B Shown along Figure 13A The cross-sectional view along the dot-dash line A1-A2 is shown. The cross-sectional view along the dot-dash line B1-B2 and the dot-dash line B3-B4 can be referred to. Figure 12B .

[0281] The semiconductor device 10E includes the transistor 100B and the transistor 200E. The transistor 200E differs from the transistor 200D included in the semiconductor device 10D shown in the structural example 5 in that the transistor 200E does not include the insulating layer 195 between the conductive layers 212a and 212b and the semiconductor layer 208.

[0282] The conductive layer 212 a and the conductive layer 212 b both include regions in contact with the top surface and side surfaces of the semiconductor layer 208 .

[0283] The conductive layers 212a and 212b can be formed by the same process as the conductive layers 104 and 204. For example, a conductive film can be formed after the insulating layers 106A and 106B are formed, and the conductive film can be processed to form the conductive layers 104, 204, 212a, and 212b. By forming the conductive layers 104, 204, 212a, and 212b in the same process, the manufacturing cost of the semiconductor device 10E can be reduced. Note that no Figure 12A The openings 147a and 147b are shown.

[0284] Figure 13B The structure shown is that neither the region 208L nor the region 208D is provided in the region in contact with the conductive layer 212a or the region in contact with the conductive layer 212b of the semiconductor layer 208. For example, after the conductive layers 104, 204, 212a, and 212b are formed, these conductive layers can be used as masks to add impurity elements to the semiconductor layer 208. Note that the region in contact with the conductive layer 212a and the region 208D adjacent to the region in the semiconductor layer 208 serve as one of the source region and the drain region. The region in contact with the conductive layer 212b and the region 208D adjacent to the region in the semiconductor layer 208 serve as the other of the source region and the drain region.

[0285] Figure 13B Although the structure in which the region 208L and the region 208D are not provided in the region in contact with the conductive layer 212a or the region in contact with the conductive layer 212b of the semiconductor layer 208 is shown, one embodiment of the present invention is not limited to this. For example, the region 208D may be provided in the region in contact with the conductive layer 212a or the region in contact with the conductive layer 212b of the semiconductor layer 208.

[0286] in addition, Figure 13B The conductive layer 212a and the conductive layer 212b shown in FIG. 1 can also be used in other structural examples.

[0287] The transistor 100B can refer to the description of structural example 5, so detailed description is omitted.

[0288] <Structure Example 7> For a top view of the semiconductor device 10F, refer to Figure 13A . Figure 14 Shown along Figure 13A The cross-sectional view along the dot-dash line A1-A2 is shown. The cross-sectional view along the dot-dash line B1-B2 and the dot-dash line B3-B4 can be referred to. Figure 7B .

[0289] The semiconductor device 10F includes a transistor 100A and a transistor 200F. The transistor 200F differs from the transistor 200E included in the semiconductor device 10E shown in the structural example 5 in that the transistor 200F includes an insulating layer 106C and an insulating layer 106D.

[0290] Insulating layer 106C and insulating layer 106D are formed using the same process as insulating layer 106A and insulating layer 106B. Insulating layer 106C is provided in a region overlapping with conductive layer 212a and includes a region in contact with a portion of the bottom surface of conductive layer 212a. Insulating layer 106D is provided in a region overlapping with conductive layer 212b and includes a region in contact with a portion of the bottom surface of conductive layer 212b. Insulating layer 106C and insulating layer 106D may each cover an end portion of semiconductor layer 108. Insulating layer 106C is provided between insulating layer 120 and conductive layer 212a and between semiconductor layer 208 and conductive layer 212a. Insulating layer 106D is provided between insulating layer 120 and conductive layer 212b and between semiconductor layer 208 and conductive layer 212b.

[0291] Figure 14 The structure shown is such that the end of the conductive layer 204 is aligned or approximately aligned with the end of the insulating layer 106B. The insulating layer 106B can be formed, for example, using a resist mask used to form the conductive layer 204. This structure can simplify the process.

[0292] Region 208D is formed in a region that does not overlap with conductive layer 204, conductive layer 212a, and conductive layer 212b. Alternatively, by processing the conductive layer 204 so that the end portion is located inside the end portion of insulating layer 106B, region 208L may be formed in a region that overlaps with insulating layer 106B but does not overlap with conductive layer 204 (see FIG. Figure 13B ).

[0293] in addition, Figure 14 The insulating layer 106C and the insulating layer 106D shown may also be used in other structural examples.

[0294] The transistor 100A can refer to the description of Structural Example 4, so detailed description is omitted.

[0295] <Structure Example 8> Figure 15A A top view of the semiconductor device 10G is shown. Figure 15B Shown along Figure 15A The cross-sectional view along the dot-dash line A1-A2 is shown. The cross-sectional view along the dot-dash line B1-B2 and the dot-dash line B3-B4 can be referred to. Figure 7B .

[0296] The semiconductor device 10G includes the transistor 100 and a transistor 200G. The transistor 200G differs from the transistor 200F included in the semiconductor device 10F shown in the structural example 7 in that the insulating layer 106 of the transistor 200G includes an opening 137a and an opening 137b.

[0297] Openings 137a and 137b are provided in the region of insulating layer 106 that overlaps with semiconductor layer 208. In opening 137a, conductive layer 212a includes a region in contact with semiconductor layer 208, and in opening 137b, conductive layer 212b includes a region in contact with semiconductor layer 208. Opening 137a is preferably provided so that the end portion of conductive layer 212a on the channel formation region side protrudes further toward the channel formation region. Similarly, opening 137b is preferably provided so that the end portion of conductive layer 212b on the channel formation region side protrudes further toward the channel formation region. Thus, in opening 137a, a portion of the end portion of conductive layer 212a contacts the top surface of semiconductor layer 208. In opening 137b, a portion of the end portion of conductive layer 212b contacts the top surface of semiconductor layer 208. Region 208D is formed in a region that does not overlap with conductive layer 204, conductive layer 212a, and conductive layer 212b. Region 208L is formed in a region that overlaps with insulating layer 106 and does not overlap with conductive layer 204. Thus, a region of semiconductor layer 208 that contacts conductive layer 212a can be adjacent to region 208D. Similarly, a region of semiconductor layer 208 that contacts conductive layer 212b can be adjacent to region 208D.

[0298] The insulating layer 106 includes a region that contacts a portion of the bottom surface of the conductive layer 212a and a portion of the bottom surface of the conductive layer 212b. The insulating layer 106 may also cover an end portion of the semiconductor layer 208. The insulating layer 106 is provided between the insulating layer 120 and the conductive layer 212a, between the insulating layer 120 and the conductive layer 212b, between the semiconductor layer 208 and the conductive layer 212a, and between the semiconductor layer 208 and the conductive layer 212b.

[0299] Since the transistor 100 can refer to the description of Structural Example 1, detailed description is omitted.

[0300] <Structure Example 9> For a top view of the semiconductor device 10H, refer to Figure 7A . Figure 16A Shown along Figure 7A The cross-sectional view of the section along the dot-dash line A1-A2 is shown. Figure 16B Cross-sectional views along the dashed-dotted line B1 - B2 and the dashed-dotted line B3 - B4 are shown.

[0301] Semiconductor device 10H includes transistor 100C and transistor 200H. Transistor 100C differs primarily from transistor 100 included in semiconductor device 10A shown in Structural Example 2 in that insulating layer 120 has a stacked-layer structure. Transistor 200H differs primarily from transistor 200A included in semiconductor device 10A shown in Structural Example 2 in that insulating layer 120 has a stacked-layer structure and conductive layer 202 is provided between insulating layer 110 and insulating layer 120.

[0302] Conductive layer 202 is provided on insulating layer 110. Conductive layer 202 is formed in a different process from conductive layer 112a. Providing conductive layer 202 on insulating layer 110 shortens the distance between conductive layer 202, which serves as the second gate electrode, and semiconductor layer 208, thereby increasing the intensity of the gate electric field applied to semiconductor layer 208.

[0303] Figure 16A and Figure 16B The structure shown here is one in which conductive layer 202 is provided in contact with the top surface of insulating layer 110c. For insulating layer 110c in contact with conductive layer 202, it is preferable to use an insulating layer that does not easily diffuse the metal elements contained in conductive layer 202. Insulating layer 110c preferably functions as a barrier film to suppress gas escape from insulating layer 110b and also as a barrier film to suppress diffusion of metal elements from conductive layer 202. The above-mentioned materials can be used as appropriate for insulating layer 110c.

[0304] The insulating layer 120 is provided in contact with the top surface and side surfaces of the conductive layer 202. The insulating layer 120 preferably has a stacked structure. Figure 16A and Figure 16B The insulating layer 120 is shown as having a stacked structure of an insulating layer 120a and an insulating layer 120b on the insulating layer 120a. The insulating layer 120a in contact with the conductive layer 202 is preferably an insulating layer in which the metal element contained in the conductive layer 202 is not easily diffused. The insulating layer 120a is preferably used as a barrier film to suppress the diffusion of the metal element from the conductive layer 202. The insulating layer 120a can use the same material as the insulating layer 110a and the insulating layer 110c. The insulating layer 120a includes a region in contact with the insulating layer 110c. Note that the insulating layer 120a, the insulating layer 110a, and the insulating layer 110c can use the same material or different materials. The insulating layer 120b in contact with the semiconductor layer 208 is preferably made of an oxide or an oxynitride. The insulating layer 120b is preferably made of a film that releases oxygen when heated. The insulating layer 120b can use the same material as the insulating layer 110b. Note that the insulating layer 120b and the insulating layer 110b can use the same material or different materials.

[0305] Figure 16A and Figure 16B The insulating layer 120 is shown as having a two-layer stacked structure of the insulating layer 120a and the insulating layer 120b, but one embodiment of the present invention is not limited thereto. The insulating layer 120 may have a single-layer structure or a stacked structure of three or more layers.

[0306] Notice, Figure 16B The conductive layer 202 and the insulating layer 120 shown in FIG. 1 may also be used in other structural examples.

[0307] <Structural Example 10> A transistor group including a plurality of transistors may be used instead of the transistor 100 , the transistor 100A, the transistor 100B, and the transistor 100C described above. Figure 17A A top view of a semiconductor device 10J including a transistor group is shown. Figure 17B Shown along Figure 17A The cross-sectional view is a cross-sectional view taken along the dashed line A3-A4. Figure 18A A perspective view of a semiconductor device 10J is shown.

[0308] The semiconductor device 10J includes a transistor group 100D and a transistor 200A. The semiconductor device 10J differs from the semiconductor device 10A shown in the second structural example in that the semiconductor device 10J includes a transistor group 100D instead of the transistor 100.

[0309] Figure 18B The equivalent circuit diagram of transistor group 100D is shown. Transistor group 100D includes transistors 100_1 through 100_4. Transistors 100_1 through 100_4 are connected in parallel, and transistor group 100D can be considered a single transistor. The gate electrodes of transistors 100_1 through 100_4 are electrically connected to one another. The source electrodes of transistors 100_1 through 100_4 are electrically connected to one another. The drain electrodes of transistors 100_1 through 100_4 are electrically connected to one another.

[0310] Note that although a structure in which four transistors are connected in parallel is shown here, one embodiment of the present invention is not limited thereto. There is no particular limitation on the number of transistors connected in parallel. Figure 18C As shown, the transistor group 100D may include transistors 100_1 to 100_p (p is an integer greater than or equal to 2). The transistors 100_1 to 100_p are connected in parallel, and the transistor group 100D may be regarded as one transistor.

[0311] The gate electrodes of transistors 100_1 to 100_p are electrically connected to one another. The source electrodes of transistors 100_1 to 100_p are electrically connected to one another. The drain electrodes of transistors 100_1 to 100_p are electrically connected to one another.

[0312] Notice, Figure 18B and Figure 18C Each transistor is an n-channel transistor, but one embodiment of the present invention is not limited thereto. Each transistor may also be a p-channel transistor.

[0313] The transistors included in the transistor group 100D may adopt the structure of any of the transistors 100 to 100C described above. Figure 17B Show that Figure 1B The structure of transistor 100 shown in FIG. 1 is used as an example for transistors 100_1 through 100_4. Transistor group 100D includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. Conductive layer 104 serves as the gate electrode for transistors 100_1 through 100_4. A portion of insulating layer 106 serves as the gate insulating layer for transistors 100_1 through 100_4. Conductive layer 112a serves as one of the source and drain electrodes for transistors 100_1 through 100_4, while conductive layer 112b serves as the other of the source and drain electrodes. Regarding transistor 200A, reference can be made to the above description, so a detailed description will be omitted.

[0314] Figure 19A 1 is a perspective view schematically showing the conductive layer 112a included in the transistor group 100D and the conductive layer 202 included in the transistor 200A. The conductive layer 112a includes openings 145_1 to 145_4 in the region in contact with the semiconductor layer 108. The conductive layer 112a_1 is exposed in the openings 145_1 to 145_4.

[0315] Figure 19B 1 is a perspective view schematically showing the conductive layer 112a, the conductive layer 112b, the openings 141_1 to 141_4, and the openings 143_1 to 143_4 included in the transistor group 100D, and the conductive layer 202 included in the transistor 200A. Note that the openings 141_1 to 141_4 provided in the insulating layer 110 and the insulating layer 120 are indicated by dotted lines. The openings 141_1 to 141_4 are preferably provided in a region overlapping with the openings 145_1 to 145_4. The conductive layer 112a_1 is preferably exposed in the openings 141_1 to 141_4. In addition, as shown in FIG. Figure 19B As shown, the conductive layer 112 b includes openings 143_1 to 143_4 in a region overlapping with the conductive layer 112 a .

[0316] The top surfaces of openings 141_1 through 141_4 and openings 143_1 through 143_4 are preferably circular. Furthermore, the widths of openings 141_1 through 141_4 are preferably equal or substantially equal. Similarly, the widths of openings 143_1 through 143_4 are preferably equal or substantially equal. When the widths of openings 141_1 through 141_4 are equal or substantially equal, and the widths of openings 143_1 through 143_4 are equal or substantially equal, the processing accuracy when forming openings 141_1 through 141_4 and openings 143_1 through 143_4 can be improved.

[0317] When the transistor group 100D is regarded as a single transistor, the channel width of the transistor is the sum of the channel widths of the transistors 100_1 to 100_4. For example, when the top surfaces of the openings 143_1 to 143_4 are circular and the widths of the openings 143_1 to 143_4 are each expressed as width D143, the transistor group 100D can be regarded as a transistor with a channel width of "D143×π×4" (see Figure 4A and Figure 4B ). The transistor group 100D composed of p transistors can be regarded as a transistor having a channel width of "D143×π×p". In addition, the transistor group 100D can be regarded as a transistor having a channel length L100 (refer to Figure 4B By connecting multiple transistors in parallel, the channel width increases, which can increase the on-state current. Furthermore, by adjusting the number of transistors connected in parallel (p), the channel width can be varied. The number of transistors connected in parallel (p) can be determined to achieve the desired on-state current.

[0318] Figure 20A 1 is a perspective view schematically showing the conductive layer 112a and the semiconductor layer 108 included in the transistor group 100D and the conductive layer 202 and the semiconductor layer 208 included in the transistor 200A. Figure 20A As shown, the semiconductor layer 108 is provided so as to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4. In the openings 141_1 to 141_4, the semiconductor layer 108 includes a region in contact with the top surface of the conductive layer 112a. Specifically, in the openings 141_1 to 141_4, the semiconductor layer 108 preferably includes a region in contact with the top surface of the conductive layer 112a_1. Note that Figure 20A Although the transistors 100_1 to 100_4 share the semiconductor layer 108, one embodiment of the present invention is not limited thereto. The semiconductor layer 108 may be separated for each of the transistors 100_1 to 100_4.

[0319] Notice, Figure 19A, etc., illustrate a structure in which the conductive layer 112a includes four openings 145 (opening 145_1 to opening 145_4). However, one embodiment of the present invention is not limited thereto. The conductive layer 112a may include at least one opening including openings 141_1 to 141_4. For example, the conductive layer 112a may include a single opening including openings 141_1 to 141_4. In this opening, the semiconductor layer 108 of the transistors 100_1 to 100_4 may also be in contact with the conductive layer 112a_1.

[0320] Figure 20B 1 is a perspective view schematically showing the conductive layer 112a and the conductive layer 104 included in the transistor group 100D and the conductive layer 202 and the conductive layer 204 included in the transistor 200A. Figure 20B As shown, the conductive layer 104 is disposed to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4 .

[0321] Figure 17B The above-mentioned transistors 100 are connected in parallel, but one embodiment of the present invention is not limited thereto. A transistor group in which any one of the transistors 100, 100A, 100B, and 100C is connected in parallel may be used.

[0322] Notice, Figure 17A The top view and Figure 18A The perspective diagrams shown in FIG and FIG show a structure in which the transistors 100_1 to 100_4 are arranged in two rows and two columns. However, there is no particular limitation on the arrangement of the transistors included in the transistor group 100D. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0323] Notice, Figure 17A The transistor group 100D shown in FIG. 1 can also be used in other structural examples.

[0324] <Structural Example 11> Figure 21A A top view of the semiconductor device 10K is shown. Figure 21B Shown along Figure 21A The cross-sectional view is a cross-sectional view taken along the dashed line A5-A6. Figure 22A A perspective view of a semiconductor device 10K is shown.

[0325] The semiconductor device 10K includes a transistor group 100E and a transistor 200A. The semiconductor device 10K differs from the semiconductor device 10J shown in the above-described structural example 10 mainly in that the semiconductor device 10K includes a transistor group 100E instead of the transistor group 100D.

[0326] In the transistor group 100E, the above-mentioned transistors 100 are connected in series. Figure 22B FIG. 1 shows an equivalent circuit diagram of a transistor group 100E. The transistor group 100E includes transistors 100_1 to 100_4. The transistors 100_1 to 100_4 are connected in series, and the transistor group 100E can be regarded as a single transistor.

[0327] Note that although a structure in which four transistors are connected in series is shown here, one embodiment of the present invention is not limited thereto. There is no particular limitation on the number of transistors connected in series. Figure 22C As shown, the transistor group 100E may include transistors 100_1 to 100_q (q is an integer greater than or equal to 2). The transistors 100_1 to 100_q are connected in series, and the transistor group 100E may be regarded as one transistor.

[0328] Notice, Figure 22B and Figure 22C Although each transistor shown is an n-channel transistor, one embodiment of the present invention is not limited thereto and each transistor may be a p-channel transistor.

[0329] The transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. The conductive layer 112a serves as one of a source electrode and a drain electrode of the transistor 100_1, and the conductive layer 112b serves as the other.

[0330] Transistor 100_2 includes conductive layer 104, insulating layer 106, semiconductor layer 108_2, conductive layer 112b, and conductive layer 112c. Conductive layer 112b serves as one of the source and drain electrodes of transistor 100_2, while conductive layer 112c serves as the other. Conductive layer 112b is shared by transistor 100_1 and transistor 100_2.

[0331] Transistor 100_3 includes conductive layer 104, insulating layer 106, semiconductor layer 108_3, conductive layer 112c, and conductive layer 112d. Conductive layer 112c serves as one of the source and drain electrodes of transistor 100_3, while conductive layer 112d serves as the other. Conductive layer 112c is shared by transistors 100_2 and 100_3.

[0332] Transistor 100_4 includes conductive layer 104, insulating layer 106, semiconductor layer 108_4, conductive layer 112d, and conductive layer 112e. Conductive layer 112d serves as one of the source and drain electrodes of transistor 100_4, while conductive layer 112e serves as the other. Conductive layer 112d is shared by transistor 100_3 and transistor 100_4.

[0333] Figure 23A This is a perspective view schematically illustrating the conductive layers 112a, 112c, and 112e included in the transistor group 100E, and the conductive layer 202 included in the transistor 200A. The conductive layers 112a, 112c, 112e, and 202 can be formed through the same process. A structure can be employed in which the conductive layer 112a_2 includes an opening 145_1, and the semiconductor layer 108_1 contacts the conductive layer 112a_1 through the opening 145_1. A structure can be employed in which the conductive layer 112c_2 includes an opening 145_2 and an opening 145_3, and the semiconductor layers 108_2 and 108_3 contact the conductive layer 112c_1 through the openings 145_2 and 145_3. The following structure may be employed: the conductive layer 112 e_2 includes an opening 145_4 , and the semiconductor layer 108_4 contacts the conductive layer 112 e_1 through the opening 145_4 .

[0334] Figure 23B 143_1 and 143_2 are provided in the conductive layer 112b, and the conductive layer 112d has openings 143_3 and 143_4.

[0335] Figure 24A 1 is a perspective view schematically illustrating the conductive layers 112a, 112c, and 112e, the semiconductor layers 108_1 to 108_4 included in the transistor group 100E, and the conductive layer 202 and the semiconductor layer 208 included in the transistor 200A. The semiconductor layers 108_1 to 108_4 and the semiconductor layer 208 can be formed in the same process.

[0336] Figure 24B 1 is a perspective view schematically showing conductive layers 112a, 112c, 112e, and 104 included in transistor group 100E, and conductive layers 202 and 204 included in transistor 200A. Conductive layer 104 serves as gate electrodes of transistors 100_1 to 100_4.

[0337] The other of the source and drain electrodes of the transistor 100_1 is electrically connected to one of the source and drain electrodes of the transistor 100_2. The other of the source and drain electrodes of the transistor 100_2 is electrically connected to one of the source and drain electrodes of the transistor 100_3. The other of the source and drain electrodes of the transistor 100_3 is electrically connected to one of the source and drain electrodes of the transistor 100_4.

[0338] When the transistor group 100E is regarded as a single transistor, the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4. For example, when the channel lengths of the transistors 100_1 to 100_4 are each expressed as a channel length L100, the transistor group 100E can be regarded as a transistor with a channel length of "L100×4" (see Figure 4B ). The transistor group 100E composed of q transistors can be regarded as a transistor having a channel length of "L100×q". In addition, the transistor group 100E can be regarded as a transistor having a channel width of W100 (refer to Figure 4A and Figure 4B By connecting multiple transistors in series, the channel length increases, which can improve saturation. Furthermore, by adjusting the number of transistors connected in series (q), the channel length can be varied. The number of transistors connected in series (q) can be determined to achieve the desired saturation.

[0339] Figure 21B The transistors 100 are connected in series, but one embodiment of the present invention is not limited thereto. A transistor group in which any one of the transistors 100, 100A, 100B, and 100C is connected in series may be used.

[0340] Notice, Figure 21A The top view and Figure 22A The perspective diagrams shown in FIG and FIG show a structure in which the transistors 100_1 to 100_4 are arranged in two rows and two columns. However, there is no particular limitation on the arrangement of the transistors included in the transistor group 100E. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0341] Notice, Figure 21A The transistor group 100E shown in FIG. 1 can also be used in other structural examples.

[0342] <Manufacturing Method Example 1> Hereinafter, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to the accompanying drawings. Figure 7BThe semiconductor layer 108 and the semiconductor layer 208 of the semiconductor device 10A shown in FIG. 1A and FIG. 2A are described using an oxide semiconductor structure as an example of a manufacturing method thereof.

[0343] Note that thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). Examples of CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD. Furthermore, one thermal CVD method includes metal organic chemical vapor deposition (MOCVD).

[0344] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and blade coating.

[0345] When processing thin films constituting semiconductor devices, photolithography or other methods can be used. Alternatively, thin films can be processed using nanoimprinting, sandblasting, lift-off, or other methods. Furthermore, island-shaped thin films can be directly formed using a deposition method using a shadow mask such as a metal mask.

[0346] Photolithography typically involves two methods. One involves forming a resist mask on the film to be processed, processing the film by etching, etc., and then removing the resist mask. The other involves forming a photosensitive film, then exposing it to light and developing it, processing the film into the desired shape.

[0347] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm) or a mixture of these lights can be used. In addition, ultraviolet light, KrF laser or ArF laser, etc. can also be used. In addition, exposure can also be performed using liquid immersion exposure technology. In addition, as the light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-violet) light or X-rays can also be used. In addition, an electron beam can also be used instead of the light used for exposure. When extreme ultraviolet light, X-rays or electron beams are used, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0348] As a method for etching the thin film, for example, dry etching, wet etching, or sand blasting can be used.

[0349] Figures 25A to 28C The drawings are diagrams for explaining a method for manufacturing the semiconductor device 10A, and are cross-sectional views taken along a dashed line A1-A2.

[0350] [Formation of Conductive Layer 112a and Conductive Layer 202] A conductive film 112a_1f to be the conductive layer 112a_1 and the conductive layer 202_1 and a conductive film 112a_2f to be the conductive layer 112a_2 and the conductive layer 202_2 are formed over the substrate 102. Figure 25A The conductive films 112a_1f and 112a_2f can be formed by, for example, sputtering as appropriate.

[0351] Next, a resist mask is formed on the conductive films 112a_1f and 112a_2f by a photolithography process, and then the conductive films 112a_1f and 112a_2f are processed to form the conductive layer 112a_1 and the conductive layer 112a_2A on the conductive layer 112a_1, and the conductive layer 202_1 and the conductive layer 202_2 on the conductive layer 202_1 ( Figure 25B The conductive films 112a-1f and 112a-2f can be processed by one or both of wet etching and dry etching. Thus, the conductive layer 202 serving as the second gate electrode of the transistor 200A is formed.

[0352] Next, a portion of the conductive layer 112a_2A is removed to form a conductive layer 112a_2 ( Figure 25C ). Thus, a conductive layer 112a serving as one of a source electrode and a drain electrode of the transistor 100 is formed.

[0353] [Formation of Insulating Film 110af and Insulating Film 110bf] Next, an insulating film 110 af to become the insulating layer 110 a and an insulating film 110 bf to become the insulating layer 110 b are formed over the substrate 102 , the conductive layer 112 a , and the conductive layer 202 .

[0354] The insulating films 110af and 110bf can be formed using a PECVD method. After forming the insulating film 110af, the insulating film 110bf is preferably formed continuously in a vacuum, without exposing the surface of the insulating film 110af to the atmosphere. By continuously forming the insulating films 110af and 110bf, it is possible to suppress the adhesion of impurities from the atmosphere to the surface of the insulating film 110af. Examples of such impurities include water and organic matter.

[0355] The substrate temperature during formation of the insulating films 110af and 110bf is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and even more preferably 350°C to 400°C. By setting the substrate temperature during formation of the insulating films 110af and 110bf within the above range, the release of impurities (e.g., water and hydrogen) from the insulating films 110af and 110bf themselves can be reduced, thereby suppressing the diffusion of impurities into the semiconductor layer 108. Consequently, a transistor exhibiting excellent electrical characteristics and high reliability can be realized.

[0356] Note that since the insulating films 110af and 110bf are formed first and then the semiconductor layers 108 and 208 are formed, there is no concern that oxygen will be released from the semiconductor layers 108 and 208 due to heat applied when forming the insulating films 110af and 110bf.

[0357] Heat treatment may be performed after the insulating films 110af and 110bf are formed. The heat treatment can remove water and hydrogen from the surfaces and the inner layers of the insulating films 110af and 110bf.

[0358] The heat treatment temperature is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. Clean dry air (CDA) can also be used as a nitrogen-containing or oxygen-containing atmosphere. Note that the content of hydrogen, oxygen, and the like in this atmosphere is preferably as low as possible. A high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is preferably used. Using an atmosphere with minimal hydrogen, water, and the like content minimizes absorption of hydrogen, water, and the like by the insulating films 110af and 110bf. This heat treatment can be performed in, for example, an oven or a rapid thermal annealing (RTA) apparatus. Using an RTA apparatus can shorten the heat treatment time.

[0359] Next, a metal oxide layer 180 ( Figure 25D ).

[0360] The metal oxide layer 180 can be either an insulating layer or a conductive layer. The metal oxide layer 180 can be made of, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO).

[0361] The metal oxide layer 180 is preferably an oxide material containing one or more elements common to the semiconductor layer 108 or the semiconductor layer 208. In particular, an oxide semiconductor material that can be used for the semiconductor layer 108 or the semiconductor layer 208 is preferably used.

[0362] The metal oxide layer 180 may be a metal oxide film formed using a sputtering target having the same composition as the semiconductor layer 108 or the semiconductor layer 208. Using a sputtering target having the same composition is preferred because a production apparatus and a sputtering target can be used in common.

[0363] When a metal oxide material containing indium and gallium is used for the semiconductor layers 108, 208, and 180, the metal oxide layer 180 may use a material having a higher gallium content than the semiconductor layers 108 and 208. Using a material having a high gallium content for the metal oxide layer 180 is preferred because it can improve the barrier properties against oxygen.

[0364] The metal oxide layer 180 is preferably formed in an oxygen-containing atmosphere, for example. In particular, it is preferably formed by sputtering in an oxygen-containing atmosphere. This allows oxygen to be appropriately supplied to the insulating film 110bf during the formation of the metal oxide layer 180.

[0365] For example, oxygen may be used as a deposition gas, and the metal oxide layer 180 may be formed by a reactive sputtering method using a metal target. For example, when aluminum is used as a metal target, an aluminum oxide film may be formed.

[0366] When forming metal oxide layer 180, a higher oxygen flow rate ratio of the deposition gas introduced into the process chamber of the deposition apparatus or a higher oxygen partial pressure within the process chamber can increase the amount of oxygen supplied to insulating film 110bf. The oxygen flow rate ratio or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% to keep the oxygen partial pressure as close to 100% as possible.

[0367] In this way, by forming the metal oxide layer 180 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf while preventing oxygen from being released from the insulating film 110bf during the formation of the metal oxide layer 180. As a result, a large amount of oxygen can be enclosed in the insulating film 110bf. Furthermore, a large amount of oxygen can be supplied to the semiconductor layer 108 during the subsequent heat treatment. As a result, the oxygen vacancies (V O ) and V O H, and a transistor with good electrical characteristics and high reliability can be realized.

[0368] Heat treatment may be performed after forming the metal oxide layer 180. Regarding the heat treatment, reference can be made to the above description, so detailed description is omitted. Performing heat treatment after forming the metal oxide layer 180 allows oxygen to be efficiently supplied from the metal oxide layer 180 to the insulating film 110bf.

[0369] After forming the metal oxide layer 180 or after the aforementioned heat treatment, oxygen may be supplied to the insulating film 110bf through the metal oxide layer 180. Examples of methods for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatuses that convert gas into plasma using high-frequency power include plasma etching equipment and plasma ashing equipment.

[0370] Next, the metal oxide layer 180 is removed.

[0371] While there are no particular limitations on the method for removing the metal oxide layer 180, a wet etching method can be appropriately employed. By utilizing the wet etching method, etching of the insulating film 110bf can be suppressed when removing the metal oxide layer 180. Consequently, the thickness of the insulating film 110bf can be suppressed from being reduced, and the thickness of the insulating layer 110b can be made uniform.

[0372] The oxygen supply treatment for the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. can be supplied to the insulating film 110bf using ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that inhibits oxygen desorption may be formed on the insulating film 110bf, and then oxygen may be added to the insulating film 110bf through the film. Preferably, the film is removed after the oxygen is supplied. The film that inhibits oxygen desorption may be a conductive film or semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0373] [Formation of Insulating Film 110cf and Formation of Insulating Film 120f] Next, an insulating film 110cf to become the insulating layer 110c and an insulating film 120f to become the insulating layer 120 are formed on the insulating film 110bf. Figure 25E Since the formation of the insulating film 110cf and the insulating film 120f can refer to the description of the formation of the insulating film 110af and the insulating film 110bf, their detailed description is omitted.

[0374] [Formation of Conductive Film 112f] Next, a conductive film 112f ( Figure 26A ) The conductive film 112f can be formed by, for example, sputtering as appropriate.

[0375] [Formation of Opening 141 and Formation of Opening 143] Next, the conductive film 112f is processed to form a conductive layer 112B ( Figure 26B The conductive layer 112B can be formed by using one or both of a wet etching method and a dry etching method. For example, the conductive layer 112B can be formed by using a wet etching method as appropriate.

[0376] Next, the conductive layer 112B in the region overlapping the opening 145 is removed to form the conductive layer 112b including the opening 143. The opening 143 can be formed using one or both of wet etching and dry etching. For example, the opening 143 can be formed using wet etching as appropriate.

[0377] Next, the insulating film 120f and the insulating film 110f (insulating film 110af, insulating film 110bf, and insulating film 110cf) in the region overlapping with the opening 143 are removed, and the insulating layer 120 and the insulating layer 110 ( Figure 26C The opening 141 can be formed by wet etching or dry etching, or both. For example, the opening 141 can be formed by dry etching as appropriate. The opening 141 is provided in a region overlapping the opening 145. The conductive layer 112a_1 is exposed in the opening 145.

[0378] The opening 141 can be formed using, for example, a resist mask used to form the opening 143. Specifically, a resist mask can be formed on the conductive film 112f, and the conductive film 112f can be removed using the resist mask to form the opening 143. The insulating film 120f and the insulating film 110f can also be removed using the resist mask to form the opening 141. The opening 143 can also be formed using a resist mask different from the resist mask used to form the opening 141.

[0379] Alternatively, a portion of the conductive layer 112a (specifically, the conductive layer 112a_1) in the region overlapping with the opening 141 may be removed when or after the opening 141 is formed. By removing a portion of the conductive layer 112a_1, Figure 6A and Figure 6B The structure shown.

[0380] [Formation of Semiconductor Layer 108 and Semiconductor Layer 208] Next, a metal oxide film 108f ( 108f ) to be the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the opening 141 and the opening 143 . Figure 26D The metal oxide film 108f is provided in contact with the top surface of the insulating layer 120, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a_1.

[0381] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

[0382] The metal oxide film 108f is preferably a dense film with as few defects as possible. The metal oxide film 108f is preferably a high-purity film with as few impurities as possible containing hydrogen. In particular, a crystalline metal oxide film is preferably used as the metal oxide film 108f.

[0383] When forming the metal oxide film 108f, an oxygen gas is preferably used. By using an oxygen gas when forming the metal oxide film 108f, oxygen can be appropriately supplied to the insulating layer 120 and the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 120, oxygen can be appropriately supplied to the insulating layer 120. Similarly, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be appropriately supplied to the insulating layer 110b.

[0384] By supplying oxygen to the insulating layer 120 and the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 and the semiconductor layer 208 in a subsequent step, thereby reducing oxygen vacancies (V O ) and V O H.

[0385] When depositing the metal oxide film 108f, an oxygen gas and an inert gas (e.g., helium, argon, xenon, etc.) may be mixed. Note that, as the oxygen flow rate ratio or oxygen partial pressure during deposition of the metal oxide film 108f increases, the crystallinity of the metal oxide film 108f increases, and a transistor with high reliability can be realized. On the other hand, as the oxygen flow rate ratio or oxygen partial pressure decreases, the crystallinity of the metal oxide film 108f decreases, and a transistor with high on-state current can be realized.

[0386] When the substrate temperature is high during the formation of the metal oxide film 108f, a more crystalline and dense metal oxide film can be formed. On the other hand, when the substrate temperature is low, a less crystalline and more conductive metal oxide film 108f can be formed.

[0387] The substrate temperature during formation of the metal oxide film 108f is preferably between room temperature and 250°C, preferably between room temperature and 200°C, and more preferably between room temperature and 140°C. For example, the substrate temperature is preferably between room temperature and below 140°C to improve productivity. By depositing the metal oxide film 108f at room temperature or without heating the substrate, the crystallinity can be reduced.

[0388] Before depositing the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing impurities (for example, water, hydrogen, and organic matter) adsorbed on the surfaces of the insulating layer 120 and the insulating layer 110 and a treatment for supplying oxygen to the insulating layer 120 and the insulating layer 110. For example, a heat treatment can be performed at a temperature of 70°C to 200°C in a reduced pressure atmosphere. Alternatively, a plasma treatment in an oxygen-containing atmosphere can be performed. Alternatively, oxygen can be supplied to the insulating layer 120 and the insulating layer 110 by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). When a plasma treatment containing nitrous oxide gas is performed, impurities on the surfaces of the insulating layer 120 and the insulating layer 110 can be appropriately removed and oxygen can be supplied to the insulating layer 120 and the insulating layer 110.

[0389] Note that when the semiconductor layer 108 and the semiconductor layer 208 have a stacked-layer structure, it is preferable that an upper metal oxide film be deposited continuously after a lower metal oxide film is deposited without exposing the surface of the metal oxide film to the atmosphere.

[0390] Next, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 ( Figure 27A ).

[0391] The semiconductor layer 108 and the semiconductor layer 208 can be formed using one or both of a wet etching method and a dry etching method. The semiconductor layer 108 and the semiconductor layer 208 can be formed using, for example, a wet etching method as appropriate. At this time, sometimes a portion of the conductive layer 112b in the area that does not overlap with the semiconductor layer 108 is etched and thinned. Similarly, sometimes a portion of the insulating layer 120 in the area that does not overlap with the semiconductor layer 108, the conductive layer 112b, and the semiconductor layer 208 is etched and the thickness becomes smaller. For example, sometimes the insulating layer 120 in the area that does not overlap with the semiconductor layer 108, the conductive layer 112b, and the semiconductor layer 208 disappears due to etching, and the surface of the insulating layer 110 (specifically, the insulating layer 110c) is exposed. Note that in the etching of the metal oxide film 108f, by using a material with a high selectivity as the insulating layer 110c, the thickness of the insulating layer 110c can be suppressed from being reduced.

[0392] It is preferable to perform heat treatment after depositing the metal oxide film 108f or processing the metal oxide film 108f into the semiconductor layer 108 or the semiconductor layer 208. The heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108 or the semiconductor layer 208 or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108 or the semiconductor layer 208. In addition, the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 or the semiconductor layer 208 (for example, reduce defects and improve crystallinity).

[0393] The heat treatment allows oxygen to be supplied from the insulating layer 110b and the insulating layer 120 to the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208. In this case, the heat treatment is preferably performed before processing into the semiconductor layer 108 and the semiconductor layer 208. The heat treatment can be referred to above, and detailed description thereof will be omitted.

[0394] Note that this heat treatment is not necessarily required. It is also possible to skip the heat treatment in this step and use the heat treatment performed in a subsequent step as the heat treatment in this step. Sometimes, a high-temperature treatment in a subsequent step (e.g., a deposition step) can also be used as the heat treatment in this step.

[0395] [Formation of Insulating Layer 106] Next, the insulating layer 106 is formed so as to cover the semiconductor layer 108, the conductive layer 112b, the semiconductor layer 208, and the insulating layer 120. Figure 27B The insulating layer 106 can be formed by a PECVD method as appropriate.

[0396] When an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 is preferably used as a barrier film for suppressing oxygen diffusion. By providing the insulating layer 106 with the function of suppressing oxygen diffusion, diffusion of oxygen in the semiconductor layer 108 and the semiconductor layer 208 to the upper side of the insulating layer 106 is suppressed, thereby suppressing the increase of oxygen vacancies (V O ). As a result, a transistor having good electrical characteristics and high reliability can be realized.

[0397] By increasing the temperature at which the insulating layer 106 serving as the gate insulating layer of the transistor 100 and the transistor 200A is formed, an insulating layer with fewer defects can be formed. However, when the temperature at which the insulating layer 106 is formed is high, oxygen is released from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V O ) and V O H increases. The substrate temperature during formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, more preferably 250° C. or higher and 450° C. or lower, more preferably 300° C. or higher and 450° C. or lower, and more preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced while oxygen desorption from the semiconductor layers 108 and 208 can be suppressed. Consequently, a transistor exhibiting excellent electrical characteristics and high reliability can be realized.

[0398] Before forming the insulating layer 106, the surface of the semiconductor layer 108 and the surface of the semiconductor layer 208 may also be subjected to plasma treatment. By this plasma treatment, impurities (for example, water) adsorbed on the surface of the semiconductor layer 108 and the surface of the semiconductor layer 208 can be reduced. Therefore, impurities in the interface between the semiconductor layer 108 and the insulating layer 106 and the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, so that a transistor with high reliability can be realized. In particular, it is preferable to perform plasma treatment when the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the atmosphere between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106. The plasma treatment can be performed, for example, in an atmosphere containing one or more of oxygen, ozone, nitrogen, nitrous oxide and argon. The plasma treatment and the deposition of the insulating layer 106 are preferably performed continuously without being exposed to the atmosphere.

[0399] [Formation of Conductive Layers 104 and 204] Next, a conductive film 104f ( 104f ) to be the conductive layer 104 and the conductive layer 204 is formed on the insulating layer 106. Figure 27C) The conductive film 104f can be formed by, for example, sputtering as appropriate.

[0400] Next, a resist mask is formed over the conductive film 104f by a photolithography process, and then the conductive film 104f is processed, thereby forming the conductive layer 104 serving as the gate electrode of the transistor 100 and the conductive layer 204 serving as the first gate electrode of the transistor 200A ( Figure 28A ) The conductive film 104f can be processed by using one or both of a wet etching method and a dry etching method.

[0401] Through the above steps, the transistor 100 can be manufactured.

[0402] [Formation of Region 208D] Next, the impurity 190 (also referred to as adding or implanting) is supplied to the semiconductor layer 208 through the insulating layer 106 using the conductive layer 204 as a mask. Figure 28B ).exist Figure 28B In FIG, the supplied impurity 190 is indicated by an arrow. This allows the formation of a region 208D in the semiconductor layer 208 that does not overlap with the conductive layer 204. At this time, it is preferable to determine the processing conditions for supplying the impurity 190 based on the material and thickness of the conductive layer 204, which serves as a mask, so that the impurity 190 is minimized in the region of the semiconductor layer 208 that overlaps with the conductive layer 204. This allows the formation of a channel formation region with a sufficiently low impurity concentration in the region of the semiconductor layer 208 that overlaps with the conductive layer 204. Similarly, the semiconductor layer 108 also forms a region 108D in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104.

[0403] The impurity 190 can be supplied using a plasma ion doping method or an ion implantation method as appropriate. By using these methods, the concentration distribution in the depth direction can be controlled with high precision according to the ion acceleration voltage and dose, etc. By using the plasma doping method, productivity can be improved. In addition, by using the ion implantation method using mass separation, the purity of the supplied impurities can be increased.

[0404] In the process of supplying the impurity 190, the process conditions are preferably controlled so that the concentration is highest at the interface between the semiconductor layer 208 and the insulating layer 106, at a portion of the semiconductor layer 208 close to the interface, or at a portion of the insulating layer 106 close to the interface. This allows the impurity 190 having an optimal concentration to be supplied to both the semiconductor layer 208 and the insulating layer 106 in a single process.

[0405] As a raw material for supplying the impurity 190, for example, a gas containing the above-mentioned impurity elements can be used. When supplying boron, typically one or more of B2H6 gas and BF3 gas can be used. In addition, when supplying phosphorus, typically PH3 gas can be used. Alternatively, a mixed gas in which these source gases are diluted with a rare gas can be used.

[0406] As a raw material for supplying the impurity 190, for example, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Note that the raw material is not limited to gases; solids or liquids may be heated and vaporized.

[0407] By setting conditions such as the acceleration voltage and the dose according to the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 208, the addition of the impurity 190 can be controlled.

[0408] When boron is added by ion implantation or plasma ion doping, the acceleration voltage may be, for example, 5 kV to 100 kV, preferably 7 kV to 70 kV, more preferably 10 kV to 50 kV. In addition, the dose may be, for example, 1×10 13 ions / cm 2 Above and 1×10 17 ions / cm 2 Below, preferably 1×10 14 ions / cm 2 Above and 5×10 16 ions / cm 2 Below, more preferably 1×10 15 ions / cm 2 Above and 3×10 16 ions / cm 2 the following.

[0409] When phosphorus ions are added by ion implantation or plasma ion doping, the acceleration voltage may be, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, and more preferably 40 kV or more and 80 kV or less. 13 ions / cm 2 Above and 1×10 17 ions / cm 2 Below, preferably 1×10 14 ions / cm 2 Above and 5×10 16 ions / cm 2 Below, more preferably 1×10 15ions / cm 2 Above and 3×10 16 ions / cm 2 the following.

[0410] Note that the method for supplying the impurity 190 is not limited to this method; for example, plasma treatment or treatment utilizing thermal diffusion caused by heating may also be performed. When plasma treatment is employed, the impurity can be added by first generating plasma in a gas atmosphere containing the impurity to be added and then performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

[0411] For example, by performing plasma treatment in an atmosphere containing hydrogen gas using a plasma CVD apparatus, hydrogen can be supplied as the impurity 190 to the region of the semiconductor layer 208 that does not overlap with the conductive layer 204 and the region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Furthermore, by using the plasma CVD apparatus for performing the process of supplying the impurity 190 and forming the insulating layer 106, the process of supplying the impurity 190 and forming the insulating layer 106 can be performed continuously within the apparatus, thereby improving productivity.

[0412] In one embodiment of the present invention, the impurity 190 can be supplied to the semiconductor layer 208 through the insulating layer 106. This can suppress damage to the semiconductor layer 208 during the supply of the impurity 190, even when the semiconductor layer 208 is crystalline, thereby suppressing loss of crystallinity. This is suitable for applications where resistance increases due to reduced crystallinity. Similarly, damage to the semiconductor layer 108 can be reduced.

[0413] [Formation of Insulating Layer 195] Next, an insulating layer 195 is formed so as to cover the conductive layer 104, the conductive layer 204, and the insulating layer 106 ( Figure 28C ) The insulating layer 195 can be formed by using a PECVD method as appropriate.

[0414] If the deposition temperature of insulating layer 195 is too high, impurities contained in regions 108D and 208D may diffuse into the peripheral portions of semiconductor layers 108 and 208, including the channel formation regions. Furthermore, the resistance of regions 108D and 208D may increase. Therefore, the deposition temperature of insulating layer 195 should be determined in consideration of the diffusion of impurities.

[0415] The deposition temperature of insulating layer 195 is preferably, for example, 150° C. to 400° C., more preferably 180° C. to 360° C., and even more preferably 200° C. to 250° C. By depositing insulating layer 195 at a low temperature, even a transistor with a short channel length can have excellent electrical characteristics.

[0416] Alternatively, a heat treatment may be performed after forming the insulating layer 195. This heat treatment can sometimes further reduce the resistance of the regions 108D and 208D. For example, by performing a heat treatment, it is possible to appropriately diffuse the impurities to form the regions 108D and 208D having an ideal concentration gradient of the impurity 190. For details about the heat treatment, reference can be made to the above description, so a detailed description is omitted. Note that when the heat treatment temperature is too high (e.g., above 500°C), the impurity 190 diffuses into the channel formation region, which may deteriorate the electrical characteristics and reliability of the transistor.

[0417] Note that this heat treatment is not necessarily required. Alternatively, heat treatment may be omitted in this step and a heat treatment performed in a subsequent step may be used as the heat treatment in this step. Sometimes, a high-temperature treatment in a subsequent step (e.g., a deposition step) may be used as the heat treatment in this step.

[0418] Next, the insulating layer 106 and the insulating layer 195 are partially etched to form an opening 147 a and an opening 147 b reaching the region 208D.

[0419] Next, a conductive film is formed over the insulating layer 195 so as to cover the openings 147a and 147b, and the conductive film is processed to form conductive layers 212a and 212b ( Figure 7B ).

[0420] Through the above steps, the transistor 200A can be manufactured.

[0421] Through the above-described steps, the semiconductor device 10A can be manufactured.

[0422] <Manufacturing Method Example 2> by Figure 13A The semiconductor layer 108 and the semiconductor layer 208 of the semiconductor device 10E shown in FIG. 1A and FIG. 2A are described using an oxide semiconductor structure as an example of a manufacturing method thereof.

[0423] Figures 29A to 30B Each of the drawings is a diagram for explaining a method for manufacturing the semiconductor device 10E, and each of the drawings is a cross-sectional view taken along a dashed line A1-A2.

[0424] The steps to form the insulating layer 106 are the same as those in the manufacturing method described in the above-mentioned <Manufacturing Method Example 1>. Figures 25A to 27B A method for manufacturing a semiconductor device.

[0425] [Formation of Insulating Layer 106A and Insulating Layer 106B] Next, a resist mask is formed on the insulating layer 106 by a photolithography process, and then the insulating layer 106 is processed, thereby forming an insulating layer 106A serving as a gate insulating layer of the transistor 100B and an insulating layer 106B serving as a first gate insulating layer of the transistor 200E ( Figure 29A The insulating layer 106A is provided in a region overlapping with the semiconductor layer 108. The insulating layer 106B is provided in a region overlapping with the semiconductor layer 208. The insulating layer 106 can be processed by wet etching or dry etching, or both. Dry etching can be used as appropriate for processing the insulating layer 106.

[0426] [Formation of Conductive Layers 104 and 204] Next, a conductive film 104f (which will become the conductive layers 104, 204, 212a, and 212b) is formed over the insulating layer 120, the conductive layer 112b, the semiconductor layer 108, the semiconductor layer 208, the insulating layer 106A, and the insulating layer 106B. Figure 29B ) The conductive film 104f can be formed by, for example, sputtering as appropriate.

[0427] Next, a resist mask is formed over the conductive film 104f by a photolithography process, and then the conductive film 104f is processed, thereby forming the conductive layer 104 serving as the gate electrode of the transistor 100B, the conductive layer 204 serving as the first gate electrode of the transistor 200A, and the conductive layers 212a and 212b serving as the source and drain electrodes ( Figure 30A The conductive layer 104 is provided in a region overlapping with the semiconductor layer 108 via the insulating layer 106A. The conductive layer 204 is provided in a region overlapping with the semiconductor layer 208 via the insulating layer 106B. The conductive film 104f can be processed by either or both wet etching and dry etching.

[0428] Through the above steps, the transistor 100B can be manufactured.

[0429] [Formation of Regions 208L and 208D] Next, the impurity 190 is supplied to the semiconductor layer 208 through the insulating layer 106B using the conductive layer 204, the conductive layer 212a, and the conductive layer 212b as masks. Figure 30B ).exist Figure 30BIn FIG, arrows indicate the supplied impurity 190. This allows the formation of regions 208L and 208D in semiconductor layer 208. Region 208L is formed in a region that overlaps with insulating layer 106B and does not overlap with conductive layer 204. Region 208D is formed in a region that does not overlap with insulating layer 106B, conductive layer 204, conductive layer 212a, and conductive layer 212b. The same applies to semiconductor layer 108, where regions 108L and 108D are formed. The supply of impurity 190 can be referred to the above description, so a detailed description will be omitted.

[0430] Since the formation of the insulating layer 195 can refer to the above-mentioned <Manufacturing Method Example 1>, detailed description is omitted.

[0431] Through the above steps, the transistor 200E can be manufactured.

[0432] Through the above-described steps, the semiconductor device 10E can be manufactured.

[0433] <Manufacturing Method Example 3> by Figure 14 A method for manufacturing the semiconductor layer 108 and the semiconductor layer 208 of the semiconductor device 10F shown in A will be described using an oxide semiconductor structure as an example.

[0434] Figures 31A to 32B Each of the drawings is a diagram for explaining a method for manufacturing the semiconductor device 10F. Each of the drawings is a cross-sectional view taken along a dashed line A1-A2.

[0435] The steps to form the insulating layer 106 are the same as those in the manufacturing method described in the above-mentioned <Manufacturing Method Example 1>. Figures 25A to 27B A method for manufacturing a semiconductor device.

[0436] [Formation of Insulating Layer 106A and Insulating Layer 106B] Next, the insulating layer 106 is processed to form openings 139a and 139b in the region overlapping with the semiconductor layer 208 ( Figure 31A The insulating layer 106 may be processed by one or both of a wet etching method and a dry etching method. The insulating layer 106 may be processed by a dry etching method as appropriate.

[0437] [Formation of Conductive Layer 104, Conductive Layer 204, Conductive Layer 212a, and Conductive Layer 212b] Next, a conductive film 104f (which will become the conductive layers 104, 204, 212a, and 212b) is formed over the insulating layer 120, the conductive layer 112b, the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 106. Figure 31B) The conductive film 104f can be formed by, for example, sputtering as appropriate.

[0438] Next, after forming a resist mask on the conductive film 104f by a photolithography process, the conductive film 104f and the insulating layer 106 are processed to form the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b, and the insulating layer 106A, the insulating layer 106B, the insulating layer 106C, and the insulating layer 106D ( Figure 32A ) The conductive film 104f and the insulating layer 106 can be processed by either or both of a wet etching method and a dry etching method.

[0439] Through the above steps, the transistor 100A can be manufactured.

[0440] [Formation of Region 208D] Next, the semiconductor layer 208 is supplied with impurities 190 ( Figure 32B ).exist Figure 32B In FIG, the supplied impurity 190 is indicated by an arrow. As a result, a region 208D can be formed in the semiconductor layer 208. The region 108D is also formed in the semiconductor layer 108. The supply of the impurity 190 can be referred to the above description, so detailed description is omitted.

[0441] Since the formation of the insulating layer 195 can refer to the above-mentioned <Manufacturing Method Example 1>, detailed description is omitted.

[0442] Through the above steps, the transistor 200F can be manufactured.

[0443] Through the above-described steps, the semiconductor device 10F can be manufactured.

[0444] <Manufacturing Method Example 4> by Figure 15B The semiconductor layer 108 and the semiconductor layer 208 of the semiconductor device 10G shown will be described using an oxide semiconductor structure as an example of a manufacturing method thereof.

[0445] Figures 33A to 34B Each of the drawings is a diagram for explaining a method for manufacturing the semiconductor device 10G, and each of the drawings is a cross-sectional view taken along a dashed line A1-A2.

[0446] The steps to form the insulating layer 106 are the same as those in the manufacturing method described in the above-mentioned <Manufacturing Method Example 1>. Figures 25A to 27B A method for manufacturing a semiconductor device.

[0447] [Formation of Openings 137a and 137b] Next, the insulating layer 106 is processed to form openings 137a and 137b in the region overlapping with the semiconductor layer 208 ( Figure 33A The insulating layer 106 can be processed by one or both of a wet etching method and a dry etching method. The insulating layer 106 can be processed by a dry etching method as appropriate.

[0448] [Formation of Conductive Layer 104, Conductive Layer 204, Conductive Layer 212a, and Conductive Layer 212b] Next, a conductive film 104f (which will become the conductive layers 104, 204, 212a, and 212b) is formed over the insulating layer 120, the conductive layer 112b, the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 106. Figure 33B ) The conductive film 104f can be formed by, for example, sputtering as appropriate.

[0449] Next, a resist mask is formed over the conductive film 104f by a photolithography process, and then the conductive film 104f is processed, thereby forming the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b ( Figure 34A ) The conductive film 104f can be processed by using one or both of a wet etching method and a dry etching method.

[0450] Through the above steps, the transistor 100 can be manufactured.

[0451] [Formation of Regions 208L and 208D] Next, the impurity 190 is supplied to the semiconductor layer 208 through the insulating layer 106 using the conductive layer 204, the conductive layer 212a, and the conductive layer 212b as masks ( Figure 34B ).exist Figure 34B In FIG, the supplied impurity 190 is indicated by arrows. As a result, regions 208L and 208D can be formed in the semiconductor layer 208. Region 208L is formed in a region that overlaps with the insulating layer 106 and does not overlap with the conductive layer 204. Region 208D is formed in a region that does not overlap with the insulating layer 106, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b. Similarly, region 108D is formed in a region of the semiconductor layer 108 that overlaps with the conductive layer 104. Note that the amount of impurity 190 supplied to region 108D may be substantially the same as the amount of impurity supplied to region 208L. The supply of impurity 190 can be referred to the above description, so a detailed description is omitted.

[0452] Since the formation of the insulating layer 195 can refer to the above-mentioned <Manufacturing Method Example 1>, detailed description is omitted.

[0453] Through the above steps, the transistor 200G can be manufactured.

[0454] Through the above-described steps, the semiconductor device 10G can be manufactured.

[0455] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0456] (Implementation Method 2) In this embodiment, a structural example of a display device in which a semiconductor device according to one embodiment of the present invention can be used will be described.

[0457] Figure 35A A perspective view of a display device 50 according to one embodiment of the present invention is shown. The display device 50 has a structure in which a substrate 152 and a substrate 101 are bonded together. Figure 35A , the substrate 152 is indicated by a dotted line.

[0458] The display device 50 includes a display portion 235 , a connection portion 140 , a first driver circuit portion 231 , a second driver circuit portion 232 , wiring 165 , and the like. Figure 35A The example in which the display device 50 is mounted with IC173 and FPC172 is shown. Figure 35A The structure shown is called a display module including a display device 50, an IC (integrated circuit), and an FPC.

[0459] The connection portion 140 is provided on the outer side of the display portion 235. The connection portion 140 may be provided along one side or multiple sides of the display portion 235. There may also be one or more connection portions 140. Figure 35A The example in which the connection portion 140 is provided so as to surround the four sides of the display portion 235 is shown. In the connection portion 140, the common electrode of the light emitting device is electrically connected to the conductive layer, and power can be supplied to the common electrode.

[0460] The wiring 165 has a function of supplying signals and power to the display portion 235, the first driver circuit portion 231, and the second driver circuit portion 232. The signals and power are input to the wiring 165 from the outside through the FPC 172 or from the IC 173.

[0461] Figure 35A The following illustrates an example of IC 173 being provided on substrate 101 using a COG (Chip On Glass) or COF (Chip On Film) method. IC 173 may also include, for example, a scan line driver circuit or a signal line driver circuit. Note that the display device 50 and the display module do not necessarily need to be provided with an IC. Alternatively, the IC may be mounted on an FPC using a COF method or the like.

[0462] The display unit 235 includes a plurality of pixels 230 arranged in a matrix. As the pixels 230, for example, three types of pixels, namely, pixel 230a, pixel 230b, and pixel 230c, can be used. Pixel 230a, pixel 230b, and pixel 230c all include a display device (also referred to as a display element). As display devices, for example, liquid crystal devices (also referred to as liquid crystal elements) and light-emitting devices can be cited. As light-emitting devices, for example, OLED (Organic Light Emitting Diode) and QLED (Quantum-dot Light Emitting Diode) are preferably used. As luminescent substances contained in the light-emitting device, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials) and inorganic compounds (quantum dot materials, etc.) can be cited. In addition, as light-emitting devices, LEDs such as Micro LEDs can also be used.

[0463] Pixels 230a, 230b, and 230c each have the function of presenting different light. For example, pixels 230a, 230b, and 230c may each have the function of presenting red (R), green (G), and blue (B), respectively. Alternatively, pixels 230a, 230b, and 230c may each have the function of presenting yellow (Y), cyan (C), and magenta (M), respectively.

[0464] By using one pixel 230a, one pixel 230b, and one pixel 230c to form one pixel 240, full-color display can be achieved. Therefore, the pixel 230 is used as a sub-pixel. Figure 35A The display device 50 shown in the figure shows an example of pixels 230 used as sub-pixels arranged in a stripe arrangement. The number of sub-pixels constituting a pixel 240 is not limited to three and may be four or more. For example, four sub-pixels each representing R, G, B, and white (W) light may be included. Alternatively, four sub-pixels each representing four types of light may be included.

[0465] Figure 35B 1 is a block diagram illustrating a display device 50. The display device 50 includes a display unit 235, a first drive circuit unit 231, and a second drive circuit unit 232. The display unit 235 includes a plurality of pixels 230 arranged in a matrix of m rows and n columns (m and n are independently integers greater than 1). Figure 35BIn the display unit 235, the pixel 230 in the first row and the nth column is described as pixel 230[1,n], the pixel 230 in the mth row and the first column is described as pixel 230[m,1], and the pixel 230 in the mth row and the nth column is described as pixel 230[m,n]. In addition, an arbitrary pixel 230 in the display unit 235 may be described as pixel 230[r,s]. r is an integer greater than 1 and less than m, and s is an integer greater than 1 and less than n.

[0466] The circuit included in the first driver circuit portion 231 is used, for example, as a scan line driver circuit. The circuit included in the second driver circuit portion 232 is used, for example, as a signal line driver circuit. Note that a circuit may also be provided at a position opposite the first driver circuit portion 231 across the display portion 235. A circuit may also be provided at a position opposite the second driver circuit portion 232 across the display portion 235. Note that the circuits included in the first driver circuit portion 231 and the second driver circuit portion 232 are sometimes collectively referred to as peripheral driver circuits.

[0467] As the peripheral driver circuit 233, various circuits such as a shift register circuit, a level converter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit can be used. Transistors and capacitors can be used in the peripheral driver circuit 233. The transistors in the peripheral driver circuit 233 can also be formed using the same process as the transistors in the pixel 230.

[0468] The display device 50 includes m wirings 236 arranged substantially parallel to one another and having their potentials controlled by the circuit in the first driver circuit portion 231 , and n wirings 237 arranged substantially parallel to one another and having their potentials controlled by the circuit in the second driver circuit portion 232 .

[0469] exist Figure 35B , an example is shown in which the wiring 236 and the wiring 237 are connected to the pixel 230. However, the wiring 236 and the wiring 237 are just examples, and the wiring connected to the pixel 230 is not limited to the wiring 236 and the wiring 237.

[0470] <Configuration Example of Peripheral Driver Circuit> As a circuit that can be used in a peripheral driver circuit, a configuration example will be described taking a latch circuit as an example.

[0471] Figure 36A : is a circuit diagram showing a configuration example of the latch circuit LAT. Figure 36A The latch circuit LAT shown includes a transistor Tr31, a transistor Tr33, a transistor Tr35, a transistor Tr36, a capacitor C31, and an inverter circuit INV. Figure 36AIn FIG, a node electrically connecting one of the source and drain of the transistor Tr33, the gate of the transistor Tr35, and one electrode of the capacitor C31 is referred to as a node N.

[0472] exist Figure 36A In the latch circuit LAT shown, when a high-potential signal is input to terminal SMP, transistor Tr33 turns on. Consequently, the potential of node N becomes equal to the potential of terminal ROUT, and data corresponding to the signal input from terminal ROUT to latch circuit LAT is written to latch circuit LAT. After data is written to latch circuit LAT, transistor Tr33 turns off by lowering the potential of terminal SMP. Consequently, the potential of node N is maintained, and the data written to latch circuit LAT is retained. Specifically, for example, when the potential of node N is low, latch circuit LAT can hold data "0," and when the potential of node N is high, latch circuit LAT can hold data "1."

[0473] Transistor Tr33 is preferably a transistor with a low off-state current. An OS transistor can be used as appropriate for transistor Tr33. Therefore, the latch circuit LAT can retain data for a long time. Consequently, the frequency of rewriting data to the latch circuit LAT can be reduced.

[0474] In this specification, "writing data to the latch circuit LAT so that the signal input from the terminal SP2 is output to the terminal LIN" may be simply referred to as "writing data to the latch circuit LAT." That is, for example, "writing data "1" to the latch circuit LAT" may be simply referred to as "writing data to the latch circuit LAT."

[0475] In the latch circuit LAT, a semiconductor device according to one embodiment of the present invention can be appropriately used. For example, one or more of the transistors Tr31, Tr33, Tr35, and Tr36 can be used. Figure 1B The transistor 100 or the transistor 200 shown in the figure.

[0476] Figure 36B 1 and 2 show a configuration example of an inverter circuit INV. The inverter circuit INV includes a transistor Tr41, a transistor Tr43, a transistor Tr45, a transistor Tr47, and a capacitor C41.

[0477] When the latch circuit LAT has Figure 36A The structure shown in FIG. 1 and the inverter circuit INV have Figure 36BIn the structure shown, all transistors in the latch circuit LAT use transistors of the same polarity, for example, n-channel transistors. Therefore, for example, in addition to transistor Tr33, transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47 can also be OS transistors. Consequently, all transistors in the latch circuit LAT can be manufactured using the same process.

[0478] In the inverter circuit INV, the semiconductor device according to one embodiment of the present invention can be appropriately used. For example, one or more of the transistor Tr41, the transistor Tr43, the transistor Tr45, and the transistor Tr47 can be used. Figure 1B The transistor 100 or the transistor 200 shown in the figure.

[0479] <Structural Example of Pixel Circuit> Figure 37A FIG. 5 shows a structural example of a pixel 230. The pixel 230 includes a pixel circuit 51 and a light emitting device 61.

[0480] Figure 37A The pixel circuit 51 shown is a 2Tr1C type pixel circuit including a transistor 52A, a transistor 52B, and a capacitor 53 .

[0481] In transistor 52A, one of its source and drain is electrically connected to the gate of transistor 52B and one terminal of capacitor 53, while the other is electrically connected to wiring SL. The gate of transistor 52A is electrically connected to wiring GL. One of the source and drain electrodes of transistor 52B and the other terminal of capacitor 53 are electrically connected to the anode of light-emitting device 61. The other of the source and drain electrodes of transistor 52B is electrically connected to wiring ANO. The cathode of light-emitting device 61 is electrically connected to wiring VCOM.

[0482] Wiring GL corresponds to wiring 236, and wiring SL corresponds to wiring 237. Wiring VCOM supplies a potential for supplying current to light-emitting device 61. Transistor 52A controls the conduction state or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO, and VSS is supplied to wiring VCOM.

[0483] The transistor 52B has a function of controlling the amount of current flowing through the light emitting device 61. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of light emitted by the light emitting device 61 is controlled according to an image signal supplied to the gate of the transistor 52B.

[0484] A part or all of the transistors included in the pixel circuit 51 may be provided with a back gate electrode. Figure 37A The pixel circuit 51 shown in the figure shows a structure in which the transistor 52B includes a back gate electrode and the back gate electrode is electrically connected to one of the source electrode and the drain electrode of the transistor 52B. Alternatively, the back gate electrode of the transistor 52B may be electrically connected to the gate electrode of the transistor 52B.

[0485] The pixel circuit 51 can be applied to the above-mentioned semiconductor device. For example, as the transistor 52A, Figure 7B The transistor 100 shown in FIG. 1 may use the transistor 200A as the transistor 52B.

[0486] Figure 37B Shown with Figure 37A The pixel 230 shown in FIG. 1 is a different structural example. The pixel 230 includes a pixel circuit 51A and a light emitting device 61 .

[0487] Figure 37B The pixel circuit 51A shown is Figure 37A The pixel circuit 51 shown is different mainly in that it includes a transistor 52C. The pixel circuit 51A is a 3Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53.

[0488] One of the source and drain electrodes of the transistor 52C is electrically connected to one of the source and drain electrodes of the transistor 52B. The other of the source and drain electrodes of the transistor 52C is electrically connected to the wiring V0. For example, the wiring V0 is supplied with a reference potential.

[0489] Transistor 52C has a function of controlling the conduction state or non-conduction state between one of the source and drain of transistor 52B and wiring V0 according to the potential of wiring GL. The reference potential of wiring V0 supplied through transistor 52C can suppress potential variations between the gate and source of transistor 52B.

[0490] Furthermore, wiring V0 can be used to obtain a current value that can be used to set pixel parameters. Specifically, wiring V0 can be used as a monitoring line for outputting the current flowing through transistor 52B or the current flowing through light-emitting device 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit, etc., and output externally. Alternatively, it can be converted into a digital signal by an A / D converter, etc., and output externally.

[0491] The above-mentioned semiconductor device can be applied to the pixel circuit 51A. For example, the transistor 52A and the transistor 52C can be used. Figure 7B The transistor 100 shown in FIG. 1 may use the transistor 200A as the transistor 52B.

[0492] Note that there is no particular limitation on the pixel circuit that can be used in one embodiment of the present invention.

[0493] Figure 37C A configuration example of the pixel circuit 51A is shown. Figure 37C is a cross-sectional view of the pixel circuit 51A.

[0494] Figure 37C Show that Figure 13B The semiconductor device 10E shown in FIG. 1 is used for the pixel circuit 51A. Specifically, the transistor 100B is used for the transistor 52A and the transistor 52C, and the transistor 200E is used for the transistor 52B.

[0495] Preferably, transistor 52B, which serves as a drive transistor for controlling the current flowing through light-emitting device 61, has a higher saturation characteristic than transistor 52A, which serves as a select transistor for controlling the selection state of pixel 230. Using transistor 200E, which has a long channel length, as transistor 52B allows for a highly reliable display device. Furthermore, using transistor 100B as transistors 52A and 52C allows for a smaller footprint of pixel circuit 51A, thereby enabling a high-definition display device.

[0496] Note that transistor 100B can also be used as transistor 52B. Using transistor 100B with a short channel length as transistor 52B can realize a display device with high brightness. In addition, the area occupied by pixel circuit 51A can be reduced, thereby realizing a high-definition display device.

[0497] The conductive layer 212a included in the transistor 52B is electrically connected to the conductive layer 202 through the opening 133 provided in the insulating layer 120 and the insulating layer 110. In addition, the conductive layer 212a is electrically connected to the conductive layer 112b included in the transistor 52C. Figure 37C The electrical connection between transistor 52A and transistor 52B is omitted. For example, a first opening reaching conductive layer 112 b included in transistor 52A and a second opening reaching conductive layer 204 included in transistor 52B are provided in insulating layer 195. By providing a first wiring on insulating layer 195 so as to cover the first opening and the second opening, conductive layer 112 b included in transistor 52A and conductive layer 204 included in transistor 52B can be electrically connected via the first wiring.

[0498] exist Figure 37CCapacitor 53 is omitted. Capacitor 53 can be formed, for example, in a region with insulating layer 106 interposed between conductive layer 204 serving as the gate electrode of transistor 52B and conductive layer 112b serving as the gate electrode, source electrode, or drain electrode of transistor 52C. The structure of capacitor 53 is not particularly limited.

[0499] An insulating layer 195 is provided to cover the transistor 52A, the transistor 52B, the transistor 52C, and the capacitor 53. An insulating layer 197 is provided to cover the insulating layer 195. The light-emitting device 61 may be provided on the insulating layer 197. Figure 37C Pixel electrode 111, serving as one electrode of light-emitting device 61, is shown. Pixel electrode 111 is electrically connected to conductive layer 112b included in transistor 52C via openings 135 provided in insulating layer 195 and insulating layer 197. Insulating layer 195 can be described with reference to the above description, so a detailed description is omitted. Insulating layer 197 has the function of reducing the unevenness caused by transistors 52A, 52B, and 52C, thereby making the surface on which light-emitting device 61 is formed more flat. Note that in this specification and other documents, insulating layer 197 may sometimes be referred to as a planarizing layer.

[0500] An insulating layer composed of an organic material can be suitably used as the insulating layer 197. A photosensitive organic resin is preferably used as the organic material, and for example, a photosensitive resin composition including an acrylic resin is preferably used. Note that in this specification, the term "acrylic resin" does not refer only to polymethacrylate or methacrylic resin but may also refer to acrylic polymers in a broad sense.

[0501] As the insulating layer 197, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of the above resins can also be used. In addition, as the insulating layer 197, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose or alcohol-soluble polyamide resin can also be used. In addition, a photoresist can also be used as a photosensitive resin. As the photosensitive organic resin, a positive material or a negative material can be used.

[0502] Insulating layer 197 may also have a stacked structure of an organic insulating layer and an inorganic insulating layer. For example, insulating layer 197 may have a stacked structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. Providing an inorganic insulating layer on the outermost surface of insulating layer 197 allows it to function as an etching protection layer. This prevents a portion of insulating layer 197 from being etched during formation of pixel electrode 111, which could reduce the flatness of insulating layer 197.

[0503] The pixel electrode 111 is electrically connected to the conductive layer 112 b through an opening provided in the insulating layer 197 and the insulating layer 195 .

[0504] A display device according to one embodiment of the present invention may also adopt any one of the following structures: a top emission type that emits light in a direction opposite to the substrate on which the light-emitting device is formed, a bottom emission type that emits light to one side of the substrate on which the light-emitting device is formed, or a dual emission type that emits light to both sides.

[0505] Figure 38A and Figure 38B Shown with Figure 37C The pixel circuit 51A shown is a different structural example. Figure 38A Show that Figure 14 The semiconductor device 10F shown in A is used for the pixel circuit 51A. Specifically, the transistor 100A is used for the transistor 52A and the transistor 52C, and the transistor 200F is used for the transistor 52B. Figure 38B Show that Figure 14 The semiconductor device 10G shown in FIG. 1 is used for the pixel circuit 51A. Specifically, the transistor 100 is used for the transistors 52A and 52C, and the transistor 200G is used for the transistor 52B. The above description of each transistor can be referred to, so detailed description is omitted.

[0506] Figure 39 Shown with Figure 37C 、 Figure 38A and Figure 38B The pixel circuit 51A shown is a different structural example. Figure 39 Show that Figure 16A The semiconductor device 10H shown is used in the pixel circuit 51A. Specifically, the transistor 100C is used as the transistor 52C, and the transistor 200H is used as the transistor 52B. Since the transistors 52B and 52C can be described above, detailed descriptions are omitted.

[0507] The transistor 52A may be provided above the transistor 52B. Figure 39 Show that Figure 1BThe structure of the transistor 100 shown in FIG. 1 is used as an example for the transistor 52A. The transistor 52A includes a conductive layer 203, an insulating layer 107, a semiconductor layer 109, a conductive layer 116a, and a conductive layer 116b. The conductive layer 203 serves as a gate electrode. The conductive layer 203 can use the same material as that used for the conductive layers 104 and 204. A portion of the insulating layer 107 serves as a gate insulating layer. The insulating layer 107 can use the same material as that used for the insulating layer 106. The conductive layer 116a serves as one of the source electrode and the drain electrode, and the conductive layer 116b serves as the other of the source electrode and the drain electrode. The conductive layers 116a and 116b can use the same material as that used for the conductive layers 112a and 112b. The semiconductor layer 109 can use the same material as that used for the semiconductor layers 108 and 208.

[0508] An insulating layer 150 is provided over the insulating layer 195, the conductive layer 212a, and the conductive layer 212b. The insulating layer 150 can use the same material as the insulating layer 195. Openings that reach the conductive layer 104 are provided in the insulating layer 195 and the insulating layer 150, and the conductive layer 116a is provided to cover the openings. Thus, the conductive layer 116a, which serves as one of the source and drain electrodes of the transistor 52A, is electrically connected to the conductive layer 204, which serves as the gate electrode of the transistor 52B. An insulating layer 210 is provided over the insulating layer 150 and the conductive layer 116a. The insulating layer 210 can use the same material as the insulating layer 110. The insulating layer 210 preferably has a stacked-layer structure. Figure 39 The insulating layer 210 is shown as an example of a stacked structure having an insulating layer 210a, an insulating layer 210b on the insulating layer 210a, and an insulating layer 210c on the insulating layer 210b. The insulating layer 210a can refer to the description regarding the insulating layer 110a, the insulating layer 210b can refer to the description regarding the insulating layer 110b, and the insulating layer 210c can refer to the description regarding the insulating layer 110c. A conductive layer 116b is provided on the insulating layer 110. The conductive layer 116b and the insulating layer 110 include an opening that reaches the conductive layer 116a. The semiconductor layer 109 is provided so as to cover the opening. The insulating layer 107 is provided on the semiconductor layer 109, and the conductive layer 203 is provided on the insulating layer 107.

[0509] An insulating layer 199 is provided over the transistor 52A. The insulating layer 199 can use a material that can be used for the insulating layer 195. An insulating layer 197 is provided over the insulating layer 199.

[0510] Insulating layer 150, insulating layer 210, and insulating layer 107 have openings that reach conductive layer 212a included in transistor 52B, and conductive layer 206 is provided to cover these openings. Conductive layer 206 can be formed, for example, by the same process as conductive layer 203. Insulating layer 199 and insulating layer 197 have openings that reach conductive layer 206, and pixel electrode 111, serving as one electrode of light-emitting device 61, is provided to cover these openings. Thus, pixel electrode 111, serving as one electrode of light-emitting device 61, and conductive layer 212a, serving as one of the source and drain electrodes of transistor 52B, are electrically connected via conductive layer 206. Furthermore, conductive layer 212a is electrically connected to conductive layer 112b included in transistor 52C.

[0511] Figure 39 An example is shown in which capacitor 53 is formed by sandwiching insulating layer 150 between conductive layer 116a serving as one of the source electrode and drain electrodes of transistor 52A and conductive layer 212b serving as one of the source electrode and drain electrodes of transistor 52B, but there is no particular limitation on the structure of capacitor 53.

[0512] <Configuration Example of Display Device> Figure 40 An example of a cross section of the display device 50 including a portion of the region including the FPC 172 , a portion of the peripheral driver circuit 233 , a portion of the display portion 235 , a portion of the connection portion 140 , and a portion of the region including the end portion is shown.

[0513] In display device 50, transistors are provided on substrate 102, an insulating layer is provided on the transistors, and light-emitting devices 130R, 130G, and 130B are provided on the insulating layer. A protective layer 131 is provided to cover these light-emitting devices. A substrate 152 is bonded to protective layer 131 via an adhesive layer 142.

[0514] Note that when describing common features among the light-emitting devices 130R, 130G, and 130B, the letters distinguishing them may be omitted and described as light-emitting devices 130. Similarly, when describing common features among other components distinguished by letters, the letters may be omitted.

[0515] The display portion 235 may include transistors for controlling the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B. Figure 40 1 and 2 show transistors 205R and 205G for controlling the light emitting device 130R and 130G, respectively. Figure 402 shows the transistor 201 provided in the peripheral driver circuit 233. The transistor 205R, the transistor 205G, and the transistor 201 can use the transistor or transistor group described in Embodiment 1 as appropriate. Figure 40 The electrical connections between transistors are omitted.

[0516] Sometimes, the transistors provided in the peripheral driver circuit 233 are required to have a larger on-state current than the transistors provided in the display unit 235. The channel length of the transistors provided in the peripheral driver circuit 233 is preferably short. For example, as the transistors provided in the peripheral driver circuit 233, one or more of the transistors 100 to 100C and the transistor group 100D can be appropriately used. In addition, as the transistors provided in the display unit 235, one or more of the transistors 200 to 200H can be appropriately used. Note that the display unit 235 can also use one or more of the transistors 100 to 100C and the transistor group 100D, and the peripheral driver circuit 233 can also use one or more of the transistors 200 to 200H.

[0517] A structure may be adopted in which the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B emit red (R) light, green (G) light, and blue (B) light, respectively.

[0518] In a pair of electrodes included in a light emitting device, one electrode is used as an anode and the other electrode is used as a cathode. The following description sometimes uses the case where the pixel electrode is used as an anode and the common electrode is used as a cathode as an example.

[0519] The light emitting device 130R includes a pixel electrode 111R, an island layer 113R on the pixel electrode 111R, a common layer 114 on the island layer 113R, and a common electrode 115 on the common layer 114. In the light emitting device 130R, the layer 113R and the common layer 114 may be collectively referred to as an EL layer.

[0520] The light emitting device 130G includes a pixel electrode 111G, an island layer 113G on the pixel electrode 111G, a common layer 114 on the island layer 113G, and a common electrode 115 on the common layer 114. In the light emitting device 130G, the layer 113G and the common layer 114 may be collectively referred to as an EL layer.

[0521] The light emitting device 130B includes a pixel electrode 111B, an island layer 113B on the pixel electrode 111B, a common layer 114 on the island layer 113B, and a common electrode 115 on the common layer 114. In the light emitting device 130B, the layer 113B and the common layer 114 may be collectively referred to as an EL layer.

[0522] In this specification and other documents, among the EL layers included in a light-emitting device, an island-shaped layer provided for each light-emitting device is referred to as layer 113B, layer 113G, or layer 113R, and a layer shared by a plurality of light-emitting devices is referred to as common layer 114. Furthermore, in this specification and other documents, layers 113R, 113G, and 113B excluding common layer 114 may be referred to as island-shaped EL layers, EL layers formed in an island shape, or the like.

[0523] Layer 113R, layer 113G, and layer 113B are separated from each other. Providing island-shaped EL layers in each light-emitting device can suppress leakage current between adjacent light-emitting devices. This suppresses unintended light emission due to crosstalk, enabling the realization of a display device with very high contrast. In particular, a display device with high current efficiency at low brightness can be realized. Hereinafter, layers 113R, 113G, and 113B may be collectively referred to as layer 113.

[0524] exist Figure 40 In the embodiment, no insulating layer (also referred to as a partition dam, partition wall, bank, spacer, etc.) covering the top surface end of the pixel electrode 111R is provided between the pixel electrode 111R and the layer 113R. In addition, no insulating layer covering the top surface end of the pixel electrode 111G is provided between the pixel electrode 111G and the layer 113G. Therefore, the interval between adjacent light-emitting devices can be made extremely small. Thus, a high-definition or high-resolution display device can be realized. In addition, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device. In addition, by adopting a structure in which no insulating layer covering the end of the pixel electrode is provided, the light emission from the EL layer can be efficiently extracted. Therefore, a display device of one embodiment of the present invention can make viewing angle dependence extremely small.

[0525] Layer 113R, layer 113G, and layer 113B include at least a light-emitting layer. Preferably, layer 113R, layer 113G, and layer 113B include a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light, respectively. In other words, layer 113R, layer 113G, and layer 113B contain a light-emitting material that emits red light, a light-emitting material that emits green light, and a light-emitting material that emits blue light, respectively. In addition, layer 113R, layer 113G, and layer 113B may also include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0526] like Figure 40 As shown, the end of layer 113G is preferably located outside the end of pixel electrode 111G. Note that although the pixel electrode 111G and layer 113G are described here as an example, the same applies to pixel electrode 111R and layer 113R, and pixel electrode 111B and layer 113B.

[0527] exist Figure 40 In the embodiment, the layer 113G is formed so as to cover the end of the pixel electrode 111G. This structure allows the entire top surface of the pixel electrode to be used as a light-emitting area, and compared with a structure in which the end of the island-shaped EL layer is located inside the end of the pixel electrode, it is easy to increase the aperture ratio.

[0528] By covering the sides of the pixel electrode 111 with the EL layer, contact between the pixel electrode 111 and the common electrode 115 can be prevented, thereby preventing short circuits in the light-emitting device. Furthermore, the distance between the light-emitting region of the EL layer (i.e., the region overlapping the pixel electrode) and the ends of the EL layer can be increased. Because the ends of the EL layer may be damaged during processing, using an area farther from the ends of the EL layer as the light-emitting region can sometimes improve the reliability of the light-emitting device.

[0529] Note that in Figure 40 In the figure, the thicknesses of layers 113R, 113G, and 113B are shown as being the same, but one embodiment of the present invention is not limited thereto. The thicknesses of layers 113R, 113G, and 113B may also be different. For example, the thicknesses are preferably set so as to achieve an enhanced optical path length for light emitted from layers 113R, 113G, and 113B. This allows for a microcavity structure to be implemented, thereby improving the color purity of each light-emitting device.

[0530] Common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. Light-emitting devices 130R, 130G, and 130B all include common layer 114.

[0531] Light emitting devices 130R, 130G, and 130B share a common electrode 115. Common electrode 115 shared by the plurality of light emitting devices is electrically connected to conductive layer 123 provided in connection portion 140. Conductive layer 123 can be formed by the same process as pixel electrodes 111R, 111G, and 111B.

[0532] Figure 40 The display device 50 shown is a top emission type. The light emitting device emits light to the substrate 152 side. The substrate 152 is preferably made of a material with high transmittance to visible light. The pixel electrode 111 includes a material that reflects visible light, and the common electrode 115 includes a material that allows visible light to pass through. Figure 40 In FIG. 1 , dotted arrows respectively indicate light R, light G, and light B emitted from the light emitting device 130R, the light emitting device 130G, and the light emitting device 130B to the substrate 152 side.

[0533] A protective layer 131 is provided on the light emitting device 130R, the light emitting device 130G and the light emitting device 130B. The protective layer 131 and the substrate 152 are bonded by an adhesive layer 142. The substrate 152 is provided with a light shielding layer 117. The sealing of the light emitting device can adopt a solid sealing structure or a hollow sealing structure. Figure 40 In the embodiment, the space between substrate 152 and substrate 101 is filled with adhesive layer 142, i.e., a solid sealing structure is adopted. Alternatively, a hollow sealing structure can be adopted in which the space is filled with an inert gas (such as nitrogen or argon). In this case, adhesive layer 142 can also be provided so as not to overlap with the light-emitting device. Alternatively, a resin different from that of the frame-shaped adhesive layer 142 can be used to fill the space.

[0534] A protective layer 131 is preferably provided on the light-emitting devices 130R, 130G, and 130B. Providing the protective layer 131 can prevent oxidation of the common electrode 115 and the intrusion of impurities (such as water and oxygen) into the light-emitting devices. Consequently, degradation of the light-emitting devices is suppressed, and the reliability of the display device can be improved. The protective layer 131 can have a single-layer structure or a stacked structure of two or more layers. There is no limitation on the conductivity of the protective layer 131. As the protective layer 131, at least one of an insulating layer, a semiconductor layer, and a conductive layer can be used.

[0535] Protective layer 131 may be made of an inorganic material. For example, protective layer 131 may be made of one or more of an oxide, an oxynitride, an oxynitride, and a nitride. Specifically, examples include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, and hafnium oxide. In particular, protective layer 131 preferably includes a nitride or an oxynitride, and more preferably includes a nitride.

[0536] The protective layer 131 may also be made of In-Sn oxide (ITO), In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or In-Ga-Zn oxide (IGZO). This layer preferably has a high resistance, and more specifically, a higher resistance than the common electrode 115. This layer may also contain nitrogen.

[0537] When light emitted from the light emitting device 130 is extracted through the protective layer 131, the protective layer 131 preferably has high visible light transmittance. For example, In—Sn oxide, In—Ga—Zn oxide, and aluminum oxide are preferred because they all have high visible light transmittance.

[0538] Furthermore, the protective layer 131 may include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film.

[0539] Examples of a method for depositing the protective layer 131 include vacuum evaporation, sputtering, CVD, and ALD. The protective layer 131 may have a stacked structure formed using different deposition methods.

[0540] The protective layer 131 is provided at least in the display portion 235, and is preferably provided to cover the entire display portion 235. The protective layer 131 is preferably provided to cover the connection portion 140 and the peripheral driver circuit 233 in addition to the display portion 235. Furthermore, the protective layer 131 is preferably provided to extend to the end of the display device 50.

[0541] Figure 41A An enlarged view of the light emitting device 130G, the transistor 205G, and their vicinity is shown.

[0542] The pixel electrode 111G included in the light emitting device 130G has a stacked-layer structure of a conductive layer 124G, a conductive layer 126G on the conductive layer 124G, and a conductive layer 129G on the conductive layer 126G.

[0543] The conductive layer 124G is electrically connected to the conductive layer 212 a of the transistor 205G through an opening provided in the insulating layer 199 , the insulating layer 197 , and the insulating layer 239 .

[0544] The end of conductive layer 124G is located outside the end of conductive layer 126G. The end of conductive layer 126G is located inside the end of conductive layer 129G. The end of conductive layer 124G is located inside the end of conductive layer 129G. In other words, the end of conductive layer 126G is located on conductive layer 124G. Furthermore, the end of conductive layer 129G is located on conductive layer 124G. The top and side surfaces of conductive layer 126G are covered by conductive layer 129G.

[0545] There are no particular restrictions on the transmittance and reflectivity of the conductive layer 124G with respect to visible light. The conductive layer 124G can be a conductive layer that is transmittance to visible light or a conductive layer that is reflective to visible light. As a conductive layer that is transmittance to visible light, for example, a conductive layer including an oxide conductor (also referred to as an oxide conductive layer) can be used. Specifically, In-Si-Sn oxide (also referred to as ITSO) can be suitably used as the conductive layer 124G. As a conductive layer that is reflective to visible light, for example, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, silver, tin, zinc, platinum, gold, molybdenum, tantalum, or tungsten, or an alloy containing these elements as main components (for example, an alloy of silver, palladium, and copper (APC: Ag-Pd-Cu)) can be used. The conductive layer 124G can also have a stacked structure of a conductive layer that is transmittance to visible light and a reflective conductive layer on the conductive layer. It is preferable to suitably use a material that has high adhesion to the surface on which the conductive layer 124G is formed (here, the insulating layer 239) for the conductive layer 124G. This can suppress film peeling of the conductive layer 124G.

[0546] Conductive layer 126G can be a conductive layer that is reflective of visible light. Conductive layer 126G may also have a stacked structure of a conductive layer that is transmissive of visible light and a reflective conductive layer thereon. Materials that can be used for conductive layer 124G can be used for conductive layer 126G. Specifically, a stacked structure of In-Si-Sn oxide (ITSO) or an alloy of silver and palladium and copper (APC) on In-Si-Sn oxide (ITSO) can be used as appropriate for conductive layer 126G.

[0547] The conductive layer 129G can use the same material as that used for the conductive layer 124G. For example, the conductive layer 129G can use a conductive layer that is transparent to visible light. Specifically, the conductive layer 129G can use In—Si—Sn oxide (ITSO).

[0548] When conductive layer 126G is made of a material that is easily oxidized, conductive layer 129G is made of a material that is not easily oxidized, and conductive layer 129G covers conductive layer 126G. This can suppress oxidation of conductive layer 126G. Furthermore, precipitation of metal components contained in conductive layer 126G can be suppressed. For example, when conductive layer 126G is made of a material containing silver, In-Si-Sn oxide (ITSO) can be suitably used for conductive layer 129G. This can suppress oxidation of conductive layer 126G and suppress precipitation of silver.

[0549] The ends of conductive layers 129G, 126G, and 124G may also be aligned or substantially aligned. Layer 113G may also be in contact with the side surfaces of conductive layers 129G, 126G, and 124G.

[0550] For example, after depositing the first conductive film to become the conductive layer 124G, the layer 128, the second conductive film to become the conductive layer 126G, and the third conductive film to become the conductive layer 129G, a resist mask is formed on the third conductive film. The first conductive film, the second conductive film, and the third conductive film are processed using the resist mask, thereby forming the conductive layers 124G, 126G, and 129G. By processing the first conductive film, the second conductive film, and the third conductive film in the same process to form the conductive layers 124G, 126G, and 129G, the process can be simplified.

[0551] Alternatively, the side surfaces of conductive layer 124G and the top and side surfaces of conductive layer 126G may be covered by conductive layer 129G. Layer 113G may include regions in contact with the top and side surfaces of conductive layer 129G but not with conductive layers 124G and 126G.

[0552] For example, after depositing a first conductive film to become conductive layer 124G and a second conductive film to become conductive layer 126G, a resist mask is formed on the second conductive film, and the first and second conductive films are processed using the resist mask to form conductive layers 124G and 126G. Then, a third conductive film to become conductive layer 129G is deposited so as to cover conductive layers 124G and 126G, and the third conductive film is processed to form conductive layer 129G. Forming conductive layers 124G and 126G by processing the first and second conductive films in the same process can simplify the process. Furthermore, even if a material that easily diffuses, such as silver, is used for conductive layers 124G and 126G, diffusion of the material can be suppressed by covering the top and side surfaces of conductive layers 124G and 126G with conductive layer 129G.

[0553] The pixel electrode 111R in the light-emitting device 130R and the pixel electrode 111B in the light-emitting device 130B may have the same structure as the pixel electrode 111G.

[0554] Concave portions are formed in conductive layer 124R, conductive layer 124G, and conductive layer 124B so as to cover openings provided in insulating layer 199, insulating layer 197, and insulating layer 239. Layer 128 is embedded in these concave portions.

[0555] Layer 128 flattens the concave portions of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B are provided on conductive layers 124R, 124G, and 124B, and layer 128, and are electrically connected to conductive layers 124R, 124G, and 124B. Therefore, even the areas overlapping the concave portions of conductive layers 124R, 124G, and 124B can be used as light-emitting areas, thereby increasing the pixel aperture ratio.

[0556] Layer 128 flattens the recessed portions formed in conductive layers 124R, 124G, and 124B. Layer 128 improves the flatness of the top surfaces of pixel electrodes 111R, 111G, and 111B, where layers 113R, 113G, and 113B are formed.

[0557] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128.

[0558] An insulating layer composed of an organic material can be suitably used as layer 128. A photosensitive organic resin is preferably used as the organic material, and for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification, etc., the term "acrylic resin" does not refer solely to polymethacrylate or methacrylic resin but may also refer to acrylic polymers in a broad sense.

[0559] As layer 128, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of the above resins can also be used. In addition, as insulating layer 127, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose or alcohol-soluble polyamide resin can also be used. In addition, as a photosensitive organic resin, a photoresist can also be used. As a photosensitive organic resin, a positive material or a negative material can be used.

[0560] Note that when the layer 128 is a conductive layer, the layer 128 can also serve as part of the pixel electrode. The layer 128 can be made of, for example, an organic resin in which metal particles are dispersed.

[0561] exist Figure 41A

[0014] and

[0015] show that the top surface of layer 128 has a convex shape with the center and the vicinity thereof convex when viewed in cross section, i.e., a convexly curved surface. However, the shape of layer 128 is not particularly limited. The top surface of layer 128 may also have a concave shape with the center and the vicinity thereof concave when viewed in cross section. Alternatively, the top surface of layer 128 may have one or both of a convex and concave surface. Furthermore, the number of convex and concave surfaces on the top surface of layer 128 is not limited and may be one or more.

[0562] The height of the top surface of layer 128 may be the same as or substantially the same as the height of the top surface of conductive layer 124G, or may be different. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124G.

[0563] Figure 41B An enlarged view of connecting portion 140 is shown. Conductive layer 123 may have a stacked structure comprising, for example, a conductive layer 124p, a conductive layer 126p on conductive layer 124p, and a conductive layer 129p on conductive layer 126p. Conductive layer 124p may be formed in the same process as conductive layers 124R, 124G, and 124B. Conductive layer 126p may be formed in the same process as conductive layers 126R, 126G, and 126B. Conductive layer 129p may be formed in the same process as conductive layers 129R, 129G, and 129B.

[0564] Figure 41B , etc. show an example in which the common layer 114 is not provided in the connection portion 140, but the common electrode 115 is provided on the conductive layer 123. Note that a structure in which the common layer 114 is provided on the conductive layer 123 and the conductive layer 123 and the common electrode 115 are electrically connected via the common layer 114 may also be employed. For example, by using a mask for defining a deposition range (also referred to as a range mask or a coarse metal mask to distinguish it from a high-definition metal mask), the area where the common layer 114 is deposited can be different from the area where the common electrode 115 is deposited.

[0565] A connection portion 214 is provided in a region of the substrate 101 that does not overlap with the substrate 152. In the connection portion 214, the wiring 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242. The conductive layer 166 is exposed on the top surface of the connection portion 214. Therefore, the connection portion 214 and the FPC 172 can be electrically connected via the connection layer 242. Figure 40 , etc., shows a structure in which the wiring 165 is used as a source electrode or a drain electrode of the transistor 201. Note that the conductive layer 112a of the transistor 201 may be electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.

[0566] As the connection layer 242 , for example, an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP) can be used.

[0567] Note that in order to electrically connect FPC 172 to conductive layer 166, some portions of connection portion 214 are not provided with protective layer 131. For example, after protective layer 131 is deposited on the entire surface of display device 50, the conductive layer 166 can be exposed by removing the region of protective layer 131 that overlaps with conductive layer 166 using a mask.

[0568] Figure 41C An enlarged view of connection portion 214 is shown. Conductive layer 166 may have a stacked structure comprising, for example, a conductive layer 124q, a conductive layer 126q on conductive layer 124q, and a conductive layer 129q on conductive layer 126q. Conductive layer 124q may be formed in the same process as conductive layers 124R, 124G, and 124B. Conductive layer 126q may be formed in the same process as conductive layers 126R, 126G, and 126B. Conductive layer 129q may be formed in the same process as conductive layers 129R, 129G, and 129B.

[0569] Figure 40 , etc., illustrate a structure in which the thickness of conductive layer 129p and conductive layer 129q differs from the thickness of conductive layer 129R, conductive layer 129G, and conductive layer 129B. The thicknesses of conductive layers 129p, conductive layer 129q, conductive layer 129R, conductive layer 129G, and conductive layer 129B may also differ depending on the resistivity of the materials used for these layers. When the thicknesses are different, conductive layers 129p and conductive layer 129q may be formed in a different process from conductive layers 129R, conductive layer 129G, and conductive layer 129B. Alternatively, the process for forming conductive layers 129p and conductive layer 129q may be partially identical to the process for forming conductive layers 129R, conductive layer 129G, and conductive layer 129B. Furthermore, the thicknesses of conductive layers 129p and conductive layer 129q may differ.

[0570] Notice, Figure 40 The pixel electrode 111R, the pixel electrode 111G, the pixel electrode 111B, the conductive layer 123, and the conductive layer 166 shown in FIG. 11 can also be applied to other structural examples.

[0571] An insulating layer 125 and an insulating layer 127 on the insulating layer 125 are provided in the region between adjacent light emitting devices. Figure 40Although a cross-section of multiple insulating layers 125 and multiple insulating layers 127 is shown, when viewing the display device 50 from above, the insulating layers 125 and 127 may each be formed as a continuous layer. In other words, the display device 50 may include, for example, one insulating layer 125 and one insulating layer 127. Alternatively, the display device 50 may include multiple insulating layers 125 and multiple insulating layers 127 that are separated from each other.

[0572] Mask layers 118R and 119R are positioned on layer 113R, mask layers 118G and 119G are positioned on layer 113G, and mask layers 118B and 119B are positioned on layer 113B. Mask layers 118R, 119R, 118G, 119G, 118B, and 119B include openings in portions overlapping with the light-emitting region. Mask layers 118R and 119R are the remnants of the mask layer that was placed in contact with the top surface of layer 113R during processing of layer 113R. Similarly, mask layers 118G and 119G, and mask layers 118B and 119B are the remnants of the mask layer that was placed during formation of layers 113G and 113B, respectively. In this manner, a display device according to one embodiment of the present invention may also have a portion of the mask layer used to protect the EL layer during manufacturing remaining. Furthermore, any two or all of mask layer 118R, mask layer 118G, and mask layer 118B may be made of the same material or different materials. Furthermore, any two or all of mask layer 119R, mask layer 119G, and mask layer 119B may be made of the same material or different materials. Note that hereinafter, mask layer 118R, mask layer 118G, and mask layer 118B may be collectively referred to as mask layer 118, and mask layer 119R, mask layer 119G, and mask layer 119B may be collectively referred to as mask layer 119.

[0573] As the mask layer 118 and the mask layer 119 , for example, one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an organic insulating film, and an inorganic insulating film can be used.

[0574] Mask layers 118 and 119 can each be made of, for example, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or alloys containing these metal materials. Low-melting-point materials such as aluminum and silver are particularly preferred. Using a metal material that blocks ultraviolet light for one or both of mask layers 118 and 119 can suppress ultraviolet light exposure to layer 113, thereby preventing degradation of layer 113.

[0575] Metal oxides can be used for the mask layers 118 and 119. Examples of the metal oxides include In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.

[0576] Different materials may be used for the mask layer 118 and the mask layer 119. Alternatively, a structure without the mask layer 119 may be employed.

[0577] like Figure 40 As shown, one end of mask layer 118R and mask layer 119R (the end on the side opposite to the light-emitting region, the outer end) is aligned or approximately aligned with an end of layer 113R, and the other end of mask layer 118R and mask layer 119R is located on layer 113R. Here, the other end of mask layer 118R and mask layer 119R (the end on the side of the light-emitting region, the inner end) preferably overlaps with layer 113R and pixel electrode 111R. In this case, the other end of mask layer 118R and mask layer 119R is easily formed on the substantially flat surface of layer 113R. The same applies to mask layer 118G, mask layer 118B, mask layer 118G, and mask layer 119G. Furthermore, mask layer 118 and mask layer 119B remain, for example, between the top surface of the EL layer (layer 113R, layer 113G, or layer 113B) processed into an island shape and insulating layer 125.

[0578] When the ends are aligned or approximately aligned, and the top surface shapes are consistent or approximately consistent, it can be said that at least a portion of the edges of the stacked layers overlap when viewed from above. This includes, for example, cases where the upper and lower layers are processed using the same mask pattern, or a portion of the mask pattern is identical. However, in practice, there are cases where the edges do not overlap, and sometimes the upper layer is located inside or outside the lower layer. In these cases, it can also be said that the ends are "approximately aligned" or "the top surface shapes are approximately consistent."

[0579] The side surfaces of the layers 113R, 113G, and 113B are covered with the insulating layer 125. The insulating layer 127 overlaps the side surfaces of the layers 113R, 113G, and 113B with the insulating layer 125 interposed therebetween.

[0580] By covering a portion of the top surfaces and side surfaces of the layers 113R, 113G, and 113B with at least one of the insulating layer 125, the insulating layer 127, the mask layer 118, and the mask layer 119, the common layer 114 (or the common electrode 115) can be prevented from contacting the side surfaces of the pixel electrodes 111R, 111G, 111B, the layers 113R, 113G, and 113B, thereby preventing short circuits in the light-emitting device. This improves the reliability of the light-emitting device.

[0581] The insulating layer 125 preferably contacts the side surfaces of layer 113R, layer 113G, and layer 113B. This structure, in which the insulating layer 125 contacts layers 113R, layer 113G, and layer 113B, prevents delamination of layers 113R, layer 113G, and layer 113B. When the insulating layer is in close contact with layer 113B, layer 113G, or layer 113R, adjacent layers 113B and the like are fixed or bonded by the insulating layer. This improves the reliability of the light-emitting device and the manufacturing yield of the light-emitting device.

[0582] Alternatively, insulating layers 125 and 127 may cover a portion of the top surfaces and both the side surfaces of layers 113R, 113G, and 113B. This structure further prevents film peeling of the EL layer, thereby improving the reliability of the light-emitting device and further increasing the manufacturing yield of the light-emitting device.

[0583] Insulating layer 127 is provided on insulating layer 125 so as to fill the recess formed in insulating layer 125. Insulating layer 127 may overlap with a portion of the top surface and side surfaces of each of layers 113R, 113G, and 113B via insulating layer 125. Insulating layer 127 preferably covers at least a portion of the side surfaces of insulating layer 125.

[0584] By providing the insulating layers 125 and 127, the gaps between adjacent island layers can be filled. This can reduce the unevenness of the formed surface of layers (e.g., the carrier injection layer and the common electrode) disposed on the island layers, thereby further flattening the surface. This improves the coverage of the carrier injection layer and the common electrode.

[0585] The common layer 114 and the common electrode 115 are provided on the layer 113R, the layer 113G, the layer 113B, the mask layer 118, the mask layer 119, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, steps are generated due to the region where the pixel electrode and the island EL layer are provided and the region where the pixel electrode and the island EL layer are not provided (the region between the light-emitting devices). The display device of one embodiment of the present invention can flatten the steps by including the insulating layer 125 and the insulating layer 127, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection caused by disconnection can be suppressed. Alternatively, the increase in resistance caused by local thinning of the thickness of the common electrode 115 due to the steps can be suppressed.

[0586] The top surface of the insulating layer 127 is preferably flat, but may have a convex portion, a convexly curved surface, a concavely curved surface, or a concave portion. For example, the top surface of the insulating layer 127 is preferably a convexly curved surface with a large curvature radius.

[0587] The insulating la...

Claims

1. A semiconductor device comprising: a first transistor; as well as The second transistor, The first transistor includes a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a second conductive layer on the second insulating layer, a first semiconductor layer, a third insulating layer and a third conductive layer. The first insulating layer, the second insulating layer and the second conductive layer include an opening reaching the first conductive layer, The first semiconductor layer is in contact with the top surface and side surfaces of the second conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second insulating layer, and the top surface of the first conductive layer. The third insulating layer is disposed on the first semiconductor layer. The third conductive layer is disposed on the third insulating layer, Furthermore, the second transistor includes a second semiconductor layer on the second insulating layer, the third insulating layer on the second semiconductor layer, and a fourth conductive layer including a region overlapping the second semiconductor layer via the third insulating layer.

2. A semiconductor device comprising: a first transistor; a second transistor; as well as Substrate, The first transistor includes a first conductive layer on the substrate, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a second conductive layer on the second insulating layer, a first semiconductor layer, a third insulating layer and a third conductive layer. The first insulating layer, the second insulating layer and the second conductive layer include an opening reaching the first conductive layer, The first semiconductor layer is in contact with the top surface and side surfaces of the second conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second insulating layer, and the top surface of the first conductive layer. The third insulating layer is disposed on the first semiconductor layer. The third conductive layer is disposed on the third insulating layer, The second transistor includes a second semiconductor layer on the second insulating layer, the third insulating layer on the second semiconductor layer, a fourth conductive layer including a region overlapping the second semiconductor layer via the third insulating layer, and a fifth conductive layer on the substrate. Furthermore, the fifth conductive layer includes a region overlapping the fourth conductive layer via the second semiconductor layer.

3. A semiconductor device comprising: a first transistor; as well as The second transistor, The first transistor includes a first conductive layer, a first insulating layer on the first conductive layer, a second insulating layer on the first insulating layer, a second conductive layer on the second insulating layer, a first semiconductor layer, a third insulating layer and a third conductive layer. The first insulating layer, the second insulating layer and the second conductive layer include an opening reaching the first conductive layer, The first semiconductor layer is in contact with the top surface and side surfaces of the second conductive layer, the side surfaces of the first insulating layer, the side surfaces of the second insulating layer, and the top surface of the first conductive layer. The third insulating layer is disposed on the first semiconductor layer. The third conductive layer is disposed on the third insulating layer, The second transistor includes a second semiconductor layer on the second insulating layer, the third insulating layer on the second semiconductor layer, a fourth conductive layer including a region overlapping the second semiconductor layer via the third insulating layer, and a fifth conductive layer on the first insulating layer. Furthermore, the fifth conductive layer includes a region overlapping the fourth conductive layer via the second semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, The first semiconductor layer and the second semiconductor layer both contain metal oxide.

5. The semiconductor device according to any one of claims 1 to 3, The first semiconductor layer and the second semiconductor layer include the same material.

6. The semiconductor device according to any one of claims 1 to 3, The third conductive layer and the fourth conductive layer include the same material.

7. The semiconductor device according to any one of claims 1 to 3, The first insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer, the fourth insulating layer includes a region having a higher film density than the fifth insulating layer, And the sixth insulating layer includes a region whose film density is higher than that of the fifth insulating layer.

8. The semiconductor device according to any one of claims 1 to 3, The first insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer, The fourth insulating layer includes a region having a nitrogen content higher than that of the fifth insulating layer, And the sixth insulating layer includes a region containing more nitrogen than the fifth insulating layer.

9. The semiconductor device according to any one of claims 1 to 3, The second insulating layer includes a seventh insulating layer and an eighth insulating layer on the seventh insulating layer, And the seventh insulating layer includes a region whose film density is higher than that of the eighth insulating layer.

10. The semiconductor device according to any one of claims 1 to 3, The second insulating layer includes a seventh insulating layer and an eighth insulating layer on the seventh insulating layer, And the seventh insulating layer includes a region containing more nitrogen than the eighth insulating layer.

11. A method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive film; Processing the first conductive film to form a first conductive layer and a second conductive layer; forming a first insulating film on the first conductive layer and the second conductive layer; forming a second conductive film on the first insulating film; Processing the first insulating film and the second conductive film to form a first insulating layer and a third conductive layer including an opening in a region overlapping the first conductive layer; forming a first semiconductor layer in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the third conductive layer, and a second semiconductor layer in contact with a top surface of the first insulating layer; forming a second insulating layer on the first semiconductor layer and the second semiconductor layer; as well as A fourth conductive layer including a region overlapping the first semiconductor layer and a fifth conductive layer including a region overlapping the second semiconductor layer are formed on the second insulating layer.

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