LDO switching circuit, LDO switching method, chip, electronic device and readable medium

Abstract

The present disclosure relates to the technical field of power supply control, and specifically discloses an LDO switching circuit, an LDO switching method, a chip, an electronic device and a readable medium. The circuit comprises: a first LDO and a second LDO; wherein the first LDO and the second LDO share the same voltage input end and the same voltage output end; an adjusting unit is arranged in the first LDO, and the adjusting unit is used for adjusting a first output voltage of the first LDO output to the voltage output end; under the condition that the adjusting unit is in an open state, the first output voltage of the first LDO is reduced, so that the first output voltage of the first LDO is less than a second output voltage of the second LDO, to drive the first LDO to be turned off, and the second LDO is used as a power supply; under the condition that the adjusting unit is in a closed state, the first output voltage of the first LDO is increased, so that the first output voltage of the first LDO is greater than the second output voltage of the second LDO, to drive the second LDO to be turned off, and the first LDO is used as the power supply. The circuit reduces the switching complexity of the LDO and improves the switching stability of the LDO.

Description

Technical Field

[0001] This disclosure relates to the field of power control technology, specifically to an LDO switching circuit, an LDO switching method, a chip, an electronic device, and a readable medium. Background Technology

[0002] To enable diverse power supply options for the chip, different power requirements exist for different application scenarios. When the chip temperature is low, an external low dropout regulator (LDO) is used for power supply; when high integration is required, an internal LDO is used for power supply.

[0003] In existing LDO switching methods, the internal LDO of the chip is usually turned on or off through a switch control register. However, in the above method, if the external LDO of the chip fails and the internal LDO of the chip is turned off, the entire chip will have no power. At this time, the switch control register cannot turn on the internal LDO of the chip, thus getting stuck in an infinite loop where the LDO cannot be turned on, resulting in abnormal LDO switching. Summary of the Invention

[0004] To address this issue, this disclosure provides an LDO switching circuit, an LDO switching method, a chip, a device, and a readable medium to solve the problem of abnormal LDO switching caused by the opening or closing of the LDO in the prior art.

[0005] To achieve the above objectives, the first aspect of this disclosure provides an LDO switching circuit, which includes a first LDO and a second LDO; wherein the first LDO and the second LDO share the same voltage input terminal and the same voltage output terminal, and the second LDO outputs a fixed second output voltage to the voltage output terminal when it is turned on.

[0006] The first LDO is provided with an adjustment unit, which is used to adjust the first output voltage from the first LDO to the voltage output terminal;

[0007] When the adjustment unit is in the on state, the first output voltage of the first LDO decreases, making the first output voltage of the first LDO less than the second output voltage of the second LDO, so as to drive the first LDO to turn off, and the second LDO becomes the power supply.

[0008] When the regulating unit is in the off state, the first output voltage of the first LDO is increased, making the first output voltage of the first LDO greater than the second output voltage of the second LDO, so as to drive the second LDO to turn off, and the first LDO becomes the power supply.

[0009] In one alternative implementation, the first LDO includes a transistor, a first voltage divider resistor, a second voltage divider resistor, an error amplifier, and an adjustment unit.

[0010] The gate of the transistor is connected to the output terminal of the error amplifier, and the other two terminals of the transistor are connected to the voltage input terminal and the voltage output terminal, respectively.

[0011] The first end of the first voltage divider resistor is connected to the voltage output terminal, and the second end of the first voltage divider resistor is connected to the second input terminal of the error amplifier and the first end of the second voltage divider resistor, respectively.

[0012] The first input terminal of the error amplifier is used to input a reference voltage, and the second input terminal of the error amplifier is connected to the second terminal of the first voltage divider resistor and is used to input the voltage value of the second terminal of the first voltage divider resistor.

[0013] The second end of the second voltage divider resistor is connected to the ground terminal, and the first end of the second voltage divider resistor is connected to the second end of the first voltage divider resistor;

[0014] The adjustment unit is disposed on the first voltage divider resistor and is used to adjust the resistance value of the first voltage divider resistor in order to adjust the voltage value input to the second input terminal of the error amplifier.

[0015] In one alternative implementation, the first voltage divider resistor includes a plurality of series sub-resistors, and when all sub-resistors of the first voltage divider resistor are active, the first output voltage of the first LDO is greater than the second output voltage of the second LDO.

[0016] The adjustment unit is connected to at least one sub-resistor and is used to control the active state of the at least one sub-resistor.

[0017] In one alternative implementation, the regulating unit includes a switching device controlled by a register, the switching device being connected in parallel with the at least one sub-resistor;

[0018] The register controls the closing of the switching device, causing at least one sub-resistor to fail, and the resistance value of the first voltage divider resistor to decrease, so that the first output voltage is less than the second output voltage of the second LDO;

[0019] The register controls the switching device to turn off, making at least one sub-resistor active, and the resistance value of the first voltage divider resistor increases so that the first output voltage is greater than the second output voltage of the second LDO.

[0020] In one optional implementation, the resistance ratio between the at least one sub-resistor and the resistance of the second voltage divider resistor is within a first preset ratio range, so that the voltage difference between the second output voltage and the first output voltage is less than a preset difference threshold, thereby stably driving the transistor of the first LDO to the cutoff state.

[0021] The first preset ratio range is determined based on the preset difference threshold, the second output voltage, and the reference voltage.

[0022] In one optional implementation, when all the sub-resistors of the first voltage divider resistor are active, the resistance ratio between the resistance of the first voltage divider resistor and the resistance of the second voltage divider resistor is within a second preset ratio range, so that the voltage difference between the first output voltage and the second output voltage is less than a preset voltage threshold, and the first LDO provides stable power.

[0023] The second preset ratio range is determined based on the preset voltage threshold, the second output voltage, and the reference voltage.

[0024] The second aspect of this disclosure provides an LDO switching method, the method comprising: responding to a power supply request of a second LDO, enabling the regulation unit of a first LDO through a register, reducing the first output voltage of the first LDO so that the first output voltage is less than the second output voltage of the second LDO, thereby driving the first LDO to turn off, and using the second LDO as the power supply.

[0025] In response to the power supply request of the first LDO, the regulating unit is turned off through the register, and the first output voltage of the first LDO is increased so that the first output voltage is greater than the second output voltage of the second LDO, so as to drive the second LDO to turn off and the first LDO becomes the power supply.

[0026] The third aspect of this disclosure provides a chip that uses the LDO switching method described above to make the chip's power supply either a first LDO or a second LDO.

[0027] A fourth aspect of this disclosure provides an electronic device, comprising:

[0028] One or more processors;

[0029] A storage device having stored one or more programs thereon, which, when executed by one or more processors, cause the one or more processors to implement the LDO switching method described above.

[0030] One or more I / O interfaces are connected between the processor and the memory and configured to enable information interaction between the processor and the memory.

[0031] The fifth aspect of this disclosure provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the LDO switching method described above.

[0032] This disclosure has the following advantages:

[0033] In the LDO switching circuit of this embodiment, the first LDO and the second LDO share the same voltage input terminal and the same voltage output terminal. When the second LDO is in the on state, it outputs a fixed second output voltage to the voltage output terminal. By setting an adjustment unit in the first LDO to adjust the first output voltage of the first LDO to the voltage output terminal, when the adjustment unit is in the on state, the first output voltage of the first LDO decreases, making the first output voltage of the first LDO less than the second output voltage of the second LDO, so as to drive the first LDO to turn off and the second LDO to serve as the power supply. When the adjustment unit is in the off state, the first output voltage of the first LDO increases, making the first output voltage of the first LDO greater than the second output voltage of the second LDO, so as to drive the second LDO to turn off and the first LDO to serve as the power supply.

[0034] As can be seen from the above, the embodiments of this disclosure, by setting an adjustment unit in the first LDO, adjust the output voltage value of the first LDO through the adjustment unit, and then directly drive the first LDO or the second LDO to turn off based on the voltage relationship between the output voltage values ​​of the first LDO and the second LDO, so as to realize the power supply switching of the LDO. Thus, when the second LDO is not turned on, even if the adjustment unit is in the on state, the first output voltage of the first LDO cannot be less than the second output voltage of the second LDO, so that the power supply can still be maintained at the first LDO. This not only reduces the switching complexity of LDO, but also effectively avoids the abnormal switching phenomenon of LDO switching through the switch control register. Attached Figure Description

[0035] The accompanying drawings are provided to further understand the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof.

[0036] Figure 1 This is a schematic diagram of LDO switching in related technologies;

[0037] Figure 2 A schematic diagram of an LDO switching circuit provided in an embodiment of this disclosure;

[0038] Figure 3This is a schematic diagram of the structure of the first LDO in an embodiment of this disclosure;

[0039] Figure 4 This is a schematic diagram of the connection of the adjustment unit in an embodiment of this disclosure;

[0040] Figure 5 This is a schematic diagram of the structure of the adjustment unit in an embodiment of this disclosure;

[0041] Figure 6 This is a schematic diagram of the structure of the adjustment unit in an embodiment of this disclosure;

[0042] Figure 7 A flowchart of an LDO switching method provided in this disclosure embodiment;

[0043] Figure 8 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0044] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0045] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the related enumerated entries.

[0046] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used in this disclosure, the singular forms “a” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0047] When the terms “comprising” and / or “made of” are used in this disclosure, they specify the presence of the said feature, integral, step, operation, element and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0048] The embodiments described herein can be described with reference to plan views and / or cross-sectional views, using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0049] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so specified in this disclosure.

[0050] LDOs are used to stabilize the input voltage at a constant output voltage to power the chip. In chip power supply solutions, depending on the different application scenarios, either an internal LDO (on-chip LDO) or an external LDO (off-chip LDO) is selected as the power supply.

[0051] However, the current LDO switching method is quite complex and may involve changes to the package or PCB routing. Figure 1 This is a schematic diagram of LDO switching in related technologies.

[0052] Reference Figure 1 In this diagram, VDD5 is the 5V input voltage, VDD33 is the 3.3V output voltage, and RL is a resistor. Both the on-chip LDO and the off-chip LDO inside the chip can convert the 5V input voltage into the 3.3V output voltage.

[0053] Accordingly, when using the on-chip LDO as the power supply, the 3.3V output VDD33 of the external LDO needs to be disconnected, and when using the external LDO as the power supply, the 3.3V output VDD33 of the on-chip LDO needs to be disconnected.

[0054] Therefore, adaptive PCB (Printed Circuit Board) modifications are required for different application needs. For example, two PCB designs may be needed, which makes LDO switching more complex.

[0055] Furthermore, if the external LDO fails and the internal LDO is turned off, the chip will have no power. In this case, the internal LDO cannot be turned on, thus falling into an infinite loop where the LDO cannot be turned on, resulting in abnormal LDO switching.

[0056] In view of this, the present disclosure provides an LDO switching circuit. By setting an adjustment unit in the first LDO, the output voltage value of the first LDO is adjusted by the adjustment unit. Then, based on the voltage relationship between the output voltage values ​​of the first LDO and the second LDO, the first LDO or the second LDO is driven to turn off, thereby realizing the power supply switching of the LDO. Thus, even if the adjustment unit is in the on state when the second LDO is not turned on, the first output voltage of the first LDO cannot be less than the second output voltage of the second LDO, so that the power supply can still be maintained for the first LDO. This not only reduces the switching complexity of LDO, but also effectively avoids the abnormal switching phenomenon of LDO switching through the switch control register.

[0057] In a first aspect, embodiments of this disclosure provide an LDO switching circuit. Figure 2 This is a schematic diagram of an LDO switching circuit provided in an embodiment of the present disclosure, with reference to... Figure 2 The circuit includes a first LDO 101 and a second LDO 102.

[0058] Among them, the first LDO 101 refers to the on-chip LDO, which is integrated inside the chip and used to power the chip, while the second LDO 102 refers to the off-chip LDO, which is an independent regulator located outside the chip and used to power the chip.

[0059] It should be noted that the first LDO 101 and the second LDO 102 share the same voltage input terminal and voltage output terminal.

[0060] In other words, the first LDO 101 receives an input voltage, such as 5V, from its voltage input terminal and converts it into a first output voltage, which is then output to the voltage output terminal. Similarly, the second LDO 102 receives an input voltage from its voltage input terminal and converts it into a second output voltage, which is then output to the voltage output terminal.

[0061] When the second LDO 102 is turned on, its second output voltage is a fixed value, such as 3.3V.

[0062] In order to achieve the power supply switching between the first LDO and the second LDO, an adjustment unit 1011 is provided inside the first LDO 101. The first output voltage of the first LDO 101 is changed by the adjustment unit 1011.

[0063] For example, by adjusting the unit 1011, the first output voltage can be increased to 3.35V or decreased to 3.25V, so that the first output voltage is greater than the second output voltage or less than the second output voltage.

[0064] Specifically, when the adjustment unit 1011 is in the on state, the first output voltage of the first LDO 101 decreases, making the first output voltage of the first LDO 101 less than the second output voltage of the second LDO 102, so as to drive the first LDO 101 to turn off, and the second LDO 102 becomes the power supply.

[0065] When the regulating unit 1011 is in the off state, the first output voltage of the first LDO 101 is increased, making the first output voltage of the first LDO 101 greater than the second output voltage of the second LDO 102, so as to drive the second LDO 102 to turn off, and the first LDO 101 becomes the power supply.

[0066] As can be seen from the working principle of LDO, LDO is based on a negative feedback mechanism, which adjusts the transistor to regulate its output voltage and keep the output voltage stable.

[0067] Since the first LDO 101 and the second LDO 102 share the same voltage output terminal, when the first output voltage of the first LDO 101 is less than the second output voltage of the second LDO 102, the voltage value at the voltage output terminal will always be higher than the first output voltage value. Therefore, in order to maintain the stability of its output voltage, the first LDO 101 will increase the gate voltage of the transistor through negative feedback, so as to reduce the first output voltage of the transistor. Thus, under the continuous negative feedback, the transistor is kept in the cutoff state, and the first LDO is turned off.

[0068] Similarly, when the first output voltage of the first LDO 101 is greater than the second output voltage of the second LDO 102, the voltage value at the voltage output terminal will always be higher than the voltage value of the second output voltage. Therefore, in order to maintain the stability of its output voltage, the second LDO 102 will increase the gate voltage of the transistor through negative feedback, so as to reduce the second output voltage of the transistor. Thus, under the continuous negative feedback, the transistor is kept in the cut-off state, and the second LDO is turned off.

[0069] Therefore, the LDO switching circuit in this embodiment does not achieve LDO switching by changing the PCB traces, but directly adjusts the voltage value of the first output voltage of the first LDO through the adjustment unit. Since the second output voltage of the second LDO is a fixed value when it is turned on, the voltage value of the first output voltage can be changed to change the voltage relationship between the first output voltage and the second output voltage. Under this voltage relationship, the first LDO or the second LDO can be automatically turned off according to its operating characteristics to achieve convenient switching between the first LDO and the second LDO.

[0070] For ease of understanding, Figure 3 A schematic diagram of the structure of the first LDO in an embodiment of this disclosure is shown, with reference to... Figure 3 :

[0071] The first LDO 101 includes a transistor 1012, a first voltage divider resistor 1013, a second voltage divider resistor 1014, an error amplifier 1015, and an adjustment unit 1011.

[0072] Among them, transistor 1012 is a regulating element, which is used to convert the input voltage at the voltage input terminal into a first output voltage and output it to the voltage output terminal.

[0073] Specifically, transistor 1012 can be a P-channel metal-oxide-semiconductor transistor (PMOS transistor) or an N-channel metal-oxide-semiconductor transistor (NMOS transistor), and this disclosure does not limit it.

[0074] In this configuration, the gate of transistor 1012 is connected to the output terminal of error amplifier 1015, while the other two terminals of the transistor (i.e., the source and the drain) are connected to the voltage input terminal and the voltage output terminal, respectively.

[0075] Specifically, such as Figure 3 As shown, when transistor 1012 is a PMOS transistor, the source of transistor 1012 is connected to the voltage input terminal, and the drain of transistor 1012 is connected to the voltage output terminal.

[0076] Correspondingly, when transistor 1012 is an NMOS transistor, the source of transistor 1012 is connected to the voltage output terminal, and the drain of transistor 1012 is connected to the voltage input terminal.

[0077] The first voltage divider resistor 1013 and the second voltage divider resistor 1014 are used to divide the voltage at the voltage output terminal.

[0078] Specifically, the first end of the first voltage divider resistor 1013 is connected to the voltage output terminal, and the second end of the first voltage divider resistor 1013 is connected to the second input terminal of the error amplifier 1015 and the first end of the second voltage divider resistor 1014, respectively.

[0079] Therefore, the voltage value (also known as the sampling voltage) at the second terminal of the first voltage divider resistor 1013 can be input to the second input terminal of the error amplifier 1015.

[0080] It should be noted that the first voltage divider resistor 1013 and the second voltage divider resistor 1014 can both be composed of one or more sub-resistors, and this embodiment does not limit this.

[0081] The second end of the second voltage divider resistor 1014 is connected to the ground terminal, and the first end of the second voltage divider resistor 1014 is connected to the second end of the first voltage divider resistor 1013.

[0082] Furthermore, the first input terminal of the error amplifier 1015 is used to input the reference voltage VREF, and the second input terminal of the error amplifier 1015 is used to input the voltage value of the second terminal of the first voltage divider resistor 1013, i.e., the sampling voltage.

[0083] It should be noted that the first and second input terminals of the error amplifier 1015 need to be determined according to the type of transistor 1012.

[0084] Specifically, when transistor 1012 is a PMOS transistor, the first input terminal of error amplifier 1015 is an inverting input terminal, and the second input terminal of error amplifier 1015 is a non-inverting input terminal. When transistor 1012 is an NMOS transistor, the first input terminal of error amplifier 1015 is a non-inverting input terminal, and the second input terminal of error amplifier 1015 is an inverting input terminal.

[0085] The error amplifier 1015 is used to amplify the voltage difference between the sampling voltage and the reference voltage VREF, and feeds the difference back to the gate of the transistor 1012 so as to adjust the conduction state of the transistor 1012 according to the change of the sampling voltage.

[0086] The reference voltage VREF can be adaptively set according to actual needs, and this embodiment does not limit it.

[0087] Therefore, when the sampling voltage at the second end of the first voltage divider resistor 1013 changes, the error amplifier 1015 feeds back the change to the gate of the transistor 1012, causing the conduction current of the transistor 1012 to change, thereby changing the voltage value of the output voltage of the transistor 1012.

[0088] It should be noted that, based on the working principle of LDO, in this embodiment, the adjustment unit 1011 needs to be set on the first voltage divider resistor 1013, so that the resistance value of the first voltage divider resistor 1013 can be adjusted by the adjustment unit 1011, thereby changing the voltage value input to the second input terminal of the error amplifier 1015, and ultimately changing the voltage value output by the transistor 1012.

[0089] For example, when the adjustment unit 1011 is in the on state, the resistance of the first voltage divider resistor 1013 decreases, which increases the voltage value input to the second input terminal of the error amplifier 1015. As a result, after the error amplifier 1015 outputs, the potential of the gate of the transistor 1012 increases, which in turn reduces the voltage difference between the gate and the source of the transistor 1012, thereby reducing the conduction current of the transistor 1012 and thus reducing the first output voltage output by the transistor 1012.

[0090] When the adjustment unit 1011 is in the off state, the resistance of the first voltage divider resistor 1013 increases, which reduces the voltage value input to the second input terminal of the error amplifier 1015. As a result, after the output of the error amplifier 1015, the potential of the gate of the transistor 1012 decreases, which in turn increases the voltage difference between the gate and source of the transistor 1012, thereby increasing the conduction current of the transistor 1012 and thus increasing the first output voltage output by the transistor 1012.

[0091] Therefore, when the first output voltage is less than the second output voltage, due to the negative feedback of the first LDO, the potential of the gate of transistor 1012 continuously increases, the conduction current of transistor 1012 continuously decreases, and finally the transistor 1012 of the first LDO 101 is turned off, so as to turn off the first LDO 101.

[0092] It should also be noted that the structure of the second LDO 102 is not adjusted in the LDO switching circuit of this embodiment. Therefore, this embodiment does not limit the specific structure of the second LDO 102. For example, the second LDO can be a PMOS LDO structure or an NMOS LDO structure, etc.

[0093] In this embodiment of the disclosure, by setting an adjustment unit 1011 on the first voltage divider resistor 1013 of the first LDO 101, the resistance value of the first voltage divider resistor 1013 is changed by adjusting the on / off state of the adjustment unit 1011, thereby adjusting the voltage value of the first output voltage, and thus changing the voltage relationship between the first output voltage and the second output voltage, so as to drive the first LDO or the second LDO to turn off, thereby realizing automatic LDO switching.

[0094] In one alternative implementation, the first voltage divider resistor 1013 includes a plurality of series sub-resistors, and when all the sub-resistors of the first voltage divider resistor 1013 are active, the first output voltage of the first LDO 101 is greater than the second output voltage of the second LDO 102.

[0095] Accordingly, in order to make the first output voltage less than the second output voltage when the adjustment unit 1011 is in the on state, the adjustment unit 1011 can be connected to at least one sub-resistor, thereby controlling the active state of the at least one sub-resistor connected thereto through the adjustment unit 1011.

[0096] For ease of understanding, Figure 4 A connection diagram of the adjustment unit in an embodiment of this disclosure is shown, with reference to... Figure 4 :

[0097] The first voltage divider resistor 1013 includes multiple series sub-resistors. By connecting the adjustment unit 1011 to at least one sub-resistor, the activation state of at least one sub-resistor can be controlled by controlling the on or off state of the adjustment unit 1011, thereby changing the resistance value of the first voltage divider resistor 1013.

[0098] In this embodiment of the disclosure, by connecting the adjustment unit to the sub-resistors inside the first voltage divider resistor, the active state of the sub-resistors is controlled. That is, by controlling the active state of some sub-resistors in the first voltage divider resistor, the first output voltage is effectively controlled to be greater than or less than the second output voltage.

[0099] In one alternative implementation, to reduce the structural complexity of the regulating unit, the regulating unit includes a switching device controlled by a register, and the switching device is connected in parallel with at least one sub-resistor.

[0100] For ease of understanding, Figure 5A schematic diagram of the structure of the adjustment unit in an embodiment of this disclosure is shown, with reference to... Figure 5 :

[0101] The regulating unit 1011 consists only of switching devices controlled by register RG, and the switching devices are connected in parallel with at least one sub-resistor.

[0102] Among them, the switching device can be any switching element that controls the on and off states according to changes in the input signal, such as a MOSFET.

[0103] Therefore, a control signal is generated through the register, for example, a low-level control signal is generated to control the switching device to close. At this time, the adjustment unit is in the open state, which causes at least one sub-resistor to be short-circuited, i.e., in a failure state. This causes the resistance value of the first voltage divider resistor 1013 to decrease, thereby reducing the voltage value of the first output voltage so that the first output voltage is less than the second output voltage of the second LDO 102.

[0104] The control signal is generated by the register, for example, a high-level control signal is generated to control the switching device to open. At this time, the adjustment unit is in the off state, so that at least one sub-resistor connected in parallel with the switching device is effective. At this time, all sub-resistors of the first voltage divider resistor 1013 are effective, and the resistance value of the first voltage divider resistor 1013 increases, thereby increasing the voltage value of the first output voltage, so that the first output voltage is greater than the second output voltage of the second LDO 102.

[0105] It should be noted that if the first voltage divider resistor 1013 includes only one sub-resistor, the adjustment unit 1011 may also include a preset sub-resistor, and the resistance value of the preset sub-resistor can be adaptively set according to actual needs.

[0106] Specifically, the preset sub-resistor can be connected in series with the switching device, and the switching device and the preset sub-resistor can be connected in parallel with the sub-resistor of the first voltage divider resistor 1013. Thus, when the adjustment unit is in the open state, the switching device is closed, the preset sub-resistor takes effect, and by being connected in parallel with the sub-resistor of the first voltage divider resistor 1013, the resistance of the first voltage divider resistor 1013 is reduced, thereby reducing the voltage value of the first output voltage.

[0107] When the adjustment unit is in the off state, the switching device is disconnected and the preset sub-resistor is ineffective. At this time, the resistance of the first voltage divider resistor 1013 increases, causing the voltage value of the first output voltage to rise.

[0108] It should also be noted that, due to the characteristics of transistor 1012, if the voltage difference between the first output voltage and the second output voltage is too large, the potential of the gate of transistor 1012 will change too quickly, which will cause transistor 1012 to oscillate or be damaged, making it impossible for LDO to be switched normally.

[0109] In an alternative implementation, in order to improve the switching stability of the LDO, the resistance ratio between the resistance value of at least one sub-resistor and the resistance value of the second voltage-dividing resistor 1014 needs to be within a first preset ratio range, so that the voltage difference between the second output voltage and the first output voltage is less than a preset difference threshold, and stably drive the transistor 1012 of the first LDO 101 to the cut-off state.

[0110] Wherein, the first preset ratio range is used to define the ratio range of the resistance ratio between the resistance value of at least one sub-resistor and the resistance value of the second voltage-dividing resistor 1014.

[0111] Specifically, the first preset ratio range needs to be determined according to the preset difference threshold, the second output voltage, and the reference voltage.

[0112] Wherein, the preset difference threshold is used to define the maximum value of the voltage difference between the second output voltage and the first output voltage when the adjustment unit is in the on state, so as to avoid too rapid change in the potential of the gate of the transistor 1012 of the first LDO 101.

[0113] Exemplarily, the correlation between the first output voltage output by the first LDO 101 and the reference voltage is:

[0114] V1 = Vref(1 + R1 / R2) Formula 1-1;

[0115] Wherein, V1 is the voltage value of the first output voltage, Vref is the voltage value of the reference voltage, R1 is the resistance value of the first voltage-dividing resistor, and R2 is the resistance value of the second voltage-dividing resistor.

[0116] Therefore, assuming that the preset difference threshold is d1, when the adjustment unit is in the on state, the first output voltage and the second output voltage need to satisfy the following relationship:

[0117] 0 < V2 - V1 ≤ d1 Formula 1-2;

[0118] Wherein, V2 is the voltage value of the second output voltage. Further, assuming that the resistance value of at least one sub-resistor is R3, according to Formula 1-1 and Formula 1-2, it can be obtained that:

[0119] 0 < V2 - Vref(1 + (R1 - R3) / R2) ≤ d1 Formula 1-3;

[0120] Therefore, according to Formula 1-3, the resistance ratio between the resistance value of at least one sub-resistor and the resistance value of the second voltage-dividing resistor, that is, the first preset ratio range in which R3 / R2 is located, can be determined.

[0121] It should be noted that the above formulas 1-3 can be adaptively adjusted according to the specific structure of the adjustment unit (such as whether its switching device is connected in series with a preset sub-resistor, etc.). The embodiments of the present disclosure do not limit this.

[0122] It should also be noted that the preset difference threshold can be adaptively set according to actual needs. For example, when the second output voltage is 3.3V, the preset difference threshold can be 0.1V, etc. The embodiments of the present disclosure do not limit this.

[0123] Thus, in the embodiments of the present disclosure, by making the resistance ratio between the resistance values of at least one sub-resistor and the second voltage-dividing resistor fall within a first preset ratio range, when the adjustment unit is in the on state, the voltage value output by the first LDO can be slightly less than the output voltage value of the second RDO, so as to stably turn off the transistor driving the first LDO and improve the switching stability of the LDO.

[0124] In an optional implementation manner, when the adjustment unit is in the off state, if the voltage difference between the first output voltage and the second output voltage is too high, the chip cannot be powered for generation, which may further cause damage to the internal components of the chip and affect the actual application. Therefore, when all the sub-resistors of the first voltage-dividing resistor 1013 are effective, the resistance ratio between the resistance value of the first voltage-dividing resistor and the resistance value of the second voltage-dividing resistor 1014 needs to fall within a second preset ratio range, so that the voltage difference between the first output voltage and the second output voltage is less than the preset voltage threshold, and thus the first LDO can provide stable power supply.

[0125] Among them, the second preset ratio range is used to limit the ratio range of the resistance ratio between the resistance value of the first voltage-dividing resistor and the resistance value of the second voltage-dividing resistor.

[0126] Specifically, the second preset ratio range needs to be determined according to the preset voltage threshold, the second output voltage, and the reference voltage.

[0127] Among them, the preset voltage threshold is used to limit the maximum value of the voltage difference between the first output voltage and the second output voltage when the adjustment unit is in the off state, so as to prevent the first output voltage output by the first LDO from exceeding the power supply voltage threshold that the chip can withstand.

[0128] Specifically, assuming that the preset voltage threshold is d2, when the adjustment unit is in the off state, at this time, all the sub-resistors of the first voltage-dividing resistor are effective, and the first output voltage and the second output voltage need to satisfy the following relationship:

[0129] 0 < V1 - V2 ≤ d2 Formula 1-4;

[0130] Thus, according to Formula 1-1 and Formula 1-4, it can be obtained that:

[0131] 0 < Vref(1 + R1 / R2) - V2 ≤ d2 Equation 1-5;

[0132] Thus, according to Equation 1-5, it can be determined that when all sub-resistors of the first voltage-dividing resistor are effective, the resistance ratio between the resistance value of the first voltage-dividing resistor and the resistance value of the second voltage-dividing resistor, that is, the second preset ratio interval where R1 / R2 is located.

[0133] It should be noted that the preset voltage threshold can be adaptively set according to the power supply voltage threshold of the chip. For example, when the power supply voltage of the chip is between 3.2V and 3.4V, if the second output voltage is 3.3V, the highest preset voltage threshold is 3.4V - 3.3V = 0.1V. The embodiments of the present disclosure do not limit this.

[0134] Thus, in the embodiments of the present disclosure, when all sub-resistors of the first voltage-dividing resistor are effective, the resistance ratio between the resistance value of the first voltage-dividing resistor and the resistance value of the second voltage-dividing resistor is in the second preset ratio interval, so that when the adjustment unit is in the off state, the voltage value output by the first LDO can be slightly higher than the output voltage value of the second RDO, so as to stably drive the transistor of the second LDO to turn off and be stably powered by the first LDO, avoiding abnormal power supply of the chip and causing damage to chip components.

[0135] It should also be noted that the specific structure of the adjustment unit 1011 in the embodiments of the present disclosure can also be adaptively adjusted according to the voltage magnitude relationship between the first output voltage of the first RDO 101 and the second output voltage of the second RDO 102 when all sub-resistors of the first voltage-dividing resistor are effective, so as to effectively adjust the first output voltage.

[0136] For ease of understanding, Figure 6 a schematic diagram of the structure of the adjustment unit in the embodiments of the present disclosure is shown.

[0137] Assume that when all sub-resistors of the first voltage-dividing resistor are effective, the first output voltage of the first RDO is less than the second output voltage of the second RDO.

[0138] Then, referring to Figure 6 (a), the adjustment unit 1011 may include a first switching device 11, a first preset resistor 12, and a second switching device 13. Among them, the first switching device 11 is connected to the first preset resistor 12, and the second switching device 13 is connected in parallel with the first switching device 11 and the first preset resistor 12.

[0139] Furthermore, the regulating unit 1011 can be connected in series with any sub-resistor of the first voltage divider resistor 1013. Thus, by disconnecting the first switching device 11 and closing the second switching device 13, the regulating unit is in the open state, at which time the first output voltage of the first RDO is less than the second output voltage of the second RDO.

[0140] By closing the first switching device 11 and opening the second switching device 13, the regulating unit is in the off state. At this time, the first output voltage of the first RDO is greater than the second output voltage of the second RDO.

[0141] It should be noted that the resistance value of the first preset resistor 12 can be adaptively set according to actual needs, and this embodiment does not limit it.

[0142] It should also be noted that, for ease of operation, both the first and second switching devices can be controlled by the same register, and their closing conditions are opposite. For example, the first switching device needs to be closed at a low level, while the second switching device needs to be closed at a high level.

[0143] For example, assuming that when all the sub-resistors of the first voltage divider resistor are active, the first output voltage of the first RDO is equal to the second output voltage of the second RDO;

[0144] So, referring to Figure 6 (b) The adjustment unit 1011 may include a first adjustment subunit for increasing the resistance value of the first voltage divider resistor and a second adjustment subunit for decreasing the resistance value of the first voltage divider resistor. The first adjustment subunit includes a third switching device 14, a second preset resistor 15 and a fourth switching device 16, and the second adjustment subunit includes a fifth switching device 17.

[0145] The third switching device 14 is connected to the second preset resistor 15, and the fourth switching device 16 is connected in parallel with the third switching device 14 and the second preset resistor 15.

[0146] Specifically, the first adjustment subunit can be connected in series with any sub-resistor of the first voltage divider resistor 1013. The second adjustment subunit must be connected in parallel with at least one sub-resistor of the first voltage divider resistor 1013.

[0147] Therefore, by disconnecting the third switching device 14 and closing the fourth switching device 16 and the fifth switching device 17, the regulating unit is put into the open state, that is, the second regulating subunit is in the open state and the first regulating subunit is in the closed state. At this time, the first output voltage of the first RDO is less than the second output voltage of the second RDO.

[0148] By closing the third switching device 14 and opening the fourth switching device 16 and the fifth switching device 17, the regulating unit is in the closed state, that is, the second regulating subunit is in the closed state and the first regulating subunit is in the open state. At this time, the first output voltage of the first RDO is greater than the second output voltage of the second RDO.

[0149] It should be noted that the resistance value of the second preset resistor can be adaptively set according to actual needs, and this embodiment does not limit it.

[0150] For ease of operation, the third, fourth, and fifth switching devices can all be controlled by the same register. Furthermore, the closing conditions of the third and fourth switching devices are opposite, while the closing conditions of the fourth and fifth switching devices are the same. For example, the third switching device needs to be closed at a low level, while the fourth and fifth switching devices need to be closed at a high level.

[0151] It should also be noted that the specific structure of the above-mentioned adjustment unit 1011 is only an example. Those skilled in the art can also adjust and modify the specific structure of the adjustment unit according to the actual application scenario, such as increasing the number of switching devices and preset resistors or modifying the connection relationship between the switching devices and preset resistors and sub-resistors. This disclosure does not limit this.

[0152] Secondly, embodiments of this disclosure provide an LDO switching method. Figure 7 A flowchart of an LDO switching method provided in this disclosure embodiment is shown below. Figure 7 The method includes:

[0153] Step S710: In response to the power supply request of the second LDO, the regulation unit of the first LDO is enabled through the register, the first output voltage of the first LDO is reduced, so that the first output voltage is less than the second output voltage of the second LDO, thereby driving the first LDO to turn off and the second LDO to serve as the power supply.

[0154] The second LDO is an off-chip LDO, while the first LDO is an on-chip LDO. The first and second LDOs share the same voltage input and output terminals. Furthermore, the second LDO outputs a fixed second output voltage to the voltage output terminal when it is enabled.

[0155] Upon receiving a power supply request from the second LDO, it indicates that an external LDO is required for power supply. The adjustment unit of the first LDO can then be enabled via a register. For example, after the adjustment unit of the first LDO is enabled, the first output voltage of the first LDO is reduced by decreasing the resistance of the first voltage divider resistor in the first LDO, making the first output voltage less than the second output voltage.

[0156] For example, assuming the second output voltage of the external LDO is 3.3V, by adjusting the first output voltage of the internal LDO to slightly lower than 3.3V, as can be seen from the working principle of LDO, under the influence of the output voltage of the external LDO, the transistor of the internal LDO will gradually be turned off, so that the internal LDO is turned off.

[0157] Step S720: In response to the power supply request of the first LDO, the regulating unit is turned off through the register, the first output voltage of the first LDO is increased, so that the first output voltage is greater than the second output voltage of the second LDO, so as to drive the second LDO to turn off, and the first LDO becomes the power supply.

[0158] Upon receiving a power supply request from the first LDO, it indicates that the on-chip LDO needs to be used for power supply. The adjustment unit of the first LDO can be turned off through the register. For example, after the adjustment unit of the first LDO is turned off, the resistance value of the first voltage divider resistor in the first LDO is increased, thereby increasing the first output voltage of the first LDO and making the first output voltage greater than the second output voltage.

[0159] For example, assuming the second output voltage of the external LDO is 3.3V, by adjusting the first output voltage of the internal LDO to slightly higher than 3.3V, as can be seen from the working principle of LDO, under the influence of the output voltage of the internal LDO, the transistor of the external LDO will gradually be turned off, so that the external LDO is turned off.

[0160] In one alternative implementation, the first LDO includes a transistor, a first voltage divider resistor, a second voltage divider resistor, an error amplifier, and an adjustment unit.

[0161] The gate of the transistor is connected to the output terminal of the error amplifier, and the other two terminals of the transistor are connected to the voltage input terminal and the voltage output terminal, respectively.

[0162] The first end of the first voltage divider resistor is connected to the voltage output terminal, and the second end of the first voltage divider resistor is connected to the second input terminal of the error amplifier and the first end of the second voltage divider resistor, respectively.

[0163] The first input terminal of the error amplifier is used to input a reference voltage, and the second input terminal of the error amplifier is connected to the second terminal of the first voltage divider resistor and is used to input the voltage value of the second terminal of the first voltage divider resistor.

[0164] The second end of the second voltage divider resistor is connected to the ground terminal, and the first end of the second voltage divider resistor is connected to the second end of the first voltage divider resistor;

[0165] The adjustment unit is disposed on the first voltage divider resistor and is used to adjust the resistance value of the first voltage divider resistor in order to adjust the voltage value input to the second input terminal of the error amplifier.

[0166] In one alternative implementation, the first voltage divider resistor includes a plurality of series sub-resistors, and when all sub-resistors of the first voltage divider resistor are active, the first output voltage of the first LDO is greater than the second output voltage of the second LDO.

[0167] The adjustment unit is connected to at least one sub-resistor and is used to control the active state of the at least one sub-resistor.

[0168] In one alternative implementation, the regulating unit includes a switching device controlled by a register, the switching device being connected in parallel with the at least one sub-resistor;

[0169] The register controls the closing of the switching device, causing at least one sub-resistor to fail, and the resistance value of the first voltage divider resistor to decrease, so that the first output voltage is less than the second output voltage of the second LDO;

[0170] The register controls the switching device to turn off, making at least one sub-resistor active, and the resistance value of the first voltage divider resistor increases so that the first output voltage is greater than the second output voltage of the second LDO.

[0171] In one optional implementation, the resistance ratio between the at least one sub-resistor and the resistance of the second voltage divider resistor is within a first preset ratio range, so that the voltage difference between the second output voltage and the first output voltage is less than a preset difference threshold, thereby stably driving the transistor of the first LDO to the cutoff state.

[0172] The first preset ratio range is determined based on the preset difference threshold, the second output voltage, and the reference voltage.

[0173] In one optional implementation, when all the sub-resistors of the first voltage divider resistor are active, the resistance ratio between the resistance of the first voltage divider resistor and the resistance of the second voltage divider resistor is within a second preset ratio range, so that the voltage difference between the first output voltage and the second output voltage is less than a preset voltage threshold, and the first LDO provides stable power.

[0174] The second preset ratio range is determined based on the preset voltage threshold, the second output voltage, and the reference voltage.

[0175] In this embodiment, the output voltage value of the first LDO, i.e. the LDO inside the chip, is adjusted by the register. Thus, without affecting the signal transmission of the register, the switching between the internal and external LDO power supply can be achieved simply by changing the output voltage value of the internal LDO. This not only does not change the chip packaging and the actual circuit connection, making the switching between internal and external LDO simple and convenient, but also avoids the risk that the LDO switching control register will not be effective after the chip is powered off, which would lead to abnormal LDO switching.

[0176] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0177] Thirdly, this disclosure provides a chip that uses the LDO switching method provided in this embodiment to make the chip's power supply either a first LDO or a second LDO. To avoid repetition, the specific steps of the LDO switching method will not be repeated here.

[0178] Fourthly, embodiments of this disclosure provide an electronic device. Figure 8 A block diagram of an electronic device provided in an embodiment of this disclosure, with reference to... Figure 8 It includes:

[0179] One or more processors 801;

[0180] The memory 802 stores one or more programs that, when executed by one or more processors, cause the one or more processors to implement any of the above-mentioned LDO switching methods.

[0181] One or more I / O interfaces 803 are connected between the processor and memory and configured to enable information exchange between the processor and memory.

[0182] Among them, processor 801 is a device with data processing capabilities, including but not limited to central processing unit (CPU); memory 802 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); I / O interface (read-write interface) 803 is connected between processor 801 and memory 802, and can realize information interaction between processor 801 and memory 802, including but not limited to data bus (Bus).

[0183] In some embodiments, the processor 801, memory 802, and I / O interface 803 are interconnected via a bus, and thus connected to other components of the computing device.

[0184] This embodiment also provides a computer-readable medium storing a computer program thereon. When the program is executed by a processor, it implements the LDO switching method provided in this embodiment. To avoid repetition, the specific steps of the LDO switching method will not be repeated here.

[0185] Those skilled in the art will understand that all or some of the steps, systems, or apparatuses in the methods, systems, and apparatuses described above can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0186] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0187] Those skilled in the art will understand that although some embodiments described herein include certain features that are included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of this embodiment and form different embodiments.

[0188] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. An LDO switching circuit, characterized by, The circuit comprises a first LDO and a second LDO; wherein the first LDO and the second LDO share a same voltage input terminal and a same voltage output terminal, and the second LDO outputs a fixed second output voltage to the voltage output terminal in an on state; The first LDO is provided with an adjusting unit, which is used for adjusting a first output voltage of the first LDO output to the voltage output terminal; In the on state of the adjusting unit, the first output voltage of the first LDO is reduced, so that the first output voltage of the first LDO is less than the second output voltage of the second LDO, to drive the first LDO to be turned off, and the second LDO is used as a power supply; In the off state of the adjusting unit, the first output voltage of the first LDO is increased, so that the first output voltage of the first LDO is greater than the second output voltage of the second LDO, to drive the second LDO to be turned off, and the first LDO is used as a power supply; The first LDO comprises a first voltage dividing resistor, and the first voltage dividing resistor comprises a plurality of series sub-resistors; the adjusting unit comprises a switch device controlled by a register, and the switch device is connected in parallel with at least one sub-resistor in the first voltage dividing resistor; The switch device is controlled to be closed by the register, so that the at least one sub-resistor is disabled, the resistance of the first voltage dividing resistor is reduced, and the first output voltage is less than the second output voltage of the second LDO; The switch device is controlled to be opened by the register, so that the at least one sub-resistor is enabled, the resistance of the first voltage dividing resistor is increased, and the first output voltage is greater than the second output voltage of the second LDO.

2. The LDO switching circuit of claim 1, wherein, The first LDO comprises a transistor, a first voltage dividing resistor, a second voltage dividing resistor, an error amplifier and an adjusting unit; The gate of the transistor is connected with the output terminal of the error amplifier, and the other two poles of the transistor are connected with the voltage input terminal and the voltage output terminal respectively; The first end of the first voltage dividing resistor is connected with the voltage output terminal, and the second end of the first voltage dividing resistor is connected with the second input terminal of the error amplifier and the first end of the second voltage dividing resistor respectively; The first input terminal of the error amplifier is used for inputting a reference voltage, and the second input terminal of the error amplifier is connected with the second end of the first voltage dividing resistor and used for inputting the voltage value of the second end of the first voltage dividing resistor; The second end of the second voltage dividing resistor is connected with a ground terminal, and the first end of the second voltage dividing resistor is connected with the second end of the first voltage dividing resistor; The adjusting unit is arranged on the first voltage dividing resistor and used for adjusting the resistance of the first voltage dividing resistor, so as to adjust the voltage value input by the second input terminal of the error amplifier.

3. The LDO switching circuit of claim 2, wherein, In the case that all the sub-resistors of the first voltage dividing resistor are enabled, the first output voltage of the first LDO is greater than the second output voltage of the second LDO; The adjusting unit is connected with at least one sub-resistor and used for controlling the enabled state of the at least one sub-resistor.

4. The LDO switching circuit of claim 3, wherein, A resistance ratio between a resistance value of the at least one sub-resistor and a resistance value of the second voltage dividing resistor is in a first preset ratio interval, so that a voltage difference between the second output voltage and the first output voltage is less than a preset difference threshold, and a transistor of the first LDO is stably driven to an off state. The first preset ratio interval is determined according to the preset difference threshold, the second output voltage and the reference voltage.

5. The LDO switching circuit of claim 3, wherein, In a case where all sub-resistors of the first voltage dividing resistor are effective, a resistance ratio between a resistance value of the first voltage dividing resistor and a resistance value of the second voltage dividing resistor is in a second preset ratio interval, so that a voltage difference between the first output voltage and the second output voltage is less than a preset voltage threshold, and the first LDO stably supplies power; The second preset ratio interval is determined according to the preset voltage threshold, the second output voltage and the reference voltage.

6. An LDO switching method, comprising: The method comprises: In response to a power supply request of a second LDO, a regulating unit of the first LDO is turned on through a register, the first output voltage of the first LDO is reduced, the first output voltage is less than a second output voltage of the second LDO, the first LDO is driven to be turned off, and the second LDO serves as a power supply; In response to a power supply request of the first LDO, the regulating unit is turned off through the register, the first output voltage of the first LDO is increased, the first output voltage is greater than the second output voltage of the second LDO, the second LDO is driven to be turned off, and the first LDO serves as a power supply; The first LDO comprises a first voltage dividing resistor, the first voltage dividing resistor comprises a plurality of serial sub-resistors, the regulating unit comprises a switching device controlled by a register, and the switching device is in parallel with at least one sub-resistor in the first voltage dividing resistor; The switching device is controlled to be closed through the register, the at least one sub-resistor is disabled, the resistance value of the first voltage dividing resistor is reduced, and the first output voltage is less than the second output voltage of the second LDO; The switching device is controlled to be opened through the register, the at least one sub-resistor is enabled, the resistance value of the first voltage dividing resistor is increased, and the first output voltage is greater than the second output voltage of the second LDO.

7. A chip, characterized by The LDO switching method of claim 6 is applied to make the power supply of the chip be the first LDO or the second LDO.

8. An electronic device, comprising: Comprise: One or more processors; A storage device having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the method of claim 6; One or more I / O interfaces connected between the processor and the memory and configured to implement information interaction between the processor and the memory.

9. A computer readable medium having a computer program stored thereon, the program being executed by a processor to implement the method of claim 6.

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