Controller, storage device, and computing system

Abstract

The present disclosure relates to a controller, a storage device, and a computing system that manages memory usage data (e.g., mapping data managed by the storage device) as log data in a buffer memory located inside the storage device, using a host memory in a low power mode. Memory usage data may be managed by updating log data during the low power mode, and commands of the host device may be processed by the updated log data after switching from the low power mode to the active mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0118708 filed on September 7, 2023 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology generally relate to a controller, a storage device, and a computing system. Background Art

[0004] The storage device may include a memory including a plurality of memory cells. The storage device may include a controller for controlling the memory. The controller may control operations of writing data into the memory, reading data from the memory, or erasing data written into the memory according to a command received from an external device such as a host device.

[0005] The storage device may operate in a mode capable of reducing power consumption under the control of the host device. When the storage device operates in a mode capable of reducing power consumption, the storage device may not communicate with the host device or may not perform transmission and reception of data.

[0006] When the storage device returns to operation in the normal mode and processes a command of the host device, efficiency in processing the command of the host device may decrease because data transmission and reception to and from the host device were not performed in the previous mode. Summary of the invention

[0007] Various embodiments of the disclosed technology are directed to providing measures capable of improving the efficiency of processing a command of a host device after a period in which a storage device operates in a power consumption mode under the control of the host device.

[0008] According to an embodiment of the disclosed technology, after a period in which a storage device operates in a mode capable of reducing power consumption under the control of a host device, efficiency in processing a command received from a host device may be improved.

[0009] In an embodiment, a storage device may include: a memory; and a controller configured to control the memory to store log data corresponding to at least some memory usage data stored in the host memory in a buffer memory when a mode change signal is received from a host device having a host memory, process a command of the host device using the log data, and send a mode change confirmation signal corresponding to the mode change signal to the host device.

[0010] In an embodiment, a computing system may include: a host device including a host memory; and a memory device including a memory, and the memory device is configured to store log data corresponding to at least some memory usage data stored in the host memory and used to process a command of the host device in a buffer memory when a mode change signal is received from the host device, and to send a mode change confirmation signal corresponding to the mode change signal to the host device.

[0011] In an embodiment, a controller may include: a buffer memory; and a processor, configured to store log data corresponding to at least some mapping data stored in a host memory included in the host device in the buffer memory when a mode change signal is received from a host device, and to send a mode change confirmation signal corresponding to the mode change signal to the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a configuration of a storage device according to an embodiment of the present disclosure.

[0013] Figures 2 to 4 is a diagram illustrating operations of a storage device in different modes according to an embodiment of the present disclosure.

[0014] Figures 5 to 7 is a diagram illustrating that a storage device manages memory usage data stored in a host memory using log data in different operation modes according to an embodiment of the present disclosure.

[0015] Figure 8 and Fig. 9 is a diagram illustrating an example in which a storage device stores log data in a buffer memory according to an embodiment of the present disclosure.

[0016] Fig.10 is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Examples or embodiments of the present disclosure will be described below with reference to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and even if the same reference numerals and symbols are shown in different drawings from each other, they can also be used to indicate the same or similar components. Further, in the following description of the examples or embodiments of the present disclosure, when it is determined that a detailed description of the well-known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure quite unclear, the description will be omitted. Terms such as "including", "having", "comprising", "consisting of", and "formed by" used herein are generally meant to allow the addition of other components unless these terms are used with the term "only". Unless the context clearly indicates otherwise, as used herein, the singular form is intended to include the plural form.

[0018] Terms such as "first", "second", "A", "B", "(A)", and "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, or quantity of an element, etc., but is only used to distinguish the corresponding element from other elements.

[0019] When it is mentioned that a first element is “connected or coupled”, “contacted or overlapped”, etc. with a second element, it should be understood that not only the first element can be “directly connected or coupled” or “directly contacted or overlapped” with the second element, but also a third element can be “interposed” between the first and second elements, or the first and second elements can be “connected or coupled”, “contacted or overlapped”, etc. with each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled”, “contacted or overlapped”, etc. with each other.

[0020] When time-related terms such as "after", "after...", "next", "before" and the like are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, unless these terms are used with the terms "directly" or "immediately", these terms may be used to describe non-continuous or non-sequential processes or operations.

[0021] In addition, when any dimension, relative dimension, etc. is mentioned, even if the relevant description is not detailed, it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Further, the term "may" fully includes all meanings of the term "can".

[0022] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0023] Figure 1is a diagram illustrating a configuration of a storage device according to an embodiment of the present disclosure.

[0024] Reference Figure 1 , the storage device 100 may include a memory 110. The storage device 100 may include a controller 120 that controls the memory 110.

[0025] For example, the memory 110 may be implemented as various types of memory such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistance random access memory, phase change random access memory, magnetoresistive random access memory, ferroelectric random access memory, and spin transfer torque random access memory. The memory 110 may be implemented in a three-dimensional array structure. The embodiments of the present disclosure may be applied not only to a flash memory in which a charge storage layer is configured by a floating gate, but also to a charge trap flash memory (CTF) in which a charge storage layer includes an insulating film.

[0026] The memory 110 may include a plurality of memory blocks BLK (or memory blocks). The memory 110 may include a memory cell array including a plurality of memory cells storing data, and the memory cell array may exist in a memory block.

[0027] The memory 110 may operate in response to the control of the controller 120. The operation of the memory 110 may include, for example, a program operation (also referred to as a "write operation"), an erase operation, and a read operation.

[0028] The controller 120 may control a program operation, an erase operation, a read operation, and a background operation using the memory 110. The background operation may include, for example, at least one of garbage collection, wear leveling, read reclamation, and bad block management operations.

[0029] The controller 120 may control the operation of the memory 110 according to a request of a device located outside the memory device 100. The controller 120 may also control the operation of the memory 110 regardless of or without a request from outside the memory device 100.

[0030] For example, the controller 120 may control the operation of the memory 110 according to a request of the host device 200. The memory device 100 and the host device 200 may be collectively referred to as a computing system.

[0031] For example, the host device 200 may be a computer, an ultra mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device constituting a data center, one of various electronic devices configuring a home network, one of various electronic devices configuring a telematics network, an RFID (radio frequency identification) device, a mobile device capable of traveling under human control or automatically driving (e.g., a vehicle, a robot, or a drone), etc. Alternatively, the host device 200 may be a virtual / augmented reality device that provides 2D or 3D virtual reality images or augmented reality images. The host device 200 may be any of various electronic devices, each of which requires a storage device 100 capable of storing data.

[0032] The host device 200 may include at least one operating system. The operating system may manage and control all functions and operations of the host device 200, and may control the mutual operation between the host device 200 and the storage device 100. According to the mobility of the host device 200, the operating system may be divided into a general operating system and a mobile operating system.

[0033] The controller 120 and the host device 200 may be separate devices from each other. In some cases, the controller 120 and the host device 200 may be implemented by being integrated into one device. Hereinafter, for ease of explanation, the controller 120 and the host device 200 are described as separate devices by way of example.

[0034] The controller 120 may include a host interface providing an interface for communicating with the host device 200. The controller 120 may include a memory interface providing an interface for communicating with the memory 110.

[0035] The controller 120 may include a control circuit that controls the overall operation of the controller 120. The control circuit may include, for example, Figure 1 The processor 121 is shown. The control circuitry may include working memory for operation of the processor 121 and may optionally include error detection and correction circuitry.

[0036] The processor 121 may communicate with the host device 200 through a host interface, and may communicate with the memory 110 through a memory interface.

[0037] The processor 121 may interpret a command input from the host device 200 and transfer the command to the memory 110 .

[0038] For example, the processor 121 may include a flash translation layer or may correspond to a flash translation layer. The processor 121 may convert a logical block address provided by the host device 200 into a physical block address. The processor 121 may receive a logical block address and convert the logical block address into a physical block address using a mapping table.

[0039] For example, the processor 121 may control the operation of the controller 120 by executing firmware. In some embodiments, the operation of the storage device 100 may be implemented such that the processor 121 executes firmware that defines the corresponding operation.

[0040] The firmware, which is a program to be executed in the storage device 100 to drive the storage device 100, may include various functional layers corresponding to the above-mentioned processor 121. For example, the firmware may include binary data defining codes for executing the various functional layers.

[0041] For example, the firmware may be loaded into the working memory from the memory 110 or an independent nonvolatile memory (eg, ROM or NOR flash memory) located outside the memory 110. When performing a startup operation after power-on, the processor 121 may first load all or part of the firmware into the working memory.

[0042] In order to control the overall operation of the controller 120, the processor 121 may execute the logic operation defined in the firmware loaded into the working memory. According to the result of executing the logic operation defined in the firmware, the processor 121 may control the controller 120 to generate a command or a signal. When a portion of the firmware defining the logic operation to be executed is not loaded into the working memory, the processor 121 may generate an event (e.g., an interrupt) for loading the corresponding portion of the firmware into the working memory.

[0043] The working memory may store firmware, program code, commands, or data required to drive the controller 120. The working memory may be located inside or outside the controller 120. The working memory may be located inside and outside the controller 120 at the same time.

[0044] The working memory can be Figure 1 The buffer memory 122 is shown. Optionally, the working memory can be connected to Figure 1 The buffer memory 122 is shown as being separately provided. The buffer memory 122 may be located inside or outside the controller 120.

[0045] The working memory or buffer memory 122 may be, for example, a volatile memory including at least one of SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM).

[0046] When the capacity of the working memory or the buffer memory 122 included in the controller 120 is small, the processor 121 of the controller 120 may store data required for the operation by utilizing a partial area of ​​the host memory 210 included in the host device 200. The processor 121 may allocate a partial area of ​​the host memory 210, may store data in the allocated area, and may use the stored data when performing a required operation.

[0047] For example, the processor 121 may store the memory usage data MUD in the host memory 210 included in the host device 200. The memory usage data MUD may be at least some of various types of data used by the processor 121 to control operations of the controller 120 or the memory 110.

[0048] The memory usage data MUD may be, for example, mapping data (MD), but the embodiments of the present disclosure are not limited thereto.

[0049] When the capacity of the working memory or the buffer memory 122 included in the controller 120 or the storage device 100 is reduced, the processor 121 may store the memory usage data MUD in the host memory 210 and may use the memory usage data MUD. When the capacity of the working memory or the buffer memory 122 included in the storage device 100 is reduced, the operation performance of the storage device 100 may be maintained.

[0050] According to the operation mode of the storage device 100 , embodiments of the present disclosure may provide measures for managing and using the memory usage data MUD stored in the host memory 210 .

[0051] While the operation efficiency of the storage device 100 is improved by using the host memory 210 , the operation performance of the storage device 100 may be prevented from being degraded in certain operation modes by using the host memory 210 .

[0052] Figures 2 to 4 is a diagram illustrating operations of a storage device in different modes according to an embodiment of the present disclosure.

[0053] Reference Figure 2 , the storage device 100 may include a memory 110 and a controller 120. The controller 120 may include a processor 121 and a buffer memory 122. In some embodiments, the buffer memory 122 may be located outside the controller 120.

[0054] The host device 200 may include a host memory 210. The storage device 100 may allocate and use a partial area of ​​the host memory 210. For example, the storage device 100 may store memory usage data MUD in the host memory 210.

[0055] As in the above example, the memory usage data MUD as data used for the operation of the storage device 100 may be mapping data (MD), but is not limited to this example. The memory usage data MUD may be a part of data that can be used for the operation of the storage device 100 when stored in a volatile memory (e.g., the buffer memory 122 or a working memory included in the storage device 100).

[0056] Hereinafter, for convenience of explanation, the memory usage data MUD is mapping data (MD) in some examples, but embodiments of the present disclosure are not limited thereto.

[0057] When operating in the active mode, the memory device 100 may perform operations according to commands received from the host device 200. According to the commands of the host device 200, the memory device 100 may control operations of writing data to the memory 110, reading data from the memory 110, or erasing data written to the memory 110.

[0058] For example, when performing an operation according to a read command from the host device 200, the controller 120 included in the storage device 100 may use the memory usage data MUD stored in the host memory 210. The controller 120 may convert a logical block address into a physical block address using the memory usage data MUD, and may provide data stored in the physical block address of the memory 110 to the host device 200.

[0059] Since the controller 120 processes the command of the host device 200 while accessing the host memory 210 , performance may be improved compared to a case where the controller 120 processes the command of the host device 200 using mapping data (MD) stored in the memory 110 .

[0060] Reference Figure 2 , the storage device 100 can operate in a mode capable of reducing power consumption under the control of the host device 200.

[0061] For example, in the power consumption mode, the host device 200 may send a mode change signal to the controller 120, as shown in ①. The mode change signal may be, for example, a signal indicating switching from the active mode to the low power mode. In other embodiments, the mode change signal may be a signal capable of indicating a change between at least three modes.

[0062] When receiving the mode change signal from the host device 200 , the controller 120 may check the memory usage data MUD stored in the host memory 210 .

[0063] As shown in ②, the controller 120 may generate log data JD corresponding to the memory usage data MUD stored in the host memory 210. The controller 120 may store the log data JD in the buffer memory 122.

[0064] For example, the log data JD may be the same data as the memory usage data MUD.

[0065] In other examples, the log data JD may be various types of data that may identify or specify the memory usage data MUD.

[0066] For example, when at least two memory usage data MUD are continuous, the log data JD may be data including basic data corresponding to the first memory usage data MUD and an arbitrary amount of information on the memory usage data MUD continuous with the basic data.

[0067] The controller 120 may store the memory usage data MUD in the buffer memory 122 without changing the memory usage data MUD, however, the capacity of the buffer memory 122 may be smaller than the capacity of the host memory 210. Therefore, the controller 120 may generate log data JD identifying or specifying the type of the memory usage data MUD.

[0068] The controller 120 may generate at least some of the memory usage data MUD as log data JD. When only some of the memory usage data MUD is generated as log data JD, the controller 120 may generate the log data JD in the order of the most recently used memory usage data MUD and may be based on a predetermined capacity range of the most recently used memory usage data MUD. The log data JD corresponding to the memory usage data MUD may be stored in the buffer memory 122.

[0069] When the generation and storage of the log data JD are completed, the controller 120 may transmit a mode change confirmation signal to the host device 200 as shown in ③.

[0070] When the mode change confirmation signal is sent, at least one of the host device 200 and the storage device 100 may operate in a low power mode. In the low power mode, some operations may not be performed. For example, communication between the host device 200 and the storage device 100 may not be performed. Alternatively, data transmission and reception between the host device 200 and the storage device 100 may not be performed in the low power mode.

[0071] In the low power mode, the storage device 100 may manage the log data JD stored in the buffer memory 122 .

[0072] For example, refer to Figure 3In the low power mode, at least part of the communication between the host device 200 and the storage device 100 may not be performed. For example, the controller 120 may not be allowed to access the host memory 210.

[0073] When operating in the low power mode, the processor 121 of the controller 120 may perform at least a portion of the background operation, as shown in ④.

[0074] When the processor 121 performs background operations such as garbage collection, the memory usage data MUD previously stored in the host memory 210 may change. As shown in ⑤, the processor 121 may update the log data JD stored in the buffer memory 122 related to the memory usage data MUD to be changed, and may store the update log data JD_upd in the buffer memory 122.

[0075] Although the processor 121 cannot access the host memory 210 , by updating the log data JD stored in the buffer memory 122 , the memory usage data MUD stored in the host memory 210 before the low power mode can be managed in the latest state.

[0076] The processor 121 may manage the log data JD stored in the buffer memory 122 until a signal or command received from the host device 200 instructs the storage device 100 to enter the active mode again. The processor 121 may update the log data JD when a mode change occurs and save the update in the update log data JD_upd.

[0077] When receiving a command indicating a mode change or a new operation from the host device 200 , the processor 121 may process the command of the host device 200 using the update log data JD_upd.

[0078] For example, refer to Figure 4 , when operating in low power mode, the controller 120 may receive a command from the host device 200, as shown in ⑥.

[0079] The storage device 100 may enter the active mode according to a command received from the host device 200. In some embodiments, before receiving the command, the storage device 100 may receive a signal or a command indicating entry into the active mode.

[0080] The processor 121 may perform an operation according to a command received from the host device 200 .

[0081] For example, when the command received from the host device 200 is a read command, the processor 121 may check the update log data JD_upd stored in the buffer memory 122, as shown in ⑦. When the update log data JD_upd related to the command received from the host device 200 exists in the buffer memory 122, the processor 121 may read the user data stored in the memory 110 by using the corresponding update log data JD_upd, as shown in ⑧.

[0082] After the period in which the processor 121 operates in the low power mode, the processor 121 may process a command received from the host device 200 using the update log data JD_upd stored in the buffer memory 122. The processor 121 may not read the mapping data (MD) stored in the memory 110 to process the command of the host device 200.

[0083] However, when the mapping data (MD) related to the command of the host device 200 does not exist in the buffer memory 122 , the processor 121 may process the command of the host device 200 by using the mapping data (MD) stored in the memory 110 .

[0084] In addition, the processor 121 may process a command of the host device 200 using the memory usage data MUD stored in the host memory 210. The memory usage data MUD stored in the host memory 210 may correspond to the mapping data MD that is not updated during the low power mode.

[0085] The processor 121 may store memory usage data MUD corresponding to the update log data JD_upd for processing the command of the host device 200 in the host memory 210. For example, the host device 200 may read the update log data JD_upd stored in the buffer memory 122 and may store the corresponding memory usage data MUD in the host memory 210.

[0086] During the partial period of the active mode, the memory usage data MUD stored in the buffer memory 122 and corresponding to the update log data JD_upd may be stored in the host memory 210. The partial period of the active mode may be, for example, an idle period.

[0087] Based on the update log data JD_upd stored in the buffer memory 122 and managed during the low power mode, the memory usage data MUD stored in the host memory 210 can be updated, as shown in ⑨. Since the entire mapping data (MD) is not moved and the memory usage data MUD stored in the host memory 210 is updated based on the partial update log data JD_upd, the operation efficiency after entering the active mode from the low power mode can be improved.

[0088] Since the memory device 100 stores and manages the log data JD corresponding to the memory usage data MUD stored in the host memory 210 in the buffer memory 122 , at least some of the memory usage data MUD may be maintained in the latest state by updating the log data JD_upd during the low power consumption mode period.

[0089] Since the storage device 100 processes the command of the host device 200 using the update log data JD_upd stored in the buffer memory 122 , the command generated by the host device 200 after exiting the low power mode may be efficiently processed.

[0090] In addition, since the memory usage data MUD stored in the host memory 210 is updated after the low power mode, management of the memory usage data MUD stored in the host memory 210 can be effectively performed after exiting the low power mode based on the update log data JD_upd updated during the low power mode.

[0091] Figures 5 to 7 is a diagram illustrating that a storage device manages memory usage data stored in a host memory using log data in different operation modes according to an embodiment of the present disclosure.

[0092] Reference Figure 5 In the example, six memory usage data MUD are stored in the host memory 210. Each memory usage data MUD may include information indicating a mapping relationship between an LPN corresponding to a logical block address and a VPN corresponding to a physical block address.

[0093] When receiving the mode change signal from the host device 200 , the processor 121 of the controller 120 may store log data JD corresponding to at least some of the memory usage data MUD stored in the host memory 210 in the buffer memory 122 .

[0094] In the example, Figure 5 As shown, the log data JD may be the same data as the memory usage data MUD.

[0095] In some embodiments, the log data JD may be data including one basic data and information about the number of data continuous with the basic data. For example, when the memory usage data MUD A includes mapping information of LPN 0, LPN 1, and LPN 2, the log data JD may include mapping information about LPN 0 and 2 indicating the number of continuous mapping information.

[0096] The type of log data JD may be set according to the total size of log data JD that can be stored in the buffer memory 122 .

[0097] The processor 121 may store the log data JD corresponding to at least some of the memory usage data MUD stored in the host memory 210 in the buffer memory 122 according to the capacity allowed by the buffer memory 122. The processor 121 may preferentially store the log data JD corresponding to the most recently used memory usage data MUD among the memory usage data MUD stored in the host memory 210 in the buffer memory 122.

[0098] Figure 5 An example is shown in which log data JD corresponding to five memory usage data MUD A, B, C, D, and E among six memory usage data MUD A, B, C, D, E, and F stored in the host memory 210 is stored in the buffer memory 122 .

[0099] Before entering the low power mode or while entering the low power mode, the processor 121 may store and manage log data JD corresponding to at least some of the memory usage data MUD stored in the host memory 210 in the buffer memory 122 .

[0100] The processor 121 may update the log data JD changed according to the background operation performed in the low power mode. The processor 121 may process a command received from the host device 200 after the low power mode by using the update log data JD_upd.

[0101] For example, refer to Figure 6 , after log data JD corresponding to some memory usage data MUD stored in the host memory 210 is stored in the buffer memory 122, the low power mode may be entered.

[0102] The processor 121 may perform background operations in a low power mode.

[0103] The processor 121 may update the log data JD changed according to the background operation, and at least a portion of the log data JD stored in the buffer memory 122 may be changed. For example, the physical block address mapped to the LPN 0 corresponding to the logical block address may be changed from VPN A to VPN X. The physical block address mapped to the LPN 500 corresponding to the logical block address may be changed from VPN B to VPN Y.

[0104] The processor 121 may update the log data JD stored in the buffer memory 122 according to the changed mapping information. Figure 6In this case, the log data JD A, B, and C stored in the buffer memory 122 may be updated to update log data JD_upd A′, B′, and C′.

[0105] The processor 121 may manage the memory usage data MUD stored in the host memory 210 during the low power mode without accessing the host memory 210 , thereby reflecting the latest status by updating the log data JD stored in the buffer memory 122 .

[0106] When receiving a command of the host device 200 after exiting the low power mode, the processor 121 may process the command using the update log data JD_upd stored in the buffer memory 122 .

[0107] For example, when receiving a command from the host device 200 , the processor 121 may check whether log data JD related to the command exists in the buffer memory 122 .

[0108] The processor 121 may scan the log data JD stored in the buffer memory 122 .

[0109] The processor 121 may perform scanning in the order of the log data JD corresponding to the most recently used memory usage data MUD. For example, when the memory usage data MUD A, B, C, D, and E are most recently used in this order and the corresponding log data JD is stored in the buffer memory 122, the processor 121 may perform scanning in the order of updating the log data JD_upd A', B', and C' and then the log data JD D and E.

[0110] When scanning the log data JD stored in the buffer memory 122 , the processor 121 may check whether the log data JD is related to a command received from the host device 200 .

[0111] For example, the update log data JD_upd B′ may include mapping information required for a command from the host device 200. The processor 121 may convert a logical block address according to a command of the host device 200 into a physical block address using the update log data JD_upd B′ stored in the buffer memory 122. Then, the processor 121 may read data stored in the memory 110 based on the converted physical block address, and may provide the read data to the host device 200.

[0112] Therefore, the processor 121 does not need to read the mapping data (MD) stored in the memory 110 to process the command of the host device 200. The command processing speed of the processor 121 after the low power mode ends can be increased.

[0113] The processor 121 may store the update log data JD_upd in the host memory 210 .

[0114] Reference Figure 7 , after switching from the low power mode to the active mode, the processor 121 may store the update log data JD_upd A′, B′, and C′ stored in the buffer memory 122 in the host memory 210 .

[0115] For example, during an idle period or a preset period (two active modes), the processor 121 may store the update log data JD_upd stored in the buffer memory 122 in the host memory 210. In other embodiments, the host device 200 may read the update log data JD_upd from the host memory 210 and store the update log data JD_upd in the host memory 210.

[0116] When processing commands from the host device 200, update log data JD_upd may also be stored in the host memory 210. For example, as described above with reference to Figure 6 As described, when a command of the host device 200 is processed, the update log data JD_upd B′ may be stored in the host memory 210 .

[0117] The processor 121 may not transmit the unupdated log data JD D and E among the log data JD stored in the buffer memory 122 to the host memory 210. The update of the memory usage data MUD stored in the host memory 210 may be performed only on the memory usage data MUD corresponding to the update log data JD_upd. Therefore, the amount of data transmitted and received between the host device 200 and the storage device 100 for updating the memory usage data MUD may be reduced.

[0118] The processor 121 of the controller 120 may use the buffer memory 122 to manage the log data JD corresponding to the memory usage data MUD stored in the host memory 210. The buffer memory 122 storing the log data JD may be the buffer memory 122 for mapping data (MD). Alternatively, the buffer memory storing the log data JD may be provided separately from the buffer memory 122 for mapping data (MD).

[0119] Figure 8 and Fig. 9 is a diagram illustrating that a storage device according to an embodiment of the present disclosure stores log data in a buffer memory.

[0120] Reference Figure 8, the controller 120 included in the storage device 100 may include a processor 121, a first buffer memory (BufM1) 122a and a second buffer memory (BufM2) 122b. The first buffer memory 122a and the second buffer memory 122b may be volatile memories, examples of which are described above.

[0121] The first buffer memory 122a may store, for example, mapping data MD. The mapping data MD may be stored in the first buffer memory 122a and the host memory 210 and may be used when performing an operation according to a command of the host device 200. The size of the first buffer memory 122a may be smaller than that of the host memory 210.

[0122] The second buffer memory 122b may store the log data JD. For example, the second buffer memory 122b may be a buffer memory 122 for storing other types of data in a mode other than the low power mode.

[0123] When entering the low power mode, the processor 121 may store the log data JD in the second buffer memory 122 b . The processor 121 may move the map data MD stored in the first buffer memory 122 a to the memory 110 .

[0124] In the low power mode, the processor 121 may update log data JD changed according to background operation. The update log data JD_upd may be stored in the second buffer memory 122b.

[0125] After the low power mode, the processor 121 may receive a command from the host device 200. The processor 121 may process the command of the host device 200 using the update log data JD_upd stored in the second buffer memory 122b.

[0126] The processor 121 may read data according to a command of the host device 200 using the update log data JD_upd, and may provide the read data to the host device 200. The processor 121 may update the memory usage data MUD stored in the host memory 210 by providing the update log data JD_upd to the host device 200.

[0127] For example, the update log data JD_upd may be stored in the first storage area 211 of the host memory 210. User data according to a command processed using the update log data JD_upd may be stored in the second storage area 212 of the host memory 210, for example.

[0128] For the buffer memory 122 included in the controller 120, the processor 121 may manage the log data JD using the second buffer memory 122b separate from the first buffer memory 122a for the map data MD. Therefore, the processor 121 may efficiently process the command of the host device 200 after the low power mode.

[0129] In another embodiment, the log data JD may be stored and managed in the first buffer memory 122 a , which is described above as storing the mapping data MD.

[0130] For example, refer to Fig. 9 , the controller 120 may include a first buffer memory 122a and a second buffer memory 122b. The first buffer memory 122a may be a buffer memory 122 for mapping data MD. The second buffer memory 122b may be a buffer memory 122 for data other than the mapping data MD.

[0131] When the host device 200 switches the operation to the low power mode, the controller 120 may receive a mode change signal from the host device 200 as indicated by ①.

[0132] For example, the processor 121 of the controller 120 may move the mapping data MD stored in the first buffer memory 122a to the memory 110, as shown in ②. As shown in ③, the processor 121 may generate log data JD corresponding to the memory usage data MUD stored in the host memory 210, and may store the log data JD in the first buffer memory 122a.

[0133] As shown in ④, the processor 121 may send a mode change confirmation signal to the host device 200 .

[0134] In the active mode and before the low power mode, the mapping data MD may be stored and managed in, for example, the first buffer memory 122 a and the host memory 210 .

[0135] When switching from the active mode to the low power mode, it may be managed by moving the map data MD stored in the first buffer memory 122a to the memory 110, and the first buffer memory 122a enters a state in which data other than the map data MD may be stored.

[0136] In the low power mode, log data JD corresponding to the memory usage data MUD stored in the host memory 210 may be stored and managed in the first buffer memory 122 a .

[0137] According to the background operation performed by the processor 121 during the low power mode, the log data JD stored in the first buffer memory 122 a may be managed by updating.

[0138] When an operation according to a command of the host device 200 is performed in active mode and after low power mode, the log data JD stored in the first buffer memory 122a may be used. The memory usage data MUD stored in the host memory 210 may be updated according to the update log data JD_upd stored in the first buffer memory 122a.

[0139] At least a portion of the mapping data MD moved from the first buffer memory 122 a to the memory 110 upon entering the low power mode may be moved back to the first buffer memory 122 a .

[0140] During the low power mode, the first buffer memory 122a for the mapping data MD may be used to manage log data JD corresponding to the memory usage data MUD of the host memory 210. The log data JD may be managed and updated without adding a separate buffer memory 122.

[0141] The second buffer memory 122b included in the controller 120 may be used for other data. For example, the log data JD may be managed by using the first buffer memory 122a for the mapping data MD and the second buffer memory 122b for data other than the mapping data MD.

[0142] Since log data JD corresponding to memory usage data MUD stored in the host memory 210 is stored and managed in at least a portion of the first and second buffer memories 122a and 122b, efficiency may be improved when processing a command of the host device 200 after a low power mode.

[0143] Fig.10 is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure.

[0144] Reference Fig.10 , the storage device 100 may enter a low power mode under the control of the host device 200 ( S1000 ).

[0145] When entering the low power mode or before entering the low power mode, the storage device 100 may store the log data JD corresponding to the memory usage data MUD stored in the host memory 210 in the buffer memory 122. The memory usage data MUD may be, for example, the mapping data MD.

[0146] The storage device 100 may update the log data JD stored in the buffer memory 122 according to the mapping data MD changed while performing the background operation (S1010). When the physical block address mapped to the logical block address changes, the change may be managed by the update of the log data JD.

[0147] The storage device 100 may enter an active mode under the control of the host device 200 ( S1020 ).

[0148] The storage device 100 may search for a logical block address according to a command of the host device 200 from among the log data JD stored in the buffer memory 122 ( S1030 ).

[0149] When the logical block address according to the command of the host device 200 exists as the log data JD stored in the buffer memory 122 ( S1040 ), the storage device 100 may process the command of the host device 200 using the log data JD stored in the buffer memory 122 ( S1050 ).

[0150] Since the command of the host device 200 is processed using the log data JD stored in the buffer memory 122, the storage device 100 may not read the mapping data MD stored in the memory 110 to process the command. In this way, the time required to process the command of the host device 200 after switching from the low power mode to the active mode can be reduced.

[0151] When the logical block address according to the command of the host device 200 does not exist as log data JD in the buffer memory 122, the storage device 100 can process the command of the host device 200 by using the memory usage data MUD stored in the host memory 210 or the mapping data MD stored in the memory 110 (S1060).

[0152] During a period in low power mode, the storage device 100 that manages mapping data MD using the host memory 210 of the host device 200 can manage the update of the mapping data MD through the log data JD stored in the buffer memory 122. In the low power mode, the sending and receiving of data to and from the host device 200 is not performed or restricted.

[0153] After switching from the low power mode to the active mode, processing of a command of the host device 200 may be easily performed through the log data JD.

[0154] Since the memory usage data MUD of the host memory 210 is updated based on the update log data JD_upd, the amount of data transmitted and received for the purpose of updating can be reduced.

[0155] By improving the management efficiency of the mapping data MD in the low power mode using the host memory 210 , the operation performance of the memory device 100 may be improved.

[0156] Although various embodiments of the disclosed technology have been described with specific particulars and different details for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible based on the contents disclosed or described in the disclosed technology, without departing from the spirit and scope of the disclosed technology as defined in the appended claims.

Claims

1. A storage device, comprising: Memory; as well as Controller: upon receiving a mode change signal from a host device having a host memory, controlling the memory to store log data corresponding to at least some memory usage data stored in the host memory in a buffer memory, processing commands of the host device using the log data, and A mode change confirmation signal corresponding to the mode change signal is transmitted to the host device.

2. The storage device according to claim 1, wherein: The controller performs a background operation after sending the mode change confirmation signal, and updates the log data according to the background operation.

3. The storage device according to claim 2, wherein: Upon receiving the command from the host device, the controller searches for log data stored in the buffer memory, and when there is log data related to the command, provides data corresponding to the command to the host device using the log data.

4. The storage device according to claim 3, wherein: When the log data is not associated with a command of the host device, the controller provides data corresponding to the command to the host device using mapping data stored in the memory.

5. The storage device according to claim 3, wherein: When the log data is not associated with a command of the host device, the controller provides data corresponding to the command to the host device using memory usage data stored in the host memory.

6. The storage device according to claim 5, wherein: After the mode change confirmation signal is transmitted, memory usage data for providing data corresponding to the command to the host device is not updated.

7. The storage device according to claim 3, wherein: Memory usage data corresponding to log data for providing data corresponding to the command to the host device is stored in the host memory.

8. The storage device according to claim 7, wherein: Memory usage data corresponding to the log data is stored in a first storage area of ​​the host memory, and data corresponding to the command is stored in a second storage area of ​​the host memory.

9. The storage device according to claim 7, wherein: Memory usage data corresponding to log data updated after the mode change confirmation signal is transmitted among log data other than log data for providing data corresponding to the command to the host device is stored in the host memory.

10. The storage device according to claim 1, wherein: The buffer memory comprises: a first buffer memory storing mapping data different from the memory usage data; and The second buffer memory stores the log data.

11. The storage device according to claim 10, wherein: Upon receiving the mode change signal, the mapping data stored in the first buffer memory is stored in the memory.

12. The storage device according to claim 1, wherein: The buffer memory stores mapping data different from the memory usage data, and upon receiving the mode change signal, the mapping data is stored in the memory.

13. The storage device according to claim 1, wherein: The log data is the same data as at least some of the memory usage data.

14. The storage device according to claim 1, wherein: The log data is data including basic data of at least two consecutive memory usage data among at least some memory usage data and the number of memory usage data consecutive to the basic data.

15. A computing system comprising: a host device, including a host memory; as well as A memory device includes a memory, and upon receiving a mode change signal from the host device, the memory device stores log data corresponding to at least some memory usage data stored in the host memory and used for processing commands of the host device in a buffer memory, and sends a mode change confirmation signal corresponding to the mode change signal to the host device.

16. The computing system of claim 15, wherein: After sending the mode change confirmation signal, the log data is updated according to background operations of the memory device.

17. The computing system of claim 16, wherein: When the host device generates the command after the mode change confirmation signal is transmitted, memory usage data corresponding to the updated log data is stored in the host memory.

18. A controller comprising: Buffer memory; as well as A processor stores log data corresponding to at least some mapping data stored in a host memory included in the host device in the buffer memory upon receiving a mode change signal from the host device, and transmits a mode change confirmation signal corresponding to the mode change signal to the host device.

19. The controller according to claim 18, wherein: When receiving the mode change signal, the processor stores the mapping data stored in the buffer memory in a memory located externally, and stores the log data in the buffer memory.

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