Jitter increasing circuit and true random number generator

Abstract

The invention discloses a jitter increasing circuit and a true random number generator. The jitter increasing circuit comprises a current random fluctuation module and an adjustable noise module; the current output end of the current random fluctuation module is connected with the drain electrode and the grid electrode of the field effect transistor M0, and the current random fluctuation module can generate random current; the grid electrode of the field effect transistor M0 is connected with the grid electrode of the field effect transistor M1; the drain electrode of the field effect transistor M1 is grounded through a capacitor CL; the adjustable noise module is arranged beside the capacitor CL, and noise generated by the adjustable noise module can be coupled and superposed to the capacitor CL; the drain electrode of the field effect transistor M1 is connected with the high-frequency clock circuit through the phase inverter; the grid electrode of the field effect transistor M3 is connected with the clock source circuit through the phase inverter. According to the invention, a function of sampling clock random jitter increase can be realized on a common chip, noise in two dimensions of voltage and current can be superposed, the randomness of sampling clock jitter is greatly improved, and the randomness of TRNG output is further improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a jitter increasing circuit and a true random number generator. Background Art

[0002] In modern cryptographic systems, the uniform distribution and unpredictability of keys, challenges, and initialization vectors directly determine the security of the entire system. The above-mentioned key data such as keys, challenges, and initialization vectors are often generated by the true random number generator (TRNG) in the system. Therefore, designing a true random number generator to generate high-quality random numbers is the key and core of information security technology.

[0003] True random numbers cannot be generated by algorithms. The bit sequences generated by algorithms are theoretically completely predictable pseudo-random numbers. In order to obtain true random numbers, TRNG usually uses circuit characteristics such as thermal noise, jitter, chaos, and metastable states as random sources, and uses a mechanism to extract entropy sources to obtain random bit streams. According to the way of extracting random numbers, TRNG design can be divided into analog TRNG and digital TRNG. In analog TRNG, some entropy sources are very complex, and the acquisition and extraction circuits consume too many hardware resources, so it is also difficult to integrate them into digital systems. In contrast, with the development of integrated circuits, digital TRNG has obvious advantages in cost, system integration, and technology portability.

[0004] At present, digital TRNG is mainly realized in chips through clock jitter and metastable design structure. Since it is difficult to obtain unbiased physical sources, metastable TRNG is usually always accompanied by serious skew (statistical imbalance between '0' and '1'), and each skew may have an adverse effect on the extracted randomness. The random number generator based on clock jitter samples the high-speed clock through a slow clock and obtains randomness by using the uncertainty of clock jitter.

[0005] At present, in order to improve its randomness, the voltage noise on the power supply is generally converted into random jitter of the sampling clock signal based on the clock jitter. However, the inventors realize that this method is only applicable to RF circuits because, in RF applications, there will be a lot of noise on the power supply, while it is difficult for general circuits to have a lot of stable noise. Therefore, when this method is used, general circuits cannot guarantee the generation of sufficient random jitter. At the same time, the existing solution only improves the randomness through power supply noise, which is relatively weak.

[0006] Figure 1 It is a commonly used true random number generator based on clock jitter. Figure 1It can be seen that the low-frequency clock samples the high-frequency clock. The frequency of the high-frequency clock is dozens or even dozens of times that of the low-frequency clock. Compared with the low-frequency clock, the high-frequency clock is jittery and uncertain, providing a basic entropy source for randomness.

[0007] like Figure 2 As shown, some designs later introduced thermal noise into the low-frequency clock to increase the jitter of the low-frequency clock, thereby increasing the randomness of the entire random number generator.

[0008] There are also circuits that convert the noise on the power supply into random jitter of the sampling clock signal in specific RF scenarios. The working principle is as follows: First, look at Figure 3 , the reversal voltage is fixed. Ideally, the voltage before discharge is also fixed Videal. However, due to the noise disturbance on the power supply, the voltage will drift up and down. The actual voltage before discharge is Vactual. The discharge rate is the same, which causes the time to reach the reversal voltage to change. There will be a △t error, which produces random jitter. See the implementation circuit for details. Figure 4 .

[0009] When CLK_IN is high, the inverter INV1 output is low, M3 is turned off, M4 is turned on, CLK_X is charged to VDD, and CLK_S output is high; when CLK_IN is low, the inverter INV1 output is high, M3 is turned on, M4 is turned off, and the charge on the capacitor CL is discharged at a constant speed. When discharged to the flip voltage V0 of INV2, CLK_S changes from high to low.

[0010] In RF circuits, there is a lot of noise on the power supply, which can cause Figure 4 The voltage of CLK_X fluctuates up and down, which causes the time to reach the INV2 flip voltage V0 to shift △t. This is the source of random jitter. Using this clock to sample the high-speed clock will get a more random output. Summary of the invention

[0011] The present application provides a jitter adding circuit and a true random number generator, aiming to solve the problem that the existing solution of generating randomness only through voltage noise is only applicable to specific scenarios of RF circuits and the generated randomness is relatively weak.

[0012] In a first aspect, a jitter increasing circuit includes a current random fluctuation module and an adjustable noise module; the current output end of the current random fluctuation module is connected to the drain and gate of a field effect tube M0, and the current random fluctuation module can generate a random current; the gate of the field effect tube M0 is connected to the gate of the field effect tube M1, and the source of the field effect tube M0 is connected to the drain of the field effect tube M2; the drain of the field effect tube M1 is grounded through a capacitor CL; the adjustable noise module is arranged next to the capacitor CL, and the noise generated by the adjustable noise module can be coupled and superimposed on the capacitor CL;

[0013] The drain of the field effect transistor M1 is connected to the drain of the field effect transistor M4, and the source of the field effect transistor M1 is connected to the drain of the field effect transistor M3; the gate of the field effect transistor M3 is connected to the gate of the field effect transistor M4; the drain of the field effect transistor M1 is connected to the high-frequency clock circuit through an inverter; the gate of the field effect transistor M3 is connected to the clock source circuit through an inverter.

[0014] In the above scheme, optionally, the current random fluctuation module includes a plurality of current source modules with random weights, each of which includes a current source module and a weight control module; the current output end of each current source module is connected to the drain and gate of the field effect transistor M0, and the control signal input end of each current source module is connected to the control signal output end of the corresponding weight control module; each weight control module is used to adjust the current output by the corresponding current source module through the output weight value.

[0015] In the above solution, further optionally, the weight control module controls the output weight value by configuring multiple groups of PUFs.

[0016] In the above scheme, further optionally, the input end of the weight control module is used to receive a pseudo-random number or a true random number, and the weight control module controls the output weight value according to the received pseudo-random number or true random number.

[0017] In the above solution, optionally, the adjustable noise module includes a multiplexer, and each input end of the multiplexer is connected to the output end of the multiplexer through a different number of inverters and a switch.

[0018] In a second aspect, a true random number generator includes the jitter adding circuit described in the first aspect, wherein the drain of the field effect transistor M1 of the jitter adding circuit is connected to the clock input terminal of the trigger D1 through an inverter; the data input terminal of the trigger D1 is connected to a high-frequency clock circuit, and the data output terminal of the trigger D1 is used to output a true random number.

[0019] In a third aspect, a true random number generator comprises the jitter adding circuit described in the first aspect, wherein the input end of the weight control module of the jitter adding circuit is connected to the output end of the current source randomness selection circuit; the first data input end of the current source randomness selection circuit is connected to the linear feedback shift register LFSR, and the second data input end of the current source randomness selection circuit is connected to the data output end of the trigger D1; the data input end of the trigger D1 is connected to a high-frequency clock circuit, and the clock input end of the trigger D1 is connected to a low-frequency clock circuit; the drain of the field effect transistor M1 of the jitter adding circuit is connected to the clock input end of the trigger D2 through an inverter; the data input end of the trigger D2 is connected to the high-frequency clock circuit, and the data output end of the trigger D2 is used to output a true random number.

[0020] Compared with the prior art, this application has at least the following beneficial effects:

[0021] The jitter increasing circuit provided in the embodiment of the present application, on the one hand, because an adjustable noise module is added next to the capacitor CL, through the coupling effect of the adjustable noise module, even if it is not on the RF chip, the noise of the power supply voltage can be generated on the ordinary chip, thereby realizing the function of increasing the random jitter of the sampling clock on the ordinary chip; on the other hand, because a current random fluctuation module is also added, a module that can provide a random current is designed, which can also convert the randomness of the current into the random jitter of the sampling clock, and finally forms an architecture in which the voltage random jitter and the current random jitter can be superimposed on the same sampling clock at the same time, so that the noise in the two dimensions of voltage and current can be superimposed, and a more random sampling clock is realized, which can greatly improve the randomness of the sampling clock jitter and thus improve the randomness of the TRNG output; compared with the case where there is no noise superposition or only the voltage noise superposition, the sampling clock of the present design has better randomness, stronger reliability, and is less likely to be cracked. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of a true random number generator based on clock jitter;

[0023] Figure 2 The schematic diagram of the true random number generation circuit based on clock jitter which introduces thermal noise;

[0024] Figure 3 Schematic diagram of converting voltage changes into clock jitter;

[0025] Figure 4 Circuit diagram for converting voltage jitter into clock jitter;

[0026] Figure 5 A schematic diagram of a jitter increasing circuit provided by one embodiment of the present application;

[0027] Figure 6 A detailed schematic diagram of a jitter increasing circuit provided by one embodiment of the present application;

[0028] Figure 7 A schematic diagram of a current source module with random weights in one embodiment of the present application;

[0029] Figure 8 This is a schematic diagram of a weight control module in one embodiment of the present application;

[0030] Fig. 9 This is a schematic diagram of an adjustable noise module in one embodiment of the present application;

[0031] Fig.10 An architectural diagram of an overall implementation of a true random number generator provided for one embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] In the description of the present application: unless otherwise specified, expressions such as “include”, “comprising”, “having”, etc. also mean “not limited to” (certain units, components, materials, steps, etc.).

[0034] In one embodiment, a jitter increasing circuit is provided, such as Figure 5 As shown, it includes a current random fluctuation module 11 and an adjustable noise module 12; the current output end of the current random fluctuation module 1 is connected to the drain and gate of the field effect tube M0, and the current random fluctuation module 1 can generate a random current; the gate of the field effect tube M0 is connected to the gate of the field effect tube M1, and the source of the field effect tube M0 is connected to the drain of the field effect tube M2; the drain of the field effect tube M1 is grounded through the capacitor CL; the adjustable noise module 2 is arranged next to the capacitor CL, and the noise generated by the adjustable noise module 2 can be coupled and superimposed on the capacitor CL;

[0035] The drain of the field effect transistor M1 is connected to the drain of the field effect transistor M4, and the source of the field effect transistor M1 is connected to the drain of the field effect transistor M3; the gate of the field effect transistor M3 is connected to the gate of the field effect transistor M4; the drain of the field effect transistor M1 is connected to the high-frequency clock circuit through an inverter; the gate of the field effect transistor M3 is connected to the clock source circuit through an inverter.

[0036] Specifically, the drain of the field effect transistor M1 is connected to the high-frequency clock circuit via the inverter INV2 and the inverter INV3 in sequence, and the gate of the field effect transistor M3 is connected to the clock source circuit via the inverter INV1.

[0037] Furthermore, if Figure 6 As shown, the current random fluctuation module 11 includes a plurality of current source modules 111 with random weights, such as Figure 7 As shown, each random weight current source module 111 includes a current source module and a weight control module; the current output end of each current source module is connected to the drain and gate of the field effect tube M0, and the control signal input end of each current source module is connected to the control signal output end of the corresponding weight control module; each weight control module is used to adjust the current output by the corresponding current source module through the output weight value, and the weight values ​​output by all weight control modules can be different.

[0038] Specifically, if Figure 8 As shown, the weight control module can control the output weight value by configuring multiple groups of PUF (physical unclonable function). Or the input end of the weight control module is used to receive a pseudo-random number or a true random number, and the weight control module controls the output weight value through the received pseudo-random number or true random number.

[0039] That is to say, for the current random source module 111 with random weight, its weight value is different. On the one hand, the weight value of each current random source module 111 with random weight can be configured by multiple groups of PUFs, which can ensure that the weight of each group of current sources in each chip is different. On the other hand, pseudo-random numbers or true random numbers can also be used to control current sources with different weights; ultimately, a current signal with randomly changing size is output.

[0040] The core of the design of the random weight current source module 111 is to generate a current signal with random variation characteristics. This process is achieved by combining multiple current sources with adjustable parameters, and the weight value of each current source is unique, which can provide randomness in the circuit. This design is crucial to increase the randomness of the sampling clock.

[0041] Furthermore, the adjustable noise module 12 comprises a multiplexer 121 , and each input end of the multiplexer is connected to an output end of the multiplexer via a different number of inverters and a switch. Fig. 9 The schematic diagram of the adjustable noise module 12 is that clocks of different frequencies are provided by setting inverter chains of different lengths. When it is placed near the CL capacitor, a fluctuating voltage can be coupled to CL through the coupling effect.

[0042] In the jitter increasing circuit provided in the embodiment of the present application, the adjustable noise module 12 generates voltage noise, which is coupled and superimposed on CL, see Figure 5 , assuming that the discharge current I2 remains unchanged, the jitter of the output CLK_S will include power supply noise.

[0043] The current source module 111 with random weights from s1, s2, s3 to sn can control the random change of the current size by inputting random numbers, so that the current I1 will change randomly, and the current I2 will also change randomly after mirroring. In this way, when the capacitor discharges, not only the discharge voltage will change to produce jitter, but the current will also change to contribute to jitter.

[0044] In other words, the current I1 of the current source module in the jitter increase circuit is mirrored to I2, and the discharge current of the CL capacitor behind it eventually forms a structure with random discharge voltage and discharge current, but the flip voltage of the inverter INV2 is relatively fixed, and the randomness of the voltage and current will be superimposed on the jitter of the output clock, and finally a sampling clock with random jitter will be output. Using this sampling clock to sample a high-frequency clock can obtain higher-quality random numbers.

[0045] The jitter increasing circuit provided in the embodiment of the present application designs a structure that can produce noise (fluctuation) similar to the power supply voltage on an ordinary chip even if it is not on the RF chip, and adds a module that can randomly fluctuate the current, so that the noise in the two dimensions of voltage and current can be superimposed, and a more random sampling clock is realized. Compared with the case where there is no noise superposition and only the noise superposition on the voltage, the sampling clock of this design has better randomness and stronger reliability.

[0046] In the jitter increasing circuit provided in the embodiment of the present application, on the one hand, since an adjustable noise module 12 is added next to the capacitor CL, the function of increasing random jitter of the sampling clock can be achieved on an ordinary chip through the coupling effect of the adjustable noise module 12. On the other hand, since a current random fluctuation module 11 is also added, a module that can provide a random current is designed, which can also convert the randomness of the current into the random jitter of the sampling clock, and finally forms a structure in which voltage random jitter and current random jitter can be superimposed on the same sampling clock at the same time, which can greatly improve the randomness of the sampling clock jitter and thus improve the randomness of the TRNG output.

[0047] The existing solution only generates randomness through voltage noise, and the generated randomness is relatively weak. The architecture of the current solution is only applicable to specific scenarios in RF circuits. The solution provided in the embodiment of the present application can also realize the function of superimposing power supply noise disturbance in ordinary circuits; the solution provided in the embodiment of the present application adds a current noise source, so that the noise is superimposed from the two dimensions of power supply and voltage, which can be used to increase randomness and make the random number output more difficult to be cracked.

[0048] In one embodiment, a true random number generator is provided, including the jitter adding circuit provided in the above embodiment, wherein the drain of the field effect transistor M1 of the jitter adding circuit is connected to the clock input terminal of the trigger D1 through an inverter; the data input terminal of the trigger D1 is connected to the high-frequency clock circuit, and the data output terminal of the trigger D1 is used to output a true random number.

[0049] In one embodiment, another true random number generator is provided, including the jitter adding circuit provided in the above embodiment, such as Fig.10 As shown, the input end of the weight control module of the jitter increasing circuit is connected to the output end of the current source randomness selection circuit; the first data input end of the current source randomness selection circuit is connected to the linear feedback shift register LFSR, and the second data input end of the current source randomness selection circuit is connected to the data output end of the trigger D1; the data input end of the trigger D1 is connected to the high-frequency clock circuit (that is, the fast clock circuit), and the clock input end of the trigger D1 is connected to the low-frequency clock circuit (that is, the slow clock circuit); the drain of the field effect transistor M1 of the jitter increasing circuit is connected to the clock input end of the trigger D2 through an inverter; the data input end of the trigger D2 is connected to the high-frequency clock circuit, and the data output end of the trigger D2 is used to output a true random number.

[0050] Fig.10 The current source randomness selection circuit selects whether to use the true random number above (random numbers are output by sampling the fast clock through the slow clock) or the pseudo-random number generated by the LFSR (Linear Feedback Shift Register) below to input the jitter increase circuit to provide randomness for the current. The jitter random circuit also includes randomness provided by voltage noise. Finally, a sampling circuit including voltage jitter and current jitter is output to sample the fast clock and output high-quality random numbers.

[0051] The embodiment of the present application increases the randomness of the jitter of the sampling slow clock and strengthens the randomness of the entropy source extraction, so that the irrelevance between the sampling slow clock and the fast clock is further enhanced, thereby realizing a true random number generator with a higher degree of confusion.

[0052] The technical features of the above embodiments may be arbitrarily combined (as long as there is no contradiction in the combination of these technical features). To make the description concise, not all possible combinations of the technical features in the above embodiments are described; these embodiments that are not explicitly written should also be considered to be within the scope of this specification.

Claims

1. A jitter increasing circuit, characterized in that: It includes a current random fluctuation module and an adjustable noise module; the current output end of the current random fluctuation module is connected to the drain and gate of the field effect tube M0, and the current random fluctuation module can generate a random current; the gate of the field effect tube M0 is connected to the gate of the field effect tube M1, and the source of the field effect tube M0 is connected to the drain of the field effect tube M2; the drain of the field effect tube M1 is grounded through a capacitor CL; the adjustable noise module is arranged next to the capacitor CL, and the noise generated by the adjustable noise module can be coupled and superimposed on the capacitor CL; The drain of the field effect transistor M1 is connected to the drain of the field effect transistor M4, and the source of the field effect transistor M1 is connected to the drain of the field effect transistor M3; the gate of the field effect transistor M3 is connected to the gate of the field effect transistor M4; the drain of the field effect transistor M1 is connected to the high-frequency clock circuit through an inverter; the gate of the field effect transistor M3 is connected to the clock source circuit through an inverter.

2. The jitter increasing circuit according to claim 1, characterized in that: The current random fluctuation module includes multiple current source modules with random weights, each of which includes a current source module and a weight control module; the current output end of each current source module is connected to the drain and gate of the field effect transistor M0, and the control signal input end of each current source module is connected to the control signal output end of the corresponding weight control module; each weight control module is used to adjust the current output by the corresponding current source module through the output weight value.

3. The jitter increasing circuit according to claim 2, characterized in that: The weight control module controls the output weight value by configuring multiple groups of PUF.

4. The jitter increasing circuit according to claim 2, characterized in that: The input end of the weight control module is used to receive a pseudo-random number or a true random number, and the weight control module controls the output weight value according to the received pseudo-random number or true random number.

5. The jitter increasing circuit according to claim 1, characterized in that: The adjustable noise module comprises a multiplexer, and each input end of the multiplexer is connected to the output end of the multiplexer through a different number of inverters and a switch.

6. A true random number generator, characterized in that: It comprises the jitter increasing circuit as claimed in claim 1, wherein the drain of the field effect transistor M1 of the jitter increasing circuit is connected to the clock input terminal of the trigger D1 through an inverter; the data input terminal of the trigger D1 is connected to a high-frequency clock circuit, and the data output terminal of the trigger D1 is used to output a true random number.

7. A true random number generator, characterized in that: It includes the jitter adding circuit as described in claim 4, the input end of the weight control module of the jitter adding circuit is connected to the output end of the current source randomness selection circuit; the first data input end of the current source randomness selection circuit is connected to the linear feedback shift register LFSR, and the second data input end of the current source randomness selection circuit is connected to the data output end of the trigger D1; the data input end of the trigger D1 is connected to the high-frequency clock circuit, and the clock input end of the trigger D1 is connected to the low-frequency clock circuit; the drain of the field effect transistor M1 of the jitter adding circuit is connected to the clock input end of the trigger D2 through an inverter; the data input end of the trigger D2 is connected to the high-frequency clock circuit, and the data output end of the trigger D2 is used to output a true random number.

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