Instruction set generation method and device and terminal equipment
By cyclically generating and randomizing the instruction parameter set, the problem of incomplete instructions of RISC-V chip is solved, and a complete vector expansion instruction set is generated to ensure the integrity and efficiency of chip performance verification.
Patent Information
- Application Number
- CN202411634677.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-11-08
- Filing Date
- 2024-11-14
- Publication Date
- 2025-03-07
AI Technical Summary
The prior art has problems with incomplete instructions when generating instructions for RISC-V chips, which leads to the inability to effectively verify the performance of the chip.
The instruction parameter set is generated by looping, and the predefined random functions and instructions are generated to generate a complete vector expansion instruction set to ensure that the instruction parameters in any two instruction parameter sets are not exactly the same.
It realizes automatic random generation and switching instruction parameter sets to generate a complete vector expansion instruction set, which can effectively verify the performance and efficiency of the chip.
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Figure CN119576411A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present application relate to the field of chip testing technology, and in particular, to a method, apparatus, and terminal device for generating an instruction set. Background Art
[0002] RISC-V Vector Extension provides a set of standard vector operation instructions to support efficient data parallel processing. The purpose of this extension is to enhance the performance and efficiency of RISC-V chips when processing complex data parallel tasks, such as multimedia processing, scientific computing, and machine learning applications.
[0003] Currently, ISG (Instruction Stream Generation) is used to generate instructions to verify RISC-V chips. This method has the problem of incomplete instruction generation. Summary of the invention
[0004] The embodiments of the present application provide a method, apparatus and terminal device for generating an instruction set, so as to solve the problem of incomplete instruction generation.
[0005] In a first aspect, an embodiment of the present application provides a method for generating an instruction set, including:
[0006] When the current generation number of the instruction parameter set is less than the preset generation number, the following steps are executed in a loop, and when the current generation number is equal to the preset generation number, the instruction set is determined;
[0007] According to a predefined random function, an instruction parameter set is randomly generated, and the instruction parameter set is the parameter required in the vector extension instruction;
[0008] Generate at least one vector extension instruction corresponding to the instruction parameter set according to a predefined instruction generation function;
[0009] Determine the current generation count of the instruction parameter set;
[0010] Among them, the instruction parameters in any two instruction parameter sets are not completely the same, and the instruction set includes: vector extension instructions corresponding to each instruction parameter set, and the instruction set is used for chip verification.
[0011] In a possible implementation, the instruction generation function includes: instruction generation sub-functions corresponding to different data types, generating at least one vector extension instruction corresponding to the instruction parameter set according to a predefined instruction generation function, including:
[0012] Obtain at least one vector extension instruction in a text format from an instruction pool, the instruction pool comprising: a plurality of vector extension instructions in a text format;
[0013] For each vector extension instruction in a text format, determining a data type of the vector extension instruction in a text format;
[0014] Generate a sub-function and an instruction parameter set according to the instruction corresponding to the data type, and convert the vector extension instruction in text format into the vector extension instruction in assembly format.
[0015] In a possible implementation, the instruction quantity of at least one vector extension instruction is random or preset.
[0016] In a possible implementation, the type of the vector extension instruction is a first type or a second type, the first type of vector extension instruction is a single instruction, and the second type of vector extension instruction is a combination of multiple instructions that have a relationship with each other to achieve a preset test purpose.
[0017] In a possible implementation, generating at least one vector extension instruction corresponding to an instruction parameter set according to a predefined instruction generation function includes:
[0018] Get instruction insertion ratio;
[0019] At least one vector extension instruction corresponding to the instruction parameter set is generated according to a predefined instruction generation function and an instruction insertion ratio, wherein, among multiple vector extension instructions in multiple instruction parameter sets, a ratio of the second type of vector extension instructions is the instruction insertion ratio.
[0020] In a possible implementation, determining the instruction set includes:
[0021] Determine the instruction set in the vector register;
[0022] The instruction set in the vector register is written into the general register, and the instruction set in the general register is used for comparison with the reference model.
[0023] In a possible implementation, the instruction set further includes: other instructions besides the vector extension instruction.
[0024] In a second aspect, an embodiment of the present application provides a device for generating an instruction set, the device comprising:
[0025] The first determination module: when the current generation number of the instruction parameter set is less than the preset generation number, the following steps are executed in a loop, and when the current generation number is equal to the preset generation number, the instruction set is determined;
[0026] A first generating module is used to randomly generate an instruction parameter set according to a predefined random function, where the instruction parameter set is a parameter required in a vector extension instruction;
[0027] A second generating module, configured to generate at least one vector extension instruction corresponding to the instruction parameter set according to a predefined instruction generating function;
[0028] A second determination module, used to determine the current generation number of instruction parameter sets;
[0029] Among them, the instruction parameters in any two instruction parameter sets are not completely the same, and the instruction set includes: vector extension instructions corresponding to each instruction parameter set, and the instruction set is used for chip verification.
[0030] In a third aspect, the present application provides a chip having a computer program stored thereon, and when the computer program is executed by the chip, the method as described in any one of the first aspects is implemented.
[0031] In a fourth aspect, the present application provides a chip module having a computer program stored thereon. When the computer program is executed by the chip module, the method of any one of the first aspects is implemented.
[0032] In a fifth aspect, an embodiment of the present application provides a terminal device, including:
[0033] at least one processor; and
[0034] a memory communicatively connected to at least one processor; wherein,
[0035] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor to enable the at least one processor to perform any method of the first aspect.
[0036] In a sixth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute any one of the methods in the first aspect.
[0037] In a seventh aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements any method in the first aspect when executed by a processor.
[0038] The method for generating an instruction set provided by an embodiment of the present application includes: when the current number of times the instruction parameter set is generated is less than the preset number of times, the following steps are executed in a loop, and when the current number of times the instruction parameter set is generated is equal to the preset number of times the instruction set is determined; according to a predefined random function, the instruction parameter set is randomly generated, and the instruction parameter set is the parameter required in the vector extension instruction; according to the predefined instruction generation function, at least one vector extension instruction corresponding to the instruction parameter set is generated; the current number of times the instruction parameter set is generated is determined; wherein the instruction parameters in any two instruction parameter sets are not exactly the same, and the instruction set includes: the vector extension instruction corresponding to each instruction parameter set, and the instruction set is used for chip verification. The present application can realize automatic random generation and switching of instruction parameter sets, generate vector extension instructions in different instruction parameter sets, realize traversal of different instruction parameters, and generate complete vector extension instructions. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present application;
[0040] Figure 2 A flowchart of a method for generating an instruction set provided in an embodiment of the present application;
[0041] Figure 3 A schematic diagram of a device for generating an instruction set provided in an embodiment of the present application;
[0042] Figure 4 A flowchart of another method for generating an instruction set provided in an embodiment of the present application;
[0043] Figure 5 A schematic diagram of a terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0044] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0045] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0046] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.
[0047] RISC-V Vector Extension is the stabilization and standardization of the instruction set for extended vectors, providing a set of standard vector operation instructions to support efficient data parallel processing. The purpose of RISC-V Vector Extension is to enhance the performance and efficiency of RISC-V chips when processing complex data parallel tasks, such as multimedia processing, scientific computing, and machine learning applications. In the related technology, instructions are generated based on the open source project ISG (Instruction Stream Generation). There are some problems with the instructions generated in this way, such as incorrect instructions and incomplete instructions, which result in the generated instructions being unable to pass the comparison with the reference model and the inability to implement the traversal of instruction parameters, resulting in only one instruction being verified at a time when the chip is verified, resulting in the inability to verify the performance of the chip in different scenarios.
[0048] Based on the above problems, the present application provides an instruction set generation method, which can realize automatic random generation of instruction parameter sets, and can switch instruction parameter sets, traverse different instruction parameters, generate complete vector extension instructions, and generate an instruction set including multiple vector extension instructions. It can verify multiple instructions for the chip each time, and can also verify the performance of the chip in different scenarios.
[0049] For ease of understanding, below, combined Figure 1 , the application scenarios to which the embodiments of the present application are applicable are described.
[0050] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of the present application. Figure 1, including an instruction set generation device 11 and a RISC-V chip 12, wherein the instruction set generation device 11 is used to generate an instruction set, and the instruction set is used to verify the RISC-V chip 12. RISC-V is an open source instruction set architecture based on the reduced instruction set (RISC) principle.
[0051] The method shown in the present application is described below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be described repeatedly in different embodiments.
[0052] Figure 2 A flowchart of a method for generating an instruction set provided in an embodiment of the present application. Figure 2 , the method may include:
[0053] S201, randomly generating an instruction parameter set according to a predefined random function.
[0054] Among them, the instruction parameter set is the parameters required in the vector extension instruction.
[0055] In the embodiments of this application, refer to Figure 3 The instruction set generation device includes: an operation module, a control module, a first generation module and a second generation module.
[0056] Among them, the running module can be named: RISC-V_instr_base_test, RISC-V_instr_base_test can be used as the top layer of the instruction set generation device, and is used to run other modules (running module, first generation module and second generation module) in the instruction set generation device.
[0057] Further, the control module may be named: RISC-V_asm_program_gen. The first generation module may be named: gen_config. The first generation module includes: a parameter generation unit. The parameter generation unit may be named: vector_config.
[0058] In an embodiment of the present application, a predefined random function is written into the parameter generation unit, and the parameter generation unit controls the random generation of the vector extension instructions required in the vector extension instructions based on the predefined random function. Each instruction parameter set represents different functional scenarios, such as the number of vector register combinations, the length of a single vector, the tail of the vector and how to handle the masked parts, etc.
[0059] Furthermore, the instruction parameter set includes at least one instruction parameter, such as vtype, vstart or vl. Among them, the vtype parameter is a parameter for grouping vector extension instructions in RISC-V vector extension. The lower 8-bit value includes vlmul (the number of registers that make up the vector register group), vsew (the number of bits of each vector), vta (the processing method for the tail vector), and vma (the processing method for the mask vector). The vstart parameter is an important configuration parameter in RISC-V vector extension. It is used to define which instruction to start writing when re-executing the vector extension instruction if the vector extension instruction is interrupted during execution. The vl parameter defines the number of elements operated on each time by a vector extension instruction.
[0060] In addition, the instruction parameter set may also include parameters required by other vector extension instructions, which are not limited here.
[0061] S202: Generate at least one vector extension instruction corresponding to an instruction parameter set according to a predefined instruction generation function.
[0062] Among them, refer to Figure 3 A predefined instruction generation function is written into the second generation module. The control module can control the instruction parameter set generated by the first generation module to be input into the second generation module, and then call the second generation module to generate a vector extension instruction based on the predefined instruction generation function and the instruction parameter set.
[0063] In addition, the vector extension instruction can be called a V extension instruction. Among them, since the vector extension instruction needs to be controlled by various instruction parameters (such as vtype, vstart or vl), the instruction parameters are used to impose a large number of constraints on the vector extension instruction to ensure that under the corresponding instruction parameter sets, a vector extension instruction that complies with the provisions of the vector extension instruction protocol will be generated.
[0064] Wherein, the instruction quantity of at least one vector extension instruction is random or preset.
[0065] It can be understood that when the number of instructions is preset, a modifiable parameter is preset (the parameter is the number of instructions), for example, the instruction is 100, and there is also an optional parameter (the optional parameter is the instruction parameter set), and there is also a parameter (the number of instruction parameter sets), for example, the number of instruction parameter sets is 100, so that multiple instruction parameter sets generate a total of 100×100 vector extension instructions.
[0066] In one embodiment, the type of vector extension instruction is the first type or the second type, the first type of vector extension instruction is a single instruction, and the second type of vector extension instruction is a combination of multiple instructions that have a relationship with each other to achieve a preset test purpose. It can be understood that the first type of vector extension instruction includes: an instruction, which can achieve a task by executing it alone, for example, an addition instruction can achieve an addition task. The second type of vector extension instruction includes: multiple instructions, which need to be coordinated to achieve a task, for example, an instruction to obtain an address and a load instruction can achieve a task to obtain data.
[0067] The second type of vector extension instructions include: load / store type instructions with various preconditions (such as address size, different ground access methods), wherein the load / store type instructions refer to load type instructions and / or store type instructions (load / store instructions). When data needs to be obtained, an instruction to obtain the address is required to locate the address of the data, and then a load instruction is required to obtain the data at the address.
[0068] Furthermore, after generating the vector extension instruction, the second generation module classifies the generated vector extension instruction according to the first type and the second type.
[0069] In one embodiment, at least one vector extension instruction corresponding to an instruction parameter set is generated according to a predefined instruction generation function, including: obtaining an instruction insertion ratio; generating at least one vector extension instruction corresponding to the instruction parameter set according to the predefined instruction generation function and the instruction insertion ratio, wherein, among multiple vector extension instructions in multiple instruction parameter sets, the ratio of the second type of vector extension instructions is the instruction insertion ratio.
[0070] It is understandable that the ratio of the second type of vector extension instructions included in the multiple vector extension instructions of the multiple instruction parameter sets can be set. For example, the preset instruction insertion ratio is 10 second type of vector extension instructions for every 1,000 vector extension instructions. If 100 instruction parameter sets generate 10,000 vector extension instructions corresponding to the generation of 10,000 vector extension instructions, then 9,900 first type of vector extension instructions and 100 second type of vector extension instructions are included. Among them, the second type of vector extension instructions are randomly generated in all vector extension instructions.
[0071] S203, determining the current generation count of the instruction parameter set.
[0072] In the embodiments of this application, refer to Figure 3The control module is used to control the preset number of times the instruction parameter set is generated, and the number of vector extension instructions generated corresponding to each instruction parameter set. Then the control module is used to call the first generation module to generate the instruction parameter set according to the preset number of times, and each time the first generation module is called, one instruction parameter set is generated. For example, if the preset number of times of generation is N, and N is a positive integer, then the first generation module needs to be called N times to generate N instruction parameter sets.
[0073] Wherein, each time S201 and S202 are executed, the number of times the instruction parameter set is generated is recorded.
[0074] It can be understood that the number of instruction parameter sets currently generated is the same as the current generation number.
[0075] S204, determining whether the current generation number is less than the preset generation number.
[0076] If yes, execute S201, if no, execute S205.
[0077] For example, if the preset generation number of the instruction parameter set is 3 and the current generation number is 2, execute S201 and S202; if the current generation number is 3, execute S205.
[0078] The present application can realize random generation of instruction parameter sets, and switch instruction parameter sets to generate vector extension instructions under different instruction parameter sets.
[0079] S205, determine the instruction set.
[0080] Among them, the instruction parameters in any two instruction parameter sets are not completely the same, and the instruction set includes: vector extension instructions corresponding to each instruction parameter set, and the instruction set is used for chip verification.
[0081] It can be understood that when generating multiple instruction parameter sets, the instruction parameters in any two instruction parameter sets are not completely the same. For example, three instruction parameter sets are included, wherein instruction parameter set a1 includes instruction parameters vtype 0, vstart 0, or vl 0. Instruction parameter set a2 includes instruction parameters vtype 0, vstart 1, or vl 1. Instruction parameter set a3 includes instruction parameters vtype 1, vstart 2, or vl 3.
[0082] In one embodiment, the instruction set further includes: other instructions other than vector extension instructions. Among them, other instructions include: non-extension instructions and / or other extension instructions other than V instructions. If other instructions are instructions generated by ISG, the error instructions generated by ISG can be modified and mixed with the vector extension instructions to obtain an instruction set, which is used for chip verification to ensure the completeness of the instructions.
[0083] Furthermore, the instruction set can be used for verification of RISC-V chips.
[0084] In the embodiments of the present application, it is possible to automatically and randomly generate instruction parameter sets, switch instruction parameter sets, traverse different instruction parameters, generate complete vector extension instructions, and generate instruction sets including multiple vector extension instructions. It is possible to verify multiple instructions for the chip each time, and to verify the performance of the chip in different scenarios.
[0085] Figure 4 A flowchart of a method for generating an instruction set provided in an embodiment of the present application. Figure 4 , the method may include:
[0086] S401, randomly generating an instruction parameter set according to a predefined random function.
[0087] The specific implementation process of this step refers to S201 and will not be repeated here.
[0088] S402: Obtain at least one vector extension instruction in a text format from an instruction pool.
[0089] The instruction pool includes: a plurality of vector extension instructions in text format. In the embodiment of the present application, the instruction pool includes: vector extension instructions in various text formats supported by the V extension instruction.
[0090] S403: for each vector extension instruction in a text format, determine a data type of the vector extension instruction in a text format.
[0091] In an embodiment of the present application, the instruction generation function includes: instruction generation sub-functions corresponding to different data types.
[0092] Among them, refer to Figure 3 The second generation module includes: a plurality of units, namely RISC-V_instr, RISC-V_floating_point_instr and RISC-V_vector_instr. RISC-V_instr predefines vector extension instructions in text format of various data types, and these vector extension instructions in text format are finally converted into vector extension instructions in assembly format.
[0093] For example, a data type refers to a data type that constitutes a vector extension instruction. For example, a vector extension instruction of one of the data types consists of an instruction name, a vd register (destination register), a VS1 register (first source register), a VS2 register (second source register) and a vm (mask value).
[0094] In the embodiment of the present application, the data type of each text-formatted vector extension instruction in the instruction pool is defined in RISC-V_instr.
[0095] Furthermore, RISC-V_floating_point_instr, in addition to inheriting RISC-V_instr, refers to converting the vector extension instruction in text format into floating point format, and the specific content is not limited to this.
[0096] S404, generating a sub-function and an instruction parameter set according to the instruction corresponding to the data type, and converting the vector extension instruction in the text format into the vector extension instruction in the assembly format.
[0097] Reference Figure 3 RISC-V_vector_instr inherits various parameters defined by RISC-V_floating_point_instr and RISC-V_instr, which are configured in the instruction generation sub-function. RISC-V_vector_instr defines instruction generation sub-functions corresponding to different data types.
[0098] In the embodiment of the present application, each data type corresponds to an instruction generation sub-function. For example, the instruction pool includes 400 vector extension instructions in text format, and these 400 vector extension instructions in text format have 100 data types and correspond to 100 instruction generation sub-functions.
[0099] It can be understood that for each vector extension instruction in text format, an instruction generation sub-function corresponding to the data type of the vector extension instruction in text format is used to generate the vector extension instruction in assembly format using an instruction parameter set.
[0100] Furthermore, RISC-V_vector_instr is also used to classify all generated vector extension instructions in assembly format to obtain vector extension instructions in assembly format of the first type and vector extension instructions in assembly format of the second type.
[0101] The RISC-V_vector_instr unit also defines the processing methods for different types of load / store instructions (such as unit, index or stride), and the specific processing method is not limited here.
[0102] S405, determining the current generation count of the instruction parameter set.
[0103] S406, determining whether the current generation number is less than the preset generation number.
[0104] If yes, execute S401, if no, execute S407.
[0105] The specific implementation process of S405 and S406 refers to S203 and S204, which will not be repeated here.
[0106] S407, determine the instruction set in the vector register.
[0107] In the embodiment of the present application, a vector extension instruction is generated in a vector general purpose register (VGPR).
[0108] S408, writing the instruction set in the vector register into the general register.
[0109] Among them, the instruction set in the general register is used to compare with the reference model to achieve chip verification.
[0110] In the embodiment of the present application, the instruction set in the general register can be directly used for comparison with the reference model.
[0111] In summary, from the perspective of chip development, the core of the CPU (Central Processing Unit) chip is the kernel, and the kernel is decomposed to the bottom layer in the form of operation codes converted from the instruction set. For chips with newly emerging vector extension protocols, a large number of complex tests are required to ensure the correctness of the kernel. This application uses a method of randomly switching to generate vector extension instructions, which ensures that instruction parameter sets can be generated randomly in large quantities and can cover various complex functional scenarios, thereby ensuring the completeness of vector extension instructions, thereby greatly improving the completeness and efficiency of chip verification.
[0112] The execution subject of the embodiment of the present application may be a terminal device, or a chip, chip module or wireless access device set in the terminal device. The wireless access device may be implemented by software, or by a combination of software and hardware. The terminal device may be a mobile phone, a tablet computer, etc.
[0113] Figure 5 This is a schematic diagram of the structure of the terminal device provided in the embodiment of the present application. Figure 5 The terminal device 50 may include: a memory 51 and a processor 52. Exemplarily, the memory 51 and the processor 52 are interconnected via a bus 53.
[0114] The memory 51 is used to store program instructions;
[0115] The processor 52 is used to execute the program instructions stored in the memory, so as to enable the terminal device 50 to execute the method shown in the above method embodiment.
[0116] The terminal device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.
[0117] An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the above method.
[0118] The embodiment of the present application may also provide a computer program product, including a computer program, which can implement the above method when executed by a processor.
[0119] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM), flash memory, hard disk, solid state drive, magnetic tape, floppy disk, optical disc and any combination thereof.
[0120] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0121] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0122] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0123] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
[0124] In the present application, the term "include" and its variations may refer to non-restrictive inclusion; the term "or" and its variations may refer to "and / or". The terms "first", "second", etc. in the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In the present application, "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previously associated objects are in an "or" relationship.
Claims
1. A method for generating an instruction set, characterized in that: include: When the current generation number of the instruction parameter set is less than the preset generation number, the following steps are executed in a loop, and when the current generation number is equal to the preset generation number, the instruction set is determined; Randomly generate an instruction parameter set according to a predefined random function, wherein the instruction parameter set is a parameter required in a vector extension instruction; Generate at least one vector extension instruction corresponding to the instruction parameter set according to a predefined instruction generation function; Determine the current generation count of the instruction parameter set; Among them, the instruction parameters in any two instruction parameter sets are not completely the same, and the instruction set includes: vector extension instructions corresponding to each instruction parameter set, and the instruction set is used for chip verification.
2. The method for generating an instruction set according to claim 1, characterized in that: The instruction generation function includes: instruction generation sub-functions corresponding to different data types, and generating at least one vector extension instruction corresponding to the instruction parameter set according to the predefined instruction generation function, including: Obtaining at least one vector extension instruction in a text format from an instruction pool, the instruction pool comprising: a plurality of vector extension instructions in a text format; For each vector extension instruction in a text format, determining a data type of the vector extension instruction in the text format; According to the instruction generation sub-function corresponding to the data type and the instruction parameter set, the vector extension instruction in the text format is converted into the vector extension instruction in the assembly format.
3. The method for generating an instruction set according to claim 1 or 2, characterized in that: The instruction quantity of the at least one vector extension instruction is random or preset.
4. The method for generating an instruction set according to claim 3, characterized in that: The type of the vector extension instruction is a first type or a second type. The first type of vector extension instruction is a single instruction, and the second type of vector extension instruction is a combination of multiple instructions that have a relationship with each other to achieve a preset test purpose.
5. The method for generating an instruction set according to claim 4, characterized in that: The generating, according to a predefined instruction generation function, at least one vector extension instruction corresponding to the instruction parameter set comprises: Get instruction insertion ratio; At least one vector extension instruction corresponding to the instruction parameter set is generated according to a predefined instruction generation function and the instruction insertion ratio, wherein, among multiple vector extension instructions of multiple instruction parameter sets, the ratio of the second type of vector extension instructions is the instruction insertion ratio.
6. The method for generating an instruction set according to claim 1 or 2, characterized in that: The determining instruction set comprises: determining the instruction set in a vector register; The instruction set in the vector register is written into a general register, and the instruction set in the general register is used for comparison with a reference model.
7. The method for generating an instruction set according to claim 1 or 2, characterized in that: The instruction set also includes: other instructions besides the vector extension instruction.
8. A device for generating an instruction set, characterized in that: The device comprises: Control module: when the current generation number of the instruction parameter set is less than the preset generation number, loopingly executing the following steps, and when the current generation number is equal to the preset generation number, determining the instruction set; A first generating module, used for randomly generating an instruction parameter set according to a predefined random function, wherein the instruction parameter set is a parameter required in a vector extension instruction; A second generating module, configured to generate at least one vector extension instruction corresponding to the instruction parameter set according to a predefined instruction generating function; The control module is further used to determine the current generation number of the instruction parameter set; Among them, the instruction parameters in any two instruction parameter sets are not completely the same, and the instruction set includes: vector extension instructions corresponding to each instruction parameter set, and the instruction set is used for chip verification.
9. A terminal device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.
10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: in, The computer instructions are used to make a computer execute the method according to any one of claims 1 to 7.
11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.