A branch instruction conversion optimization method based on conditional execution mechanism

Abstract

The present invention discloses a branch instruction conversion optimization method based on a conditional execution mechanism. When executing an executable file in a dynamic instruction conversion mode, the x86 architecture branch instruction is analyzed to determine the related pre-instructions and jump entry instructions, the instruction set required to be executed after the jump is determined according to the jump entry instruction, and then the instruction conversion mode is determined according to the number of instructions included in the instruction set, so as to complete the conversion of the x86 architecture branch instruction to the ARM conditional execution instruction, reduce the performance loss of the processor pipeline refresh caused by the branch jump after the conversion, and expand the applicability of the program running on different hardware platforms.

Description

Technical Field

[0001] The invention belongs to the technical field of computer software development, and in particular relates to a branch instruction conversion optimization method based on a conditional execution mechanism. Background Art

[0002] Branch instructions under the existing x86 architecture will cause the processor's pipeline to be refreshed. Specifically, when executing a branch instruction, the processor usually tries to predict whether the branch will be executed. If the prediction is correct, the pipeline can continue to execute smoothly. Conversely, if the prediction is wrong, the pipeline needs to be cleared and refilled, which will lead to performance degradation. Among them, branch instructions under the x86 architecture include unconditional branch instructions JMP, conditional branch instructions JE and JNE based on flag bits, etc. For example, in a simple loop structure, if the branch conditions of each loop are mostly the same, then the processor may make correct predictions based on historical records, but if the branch conditions are more random, then the probability of misprediction will increase significantly.

[0003] When dynamically converting x86 architecture instructions to ARM architecture instructions, the existing conversion method can only directly map the branch instructions of the x86 architecture to the branch instructions of the ARM architecture. However, due to the different branch prediction mechanisms of ARM processors and Intel processors, direct mapping increases the probability of branch prediction errors, which will lead to a decrease in code execution efficiency. Therefore, in the process of converting x86 architecture instructions to ARM architecture instructions, how to improve the execution efficiency of the converted x86 architecture branch instructions becomes a technical problem that needs to be solved. Summary of the invention

[0004] In view of this, the present invention provides a branch instruction conversion optimization method based on conditional execution mechanism, which realizes the conversion of x86 architecture branch instructions to ARM conditional execution instructions by analyzing x86 architecture branch instructions to determine their related pre-instructions and jump entry instructions.

[0005] The present invention provides a branch instruction conversion optimization method based on a conditional execution mechanism, which specifically includes the following steps:

[0006] Step 1: Load the executable file through dynamic instruction conversion to obtain the current instruction to be converted;

[0007] Step 2: If the current instruction to be converted is an unconditional branch instruction in the x86 architecture, the operand of the current instruction to be converted is obtained and recorded as the first operand, and step 3 is executed; if it is a conditional branch instruction, the operand of the current instruction to be converted is obtained and recorded as the second operand, and step 4 is executed; if it is a non-conditional branch instruction, the current instruction to be converted is converted into an ARM instruction and then step 12 is executed;

[0008] Step 3, record the ARM architecture unconditional jump instruction with the same function as the current instruction to be converted as the first ARM instruction, use the first operand as the operand of the first ARM instruction, convert the current instruction to be converted into the first ARM instruction, and execute step 12;

[0009] Step 4, record the flag bit in the flag register related to the current instruction to be converted as the first flag bit, record the instruction that modifies the first flag bit that is located before the current instruction to be converted and is closest to it as the first preceding instruction, and convert the first preceding instruction into the first ARM preceding instruction; obtain the jump entry instruction according to the second operand, and form a first instruction set from the jump entry instruction to the next branch instruction and the jump entry instruction. If the first instruction set contains only one instruction, execute step 5, otherwise execute step 6;

[0010] Step 5, record the ARM instruction with the same function as the jump entry instruction as the second ARM instruction, and the ARM architecture condition code determined according to the current instruction to be converted as the first condition code; use the first condition code as a suffix of the second ARM instruction to form a first conditional ARM instruction, convert the current instruction to be converted and the jump entry instruction into the first conditional ARM instruction, and then execute step 12;

[0011] Step 6, traverse the instructions in the first instruction set, convert the current instruction into an ARM instruction with the same function and record it as the current ARM instruction, if the operand register of the current ARM instruction is the operand register of the first ARM prefix instruction, execute step 7; otherwise, execute step 10;

[0012] Step 7, re-execute register mapping for the current ARM instruction. If the mapping is successful, use the new register as the operand of the current ARM instruction, and execute step 8 when the current ARM instruction is the first instruction in the first instruction set, and execute step 11 when it is not the first instruction; if the mapping fails, add the first ARM prefix instruction after the current ARM instruction, and execute step 9 when the current ARM instruction is the first instruction in the first instruction set, and execute step 11 when it is not the first instruction;

[0013] Step 8, according to the ARM architecture condition code determined by the current instruction to be converted as the second condition code, the second condition code is used as the suffix of the current ARM instruction to form a second conditional ARM instruction, the current instruction to be converted and the jump entry instruction are converted into the second conditional ARM instruction, and step 11 is executed;

[0014] Step 9, according to the ARM architecture condition code determined by the current instruction to be converted as the third condition code, the third condition code is used as the suffix of the current ARM instruction to form a third conditional ARM instruction, the current instruction to be converted and the jump entry instruction are converted into an instruction sequence consisting of the third conditional ARM instruction and the first ARM prefix instruction, and step 11 is executed;

[0015] Step 10, if the current ARM instruction is the first instruction in the first instruction set, the ARM architecture condition code determined according to the current instruction to be converted is the fourth condition code, the fourth condition code is used as a suffix of the current ARM instruction to form a fourth conditional ARM instruction, the current instruction to be converted and the jump entry instruction are converted into the fourth conditional ARM instruction, and then step 11 is executed; otherwise, step 11 is directly executed;

[0016] Step 11: If there are unprocessed instructions in the first instruction set, execute step 6; otherwise, execute step 12;

[0017] Step 12: Save the converted ARM instruction to the output instruction queue. If the executable file has not been loaded, select the next instruction as the current instruction to be converted to execute step 2. Otherwise, execute the output instruction queue to complete the execution of the executable file and end this process.

[0018] Furthermore, the first operand and the second operand are both jump address offsets.

[0019] Furthermore, in step 12, before executing the output instruction queue, redundant instructions in the output instruction queue are deleted.

[0020] Furthermore, the method of deleting redundant instructions in the output instruction queue is: traversing the output instruction queue, searching for and deleting redundant instructions with the same execution effect; searching for all registers involved in the output instruction queue, and deleting the load and store instructions related to unused registers.

[0021] Furthermore, the ARM architecture conditional codes include EQ, NE, GT, LT, GE and LE.

[0022] Furthermore, the instruction type of the current instruction to be converted is identified by obtaining an operation code of the current instruction to be converted.

[0023] Furthermore, in the step 4, the first preceding instruction is a comparison instruction of the x86 architecture.

[0024] Furthermore, the first ARM prefix instruction is a comparison instruction of the ARM architecture. Beneficial Effects

[0025] When executing an executable file in a dynamic instruction conversion manner, the present invention analyzes the x86 architecture branch instruction to determine the related preceding instructions and jump entry instructions, determines the instruction set to be executed after the jump according to the jump entry instruction, and then determines the instruction conversion method according to the number of instructions included in the instruction set, thereby completing the conversion of the x86 architecture branch instruction to the ARM conditional execution instruction, reducing the performance loss of the processor pipeline refresh caused by the branch jump after the conversion, and expanding the applicability of the program to run on different hardware platforms. DETAILED DESCRIPTION

[0026] The present invention is described in detail with reference to the following embodiments.

[0027] The existing ARM architecture provides an important feature, namely conditional execution, which allows instructions to be executed based on specific conditions. In the currently commonly used non-conditional execution mode, the processor will execute each instruction in turn, while in the conditional execution mode of ARM, the execution of certain instructions depends on the satisfaction of specific conditions. This feature can reduce the use of branch instructions, thereby improving the execution efficiency and performance of the code. Therefore, according to the characteristics of the ARM instruction set, the present invention proposes a method for optimizing branch prediction and conditional execution during the conversion process, so as to make full use of the characteristics of the ARM instruction set and improve the execution performance of the generated ARM instructions.

[0028] The present invention provides a branch instruction conversion optimization method based on a conditional execution mechanism, the core idea of ​​which is: when executing an executable file in a dynamic instruction conversion manner, the x86 architecture branch instruction is analyzed to determine the related preceding instructions and jump entry instructions, the instruction set to be executed after the jump is determined according to the jump entry instruction, and then the instruction conversion method is determined according to the number of instructions included in the instruction set, thereby completing the conversion of the x86 architecture branch instruction to the ARM conditional execution instruction.

[0029] The present invention provides a branch instruction conversion optimization method based on a conditional execution mechanism, which specifically includes the following steps:

[0030] Step 1: Load the executable file through dynamic instruction conversion to obtain the current instruction to be converted.

[0031] Step 2. If the current instruction to be converted is an unconditional branch instruction in the x86 architecture, obtain the operand of the current instruction to be converted and record it as the first operand, and execute step 3; if the current instruction to be converted is a conditional branch instruction in the x86 architecture, obtain the operand of the current instruction to be converted and record it as the second operand, and execute step 4; if the current instruction to be converted is a non-conditional branch instruction in the x86 architecture, convert the current instruction to be converted into an ARM instruction and then execute step 12.

[0032] In the present invention, the instruction type is identified by acquiring the operation code of the current instruction to be converted. For example, the operation code of the JE instruction is 0x74, and the operation code of the JMP instruction is 0xE9 or 0xEB.

[0033] The first operand and the second operand are both jump address offsets.

[0034] Step 3: Select an unconditional jump instruction of the ARM architecture with the same function as the current instruction to be converted, record it as the first ARM instruction, use the first operand as the operand of the first ARM instruction, convert the current instruction to be converted into the first ARM instruction, and execute step 12.

[0035] Step 4. Determine the flag bit in the flag register associated with the current instruction to be converted, and record it as the first flag bit; obtain the instruction that modifies the first flag bit and is located before the current instruction to be converted and closest to the current instruction to be converted, and record it as the first predecessor instruction; record the ARM instruction converted by the first predecessor instruction as the first ARM predecessor instruction, record the operands of the first ARM predecessor instruction as the first predecessor operand and the second predecessor operand, and record the execution result of the first ARM predecessor instruction as the first result information; obtain the jump entry instruction to be executed after the jump according to the second operand, and the first instruction set is composed of the instructions from the jump entry instruction to the next branch instruction and the jump entry instruction. If the first instruction set contains only one instruction, execute step 5, otherwise execute step 6.

[0036] Step 5. Determine an ARM instruction in the ARM architecture that has the same function as the jump entry instruction, and record it as the second ARM instruction; determine the condition code in the ARM architecture according to the function of the current instruction to be converted, and record it as the first condition code; use the first condition code as a suffix of the second ARM instruction to form a first conditional ARM instruction, convert the current instruction to be converted and the jump entry instruction into the first conditional ARM instruction, and then execute step 12.

[0037] Step 6, traverse the instructions in the first instruction set, convert the current instruction into an ARM instruction with the same function and record it as the current ARM instruction. If the operand register of the current ARM instruction is the operand register of the first ARM prefix instruction, execute step 7; otherwise, execute step 10.

[0038] Step 7, re-execute register mapping for the current ARM instruction. If the mapping is successful, the operand register of the current ARM instruction is mapped to a register different from the operand register of the first ARM prefix instruction, and the newly mapped register is used as the new operand of the current ARM instruction. When the current ARM instruction is the first instruction in the first instruction set, step 8 is executed, and when it is not the first instruction, step 11 is executed. If the mapping fails, the first ARM prefix instruction is added after the current ARM instruction. When the current ARM instruction is the first instruction in the first instruction set, step 9 is executed, and when it is not the first instruction, step 11 is executed.

[0039] Step 8, determine the condition code in the ARM architecture according to the function of the current instruction to be converted and record it as the second condition code; use the second condition code as a suffix of the current ARM instruction to form a second conditional ARM instruction, convert the current instruction to be converted and the jump entry instruction into the second conditional ARM instruction, and execute step 11.

[0040] Step 9, determine the condition code in the ARM architecture according to the function of the current instruction to be converted and record it as the third condition code; use the third condition code as a suffix of the current ARM instruction to form a third conditional ARM instruction, convert the current instruction to be converted and the jump entry instruction into an instruction sequence consisting of the third conditional ARM instruction and the first ARM prefix instruction, and execute step 11.

[0041] Step 10. If the current ARM instruction is the first instruction in the first instruction set, the condition code in the ARM architecture is determined according to the function of the current instruction to be converted and recorded as the fourth condition code. The fourth condition code is used as a suffix of the current ARM instruction to form a fourth conditional ARM instruction. The current instruction to be converted and the jump entry instruction are converted into the fourth conditional ARM instruction, and then step 11 is executed; otherwise, step 11 is executed directly.

[0042] Step 11: If there are unprocessed instructions in the first instruction set, execute step 6; otherwise, execute step 12.

[0043] Step 12: Save the converted ARM instruction to the output instruction queue. If the executable file has not been loaded, select the next instruction as the current instruction to be converted to execute step 2. Otherwise, execute the output instruction queue to complete the execution of the executable file and end this process.

[0044] In order to further improve the execution efficiency of the converted code, ensure the consistency of the semantics of the code before and after the conversion, and improve the quality and efficiency of cross-architecture instruction conversion, the present invention optimizes all ARM instructions in the output instruction queue to remove redundant instructions so that the instruction queue can better meet the pipeline execution characteristics of the ARM processor. The specific method is: traverse the output instruction queue, find and delete redundant instructions with the same execution effect; find all registers involved in the output instruction queue, and delete the load and store instructions related to the unused registers. Example

[0045] In this embodiment, a branch instruction conversion optimization method based on a conditional execution mechanism provided by the present invention is adopted to realize the conversion of x86 instructions to ARM instructions, including the following steps:

[0046] S1. Analyze and identify branch instructions during the binary instruction parsing stage.

[0047] Parse the input x86 instruction stream instruction by instruction. Identify the branch instructions, such as the common unconditional jump instruction JMP, jump if equal instruction JE, jump if not equal instruction JNE, jump if greater than instruction JG, jump if greater than or equal to instruction JGE, and other conditional jump instructions and their related operands and jump target addresses. At the same time, record the comparison instructions used to set the judgment conditions before the branch instruction, such as the comparison instruction CMP, the registers involved, and the comparison relationship.

[0048] For other non-branch related instructions in the x86 instructions, they are initially converted into corresponding ARM instruction forms according to conventional register mapping, opcode conversion and other rules, and the converted ARM instructions are temporarily stored in the output instruction queue.

[0049] For the following x86 instruction code snippet example:

[0050] MOV eax, 5

[0051] MOV ebx, 6

[0052] CMP eax, ebx

[0053] JE equal_label

[0054] MOV ecx, 0

[0055] JMP end_label

[0056] equal_label:

[0057] MOV ecx, 1

[0058] end_label:

[0059] During the instruction parsing stage: identify CMP as a comparison instruction, JE as a conditional jump instruction, and the instruction blocks corresponding to the subsequent different execution branches, that is, the parts where MOV ecx, 0 and MOV ecx, 1 are located. At the same time, perform preliminary ARM conversion on non-branch related instructions such as MOV, assuming that the register mapping eax corresponds to R0, ebx corresponds to R1, and ecx corresponds to R2. Temporarily store the converted instructions such as MOV R0, #5 in the output instruction queue.

[0060] S2. Perform conditional analysis and replace ARM conditional execution instructions.

[0061] For each identified x86 branch instruction and its preceding comparison instruction, if it is an unconditional jump instruction, such as JMP, S2.1 is executed; if it is a conditional jump instruction, S2.2 is executed.

[0062] S2.1. Analyze the jump target address. In the ARM instruction system, a similar jump function can be implemented by modifying the program counter PC register, converting it into a suitable relative jump or absolute jump ARM instruction form, such as the B instruction for relative jump, etc., and adding it to the output instruction queue.

[0063] S2.2, ARM processors use condition codes to determine whether instructions are executed. In the ARM instruction set, the encoding of each instruction contains a 4-bit condition code field, which specifies the conditions that need to be met for the instruction to execute. Common condition codes, such as EQ for equality, NE for inequality, GT for greater than, and LT for less than, are based on the processor's status flags, such as the Z flag to indicate whether the result is zero, to determine whether the condition is met, and then determine whether the instruction is executed. This is different from the implementation mechanism of x86, which relies on conditional branches to make jump decisions, but it can be converted through certain rules to achieve equivalent functions.

[0064] The core idea is to first use ARM's CMP and other comparison instructions to set the conditional code, and then select the corresponding conditional execution instruction according to the need, such as instructions based on EQ, NE, GT, LT and other conditions, to implement the original x86 function of executing different code segments according to different conditions by relying on conditional branch jumps. This conversion can improve performance in some scenarios and reduce performance losses such as pipeline flushing caused by frequent jumps.

[0065] The conditional execution instruction of the ARM architecture can be understood as a combination of an instruction and a conditional suffix, wherein the instruction is a general ARM instruction, and the conditional suffix mainly includes EQ, NE, GT, LT, GE and LE. The conditional branch to conditional execution conversion is performed for each x86 conditional branch instruction, and this embodiment takes the EQ conditional execution instruction conversion as an example for explanation.

[0066] In x86 assembly, it is common to use the JE (jump if equal) instruction to decide whether to jump to a specified address to execute subsequent code based on the result of the previous operation, that is, whether the zero flag ZF is set to 1. For example, the following x86 code snippet:

[0067] MOV eax, 5

[0068] CMP eax, 5

[0069] JE equal_label

[0070] / / Here is the code executed when not equal

[0071] equal_label:

[0072] add xx, xx / / This is the code executed when they are equal. The addition instruction is just an example.

[0073] The processing process of this code is: first transfer the immediate value 5 to the register eax, then compare the value of eax with 5. If they are equal, the ZF flag will be set to 1, and then jump to equal_label to execute the subsequent code.

[0074] Convert to ARM conditional execution instructions:

[0075] In ARM assembly, to achieve similar functions, the CMP instruction is used to set the condition code for comparison operation, and then the instruction with EQ conditional execution is used to implement the operation after the conditional judgment. The corresponding ARM code is as follows:

[0076] MOV R0, #5

[0077] CMP R0, #5

[0078] ADDEQ R1, R2, R3 / / This addition instruction is executed only when the comparison results are equal (that is, the Z flag is 1)

[0079] In this code, the immediate value 5 is first transferred to register R0, and then the CMP instruction is used to compare R0 with another immediate value 5. This operation will update the conditional code flag according to the comparison result, which is equivalent to setting the ZF flag in x86. Then the conditional execution instruction ADDEQ is used. Only when the comparison result meets the equality condition, the addition operation R1 = R2 + R3 is executed. Otherwise, the ADDEQ instruction is skipped and the subsequent code is executed, thus realizing the function of selectively executing code according to the equality condition similar to the JE instruction in x86.

[0080] In the above example, only one instruction is executed when the condition is met. If more than one instruction is executed when the condition is met, for each instruction instr executed when the condition is met, the operand register that will be modified in instr is parsed, recorded as regToModify, to determine whether the register is the register required for conditional execution, such as the R0 register in the sample code. If so, the register mapping is re-executed using a dynamic mapping algorithm based on usage frequency. If remapping is possible, regToModify is remapped to other registers, recorded as newReg, and there is no need to generate instructions to initialize the value of newReg, because the register will be written by instr. If remapping is not possible due to register exhaustion or other reasons, the previous conditional judgment statement is re-executed after the instruction, and the x86 conditional branch instruction is converted to the ARM branch instruction. The instruction with the EQ suffix is ​​not selected for conversion, that is, it is strictly executed according to semantics, not conditional execution.

[0081] If it is not multiple instructions, it is directly converted into a conditional execution instruction, that is, the instr is converted into the instr+EQ instruction.

[0082] The conversion process of conditional execution instructions such as NE, GT, LT, GE and LE is similar to the above process.

[0083] S3. Further optimize and integrate all ARM instructions in the output instruction queue, mainly removing redundant instructions to better meet the pipeline execution characteristics of the ARM processor, and finally forming a complete and optimized ARM instruction stream. The specific steps are as follows:

[0084] S3.1. Traverse the temporarily stored ARM instruction queue, find and delete redundant instructions that may be generated due to rule application during the conversion process, but whose actual execution effects have been covered by other instructions.

[0085] For example, when converting from x86 instructions to ARM instructions, some instructions for initializing registers may appear repeatedly. Assume that in x86 there is a series of instructions for setting the initial value of a variable to 0, first MOV eax, 0, and then due to the branch judgment of the code logic, MOV eax, 0 appears again in a branch. After conversion to ARM instructions, similar situations like MOV R0, #0 may appear multiple times. In this case, after identifying these repeated instructions, only one valid instruction MOV R0, #0 needs to be retained.

[0086] S3.2: For the use of temporary registers, if it is found in subsequent conversions that their values ​​are not actually used or have been replaced by other equivalent operations, the related load, store and other operation instructions can also be eliminated.

[0087] For example, in the process of converting x86 architecture instructions to ARM architecture instructions, a temporary register is set up for transferring data. However, in the subsequent execution process, it is found that the purpose can be achieved by directly using the source data register in conjunction with conditional execution instructions. In this case, the instructions related to the temporary register, such as MOV R3, R2, can be deleted.

[0088] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A branch instruction conversion optimization method based on conditional execution mechanism, characterized in that: The specific steps include: Step 1: Load the executable file through dynamic instruction conversion to obtain the current instruction to be converted; Step 2: If the current instruction to be converted is an unconditional branch instruction in the x86 architecture, the operand of the current instruction to be converted is obtained and recorded as the first operand, and step 3 is executed; If it is a conditional branch instruction, the operand of the current instruction to be converted is obtained and recorded as the second operand, and step 4 is executed; If it is a non-conditional branch instruction, the current instruction to be converted is converted into an ARM instruction and then step 12 is executed; Step 3, record the ARM architecture unconditional jump instruction with the same function as the current instruction to be converted as the first ARM instruction, use the first operand as the operand of the first ARM instruction, convert the current instruction to be converted into the first ARM instruction, and execute step 12; Step 4: record the flag bit in the flag register related to the current instruction to be converted as the first flag bit, record the instruction that modifies the first flag bit and is located before and closest to the current instruction to be converted as the first preceding instruction, and convert the first preceding instruction into the first ARM preceding instruction; Obtain a jump entry instruction according to the second operand, and form a first instruction set from the jump entry instruction to the next branch instruction and the jump entry instruction. If the first instruction set contains only one instruction, execute step 5, otherwise execute step 6; Step 5: record the ARM instruction with the same function as the jump entry instruction as the second ARM instruction, and the ARM architecture condition code determined according to the current instruction to be converted as the first condition code; The first conditional code is used as a suffix of the second ARM instruction to form a first conditional ARM instruction, and the current instruction to be converted and the jump entry instruction are converted into the first conditional ARM instruction and then step 12 is executed; Step 6, traverse the instructions in the first instruction set, convert the current instruction into an ARM instruction with the same function and record it as the current ARM instruction, if the operand register of the current ARM instruction is the operand register of the first ARM prefix instruction, execute step 7; otherwise, execute step 10; Step 7, re-execute register mapping for the current ARM instruction. If the mapping is successful, use the new register as the operand of the current ARM instruction, and execute step 8 when the current ARM instruction is the first instruction in the first instruction set, and execute step 11 when it is not the first instruction; if the mapping fails, add the first ARM prefix instruction after the current ARM instruction, and execute step 9 when the current ARM instruction is the first instruction in the first instruction set, and execute step 11 when it is not the first instruction; Step 8, according to the ARM architecture condition code determined by the current instruction to be converted as the second condition code, the second condition code is used as the suffix of the current ARM instruction to form a second conditional ARM instruction, the current instruction to be converted and the jump entry instruction are converted into the second conditional ARM instruction, and step 11 is executed; Step 9, according to the ARM architecture condition code determined by the current instruction to be converted as the third condition code, the third condition code is used as the suffix of the current ARM instruction to form a third conditional ARM instruction, the current instruction to be converted and the jump entry instruction are converted into an instruction sequence consisting of the third conditional ARM instruction and the first ARM prefix instruction, and step 11 is executed; Step 10, if the current ARM instruction is the first instruction in the first instruction set, the ARM architecture condition code determined according to the current instruction to be converted is the fourth condition code, the fourth condition code is used as a suffix of the current ARM instruction to form a fourth conditional ARM instruction, the current instruction to be converted and the jump entry instruction are converted into the fourth conditional ARM instruction, and then step 11 is executed; otherwise, step 11 is directly executed; Step 11: If there are unprocessed instructions in the first instruction set, execute step 6; otherwise, execute step 12; Step 12: Save the converted ARM instruction to the output instruction queue. If the executable file has not been loaded, select the next instruction as the current instruction to be converted to execute step 2. Otherwise, execute the output instruction queue to complete the execution of the executable file and end this process.

2. The branch instruction conversion optimization method according to claim 1, characterized in that: The first operand and the second operand are both jump address offsets.

3. The branch instruction conversion optimization method according to claim 1, characterized in that: In the step 12, before executing the output instruction queue, redundant instructions in the output instruction queue are deleted.

4. The branch instruction conversion optimization method according to claim 3, characterized in that: The method of deleting redundant instructions in the output instruction queue is: traversing the output instruction queue, searching for and deleting redundant instructions with the same execution effect; searching for all registers involved in the output instruction queue, and deleting the load and store instructions related to unused registers.

5. The branch instruction conversion optimization method according to claim 1, characterized in that: The ARM architecture condition codes include EQ, NE, GT, LT, GE and LE.

6. The branch instruction conversion optimization method according to claim 1, characterized in that: The instruction type of the current instruction to be converted is identified by obtaining the operation code of the current instruction to be converted.

7. The branch instruction conversion optimization method according to claim 1, characterized in that: In the step 4, the first preceding instruction is a comparison instruction of the x86 architecture.

8. The branch instruction conversion optimization method according to claim 1, characterized in that: The first ARM prefix instruction is a comparison instruction of the ARM architecture.