Data transmission method, data processing device and electronic equipment

Abstract

The embodiment of the invention discloses a data transmission method, a data processing device and electronic equipment, relates to the technical field of chips, and solves the problem of how to develop operators aiming at chips of different chip architectures at lower cost to realize synchronization among data when a parallel data processing mode is adopted and a dependency relationship exists among the data. According to the specific scheme, the data transmission method is provided and applied to the data processing device, and the method comprises the steps that firstly, a target storage space is applied in a storage space corresponding to a first logic position; and then, transmitting the data stored in the storage space corresponding to the second logic position to the target storage space. And finally, changing a first corresponding relation between the data and the second logic position into a second corresponding relation between the data and the first logic position.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a data transmission method, a data processing device, and an electronic device. Background Art

[0002] Artificial intelligence models are being applied in more and more fields, such as natural language processing, computer vision, and autonomous driving. As the demand for the execution performance of artificial intelligence models increases, many chips dedicated to artificial intelligence models have emerged. These chips improve the execution performance of artificial intelligence models by designing dedicated hardware acceleration units, such as graphics processing units (GPUs) and neural network processing units (NPUs).

[0003] The computing network corresponding to the artificial intelligence model generally adopts a parallel data processing method to further improve the execution performance of the artificial intelligence model. However, when there is a dependency between the data, how to develop operators for chips with different chip architectures at a low cost to achieve synchronization between data becomes an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present application provide a data transmission method, a data processing device and an electronic device, which solve the problem of how to develop operators for chips with different chip architectures at a low cost to achieve synchronization between data when there are dependencies between data using a parallel data processing method.

[0005] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0006] In a first aspect of an embodiment of the present application, a data transmission method is provided, which is applied to a data processing device, and the method includes: first, applying for a target storage space in a storage space corresponding to a first logical position. Then, data stored in a storage space corresponding to a second logical position is transmitted to the target storage space. Finally, the first correspondence between the data and the second logical position is changed to a second correspondence between the data and the first logical position.

[0007] Based on this solution, data transmission is achieved through logical positions. When data is transmitted from the second logical position to the first logical position, the first corresponding relationship between the data and the second logical position is changed to the second corresponding relationship between the data and the first logical position to indicate that the data transmission is completed. It can be understood that when data transmission is performed, there is no need to consider the transmission of data between actual physical devices. Therefore, when the data transmission method is used to achieve synchronization between data, developers can pre-define the corresponding relationship between logical positions and physical devices when developing operators, and develop operators based on logical positions. When the architecture of the chip changes, by redefining the corresponding relationship between logical positions and physical devices, data can continue to be transmitted and synchronization can be achieved in the chip of the new architecture through the operator without the need to redevelop new operators, which can reduce development costs.

[0008] In combination with the first aspect, in a possible implementation, the data stored in the storage space corresponding to the second logical position is transferred to the target storage space, including: first, creating a logical pipe between the first logical position and the second logical position. Then, the data stored in the storage space corresponding to the first identifier and the second logical position is input into the logical pipe, and the first identifier is used to determine whether the data transfer to the target storage space is completed. Finally, the first identifier and the data are output from the logical pipe.

[0009] In combination with the first aspect, in a possible implementation method, the above-mentioned first identifier is located after the data and adjacent to the data, and the first correspondence between the data and the second logical position is changed to the second correspondence between the data and the first logical position, including: when the first identifier is output from the virtual exit of the logical pipeline, it is determined that the data is transmitted to the target storage space, and the first correspondence between the data and the second logical position is changed to the second correspondence between the data and the first logical position.

[0010] In conjunction with the first aspect, in a possible implementation, creating a logical pipe between a first logical location and a second logical location includes: receiving a create logical pipe command, the create logical pipe command being used to instruct to create a logical pipe according to the first logical location and the second logical location, and creating the logical pipe under the control of the create logical pipe command.

[0011] In combination with the first aspect, in a possible implementation, inputting data stored in a storage space corresponding to a first identifier and a second logical position into a logical pipe includes: receiving an enter queue command, the enter queue command being used to instruct: inputting data stored in a storage space corresponding to the first identifier and the second logical position into the logical pipe. Under the control of the enter queue command, the data stored in the storage space corresponding to the first identifier and the second logical position is input into the logical pipe.

[0012] In conjunction with the first aspect, in a possible implementation, outputting the first identifier and the data from the logical pipe includes: receiving a dequeue command, the dequeue command being used to instruct: outputting the first identifier and the data from the logical pipe. Outputting the first identifier and the data from the logical pipe under the control of the dequeue command.

[0013] In conjunction with the first aspect, in a possible implementation, applying for a target storage space in a storage space corresponding to a first logical location includes: receiving a storage space allocation command, the storage space allocation command being used to instruct: applying for a target storage space in a storage space corresponding to the first logical location. Under the control of the storage space allocation command, applying for the target storage space in the storage space corresponding to the first logical location.

[0014] In combination with the first aspect, in a possible implementation, the storage space allocation command is also used to indicate: a second identifier is set in the target storage space, and the second identifier is used to indicate that data is stored in the target storage space. The method also includes: under the control of the storage space allocation command, a second identifier is set in the target storage space. When the data is moved from the target storage space, a storage space release command is received, the storage space release command is used to indicate the release of the target storage space, and the second identifier is set to a third identifier, and the third identifier is used to indicate that the target storage space has been released. Under the control of the storage space release command, the target storage space is released, and the second identifier is set to the third identifier.

[0015] Based on this solution, by setting a second identifier in the target storage space, the second identifier is used to indicate that data is stored in the target storage space. When the data is moved from the target storage space, the target storage space is released under the control of the storage space release command, and the second identifier is set to a third identifier, and the third identifier is used to indicate that the target storage space has been released. Therefore, it is possible to determine whether the target storage space has been released through the second identifier and the third identifier, and the storage space corresponding to the first logical position can be fully utilized to improve the execution performance of the data processing device and the execution performance of the artificial intelligence model.

[0016] In combination with the first aspect, in a possible implementation, the first logical position corresponds to a first memory, the second logical position corresponds to a second memory, and the first memory and / or the second memory are located inside the data processing device.

[0017] In combination with the first aspect, in a possible implementation manner, the first memory and the second memory are located inside the data processing device, and the first memory and the second memory are the same memory.

[0018] In a second aspect of an embodiment of the present application, a data processing device is provided, the data processing device comprising a processing module and a transceiver module. The processing module is used to apply for a target storage space in the storage space corresponding to the first logical position. The transceiver module is used to transmit the data stored in the storage space corresponding to the second logical position to the target storage space. The processing module is also used to change the first corresponding relationship between the data and the second logical position to the second corresponding relationship between the data and the first logical position.

[0019] In conjunction with the second aspect, in a possible implementation, the processing module is specifically used to create a logical pipeline between the first logical location and the second logical location. The transceiver module is specifically used to input the data stored in the storage space corresponding to the first identifier and the second logical location into the logical pipeline, and the first identifier is used to determine whether the data transmission to the target storage space is completed. The transceiver module is also used to output the first identifier and the data from the logical pipeline.

[0020] In conjunction with the second aspect, in a possible implementation, the first identifier is located after the data and adjacent to the data. The processing module is specifically configured to, when the first identifier is output from the virtual exit of the logical pipeline, determine that the data is transmitted to the target storage space, and change the first corresponding relationship between the data and the second logical position to a second corresponding relationship between the data and the first logical position.

[0021] In conjunction with the second aspect, in a possible implementation, the transceiver module is specifically configured to receive a create logical pipeline command, the create logical pipeline command is used to instruct to create a logical pipeline according to the first logical position and the second logical position. The processing module is specifically configured to create a logical pipeline under the control of the create logical pipeline command.

[0022] In conjunction with the second aspect, in a possible implementation, the transceiver module is specifically used to receive an enter queue command, and the enter queue command is used to instruct: input the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipe. The transceiver module is also used to input the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipe under the control of the enter queue command.

[0023] In conjunction with the second aspect, in a possible implementation, the transceiver module is specifically used to receive a dequeue command, the dequeue command is used to instruct: output the first identifier and the data from the logical pipe. The transceiver module is also used to output the first identifier and the data from the logical pipe under the control of the dequeue command.

[0024] In conjunction with the second aspect, in a possible implementation, the transceiver module is specifically used to receive a storage space allocation command, and the storage space allocation command is used to indicate: apply for a target storage space in the storage space corresponding to the first logical position. The processing module is specifically used to apply for the target storage space in the storage space corresponding to the first logical position under the control of the storage space allocation command.

[0025] In combination with the second aspect, in a possible implementation, the storage space allocation command is also used to indicate: a second identifier is set in the target storage space, and the second identifier is used to indicate that data is stored in the target storage space. The processing module is also used to set the second identifier in the target storage space under the control of the storage space allocation command. When the data is moved from the target storage space, the transceiver module is also used to receive a storage space release command, and the storage space release command is used to indicate the release of the target storage space, and the second identifier is set to a third identifier, and the third identifier is used to indicate that the target storage space has been released. The processing module is also used to release the target storage space under the control of the storage space release command, and set the second identifier to the third identifier.

[0026] In combination with the second aspect, in a possible implementation, the first logical position corresponds to a first memory, the second logical position corresponds to a second memory, and the first memory and / or the second memory are located inside the data processing device.

[0027] In combination with the second aspect, in a possible implementation manner, the first memory and the second memory are located inside the data processing device, and the first memory and the second memory are the same memory.

[0028] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising a processor and a data processing device coupled to the processor, wherein the data processing device is the data processing device as described in the second aspect or any possible implementation of the second aspect.

[0029] Optionally, the type of the electronic device may include smart home devices, smart terminal devices, autonomous driving devices, and servers, etc. The embodiments of the present application do not limit the specific type of the electronic device.

[0030] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, which stores a computer program. When the computer program runs on an electronic device, the electronic device executes the steps in the data transmission method as described in the first aspect or any possible implementation of the first aspect.

[0031] The description of the second and fourth aspects of the present application can refer to the detailed description of the first aspect; and the beneficial effects described in the second and fourth aspects can refer to the beneficial effect analysis of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a computing network structure;

[0033] Figure 2 It is a schematic diagram of multiple pipelines in parallel;

[0034] Figure 3 It is a structural schematic diagram of a command synchronization device;

[0035] Figure 4 A flowchart of an instruction synchronization method is shown;

[0036] Figure 5 A schematic diagram of the structure of a neural network processor provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of an assembly line provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of another pipeline provided in an embodiment of the present application;

[0039] Figure 8 A schematic diagram of the structure of another neural network processor provided in an embodiment of the present application;

[0040] Fig. 9 A schematic diagram of the structure of another neural network processor provided in an embodiment of the present application;

[0041] Fig.10 A schematic diagram of an application scenario of a data transmission method provided in an embodiment of the present application;

[0042] Fig.11 A programming logic diagram provided for an embodiment of the present application;

[0043] Fig.12 A flowchart of a data transmission method provided in an embodiment of the present application;

[0044] Fig.13 A flowchart of another data transmission method provided in an embodiment of the present application;

[0045] Fig.14 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0046] Fig.15 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will discuss the making and use of each embodiment in detail. However, it should be understood that many applicable inventive concepts provided by this application can be implemented in a variety of specific environments. The specific embodiments discussed are only used to illustrate the specific ways to implement and use this description and this technology, and do not limit the scope of this application.

[0048] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0049] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when the specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuits that perform an operation, etc.

[0050] The technical scheme in the embodiment of the present application will be described below in conjunction with the accompanying drawings in the embodiment of the present application. In the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiment of the present application, the words "first", "second" and the like do not limit the quantity and order.

[0051] In this application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the words "exemplary" or "for example" is intended to present the related concepts in a concrete way.

[0052] Before introducing the embodiments of the present application, the technical terms and background technologies involved in the present application are first introduced.

[0053] Logical location: An abstract concept representing a memory location that is associated with physical hardware memory through mapping.

[0054] Logical pipe: A channel used to connect two logical locations and transfer data between them.

[0055] Operator: refers to a function that performs some calculation or transformation on input data.

[0056] O(1): represents the algorithm complexity of the computation network, 1 means executing the computation network once.

[0057] Register dependency: refers to the fact that the execution of certain instructions depends on the register operation results of other instructions, causing the instruction pipeline to pause or delay.

[0058] In-core synchronization instructions: refers to the code segments that access and operate shared data. In order to avoid concurrent access in the critical section, the programmer needs to ensure that these codes are executed atomically, that is, they cannot be interrupted before the execution is completed, just as if the entire critical section is an indivisible instruction.

[0059] The computing network corresponding to the artificial intelligence model generally adopts parallel data processing methods to further improve the execution performance of the artificial intelligence model.

[0060] For example, Figure 1 The figure shows a schematic diagram of the structure of a computing network, which includes a matrix multiplication operator and a vector addition operator. Among them, the matrix multiplication (Matmul) operator is used to receive data X and weight w (weight), perform matrix multiplication operation and output the matrix multiplication result w*X. The vector addition (Add) operator is used to receive the matrix multiplication result w*X and bias data b, perform vector addition operation and output the vector addition result w*X+b. The computing network can be represented by the calculation formula Output=w*X+b, where Output represents output.

[0061] In order to achieve O(1) execution performance, a data processing method with multiple pipelines in parallel is generally used to improve the execution performance of operators, thereby improving the execution performance of artificial intelligence models corresponding to the computing network. When multiple pipelines are in parallel, due to the sequential dependency between data, synchronization between pipelines needs to be considered.

[0062] For example, Figure 2As shown, it is a schematic diagram of multiple parallel pipelines, which include transport, calculation and removal. Data A1 is moved in during time period t1, and data B1 is moved in during time period t2. By moving data A2 in time period t3 and performing calculation 1 based on data B1 in time period t3, the parallel of transport and calculation is realized in time period t3. By performing calculation 2 based on data A2 in time period t4 and removing the calculation result of calculation 1 in time period t4, the parallel of calculation and removal is realized. Finally, the calculation result of calculation 2 is removed in time period t5. The execution performance of the operator can be effectively improved by running multiple parallel pipelines. However, taking data B1 as an example, calculation 1 needs to be executed after the completion of moving in data B1, and removing the calculation result of calculation 1 needs to be executed after the completion of calculation 1. Since there is a dependency relationship between the data used by each level of pipelines during execution, the synchronization between each level of pipelines needs to be considered.

[0063] like Figure 3 As shown, it is a structural schematic diagram of an instruction synchronization device 300. The instruction synchronization device 300 includes a first instruction queue 310, a multiplexer 320 and a plurality of second instruction queues 330, the output end of the first instruction queue 310 is coupled with the input end of the multiplexer 320, and the output end of the multiplexer 320 is coupled with the input end of the plurality of second instruction queues 330. The first instruction queue 310 is used to receive a plurality of instructions generated by operator mapping and send the plurality of instructions to the multiplexer 320. The multiplexer 320 is used to distribute the plurality of instructions to the plurality of second instruction queues 330, and insert synchronization instructions when distributing instructions, so as to achieve synchronization between instructions. Specifically, the multiplexer 320 inserts a trigger instruction and a wait instruction in the plurality of instruction queues, and triggers the wait instruction through the trigger instruction, so as to achieve synchronization.

[0064] However, the instruction synchronization device 300 needs to develop a multiplexer 320 to distribute multiple instructions to multiple second instruction queues 330, and insert synchronization instructions when distributing instructions, which will lead to a high cost of the instruction synchronization device 300.

[0065] like Figure 4 The figure shows a flowchart of an instruction synchronization method. In the instruction synchronization method, first, the developer manually inserts synchronization when developing the operator. Then, the instruction queue receives multiple instructions generated by the operator mapping, including synchronization instructions. Finally, the instruction queue sends the multiple instructions to the move stream, scalar stream, input / output (IO) stream, and compute stream. The four streams are executed in parallel, and the register dependency between the streams is guaranteed by hardware, thereby achieving instruction synchronization.

[0066] However, when this instruction synchronization method is applied to chips, developers need to understand the chip architecture and the dependencies between instructions, and manually insert synchronization instructions in the core when developing operators. This requires high requirements for developers and is inconvenient for developers to operate, which will lead to a poor experience. Moreover, when the chip architecture changes, developers need to re-insert synchronization in the operator to achieve instruction synchronization, which will lead to high development costs.

[0067] In order to solve the problem that the prior art uses a parallel data processing method to achieve synchronization between data, the developer experience is poor and the development cost is high. The embodiment of the present application provides a data transmission method, which establishes a mapping relationship between hardware and logical position (also referred to as queue position (queue position, Queposition)), and indicates the data transmission process through the change of the corresponding relationship between data and logical position. When data synchronization is achieved based on the data transmission method, data synchronization can be easily achieved on different chip architectures, which can improve the developer experience and reduce the cost of achieving synchronization.

[0068] The data transmission method provided in the embodiment of the present application can be applied to chips such as neural network processors and image processors. The embodiment of the present application is not limited to this. The following embodiment uses the data transmission method provided in the embodiment of the present application as an example of applying it to a neural network processor.

[0069] like Figure 5As shown, it is a schematic diagram of the structure of a neural network processor 500 provided in an embodiment of the present application. The neural network processor 500 includes a first memory transfer engine (memory transfer engine, MTE) 510, a first local memory L1, a second MTE 520, a second local memory L2, a third local memory L3, a matrix accelerator (cube core, CUBE) 530, a fourth local memory L4, a vector accelerator (vector core, VEC) 540, a unified memory (unified buffer, UB) 550 and a third MTE 560. The first local memory L1 is coupled to the global memory (global memory, GM) 600 through the first MTE 510, and the first local memory L1 is also coupled to the second local memory L2 and the third local memory L3 through the second MTE 520, and the first local memory L1 is also coupled to the UB 550 through the first MTE 510 and the third MTE 560. The second local memory L2 and the third local memory L3 are also coupled to the CUBE 530. The CUBE 530 is also coupled to the fourth local memory L4. The fourth local memory L4 is also coupled to the UB 550 through the VEC 540. The UB 550 is also coupled to the GM 600 through the first MTE 510 and the third MTE 560.

[0070] Among them, GM 600 is used to store original data, the first MTE 510 to the third MTE 560 are used to transmit data, CUBE 530 is used to perform matrix multiplication operations, VEC 550 is used to perform vector addition operations and transmit data, and the first local memory L1 to the fourth local memory L4 are used to store data.

[0071] The neural network processor 500 is used to execute the above Figure 1 Taking the computing network (Output = w*X+b) shown in the figure as an example, a computing flow may include: first MTE 510 → second MTE 520 → CUBE 530 → VEC 550 → third MTE 560. In the actual computing process, since the size of data X is relatively large, the first local memory L1 cannot store the complete data X. The data X can be divided into small sizes through data tiling technology, and multiple calculations are performed on multiple small-sized data to achieve the calculation of data X.

[0072] For example, when data X is divided into 6 small-sized data Y, the above calculation flow will need to perform 6 calculations to complete the calculation of data X. The 6 calculation processes can be constructed as follows: Figure 6 In order to improve the execution efficiency of the pipeline, different pipelines can be divided according to the type of device, so that the pipeline is constructed as follows: Figure 7The pipeline shown enables the devices in the neural network processor 500 to execute in parallel. Specifically, Figure 7 The pipeline on the left side of the dashed line is executed 6 times in parallel Figure 6 Taking the case that each device needs time t to transmit or calculate a small data Y once, the neural network processor 500 follows the following pipeline: Figure 6 The pipeline shown in FIG. 1 takes 30 t to complete the calculation of the data X. Figure 7 The pipeline shown in FIG. 10 takes 10 t to complete the calculation of data X. It can be understood that the neural network processor 500 performs the following steps: Figure 7 The pipeline shown in the figure processes data in a parallel manner, which can improve the data processing efficiency. In addition, when the data X is divided into more data of smaller size, the above calculation flow will need to be calculated more times. After 4t time, the time required for the neural network processor 500 to complete the calculation of one calculation flow is t in theory, which can effectively improve the data processing efficiency of the neural network processor 500 and the execution performance of the artificial intelligence model.

[0073] When the neural network processor 500 follows Figure 7 When the pipeline shown in the figure processes data, synchronization between data needs to be considered. Specifically, the lower-level pipeline needs to process the data after the upper-level pipeline has completed the data processing. For example, when the first MTE 510 completes the transfer of data Y from the GM 600 to the first local memory L1, the second MTE 520 then transfers the data Y from the first local memory L1 to the second local memory L2. The dependencies between the pipelines at each level are as follows: Figure 7 The data transmission method provided in the embodiment of the present application can be applied to the process of data synchronization.

[0074] like Figure 8As shown, it is a structural schematic diagram of another neural network processor 800 provided in an embodiment of the present application. The neural network processor 800 includes a first MTE 810, a first local memory L1, a second MTE 820, a second local memory L2, a third local memory L3, a binary tag buffer (BT BUFF) 830, a CUBE 840, a fourth local memory L4, and a fixpipe 850. The first local memory L1 is coupled to the global memory 600 through the first MTE 810, and the first local memory L1 is also coupled to the second local memory L2, the third local memory L3 and the BT BUFF 830 through the second MTE 820, and the first local memory L1 is also coupled to the fixpipe 850. The second local memory L2, the third local memory L3 and the BT BUFF 830 are coupled to the CUBE 840, the CUBE 840 is also coupled to the fourth local memory L4, and the fourth local memory L4 is also coupled to the fixpipe 850.

[0075] The GM 600 is used to store raw data, the first MTE 810, the second MTE 820 and the fixed tube 850 are used to transmit data, the CUBE 840 is used to perform matrix multiplication operations, and the first local memory L1 to the fourth local memory L4 are used to store data. The neural network processor 800 is used to perform the above Figure 1 Taking the computing network (Output = w*X+b) shown as an example, a computing flow may include: first MTE 810 → second MTE 820 → CUBE 840 → fixed tube 850. In the actual computing process, the neural network processor 800 can also perform multiple calculations on multiple data of small size, and adopt a parallel data processing method, so as to improve the data processing efficiency of the neural network processor 800 and improve the execution performance of the artificial intelligence model. The specific process can refer to the data processing process of the above-mentioned neural network processor 500, and the embodiments of the present application will not be repeated here. When the neural network processor 800 processes data in a parallel manner, it is also necessary to consider the synchronization between data. The data transmission method provided in the embodiments of the present application can also be applied to the data synchronization process.

[0076] like Fig. 9 , which is a schematic diagram of the structure of another neural network processor 900 provided in an embodiment of the present application. The neural network processor 900 includes a scalar unit 910, a VEC 920, a CUBE 930, and a unified buffer (UB) 940. The scalar unit 910 is coupled to the GM 600, and the scalar unit 910 is also coupled to the UB 940. The VEC 920 and the CUBE 930 are coupled to the UB 940, and the UB 940 is also coupled to the GM 600.

[0077] Among them, GM 600 is used to store raw data, scalar unit 910 is used to perform mathematical operations, VEC 920 is used to perform vector addition operations, CUBE 930 is used to perform matrix operations, and UB 940 is used to store data. When the neural network processor 900 processes data in parallel, synchronization between data also needs to be considered. The data transmission method provided in the embodiment of the present application can also be applied to the data synchronization process.

[0078] like Fig.10 As shown in (a), it is a schematic diagram of an application scenario of a data transmission method provided in an embodiment of the present application. When applying the data transmission method provided in an embodiment of the present application, the developer can divide the operator into three stages (Stage), which can also be called divided into multiple pipeline tasks. The three stages include: copy-in (CopyIn) stage, calculation (Compute) stage and copy-out (CopyOUT) stage. The data transmission method provided in an embodiment of the present application transmits data through a queue (queue), and uses four primitives Alloc, Enque (enter queue), Deque (dequeue), and Free to realize the insertion and pipeline cascading of identifiers, so that data transmission can be realized through logical positions. Among them, the Alloc primitive is used to indicate the allocation of a memory block of a specified size in dynamic memory, and the Free primitive is used to indicate the release of a dynamically allocated memory block.

[0079] For example, combined with Figure 5 , take a computing flow including: first MTE 510→second MTE 520→CUBE 530→VEC540→third MTE 560 as an example. Fig.10 As shown in (a), the copy-in phase may include the first MTE 510 transferring data from the GM 600 to the first local memory L1. The process of the second MTE 520 transferring data from the first local memory L1 to the second local memory L2 and the third local memory L3 is located between the copy-in phase and the calculation phase. At this time, the second local memory L2 and the third local memory L3 can be called vector input (vector in, VecIn) units. The calculation phase may include CUBE530 obtaining data from the VecIn unit for calculation and outputting the calculation result to the fourth local memory L4. The process of VEC 540 transferring data from the fourth local memory L4 to UB 550 is located between the calculation phase and the copy-out phase. At this time, the fourth local memory L4 can be called a vector output (vector out, VecOut) unit. The copy-out phase may include the third MTE560 transferring data from UB 550 to GM 600.

[0080] The following takes the transmission of copy-in stage data as an example to introduce the data transmission method provided by the embodiment of the present application. The multiple instructions generated by the operator mapping developed by the developer can instruct the first MTE 510 to perform the following steps: Fig.10 As shown in (b), take the first local memory L1 mapped as the first logical location and GM600 mapped as the second logical location as an example. First, the first MTE 510 can apply for the target storage space in the first logical location under the control of the primitive Alloc. Secondly, the first MTE 510 can create a logical pipe between the first logical location and the second logical location, and under the control of the primitive Enque, input the first identifier and the data in GM 600 into the queue. The first identifier is used to determine whether the data transfer to the target storage space is completed. Then, the first MTE 510 can output the first identifier and the data in the logical pipe from the logical pipe under the control of the primitive Deque. Finally, the first MTE 510 can determine that the data is transferred to the target storage space based on the first identifier, and change the first corresponding relationship between the data and the second logical location to the second corresponding relationship between the data and the first logical location, thereby realizing the data transmission.

[0081] In a possible embodiment, when applying the data transmission method provided in the embodiment of the present application, developers can construct a programming logic diagram to facilitate the development of operators.

[0082] For example, taking the neural network processor 800 as an example, when developing an operator, the developer can construct Fig.11 The programming logic diagram shown in FIG. GM 600 and shared memory (SHM) 700 are used to output raw data and receive calculated data. The first local memory L1 to the fourth local memory L4 and the fixed pipe 850 are used to provide buffer pools (also called resource pools) 1 to 5.

[0083] First, developers can establish a correspondence between physical devices and logical locations: GM 600 can be mapped to logical location GM 600, SHM 700 can be mapped to logical location SHM700, the first local memory L1 can be mapped to logical locations A1, B1, and C1, the second local memory L2 can be mapped to logical location A2, the third local memory L3 can be mapped to logical location B2, BT BUFF 840 can be mapped to logical location C2, and the fourth local memory L4 can be mapped to logical address D1.

[0084] Then, create logical pipes between logical positions: GM 600 and SHM 700 can be connected to logical positions A1, B1, and C1 through logical pipes, logical position A1 can also be connected to logical position A2 through logical pipes, logical position B1 can also be connected to logical position B2 through logical pipes, and other connected logical positions can also be connected through logical pipes to achieve multi-level pipeline cascading and orchestration, which will not be described in detail in the embodiments of the present application. Cascading means that logical positions are connected end to end, for example, GM 600 is connected to logical position A1 through a logical pipe, and logical position A1 is connected to logical position A2 through a logical pipe. Orchestration means that multiple logical positions are connected side by side, for example, logical positions A1, B1, and C1 are connected to logical positions A2, B2, and C2 through logical pipes, respectively.

[0085] The process of transferring data from GM 600 or SHM 700 to logical locations A1, B1, and C1 belongs to the copy-in phase. The process of transferring data from logical locations A2, B2, and C2 to D1 belongs to the calculation phase. The process of transferring data from logical location D1 to GM 600 or SHM 700 belongs to the copy-out phase. In a specific implementation, the first local memory L1 can transfer data to the second local memory L2, the third local memory L3, and the BT BUFF 830 respectively by splitting the data, and the result after the calculation by CUBE840 is aggregated in the fourth local memory L4.

[0086] In a possible embodiment, Fig.11 As shown, taking the neural network processor 800 also including VEC and UB coupled to VEC, UB as VecIn unit and VecOut unit calculated by VEC as an example, the logic position D1 can be connected to VecIn through a logic pipeline, so that the output of CUBE 840 can be cascaded with the input of VEC.

[0087] Finally, developers can develop operators more intuitively based on the programming logic diagram, which can improve development efficiency.

[0088] like Fig.12 As shown, it is a flowchart of a data transmission method provided by an embodiment of the present application. The method can be applied to a data processing device, for example, it can be specifically executed by an execution unit in the data processing device, and the data processing device can be a chip, such as the neural network processor 500, the neural network processor 800 or the neural network processor 900, and the method includes steps S1201-S1203.

[0089] S1201. An execution unit applies for a target storage space in a storage space corresponding to a first logical location.

[0090] Optionally, the types of execution units may include MTE, CUBE, VEC, fixed tube, etc. The embodiments of the present application do not limit the specific types of execution units.

[0091] For example, the data transmission method provided in the embodiment of the present application is applied to the above Figure 5 Taking the neural network processor 500 shown in the figure as an example, the execution unit can be the first MTE 510, or the second MTE 520, or the CUBE 530, or the VEC 550. The data transmission method provided in the embodiment of the present application is applied to the above Figure 8 Taking the neural network processor 800 shown as an example, the execution unit may be the first MTE 810 , or the second MTE 820 , or the CUBE 840 , or the fixed tube 850 .

[0092] The storage space corresponding to the first logical position is a storage space in a first memory, and the first memory is coupled to the execution unit.

[0093] Exemplarily, when the execution unit is the first MTE 510, the first memory may be the first local memory L1, and the storage space corresponding to the first logical position is the storage space in the first local memory L1.

[0094] Optionally, the target storage space may be all the storage space in the storage space corresponding to the first logical location, or may be part of the storage space in the storage space corresponding to the first logical location, which is not limited in the embodiment of the present application.

[0095] In a possible embodiment, the execution unit applies for the target storage space in the storage space corresponding to the first logical position, including: the execution unit receives a storage space allocation command, the storage space allocation command is used to indicate: apply for the target storage space in the storage space corresponding to the first logical position. Under the control of the storage space allocation command, the execution unit applies for the target storage space in the storage space corresponding to the first logical position.

[0096] For example, taking the execution unit as the first MTE 810 in the neural network processor 800 as an example, the developer may write the following code:

[0097] AddrA1 = QueA1.Alloc()

[0098] Among them, QueA1.Alloc() indicates applying for a target storage space in the logical location A1. This code indicates applying for a target storage space in the logical location A1 and assigning the address of the target storage space to AddrA1.

[0099] The first MTE 810 may receive a storage space allocation command generated by the code mapping, the storage space allocation command being used to instruct: applying for a target storage space in the logical location A1. The first MTE 810 may apply for a target storage space in the logical location A1 under the control of the storage space allocation command.

[0100] S1202: The execution unit transfers the data stored in the storage space corresponding to the second logical position to the target storage space.

[0101] The second logical position corresponds to a second memory, and the second memory is coupled to the execution unit.

[0102] Exemplarily, when the execution unit is the first MTE 510 , the second memory may be the GM 600 , and the storage space corresponding to the second logical position is the storage space in the GM 600 .

[0103] In a possible embodiment, the first memory and / or the second memory is located inside the data processing device, and the embodiment of the present application does not limit the specific locations of the first memory and the second memory.

[0104] Exemplarily, the first memory may be located inside the data processing device, and the second memory may be located outside the data processing device, or the first memory may be located outside the data processing device, and the second memory may be located inside the data processing device, or both the first memory and the second memory may be located inside the chip.

[0105] For example, the data transmission method provided in the embodiment of the present application is applied to the above Figure 8 The neural network processor 800 is shown as an example.

[0106] When the execution unit is the first MTE 810, the first memory may be the first local memory L1, and the second memory may be the GM 600. It can be understood that at this time, the first memory is located inside the neural network processor 800, and the second memory is located outside the neural network processor 800.

[0107] When the execution unit is a fixed pipe 850, the first memory may be GM 600, and the second memory may be the fourth local memory L4. It can be understood that at this time, the first memory is located outside the neural network processor 800, and the second memory is located inside the neural network processor 800.

[0108] When the execution unit is the second MTE 820, the first memory may be the second local memory L2, and the second memory may be the first local memory L1. It can be understood that at this time, both the first memory and the second memory are located inside the neural network processor 800.

[0109] In a possible embodiment, the first memory and the second memory are located inside the data processing device, and the first memory and the second memory are the same memory.

[0110] For example, the data transmission method provided in the embodiment of the present application is applied to the above Fig. 9 Take the neural network processor 900 as an example. When the execution unit is UB 940, the first memory and the second memory are also UB 940. It can be understood that at this time, the first memory and the second memory are both located inside the neural network processor 900, and the first memory and the second memory are the same memory UB 940.

[0111] Specifically, the execution unit transfers the data stored in the storage space corresponding to the second logical position to the target storage space, including: first, the execution unit creates a logical pipeline between the first logical position and the second logical position. Then, the execution unit inputs the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipeline, and the first identifier is used to determine whether the data transfer to the target storage space is completed. Finally, the execution unit outputs the first identifier and the data from the logical pipeline.

[0112] Optionally, the logical pipeline may follow the first-in-first-out principle of data transmission, or may transmit data in parallel to improve data transmission efficiency, which is not limited in the embodiments of the present application.

[0113] The above-mentioned creation of a logical pipeline between the first logical position and the second logical position includes: the execution unit receives a create logical pipeline command, the create logical pipeline command is used to instruct to create a logical pipeline according to the first logical position and the second logical position. The execution unit creates the logical pipeline under the control of the create logical pipeline command.

[0114] For example, Figure 8 The neural network processor 800 shown is used to perform the above Figure 1 Take the computing network (Output = w*X+b) shown in the figure as an example. When developing an operator, developers can first determine that the data flow of the CUBE 840 computing unit includes:

[0115] 1)GM 600→L1→L2→CUBE 840→L4→fixed tube 850→GM 600;

[0116] 2)GM 600→L1→L3→CUBE 840→L4→fixed tube 850→GM 600;

[0117] 3)GM 600→L1→BT BUFF 830→CUBE 840→L4→fixed pipe 850→GM 600.

[0118] Among them, data pipeline 1) is used to transmit the left matrix (weight w) of the matrix operation, data pipeline 2) is used to transmit the right matrix (data X) of the matrix operation, and data pipeline 3) is used to transmit vector addition data (bias data b).

[0119] Developers can then establish the correspondence between physical devices and logical locations, as shown above. Fig.11 As shown, it can be determined that the computation flow in the neural network processor 800 includes:

[0120] GM 600→A1→A2→CUBE 840→D1→GM 600;

[0121] GM 600→B1→B2→CUBE 840→D1→GM 600;

[0122] GM 600→C1→C2→CUBE 840→D1→GM 600.

[0123] Taking the data transmission between computing flow GM 600→A1 as an example, the developer can write the following code:

[0124] QueA1=CreateQue(GM 600→A1)

[0125] Wherein, CreateQue indicates creating a logical pipe, and QueA1 indicates the name of the created logical pipe. This code indicates creating a logical pipe QueA1 between logical locations GM 600 and A1.

[0126] As an execution unit, the first MTE 810 may receive a logical pipeline command generated by the code mapping, the logical pipeline command being used to instruct to create a logical pipeline according to the logical locations GM 600 and A1. The first MTE 810 may create a logical pipeline under the control of the logical pipeline command.

[0127] The execution unit inputs the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipeline, and the first identifier is used to determine whether the data transmission to the target storage space is completed, including: the execution unit receives an enter queue (Enque) command, and the enter queue command is used to instruct: the data stored in the storage space corresponding to the first identifier and the second logical position is input into the logical pipeline. Under the control of the enter queue command, the execution unit inputs the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipeline.

[0128] Optionally, the first identifier may be a hardware identity document (ID) or a character string, which is not limited in the embodiment of the present application.

[0129] For example, when the first identifier is a hardware ID, the hardware ID may be a register ID, and a first value may be stored in the register corresponding to the hardware ID before data transmission. The logical pipeline follows the first-in-first-out data transmission principle, and the first identifier enters the logical pipeline after the data and is adjacent to the data. When the first identifier is output from the virtual exit of the logical pipeline, the execution unit may modify the value in the corresponding register to a second value according to the hardware ID, and the second value is used to indicate that the data transmission to the target storage space is completed.

[0130] For another example, when the first identifier is a string, the first identifier can be used to indicate the size of the transmitted data. When transmitting data through a logical pipeline, the execution unit can determine whether the data transfer to the target storage is completed based on the first identifier and the size of the data output by the logical pipeline.

[0131] For another example, when the first identifier is a string, the first identifier can be used to indicate that the data transfer to the target storage space is complete. The logical pipeline follows the first-in-first-out principle of data transmission. The first identifier needs to enter the logical pipeline after the data and be adjacent to the data, so that when the first identifier is output from the virtual exit of the logical pipeline, the execution unit can determine that the data transfer to the target storage space is complete based on the first identifier. In the following embodiments of the present application, the first identifier is a string, and the first identifier is used to indicate that the data transfer to the target storage space is complete as an example for illustrative description.

[0132] For example, taking the execution unit as the first MTE 810 in the neural network processor 800 as an example, the developer may write the following code:

[0133] QueA1.Enque(AddrA1)

[0134] The code is used to generate a set synchronization event, which is used to generate a first identifier. The code is also used to instruct the first identifier and data to be input into the logic pipe QueA1, and the first identifier is located after the data and adjacent to the data.

[0135] The first MTE 810 may receive an entry queue command generated by the code mapping, and the entry queue command is used to instruct: input the first identifier and data into the logic pipe QueA1, and the first identifier is located after the data and adjacent to the data. The first MTE 810 may input the first identifier and data into the logic pipe QueA1 under the control of the entry queue command, and the first identifier is located after the data and adjacent to the data. When the execution unit is another type of execution unit, the specific process can refer to the above description, and the embodiment of the present application will not be described here.

[0136] The outputting of the first identifier and the data from the logical pipeline includes: the execution unit receives a dequeue command, the dequeue command is used to instruct: outputting the first identifier and the data from the logical pipeline. Under the control of the dequeue command, the first identifier and the data are output from the logical pipeline.

[0137] For example, taking the execution unit as the first MTE 810 in the neural network processor 800 as an example, the developer may write the following code:

[0138] AddrA1' = QueA1.Deque()

[0139] Among them, QueA1.Deque() indicates outputting data from the logical pipe QueA1, and AddrA1' indicates the address corresponding to the storage space in the first local memory L1. This code is used to indicate outputting the first identifier and data from the logical pipe QueA1 to the storage space corresponding to the address AddrA1'.

[0140] The first MTE 810 may receive a dequeue command generated by the code mapping, the dequeue command being used to instruct: outputting the first identifier and data from the logical pipe QueA1. The first MTE 810 may output the first identifier and data from the logical pipe QueA1 under the control of the dequeue command.

[0141] S1203: The execution unit changes the first corresponding relationship between the data and the second logical position to the second corresponding relationship between the data and the first logical position.

[0142] In a possible embodiment, the first identifier is located after the data and adjacent to the data, and the above-mentioned execution unit changes the first correspondence between the data and the second logical position to the second correspondence between the data and the first logical position, including: when the first identifier is output from the virtual exit of the logical pipeline, it is determined that the data is transmitted to the target storage space, and the first correspondence between the data and the second logical position is changed to the second correspondence between the data and the first logical position.

[0143] In a possible embodiment, when the first memory and the second memory are both located inside a data processing device, and the first memory and the second memory are the same memory, since the first logical position and the second logical position correspond to the same memory, no data transmission is required, and the execution unit may not insert the first identifier when executing the above steps, thereby improving the execution efficiency of the execution unit.

[0144] In a possible embodiment, the command received by the execution unit may be sent by a scalar unit in the chip. Fig. 9 In the neural network processor 900 shown, the execution unit is UB 940 as an example. The execution unit UB 940 can receive the above-mentioned commands sent by the scalar unit 910.

[0145] The data transmission method provided in the embodiment of the present application realizes data transmission through logical positions. When data is transmitted from the second logical position to the first logical position, the first corresponding relationship between the data and the second logical position is changed to the second corresponding relationship between the data and the first logical position to indicate that the data transmission is completed. It can be understood that when data transmission is performed, it is not necessary to consider the transmission of data between actual physical devices. Therefore, when the data transmission method is used to achieve synchronization between data, developers can pre-define the corresponding relationship between logical positions and physical devices when developing operators, and develop operators based on logical positions. When the architecture of the chip changes, by redefining the corresponding relationship between logical positions and physical devices, data can continue to be transmitted and synchronization can be achieved in the chip of the new architecture through the operator without the need to redevelop new operators, which can reduce development costs.

[0146] In a possible embodiment, the storage space allocation command is further used to indicate: setting a second identifier in the target storage space, the second identifier being used to indicate that data is stored in the target storage space, such as Fig.13 As shown, before the above step S1202, the method further includes step S1204.

[0147] S1204: Under the control of the storage space allocation command, the execution unit sets a second identifier in the target storage space.

[0148] like Fig.13 As shown, when the data is moved from the storage space corresponding to the address, the method further includes steps S1205-S1206 after the above step S1203.

[0149] S1205. The execution unit receives a storage space release command, where the storage space release command is used to instruct the target storage space to be released, and sets the second identifier to a third identifier, where the third identifier is used to indicate that the target storage space has been released.

[0150] For example, a developer could write code like this:

[0151] QueA1.Free(AddA1')

[0152] The code is used to instruct to release the target storage space corresponding to the address AddA1' in the first local memory L1, and generate a setting synchronization event, wherein the setting synchronization event is used to set the second flag to set the third flag.

[0153] The first MTE 810 may receive a storage space release command generated by the code mapping, where the storage space release command is used to instruct to release the target storage space, and sets the second identifier to a third identifier.

[0154] S1206: Under the control of the storage space release command, the execution unit releases the target storage space and sets the second identifier to the third identifier.

[0155] For example, under the control of the storage space release command, the first MTE 810 may release the target storage space corresponding to the address AddA1′ in the first local memory L1 and set the second identifier to the third identifier.

[0156] The data transmission method provided by the embodiment of the present application sets a second identifier in the target storage space, the second identifier is used to indicate that data is stored in the target storage space, and when the data is moved from the target storage space, the target storage space is released under the control of the storage space release command, and the second identifier is set to a third identifier, the third identifier is used to indicate that the target storage space has been released. Therefore, it is possible to determine whether the target storage space has been released through the second identifier and the third identifier, and the storage space corresponding to the first logical position can be fully utilized to improve the execution performance of the data processing device and the execution performance of the artificial intelligence model.

[0157] like Fig.14As shown, the embodiment of the present application also provides a data processing device 1400, which includes a processing module 1410 and a transceiver module 1420 coupled to the processing module 1410. The processing module 1410 is used to apply for a target storage space in the storage space corresponding to the first logical position. The transceiver module 1420 is used to transmit the data stored in the storage space corresponding to the second logical position to the target storage space. The processing module 1410 is also used to change the first corresponding relationship between the data and the second logical position to the second corresponding relationship between the data and the first logical position.

[0158] Optionally, the data processing device 1400 may be a chip or an electronic device including the chip, and the chip may be any one of a neural network processor, an image processor, and the like, which is not limited in the embodiments of the present application. For example, when the chip is a neural network processor, the chip may be any one of the neural network processor 500, the neural network processor 800, or the neural network processor 900.

[0159] In a possible embodiment, the processing module 1410 is specifically used to create a logical pipeline between the first logical location and the second logical location. The transceiver module 1420 is specifically used to input the data stored in the storage space corresponding to the first identifier and the second logical location into the logical pipeline, and the first identifier is used to determine whether the data transmission to the target storage space is completed. The transceiver module 1420 is also used to output the first identifier and the data from the logical pipeline.

[0160] In a possible embodiment, the first identifier is located after the data and adjacent to the data, and the processing module 1410 is specifically used to determine that the data is transmitted to the target storage space when the first identifier is output from the virtual exit of the logical pipeline, and change the first corresponding relationship between the data and the second logical position to a second corresponding relationship between the data and the first logical position.

[0161] In a possible embodiment, the transceiver module 1420 is specifically configured to receive a create logical pipe command, the create logical pipe command is used to instruct to create a logical pipe according to the first logical position and the second logical position. The processing module 1410 is specifically configured to create a logical pipe under the control of the create logical pipe command.

[0162] In a possible embodiment, the transceiver module 1420 is specifically used to receive an enter queue command, and the enter queue command is used to instruct: input the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipe. The transceiver module 1420 is also used to input the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipe under the control of the enter queue command.

[0163] In a possible embodiment, the transceiver module 1420 is specifically used to receive a dequeue command, the dequeue command is used to instruct: output the first identifier and data from the logical pipe. The transceiver module 1420 is also used to output the first identifier and data from the logical pipe under the control of the dequeue command.

[0164] In a possible embodiment, the transceiver module 1420 is specifically used to receive a storage space allocation command, and the storage space allocation command is used to indicate: apply for a target storage space in the storage space corresponding to the first logical position. The processing module 1410 is specifically used to apply for a target storage space in the storage space corresponding to the first logical position under the control of the storage space allocation command.

[0165] In a possible embodiment, the storage space allocation command is also used to indicate: a second identifier is set in the target storage space, and the second identifier is used to indicate that data is stored in the target storage space. The processing module 1410 is also used to set the second identifier in the target storage space under the control of the storage space allocation command. When data is moved from the target storage space, the transceiver module 1420 is also used to receive a storage space release command, and the storage space release command is used to indicate the release of the target storage space, and the second identifier is set to a third identifier, and the third identifier is used to indicate that the target storage space has been released. The processing module 1410 is also used to release the target storage space under the control of the storage space release command, and set the second identifier to the third identifier.

[0166] In a possible embodiment, the first logical position corresponds to a first memory, the second logical position corresponds to a second memory, both the first memory and the second memory are coupled to the execution unit, and the first memory and / or the second memory are located inside the data processing device.

[0167] Exemplarily, the first memory may be located inside the data processing device, and the second memory may be located outside the data processing device, or the first memory may be located outside the data processing device, and the second memory may be located inside the data processing device, or both the first memory and the second memory may be located inside the chip.

[0168] In a possible embodiment, the first memory and the second memory are located inside the data processing device, and the first memory and the second memory are the same memory.

[0169] In a possible embodiment, the processing module 1410 and the transceiver module 1420 may be integrated together and referred to as an execution unit.

[0170] Optionally, the type of the execution unit may include MTE, CUBE, VEC, fixed tube, etc. The embodiment of the present application does not limit the specific type of the execution unit.

[0171] The data processing device provided in the embodiment of the present application realizes data transmission through logical positions. When data is transmitted from the second logical position to the first logical position, the first corresponding relationship between the data and the second logical position is changed to the second corresponding relationship between the data and the first logical position to indicate that the data transmission is completed. It can be understood that when data transmission is performed, it is not necessary to consider the transmission of data between actual physical devices. Therefore, when the data transmission method is used to achieve synchronization between data, developers can pre-define the corresponding relationship between logical positions and physical devices when developing operators, and develop operators based on logical positions. When the architecture of the chip changes, by redefining the corresponding relationship between logical positions and physical devices, data can continue to be transmitted and synchronization can be achieved in the chip of the new architecture through the operator without the need to redevelop new operators, which can reduce development costs.

[0172] like Fig.15 As shown, the embodiment of the present application further provides an electronic device 1500, the electronic device 1500 includes a processor 1510, and a data processing device 1520 coupled to the processor 1510, the structure of the data processing device 1520 can be as described above Fig.14 The structure of the data processing device 1400 is shown.

[0173] In a possible embodiment, the processor 1510 may be a central processing unit (CPU).

[0174] Optionally, the type of the electronic device 1500 may include smart home devices, smart terminal devices, autonomous driving devices, and servers, etc. The embodiments of the present application do not limit the specific type of the electronic device.

[0175] Based on this, an embodiment of the present application further provides a computer-readable storage medium, in which a computer-executable instruction is stored. When at least one processor in an electronic device executes the computer-executable instruction, the electronic device executes Fig.12 and Fig.13 The steps in the data transmission method shown in any of the accompanying drawings.

[0176] The above detailed description of the data transmission method and the analysis of beneficial effects can be correspondingly referred to the data processing device 1400, the electronic device 1500 and the computer-readable storage medium, and the embodiments of the present application will not be repeated here.

[0177] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A data transmission method, characterized in that: Applied in a data processing device, the method comprises: Applying for target storage space in the storage space corresponding to the first logical location; transferring the data stored in the storage space corresponding to the second logical position to the target storage space; The first corresponding relationship between the data and the second logical position is changed to a second corresponding relationship between the data and the first logical position.

2. The method according to claim 1, characterized in that The transferring the data stored in the storage space corresponding to the second logical position to the target storage space includes: creating a logical pipe between the first logical location and the second logical location; Inputting the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipeline, wherein the first identifier is used to determine whether the data transfer to the target storage space is completed; The first identifier and the data are output from the logical pipeline.

3. The method according to claim 2, characterized in that The first identifier is located after the data and adjacent to the data, and the changing the first corresponding relationship between the data and the second logical position to the second corresponding relationship between the data and the first logical position includes: When the first identifier is output from the virtual exit of the logical pipeline, it is determined that the data is transmitted to the target storage space, and the first corresponding relationship between the data and the second logical location is changed to a second corresponding relationship between the data and the first logical location.

4. The method according to claim 2 or 3, characterized in that: The creating a logical pipe between the first logical location and the second logical location includes: receiving a create logical pipe command, wherein the create logical pipe command is used to instruct to create the logical pipe according to the first logical position and the second logical position; The logical pipe is created under the control of the create logical pipe command.

5. The method according to any one of claims 2 to 4, characterized in that: The step of inputting the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipeline includes: receiving an enter queue command, the enter queue command being used to instruct: inputting data stored in a storage space corresponding to the first identifier and the second logical position into the logical pipeline; Under the control of the enter queue command, the data stored in the storage space corresponding to the first identifier and the second logical position is input into the logical pipeline.

6. The method according to any one of claims 2 to 5, characterized in that: Outputting the first identifier and the data from the logic pipeline includes: receiving a dequeue command, wherein the dequeue command is used to instruct: outputting the first identifier and the data from the logical pipeline; The first identifier and the data are output from the logical pipe under the control of the dequeue command.

7. The method according to any one of claims 1 to 6, characterized in that The applying for a target storage space in the storage space corresponding to the first logical position includes: receiving a storage space allocation command, wherein the storage space allocation command is used to instruct: applying for the target storage space in the storage space corresponding to the first logical position; Under the control of the storage space allocation command, the target storage space is applied for in the storage space corresponding to the first logical location.

8. The method according to claim 7, characterized in that The storage space allocation command is further used to indicate: setting a second identifier in the target storage space, the second identifier being used to indicate that data is stored in the target storage space; the method further includes: Under the control of the storage space allocation command, setting the second identifier in the target storage space; When the data is moved from the target storage space; receiving a storage space release command, the storage space release command being used to instruct the target storage space to be released, and setting the second identifier to a third identifier, the third identifier being used to indicate that the target storage space has been released; Under the control of the storage space release command, the target storage space is released, and the second identifier is set to the third identifier.

9. The method according to any one of claims 1 to 8, characterized in that The first logical position corresponds to a first memory, and the second logical position corresponds to a second memory; The first memory and / or the second memory is located inside the data processing device.

10. The method according to claim 9, characterized in that The first memory and the second memory are located inside the data processing device, and the first memory and the second memory are the same memory.

11. A data processing device, characterized in that: The data processing device comprises a processing module and a transceiver module; The processing module is used to apply for a target storage space in the storage space corresponding to the first logical position; The transceiver module is used to transmit the data stored in the storage space corresponding to the second logical position to the target storage space; The processing module is further used to change the first corresponding relationship between the data and the second logical position to a second corresponding relationship between the data and the first logical position.

12. The device according to claim 11, characterized in that The processing module is specifically configured to create a logical pipeline between the first logical location and the second logical location; The transceiver module is specifically used to input the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipeline, and the first identifier is used to determine whether the data transmission to the target storage space is completed; The transceiver module is further used to output the first identifier and the data from the logical pipeline.

13. The device according to claim 12, characterized in that The first identifier is located after the data and adjacent to the data; The processing module is specifically used to determine that the data is transmitted to the target storage space when the first identifier is output from the virtual exit of the logical pipeline, and change the first corresponding relationship between the data and the second logical position to the second corresponding relationship between the data and the first logical position.

14. The device according to claim 12 or 13, characterized in that The transceiver module is specifically used to receive a create logical pipe command, where the create logical pipe command is used to instruct to create the logical pipe according to the first logical position and the second logical position; The processing module is specifically used to create the logical pipeline under the control of the create logical pipeline command.

15. The device according to any one of claims 12 to 14, characterized in that The transceiver module is specifically used to receive an enter queue command, where the enter queue command is used to instruct: input the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipeline; The transceiver module is further used to input the data stored in the storage space corresponding to the first identifier and the second logical position into the logical pipeline under the control of the enter queue command.

16. The device according to any one of claims 12 to 15, characterized in that The transceiver module is specifically used to receive a dequeue command, where the dequeue command is used to instruct: output the first identifier and the data from the logical pipeline; The transceiver module is further configured to output the first identifier and the data from the logical pipe under the control of the dequeue command.

17. The device according to any one of claims 11 to 16, characterized in that The transceiver module is specifically used to receive a storage space allocation command, wherein the storage space allocation command is used to instruct: applying for the target storage space in the storage space corresponding to the first logical position; The processing module is specifically configured to apply for the target storage space in the storage space corresponding to the first logical position under the control of the storage space allocation command.

18. The device according to claim 17, characterized in that The storage space allocation command is further used to instruct: setting a second identifier in the target storage space, the second identifier being used to indicate that data is stored in the target storage space; The processing module is further configured to set the second identifier in the target storage space under the control of the storage space allocation command; When the data is moved from the target storage space; The transceiver module is further used to receive a storage space release command, the storage space release command is used to instruct to release the target storage space, and set the second identifier to a third identifier, the third identifier is used to indicate that the target storage space has been released; The processing module is further configured to release the target storage space and set the second identifier as the third identifier under the control of the storage space release command.

19. The device according to any one of claims 11 to 18, characterized in that The first logical position corresponds to a first memory, and the second logical position corresponds to a second memory; The first memory and / or the second memory is located inside the data processing device.

20. The device according to claim 19, characterized in that The first memory and the second memory are located inside the data processing device, and the first memory and the second memory are the same memory.

21. An electronic device, characterized in that: The electronic device comprises a processor and a data processing device coupled to the processor, wherein the data processing device is the data processing device according to any one of claims 11-20.

22. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed on an electronic device, the electronic device executes the data transmission method according to any one of claims 1 to 10.

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