Key data processing system, method, device, medium and program product

Abstract

The invention relates to the technical field of data storage, and discloses a key data processing system, method and device, a medium and a program product, the key data processing system comprises a power failure monitoring module, a power failure processing module, a key data extraction module, a hardware acceleration module, a volatile memory and a memory disk; according to different monitoring results of the power-down monitoring module and the state of the key data recording switch, the key data extraction module and the power-down data processing module package corresponding data to be recorded or protected and then move the packaged data to a specific address of the volatile memory; and the recorded data or the protected data are read from the corresponding address of the volatile memory through the hardware acceleration module. The key data processing system is high in transmission rate and sufficient in storage space, can realize two functions of power-down key data protection and key data recording, and can be automatically switched to a power-down key data protection working state from a key data recording working state according to a use scene in a working process.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a key data processing system, method, device, medium and program product. Background Art

[0002] During system operation, recording key data has significant benefits in maintaining system stability, optimizing performance, troubleshooting, and future decision-making planning. However, existing solutions may have a certain impact on system performance while recording data, such as insufficient data bandwidth and insufficient storage space. Moreover, when the system loses power, the backup power supply can only continue to work for a limited time. For systems with a large amount of data to be protected, the ordinary data transmission rate in the existing power-off protection solution is difficult to meet this requirement, which can easily lead to the external receiving tool failing to write the data recorded by the capture chip into the hard disk space in time, resulting in the loss of transmission record data, which ultimately affects system analysis.

[0003] Therefore, there is an urgent need for a key data recording and protection system with high transmission rate and sufficient storage space, which can realize the two functions of power-off key data protection and key data recording. Summary of the invention

[0004] In view of this, the present application provides a key data processing system, method, device, medium and program product, which can realize two functions of power-off key data protection and key data recording, and can automatically switch from key data recording to power-off key data protection working state according to the usage scenario during operation. The technical solution is as follows.

[0005] In a first aspect, the present invention provides a key data processing system, which includes: a power failure monitoring module, a power failure processing module, a key data extraction module, a hardware acceleration module, a volatile memory and a storage disk.

[0006] The power-off monitoring module is used to monitor the power supply voltage and the state of the data recording switch, and generate a data protection instruction when the power supply voltage is less than a preset voltage; and generate a data recording instruction when the power supply voltage is not less than a preset voltage and the data recording switch is in an on state;

[0007] The key data extraction module is used to obtain the data to be recorded when receiving the data recording instruction; package the data to be recorded to obtain the recording data packet and store it in the first target storage block of the volatile memory, and generate a first command to send to the hardware acceleration module;

[0008] The power-off processing module is used to obtain the data to be protected when receiving the data protection instruction; the data to be protected includes an end tag, and the end tag is used to indicate whether the data to be protected is complete; the data to be protected is packaged to obtain a protection data packet and then stored in the second target storage block of the volatile memory, and a second command is generated and sent to the hardware acceleration module;

[0009] The hardware acceleration module is used to read the record data packet from the first target storage block of the volatile memory through the storage disk when the first command is received; and read the protection data packet from the second target storage block of the volatile memory through the storage disk when the second command is received.

[0010] A key data processing system provided by the present invention has the following advantages:

[0011] The key data processing system of the present invention includes two functions: key data recording and key data protection during power failure. The power supply voltage and the data recording switch state are monitored in real time by a power failure monitoring module, and the key data recording function or the power failure data protection function is started according to the monitoring result and the data recording switch state. When the power supply voltage is greater than or equal to the preset threshold voltage, it indicates that the system is working normally. At this time, if the data recording switch is in the on state, the key data extraction module records the key data. The key data extraction module obtains the key data from the upstream subunit module and packages it to obtain a data recording package, stores the data recording package in the first storage block of the volatile memory, and sends a first command to the hardware acceleration module so that the hardware acceleration module reads the data recording package from the first storage block of the volatile memory and moves the data recording package to the storage disk to complete the recording of the key data. When the power supply voltage is less than the preset threshold voltage, it indicates that the system is powered off, and it is necessary to stop the key data recording process, start the key data protection process, and the power failure processing module protects the key data. The power-off processing module obtains the data to be protected with an end tag from the upstream sub-unit module and packages it to obtain a data protection package. The end tag indicates whether the data is continuous and complete, and only the continuous and complete key data is protected. The data protection package is stored in the second storage block of the volatile memory, and a second command is sent to the hardware acceleration module to enable the hardware acceleration module to read the data record package from the second storage block of the volatile memory and move the data record package to the storage disk to complete the protection of the key data. The key data processing system has a high transmission rate and sufficient storage space. It records the key data to the storage disk during normal operation and quickly moves the key data to the storage disk when the power is off. It can realize the two functions of power-off key data protection and key data recording, and can automatically switch from key data recording to power-off key data protection working state according to the monitoring result of the power supply voltage during operation.

[0012] In an optional embodiment, the hardware acceleration module is also used to: when receiving the first command, determine whether the first target storage block of the volatile memory has been released; if the first target storage block of the volatile memory has not been released, send a shielding instruction to the key data extraction module, so that the key data extraction module stops storing the record data packet to the first target storage block of the volatile memory.

[0013] When the data recording function of the key data processing system of the present invention records key data, the key data extraction module will send the storage block ID for data recording to the hardware acceleration module. The hardware acceleration module determines whether the storage block for key data recording is available through the received storage block ID information. If it is not available, it will stop writing the key data into the volatile memory.

[0014] In an optional implementation, the power failure monitoring module is further used to: when the power supply voltage is less than a preset voltage, switch to a backup power supply for power supply.

[0015] In an optional embodiment, the key data processing system also includes: an arbitration module, which is used to arbitrate the data recording instruction when it receives the data recording instruction and generate a first arbitration result; the first arbitration result is used to instruct the key data extraction module to obtain the data to be recorded from the corresponding upstream sub-unit module to generate a recording data packet.

[0016] In an optional implementation manner, the arbitration module is further used for:

[0017] When a data protection instruction is received, the data protection request in the data protection instruction is arbitrated, and a second arbitration result is generated according to the end tag; the second arbitration result is used to instruct the power-off processing module to obtain continuous data to be protected from the corresponding upstream sub-unit module to generate a protection data packet.

[0018] The key data processing system of the present invention also includes an arbitration module, which is used to generate corresponding arbitration results according to data recording instructions or data protection instructions so that the key data extraction module or power-off processing module obtains corresponding data from the upstream sub-unit module according to the arbitration results to generate corresponding data packets.

[0019] In a second aspect, the present invention provides a key data processing method, which is applied to the above-mentioned key data processing system, and the method comprises:

[0020] Acquire the power supply voltage and the data recording switch state; when the power supply voltage is not less than the preset voltage and the data recording switch is in the on state, acquire the recording data packet; store the recording data packet in the first target storage block of the volatile memory; read the recording data packet from the first target storage block of the volatile memory through the storage disk.

[0021] In an optional implementation, the key data processing method further includes:

[0022] When the power supply voltage is less than the preset power supply, a protection data packet is obtained; the protection data packet is stored in a second target storage block of the volatile memory; and the protection data packet is read from the second target storage block of the volatile memory through the storage disk.

[0023] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the key data processing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0024] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the key data processing method of the first aspect or any corresponding embodiment thereof.

[0025] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the key data processing method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 It is a structural diagram of a key data processing system provided by an embodiment of the present invention.

[0028] Figure 2 It is a flowchart of a key data recording method provided by an embodiment of the present invention.

[0029] Figure 3 It is a flowchart of a key data protection method provided by an embodiment of the present invention.

[0030] Figure 4It is a schematic diagram of the processing flow of the NVMe command provided in an embodiment of the present invention.

[0031] Figure 5 It is a logic block diagram of a key data recording process according to an exemplary embodiment.

[0032] Figure 6 It is a logic block diagram of a key data protection process according to an exemplary embodiment.

[0033] Figure 7 It is a structural schematic diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0035] It should be understood that the "indication" mentioned in the embodiments of the present application can be a direct indication, an indirect indication, or an indication of an association relationship. For example, A indicates B, which can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, and B can be obtained through C; it can also mean that there is an association relationship between A and B.

[0036] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0037] In an embodiment of the present application, "predefinition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including a terminal device and a network device). The present application does not limit its specific implementation method.

[0038] First, the terms involved in this application are introduced.

[0039] NVMe: non-volatile memory express, i.e. non-volatile memory host controller interface specification; SQ: Submission Queue, i.e. submission queue; CQ: Completion Queue, i.e. completion queue; DDR: Double Data Rate, i.e. double data rate synchronous dynamic random access memory; AXI: Advanced Extensible Interface, i.e. advanced extensible interface, an on-chip bus proposed by ARM for high performance, high bandwidth and low latency; EEPROM: Electrically Erasable Programmable read only memory, i.e. electrically erasable programmable read only memory; RAM: Random Access Memory. sq_cmd: sq command word; cq_reply: cq reply word; record_pkt: record data packet; protect_data: protect data; sq_entry: sq entry; cq_entry: cq entry; sq_doorbell: sq doorbell; cq_doorbell: cq doorbell.

[0040] During system operation, recording key data has significant benefits in maintaining system stability, optimizing performance, troubleshooting, and future decision-making planning. However, data recording may have a certain impact on system performance. In application scenarios that require high-performance operation, it is necessary to weigh the relationship between data recording and system performance. Therefore, an efficient data recording method is needed to meet the current demand for large amounts of data recording. Examples of existing data recording methods include: using on-chip memories such as SRAM to record on-chip data, the chip can send the data to be recorded to a remote server or storage device through a network interface, and using Coresight technology for data recording.

[0041] These existing key data recording methods, if there is too much data to record, there will be a phenomenon that new data will overwrite old data after the RAM is full, resulting in a large amount of recorded data loss; sending recorded data to the remote end through the network interface is only available to systems that support the network interface; the Coresight architecture data bandwidth is limited by the sampling frequency of the external receiving tool. For the scenario where multiple CPU cores are recording data simultaneously, since each core may generate data that needs to be recorded in each clock cycle during operation, and the data path finally needs to merge all the data sources that need to be recorded into one data before outputting it to the outside of the chip, there is a high probability that insufficient bandwidth will cause some data links to be back-pressured. In addition, if there is too much data to record, there will be a phenomenon that new data will overwrite old data after the RAM is full, resulting in a large amount of recorded data loss.

[0042] In addition, chip power-off protection plays an important role in ensuring data security, ensuring stable system operation, and ensuring system recoverability. Therefore, it is necessary to design reasonable protection logic to ensure that necessary data can be protected during power-off. Some existing power-off protection methods are given as examples: using an uninterruptible power supply to provide a stable power supply to the chip system to protect data from loss, using EEPROM or other non-volatile memory to store important data in the chip or system, and using professional power-off protection chips.

[0043] Since the backup power supply can only keep working for a limited time when the system loses power, this method has high requirements for data transmission rate. For systems with a large amount of data that needs to be protected when the power is off, these existing power-off protection methods are difficult to meet this demand. When analyzing a multi-core complex system, it is very likely that the data recording rate inside the entire chip is relatively fast. Although the chip can output normally to the outside and the external receiving tool can also receive it normally, the writing rate to the hard disk is relatively slow, resulting in the external receiving tool being unable to write to the hard disk space in time after receiving the captured chip recording data, resulting in the loss of transmission recording data, which ultimately affects the system analysis.

[0044] In view of the shortcomings of the above-mentioned existing key data recording and power-off protection methods, a key data protection and recording method based on the NVMe protocol is introduced. NVMe is a host controller interface for PCIE-based solid-state drives, which has significant advantages in performance, power consumption, compatibility and management efficiency. NVMe is specially designed for non-volatile storage such as NAND and flash memory, and can meet the needs of high-speed storage media. The advantage of NVMe is that it can utilize parallel data paths, thereby providing better performance in acceleration. It enables existing applications as well as new applications to work more efficiently. In addition, the advantages of NVMe also include low latency, low power consumption and high compatibility.

[0045] Therefore, the embodiment of the present invention provides a key data processing system, which can realize two functions: power failure key data protection and key data recording. When the system is working normally, the key data is recorded to the storage disk, and when the system is powered off, the key data is quickly moved to the storage disk. In the working process, according to the monitoring result of the power supply voltage, the key data recording state can be automatically switched to the power failure key data protection working state. The framework structure diagram of the key data processing system is shown in FIG. Figure 1 As shown, as used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceivable.

[0046] The key data processing system comprises: a power failure monitoring module, a power failure processing module, a key data extraction module, a hardware acceleration module, a volatile memory and a storage disk.

[0047] The power-off monitoring module is used to monitor the power supply voltage and the data recording switch state. When the power supply voltage is less than a preset voltage, a data protection instruction is generated; when the power supply voltage is not less than a preset voltage and the data recording switch is in an on state, a data recording instruction is generated.

[0048] Optionally, when the power failure monitoring module detects that the power supply voltage is less than a preset voltage, it switches to a backup power supply to ensure that the data protection process can be completed smoothly.

[0049] Optionally, the key data processing system further includes an arbitration module, which is used to perform arbitration when receiving a data recording instruction or a data protection instruction, and generate an arbitration result so that the key data extraction module or the power-off processing module obtains corresponding data from the upstream sub-unit module according to the arbitration result. Specifically, the recorded data is arbitrated according to the data recording instruction issued by the power-off monitoring module, so that the key data recording module obtains the key data from the corresponding upstream sub-unit module according to the arbitration result of the recorded data to generate a data recording packet; or the protection data is arbitrated according to the data protection instruction, so that the power-off processing module obtains continuous data to be protected from the corresponding upstream sub-unit module according to the arbitration result of the protection data to generate a complete protection data packet.

[0050] The key data extraction module is used to obtain the data to be recorded when receiving a data recording instruction; package the data to be recorded to obtain a recording data packet and store it in the first target storage block of the volatile memory, and generate a first command to send to the hardware acceleration module.

[0051] Specifically, the data record packet includes key data to be recorded, a timestamp and header information. The first command includes the ID information of the first target storage block, and the hardware acceleration module determines whether the first target storage block is available according to the ID information.

[0052] A power-off processing module is used to obtain the data to be protected when receiving a data protection instruction; the data to be protected includes an end tag, and the end tag is used to indicate whether the data to be protected is complete; the data to be protected is packaged to obtain a protection data packet and then stored in the second target storage block of the volatile memory, and a second command is generated and sent to the hardware acceleration module.

[0053] Specifically, the data protection package includes the key data to be protected, a timestamp and label information. The label information is the data end mark. When the power-off processing module obtains the data to be protected from the upstream sub-unit module, it will use the label information as a basis to ensure that the acquired data to be protected is continuous and complete, thereby generating a complete protection data packet.

[0054] The hardware acceleration module is used to read the record data packet from the first target storage block of the volatile memory through the storage disk when receiving the first command; and read the protection data packet from the second target storage block of the volatile memory through the storage disk when receiving the second command.

[0055] Optionally, the hardware acceleration module is also used to: when receiving the first command, determine whether the first target storage block of the volatile memory has been released; if the first target storage block of the volatile memory has not been released, send a shielding instruction to the key data extraction module, so that the key data extraction module stops storing the record data packet in the first target storage block of the volatile memory. Specifically, the key data extraction module sends the storage block ID for data recording to the hardware acceleration module, and the hardware acceleration module determines whether the storage block for key data recording is available through the received storage block ID information. If it is not available, it stops writing the key data into the volatile memory.

[0056] Wherein, the hardware acceleration module may be an NVMe hardware acceleration module, and the storage disk may be an NVMe disk. At this time, the first command is an NVMe command for recording data, and the second command is an NVMe command for protecting data. When the NVMe hardware acceleration module receives an NVMe command, it generates an NVMe command frame according to the NVMe protocol requirements, manages it according to the submission queue requirements of the NVMe disk, delivers a submission doorbell to the NVMe disk, notifies the NVMe disk to read the data packet from the corresponding position of the volatile memory, and parses the completion entry returned by the disk, delivers the completion doorbell and generates a response as required and sends it to the corresponding upstream module.

[0057] It should be noted that the above-mentioned NVMe hardware acceleration module and NVMe disk based on the NVMe protocol are an application scenario of the solution involved in the embodiment of the present application. The solution involved in the embodiment of the present application can also be executed by other protocols that support the various functions involved in the embodiment of the present application. Hardware acceleration modules and storage disks based on multiple interface protocols can be used for data transmission, such as AHCI hardware acceleration modules and SATA storage devices based on the AHCI (Advanced Host Controller Interface) protocol for data transmission; SCSI (Small Computer System Interface) protocol can also be used to perform data transmission with hard disk drives of various types and specifications, including traditional mechanical hard disks and solid-state hard disks. However, the SATA interface protocol is suitable for mechanical hard disks with low performance, but as the performance of SSDs gradually increases, traditional standards are no longer applicable, and thus become a major bottleneck limiting SSDs. In addition, NVMe's read and write performance is nearly 6 times higher than AHCI / SATA, and 2 to 3 times higher than AHCI / PCIe SSD read and write performance.

[0058] Therefore, the use of NVMe hardware acceleration modules and NVMe disks based on the NVMe protocol can better record and protect critical data.

[0059] The key data processing system of the present invention includes two functions: key data recording and key data protection during power failure. The power supply voltage and the data recording switch state are monitored in real time by a power failure monitoring module, and the key data recording function or the power failure data protection function is started according to the monitoring result and the data recording switch state. When the power supply voltage is greater than or equal to the preset threshold voltage, it indicates that the system is working normally. At this time, if the data recording switch is in the on state, the key data extraction module records the key data. The key data extraction module obtains the key data from the upstream subunit module and packages it to obtain a data recording package, stores the data recording package in the first storage block of the volatile memory, and sends a first command to the hardware acceleration module so that the hardware acceleration module reads the data recording package from the first storage block of the volatile memory and moves the data recording package to the storage disk to complete the recording of the key data. When the power supply voltage is less than the preset threshold voltage, it indicates that the system is powered off, and it is necessary to stop the key data recording process, start the key data protection process, and the power failure processing module protects the key data. The power-off processing module obtains the data to be protected with an end tag from the upstream sub-unit module and packages it to obtain a data protection package. The end tag indicates whether the data is continuous and complete, and only the continuous and complete key data is protected. The data protection package is stored in the second storage block of the volatile memory, and a second command is sent to the hardware acceleration module to enable the hardware acceleration module to read the data record package from the second storage block of the volatile memory and move the data record package to the storage disk to complete the protection of the key data. The key data processing system has a high transmission rate and sufficient storage space. It records the key data to the storage disk during normal operation and quickly moves the key data to the storage disk when the power is off. It can realize the two functions of power-off key data protection and key data recording, and can automatically switch from key data recording to power-off key data protection working state according to the monitoring result of the power supply voltage during operation.

[0060] The key data processing system in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0061] On the basis of the above, this embodiment further proposes a key data processing method, which is applied to the above key data processing system. The method includes a key data recording method and a key data protection method.

[0062] The process of key data recording method is as follows Figure 2 As shown, the following steps are included.

[0063] S201, obtaining a power supply voltage and a data recording switch state, and when the power supply voltage is not less than a preset voltage and the data recording switch is in an on state, obtaining a recording data packet;

[0064] Specifically, in step S201, when the power supply voltage is not less than the preset voltage, it indicates that the system is operating normally, and the key data recording process is started. A data recording instruction is sent to the upstream subunit module and the key data extraction module, so that the key data extraction module obtains the key data to be recorded and packages it to obtain a data recording package.

[0065] S202: Store the recorded data packet in a first target storage block of the volatile memory.

[0066] Specifically, in step S202, the key data extraction module stores the acquired data record package in a specific data storage block of the volatile memory, and generates a first command containing the data storage block ID and sends it to the NVMe hardware acceleration module, so that the hardware acceleration module determines whether the data storage block is available, and the first command is an NVMe command for recording data.

[0067] S203: Read the record data packet from the first target storage block of the volatile memory through the storage disk.

[0068] Specifically, in step S203, the hardware acceleration module moves the data record packet from the specific data storage block of the volatile memory to the storage disk according to the received first command.

[0069] The process of key data protection methods is as follows Figure 3 As shown, the following steps are included.

[0070] S301, obtaining a power supply voltage and comparing it with a preset voltage, and when the power supply voltage is less than the preset power supply, obtaining a protection data packet.

[0071] Specifically, in step 3201, when the power supply voltage is less than the preset voltage, it indicates that the system is powered off, and the key data protection process is started. A data protection instruction is sent to the upstream sub-unit module and the power-off processing module, so that the power-off processing module obtains the key data to be protected and packages it to obtain a data protection package. It should be noted that when obtaining the key data to be protected, the end tag is used to determine whether the obtained data is continuous and complete to ensure that a complete data protection package is obtained.

[0072] S302: Store the protection data packet in a second target storage block of the volatile memory.

[0073] Specifically, in step S302, the power-off processing module stores the acquired data protection package in a specific data storage block of the volatile memory, and sends a second command to the hardware acceleration module, where the second command is an NVMe command to protect the data.

[0074] S303: Read the protection data packet from the second target storage block of the volatile memory through the storage disk.

[0075] Specifically, in step S303, the hardware acceleration module moves the data record packet from the specific data storage block of the volatile memory to the storage disk according to the received second command.

[0076] To sum up, the key data recording method and key data protection method provided in this embodiment are applied to the above-mentioned key data processing system, and different functions are selected according to the real-time monitored power supply voltage. The key data is recorded to the storage disk during normal operation, and the key data is quickly moved to the storage disk when the power is off.

[0077] The following will use an example to illustrate the key data processing system and method based on the key data processing system and method provided in the above embodiments.

[0078] Combination Figure 1 The key data processing system shown in the example includes: the upstream is the sub-unit that needs to perform key data recording or data protection, the main processing modules are the arbitration module, the power-off monitoring module, the power-off processing module, the key data extraction module and the hardware acceleration module (taking the NVMe hardware acceleration module as an example), and the downstream is the volatile memory (taking DDR as an example in this example) and the storage disk (taking the NVMe disk as an example).

[0079] Among them, the NVMe hardware acceleration module is based on the processing flow of NVMe commands, constructs the provided command word into sq_entry as required, manages sq_entry and delivers sq_doorbell according to the SQ queue requirements of the NVMe device, parses cq_entry, delivers cq_doorbell, and returns a response as required. Sq_proc is a processing module for SQ services, and cq_proc is a processing module for CQ services. Specifically, the processing flow of NVMe commands is as follows: Figure 4As shown, the following steps are included: the host writes a command to a submission queue (SQ); the host updates the doorbell of the SQ tail pointer and notifies the controller; the controller receives the notification and retrieves the command; the controller executes the command; after the execution is completed, the execution result completion queue entry (CQE) is written into the completion queue (CQ), and the CQ tail pointer is modified; the controller sends an interrupt notification that the command execution is completed; after receiving the interrupt, the host checks the command completion status; the host processes the command execution result and updates the CQ head pointer doorbell.

[0080] Key data recording process such as Figure 5 As shown, the following steps are included.

[0081] In response to the data recording instruction issued by the power-off monitoring module, the system issues a key data recording request to the subunit and the key data extraction module. The subunit writes the internal cache according to the predetermined packet format. For example, two caches can be prepared and the cache is written using the ping-pong method; after the subunit caches the complete data packet, it initiates a key data recording arbitration request. The arbitration module arbitrates the key data recording requests of each subunit and generates an arbitration result. According to the arbitration result, the key data extraction module reads the data to be recorded from the corresponding subunit, and packages the data to be recorded, adding timestamps and header information. The recorded data packet is then written to the storage block corresponding to the valid ID in the DDR. When the key data extraction module writes the data record package into the storage block, it constructs a command word and sends it to the NVMe hardware acceleration module. The command word carries the ID information of the record data storage block of DDR; the sq_proc in the NVMe hardware acceleration module generates a sq_entry according to the command word, and the sq_entry retains the ID information of the record data storage block of DDR; the sq_proc in the NVMe hardware acceleration module writes the sq_entry into DDR; the sq_proc in the NVMe hardware acceleration module generates a sq_doorbell and sends it to the NVMe disk; the NVMe disk will go to the corresponding position of DDR to get the recorded data according to the sq_doorbell.

[0082] It should be noted that the key data cache of DDR supports block storage, and the cache storing record data in DDR is divided into multiple storage blocks of the same size according to different IDs. Whether the data storage block is valid is determined by the NVMe hardware acceleration module. Specifically, the cq_proc in the NVMe hardware acceleration module receives the cq_entry returned by the disk, and can parse the ID information of the record data storage block of DDR from the cq_entry; the cq_proc in the NVMe hardware acceleration module generates cq_reply according to cq_entry and sends it to the key data extraction module; the cq_proc in the NVMe hardware acceleration module generates cq_doorbell and sends it to the NVMe disk; the key data extraction module obtains the ID information of the released DDR storage block according to cq_reply, and when generating the command word, it can be known whether the ID corresponding to the DDR storage block is available; if all the cache IDs storing record data in DDR are not released, the write signal of the key data extraction module to DDR is shielded after the data record packet is generated, and the complete data record packet will continue to be written only when there is an available record data cache block in DDR.

[0083] Key data protection processes such as Figure 6 As shown, the following steps are included.

[0084] In response to the data protection instruction issued by the power-off monitoring module, the backup power supply is turned on, and the system issues a critical data protection request to the subunit and the power-off processing module. After receiving the critical data protection request, the subunit will stop initiating the critical data record arbitration request; cache the data to be protected, and wait for the first arbitration enable, that is, when the power-off protection request is detected, initiate the power-off protection arbitration request. The arbitration module arbitrates the power-off protection requests of each subunit. When the first arbitration result is generated, the arbitration enable is pulled low. It is necessary to make the arbitration enable effective according to the protection data end flag of the subunit read in the next step to ensure that the power-off protection data of the subunit is continuous and complete. The power-off processing module obtains the arbitration result, reads the power-off protection data inside the subunit, and performs packetization, adding timestamp and tag information. The tag information is the data end flag to determine whether a complete data packet to be protected is received. After the packetization is completed, the data protection packet is written to a specific address of the DDR, and a command word is constructed and sent to the NVMe hardware acceleration module. The sq_proc in the NVMe hardware acceleration module generates sq_entry according to the command word; the sq_proc in the NVMe hardware acceleration module writes sq_entry into DDR; the sq_proc in the NVMe hardware acceleration module generates sq_doorbell and sends it to the NVMe disk; the NVMe disk will go to the corresponding position of DDR to get the power-off protection data according to sq_doorbell; the cq_proc in the NVMe hardware acceleration module receives and parses cq_entry; the cq_proc in the NVMe hardware acceleration module generates cq_doorbell and sends it to the nvme disk; the NVMe hardware acceleration module generates a power-off protection end flag.

[0085] In summary, the key data recording method and key data protection method provided in this example are based on the above-mentioned key data processing system and key data processing method, and select different functions according to the real-time monitored power supply voltage and data recording switch state, so that the key data is recorded to the NVMe disk during normal operation, and the key data is quickly moved to the NVMe disk when the power is off. The low latency and high bandwidth data transmission advantages of the NVMe protocol are utilized to quickly move key data to the disk for protection when the power is off, effectively improving the power-off protection efficiency. At the same time, in scenarios where key data needs to be recorded continuously, the data can be written to the corresponding hard disk space in a timely manner, solving the problem of low ordinary data transmission rate. Moreover, by moving the data that needs to be recorded to the NVMe disk, more key data can be stored. It supports automatic switching from key data recording to power-off key data protection working state according to the usage scenario during the working process.

[0086] The embodiment of the present invention also provides a computer device having the above Figure 1 See the key data processing system shown. Figure 7 , Figure 7is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphic information in a graphical user interface on an external input / output device (such as a display device coupled to an interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0087] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0088] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0089] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0090] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0091] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0092] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0093] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0094] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A key data processing system, characterized in that: The system includes: a power failure monitoring module, a power failure processing module, a key data extraction module, a hardware acceleration module, a volatile memory and a storage disk; The power-off monitoring module is used to monitor the power supply voltage and the state of the data recording switch, and generate a data protection instruction when the power supply voltage is less than a preset voltage; and generate a data recording instruction when the power supply voltage is not less than a preset voltage and the data recording switch is in an on state; The key data extraction module is used to obtain the data to be recorded when receiving the data recording instruction; package the data to be recorded to obtain the recording data packet and store it in the first target storage block of the volatile memory, and generate a first command to send to the hardware acceleration module; The power-off processing module is used to obtain the data to be protected when receiving the data protection instruction; the data to be protected includes an end tag, and the end tag is used to indicate whether the data to be protected is complete; the data to be protected is packaged to obtain a protection data packet and then stored in the second target storage block of the volatile memory, and a second command is generated and sent to the hardware acceleration module; The hardware acceleration module is used to read the record data packet from the first target storage block of the volatile memory through the storage disk when the first command is received; and read the protection data packet from the second target storage block of the volatile memory through the storage disk when the second command is received.

2. The key data processing system according to claim 1, characterized in that: The hardware acceleration module is further used for: When the first command is received, determining whether the first target storage block of the volatile memory has been released; If the first target storage block of the volatile memory is not released, a shielding instruction is sent to the key data extraction module, so that the key data extraction module stops storing the record data packet in the first target storage block of the volatile memory.

3. The key data processing system according to claim 1, characterized in that: The power failure monitoring module is also used for: When the power supply voltage is lower than the preset voltage, the backup power supply is switched to supply power.

4. The key data processing system according to claim 1, characterized in that: The system further comprises: The arbitration module is used to arbitrate the data recording instruction when receiving the data recording instruction and generate a first arbitration result; the first arbitration result is used to instruct the key data extraction module to obtain the data to be recorded from the corresponding upstream sub-unit module to generate the recording data packet.

5. The key data processing system according to claim 4, characterized in that: The arbitration module is further used for: When receiving the data protection instruction, arbitrating the data protection request in the data protection instruction, and generating a second arbitration result according to the end tag; The second arbitration result is used to instruct the power-off processing module to obtain continuous data to be protected from the corresponding upstream sub-unit module to generate the protection data packet.

6. A key data processing method, characterized in that: Applied to a critical data processing system as claimed in any one of claims 1 to 5, the method comprising: Get power supply voltage and data log switch status; When the power supply voltage is not less than a preset voltage and the data recording switch is in an on state, obtaining a recording data packet; storing the recorded data packet in a first target storage block of the volatile memory; The recorded data packet is read from a first target storage block of the volatile memory via the storage disk.

7. The key data processing method according to claim 6, characterized in that: The method further comprises: When the power supply voltage is less than a preset power supply, obtaining a protection data packet; storing the protection data packet in a second target storage block of the volatile memory; The protection data packet is read from a second target storage block of the volatile memory through the storage disk.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the key data processing method according to any one of claims 6 to 7 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the key data processing method according to any one of claims 6 to 7.

10. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the key data processing method according to any one of claims 6 to 7.

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