Programmable logic cluster and programmable logic device

Abstract

The embodiment of the invention provides a programmable logic cluster and a programmable logic device. The programmable logic cluster comprises a plurality of programmable logic units (CLB) arranged in an array form and a signal routing structure, wherein the signal routing structure comprises a transverse signal routing structure and a longitudinal signal routing structure, and the transverse signal routing structure is used for cascade connection between CLBs in the same column or cascade connection between the PLC and other PLCs in the transverse direction; and the longitudinal signal routing structure is used for cascade connection between the CLBs in different columns or cascade connection between the PLC and other PLCs in the longitudinal direction. Through the embodiment of the invention, the problem that the PLC wiring algorithm of the current programmable logic chip is complicated in the related technology is solved, and the effect of improving the logic function iteration efficiency is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuits, and in particular, to a programmable logic cluster and a programmable logic device. Background Art

[0002] With the rapid development of microelectronics and information technology, digital systems based on very large-scale integrated circuits (VLSI) have been widely used in various industries in the field of informatization. Modern VLSI mainly includes memory chips, application-specific integrated circuits (ASIC) and field programmable gate arrays (FPGA).

[0003] Embedded FPGA (eFPGA) can effectively combine the high performance of ASIC design and the flexibility of FPGA modules, and can overcome the problems existing in the use of traditional FPGA. Its internal programmable logic cluster (PLC) is a highly integrated digital circuit, which is often used to implement various logic functions in electronic systems. However, the current PLC in eFPGA has problems such as complex wiring algorithms. Therefore, how to design a PLC that meets multiple functional requirements and has a simple wiring algorithm is an urgent problem to be solved in the current programmable logic chip design technology. Summary of the invention

[0004] The embodiments of the present invention provide a programmable logic cluster and a programmable logic device to at least solve the problem of complex PLC wiring algorithms of current programmable logic chips in the related art.

[0005] According to one embodiment of the present invention, a programmable logic cluster PLC is provided, comprising: a plurality of programmable logic units CLB arranged in an array form, and a signal routing structure; wherein the signal routing structure comprises a horizontal signal routing structure and a vertical signal routing structure, the horizontal signal routing structure is used for cascading between the CLBs in the same column, or for cascading the PLC with other PLCs in the horizontal direction; the vertical signal routing structure is used for cascading between the CLBs in different columns, or for cascading the PLC with other PLCs in the vertical direction.

[0006] According to another embodiment of the present invention, a programmable logic device is provided, comprising: the programmable logic cluster in the above embodiment, an I / O interface part for connecting to an external I chip, and a random access memory for storing lookup table configuration values ​​in the programmable logic cluster.

[0007] Through the above-mentioned embodiment of the present invention, the programmable logic cluster is provided with a signal routing structure. The wiring algorithm of the signal routing structure is simple and can flexibly transmit signals between each PLC or CLB. Based on the signal routing structure, the transmission direction of the signal between the PLC or CLB can be transformed into different logic functions, that is, it has a faster logic function iteration speed; at the same time, since each PLC can realize a variety of more complex logic functions, when it is necessary to realize system-level functions, it is only necessary to design a wiring algorithm between multiple PLCs, and connect multiple PLCs through the signal routing structure. Compared with the traditional system-level function, which requires the design of a wiring algorithm for each CLB, the wiring algorithm in the embodiment of the present invention is simpler. Therefore, it can solve the problem of complex PLC wiring algorithms of current programmable logic chips in related technologies, thereby achieving the effect of improving the iteration efficiency of logic functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a programmable logic cluster PLC according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a connection method between an embedded FPGA and an IC according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a programmable logic unit structure according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of a structure of a CLB cascade to implement a six-input MUX selection function according to an embodiment of the present invention;

[0012] Figure 5 is a schematic structural diagram of a simplified CLB cascade for implementing a multi-bit adder function according to an embodiment of the present invention;

[0013] Figure 6 is a schematic diagram of a simplified CLB cascade structure for implementing a multi-bit counter function according to an embodiment of the present invention;

[0014] Figure 7 is a schematic structural diagram of a simplified CLB cascade for implementing a comparator function according to an embodiment of the present invention;

[0015] Figure 8 is a schematic diagram of the structure of the interface connection method between CLBs according to an embodiment of the present invention;

[0016] Fig. 9 is a schematic diagram of a horizontal signal routing structure and a vertical signal routing structure according to an embodiment of the present invention;

[0017] Fig.10It is a structural schematic diagram of a signal routing mode between horizontal CLBs within a PLC according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0019] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] To facilitate understanding of the technical solutions provided by the present invention, the relevant technologies involved in the embodiments of the present invention are explained below.

[0021] ASIC is an integrated circuit chip designed and manufactured specifically for specific applications. Unlike general-purpose IC chips, ASIC can implement multiple modules or functions in one chip, thereby reducing system complexity, improving performance, reducing power consumption and reducing size. The design process of ASIC requires in-depth understanding of the target application field, system-level design and optimization, and strict verification, testing and manufacturing processes. Therefore, ASIC has a long production cycle, high cost, and cannot be modified after production. Once any error is not detected before production, it is likely to cause ASIC tape-out failure and have a high production risk. Therefore, ASIC is generally only suitable for large-scale production and application fields with stable market demand.

[0022] FPGA is a general-purpose programmable logic device with a design that is closer to the underlying hardware architecture. It has a large amount of storage resources, DSP (Digital Signal Processing) resources, etc. It is good at data parallel computing, more flexible and low latency. At the same time, FPGA also has the characteristics of low power consumption, programmability and flexible design. Therefore, FPGA is widely used in many fields.

[0023] eFPGA refers to an FPGA that can be integrated into a SoC as an IP (intellectual property) module. It can effectively combine the high performance of ASIC design and the flexibility of FPGA modules. It has simple configuration and low power consumption, which can significantly reduce production costs. The PLC inside the eFPGA is a highly integrated digital circuit that is often used in electronic systems to implement various logic functions. It consists of multiple logic units, each of which can perform basic logic operations and state transition operations. The PLC has high flexibility and scalability, and can be customized and optimized according to different application scenarios. It is usually programmed in hardware description language (HDL) and supports the implementation of multiple digital signal processing algorithms and complex control strategies.

[0024] Figure 1 Schematic diagram of a programmable logic cluster PLC according to an embodiment of the present invention, Figure 1 As shown, the PLC includes: a plurality of programmable logic units CLB arranged in an array form, and a signal routing structure (i.e., a router); wherein the signal routing structure includes a horizontal signal routing structure and a vertical signal routing structure, the horizontal signal routing structure is used for cascading between the CLBs in the same column, or for cascading the PLC with other PLCs in the horizontal direction; the vertical signal routing structure is used for cascading between the CLBs in different columns, or for cascading the PLC with other PLCs in the vertical direction.

[0025] Figure 1 The 4X4 structure is used as an example, which does not limit the number of CLBs contained in the PLC. PLCs of other sizes can refer to Figure 1 to set it up.

[0026] In this embodiment, the PLC can implement some basic logic functions, and the CLBs are connected as follows: Figure 1 Arrange, the PLC internal signal transmission direction is as follows Figure 1 As shown by the arrow in the middle, there is a programmable structure of a signal transmission interface between each column of CLBs, which can control the signal transmission to any CLB in the next column for logic operation. The programmable structure of the signal transmission interface is functionally equivalent to the above-mentioned signal routing structure.

[0027] When multiple CLBs are connected as a PLC, introducing a router structure in the CLB connection can improve the flexibility of a single PLC, thereby maximizing the use of resources within the CLB and enhancing the functionality of the PLC.

[0028] Introducing a router structure between PLCs can appropriately simplify the interconnection structure during the interconnection between PLC and other functional modules (other PLCs).

[0029] In this embodiment, one PLC can implement one or more logic functions.

[0030] In one embodiment, an external configurable register is used in a PLC or CLB to increase a combinational logic mode to realize more required logic functions.

[0031] In one embodiment, the signal routing structure includes a plurality of multiplexers.

[0032] Figure 3 is a schematic diagram of a programmable logic unit structure according to an embodiment of the present invention, wherein the programmable logic unit structure (CLB) is composed of two 4-input LUTs, two XOR gates, two OR gates, two flip-flops (FF), and a plurality of multiplexers (MUX). Specifically, Figure 3 As shown, each of the CLBs in the PLC includes: a first lookup table, a second lookup table, a first XOR gate, a second XOR gate, a first OR gate, a second OR gate, a multiplexer, a first trigger and a second trigger; wherein the output end of the first lookup table is connected to the first input end of the first XOR gate, and the output end of the first XOR gate is connected to the first trigger through the multiplexer; the output end of the second lookup table is connected to the first input end of the second XOR gate, and the output end of the second XOR gate is connected to the second trigger through the multiplexer; the first input end of the first OR gate is connected to the output end of the first lookup table, and the first input end of the second OR gate is connected to the output end of the second lookup table. The storage of the LUT value of the PLC can be implemented using SRAM or registers.

[0033] The description of each input and output port in the CLB is shown in Table 1. It can be seen from Table 1 that in this embodiment, the transmission direction of the logic signal can be controlled by configuring the register selection signal to achieve different logic functions. The eFPGA can achieve different functional requirements by configuring the LUT values ​​of each part and selecting different multiplexers to meet the requirements of the programmable logic structure.

[0034] Table 1

[0035]

[0036] In one embodiment, for any CLB in the PLC, when the CLB is used to implement a five-input selector function, the multiplexer includes a first multiplexer; wherein the first input end of the first multiplexer is connected to the output end of the first lookup table, and the second input end of the first multiplexer is connected to the output end of the second lookup table.

[0037] In one embodiment, when the PLC is used to implement the six-input selector function, the multiple CLBs include a first CLB and a second CLB, and the first CLB and the second CLB are connected through the horizontal signal routing structure, wherein the first CLB and the second CLB are located in different columns; in the first CLB or the second CLB, the multiplexer includes a first multiplexer and a second multiplexer; the first input end of the first multiplexer is connected to the output end of the first lookup table, and the second input end of the first multiplexer is connected to the output end of the second lookup table; the second input end of the second multiplexer is connected to the output end of the first multiplexer; the horizontal signal routing structure is connected between the output end of the first multiplexer of the first CLB and the first input end of the second multiplexer of the second CLB.

[0038] In one embodiment, the multiplexer in the first CLB or the second CLB further includes a third multiplexer, and a first input terminal of the third multiplexer is connected to a configurable input signal.

[0039] In one embodiment, when the PLC is used to implement an N-bit full adder function, for any CLB in the PLC, the multiplexer in the CLB includes: a fourth multiplexer, a fifth multiplexer, a sixth multiplexer and a seventh multiplexer, where N is an integer greater than or equal to 2; wherein a first input of the fourth multiplexer is connected to an output of the first XOR gate, and a second input of the fourth multiplexer is connected to an output of the first lookup table; a first input of the fifth multiplexer is connected to an output of the second XOR gate, and a second input of the fifth multiplexer is connected to an output of the second lookup table; a first input of the sixth multiplexer is connected to a first input of the second lookup table, a second input of the sixth multiplexer is connected to an output of the seventh multiplexer, and an output of the sixth multiplexer is connected to a second input of a seventh multiplexer of an adjacent CLB; and a first input of the seventh multiplexer is connected to a first input of the first lookup table.

[0040] In one embodiment, when the PLC is used to implement a counter function, for any CLB in the PLC, the multiplexer in the CLB includes: a fourth multiplexer, a fifth multiplexer, a sixth multiplexer and a seventh multiplexer; wherein the first input of the fourth multiplexer is connected to the output of the first XOR gate, the second input of the fourth multiplexer is connected to the output of the first lookup table, and the output of the fourth multiplexer is connected to the first trigger; the first input of the fifth multiplexer is connected to the output of the second XOR gate, the second input of the fifth multiplexer is connected to the output of the second lookup table, and the output of the fifth multiplexer is connected to the second trigger; the first input of the sixth multiplexer is connected to the first input of the second lookup table, the second input of the sixth multiplexer is connected to the output of the seventh multiplexer, and the output of the sixth multiplexer is connected to the second input of the seventh multiplexer of the adjacent CLB; the first input of the seventh multiplexer is connected to the first input of the first lookup table.

[0041] In one embodiment, when the PLC is used to implement a counter function, for any CLB in the PLC, the multiplexer in the CLB includes: a ninth multiplexer, wherein the first input terminal of the ninth multiplexer is connected to the output terminal of the first trigger, the second input terminal is connected to the input signal, and the output terminal is connected to the first input terminal of the first lookup table.

[0042] In one embodiment, when the PLC is used to implement a comparator function, for any CLB in the PLC, the multiplexer in the CLB includes: a fourth multiplexer and a fifth multiplexer; wherein the first input of the fourth multiplexer is connected to the output of the first XOR gate, and the second input of the fourth multiplexer is connected to the output of the first lookup table; the first input of the fifth multiplexer is connected to the output of the second XOR gate, and the second input of the fifth multiplexer is connected to the output of the second lookup table.

[0043] In one embodiment, for any of the CLBs, the multiplexer further includes an eighth multiplexer, a first input terminal of the eighth multiplexer connected to an output terminal of the fourth multiplexer, a second input terminal connected to an output terminal of the third multiplexer, and an output terminal connected to the first trigger.

[0044] Although the functions that a single CLB can realize are relatively limited, in the above embodiments of the present invention, some more complex logic functions can be realized by connecting multiple CLBs; the PLC contains multiple CLB structures, and the router design in the PLC allows a single PLC to have more logic functions to realize feasibility, reflecting the high efficiency and flexibility of the PLC. The PLC structure in the embodiments of the present invention can further simplify the wiring algorithm of the programmable logic structure, have greater advantages in realizing certain specific functions, improve the product iteration speed, and enhance the competitiveness of enterprises.

[0045] An embodiment of the present invention also provides a programmable logic device, which includes: the programmable logic cluster PLC in the above embodiment, an I / O interface for input and output connection with an external IC chip, and a random access memory RAM for storing lookup table configuration values ​​in the programmable logic cluster.

[0046] In one embodiment, the programmable logic device is an eFPGA.

[0047] Traditional FPGAs have the following disadvantages in use: a lot of programmable resources and peripheral interface resources are wasted in hardware acceleration applications; there is significant delay in the interface between standard FPGAs and ASICs, making it difficult to meet the needs of high-speed computing; high power consumption, large area, and serious cost waste. eFPGAs can overcome the above shortcomings of traditional FPGAs.

[0048] Figure 2 Schematic diagram of the connection between the embedded FPGA and IC according to an embodiment of the present invention. Figure 2 As shown, eFPGA includes the following multiple functional blocks: PLC, input (input interface), output (output interface), RAM, among which the eFPGA programmable structure is connected to the external IC chip through the I / O interface, and can also be solidified into an IP core using Verilog code, which is convenient for integration into the IC chip.

[0049] Among them, the I / O interface transmission direction is fixed, which further simplifies the programmable routing algorithm; RAM corresponds to the storage structure in the eFPGA, which is mainly used to store the LUT configuration value in the PLC;

[0050] In addition to using SRAM (Static Random-Access Memory) to implement the storage structure within the eFPGA, it can also be implemented using registers.

[0051] In this embodiment, the various functional blocks are connected via interconnection lines, which can increase the programmable flexibility and improve the iteration speed of the compilation algorithm.

[0052] FPGA products in related technologies can also realize different logical functions, but their solution efficiency is low, the area is large, and the cost is high; in addition, FPGA products from different manufacturers or different models of the same manufacturer have the disadvantages of different processes and cannot be better compatible with IC chips; the programmable logic structure designed in the embodiment of the present invention can efficiently realize certain specific functions, with fast iteration speed and simple algorithm. The following takes the realization of selector, adder, counter and comparator functions as an example to explain the programmable logic structure in this embodiment and its working principle.

[0053] Embodiment 1

[0054] eFPGA implements selector function:

[0055] An N*bit selector consists of N*bit data input, M*bit selection signal, and 1bit output signal.

[0056] For example, a 2-to-1 selection requires 2-bit data input and 1-bit selection signal. In this embodiment, it can be realized through a 4-input LUT, that is, Figure 2 LUT0 or LUT1 in the embodiment, wherein LUT0 is functionally equivalent to the second lookup table of the above embodiment, and LUT1 is functionally equivalent to the first lookup table of the above embodiment;

[0057] For another example, a 16-to-1 selector can be implemented with a 4-input LUT, that is, by pre-storing 16 LUT values ​​in a register, and then the 4-input LUT outputs the corresponding value according to the selected trigger, thereby achieving a 16-to-1 selector.

[0058] In this embodiment, a CLB can realize the function of a one-to-N selector with any value from 1 to 32, that is, a single CLB can realize a maximum of 5-input MUX selection function (that is, 2 5 When more signals need to be selected, the MUX can be realized by cascading multiple CLB LUTs. Figure 4 is a schematic diagram of implementing a six-input MUX selection function by cascading CLBs according to an embodiment of the present invention, as shown Figure 4 As shown, when implementing the six-input MUX selection function, two PLCs are required. Figure 3 The two CLBs shown in the figure belong to different columns. After the CLB on the left implements the 5-input MUX selection function, the signal o_data_f5 is input to the CLB on the right. The signal o_data_f5 is horizontally cascaded to the i_data_f5 port of the CLB on the right. That is, by cascading two CLB structures, a maximum of 6 (i.e. 2 6 Select 1 function) Input MUX selection function.

[0059] Since the horizontal CLB connection signal selection inside the PLC is more flexible, a larger-scale MUX selection function can be implemented within a single PLC structure. When the algorithm defines a PLC in the programmable structure as a large-bit-width MUX selector function, the PLC can be defined to only satisfy this function, thereby simplifying the programmable routing algorithm.

[0060] In one embodiment, Figure 4 As shown, the CLB is provided with an i_cpu_lut0_a5 port, which is used to receive a configurable input signal and can be directly used together with the output of MUX6 as an input signal of a 2-to-1 MUX; the configuration signal can increase the configurable input signal inside a single CLB, which has a simplifying effect on some functions that require fixed input signals.

[0061] Embodiment 2

[0062] eFPGA implements adder function:

[0063] Since one LUT has only one output terminal, when implementing the adder function, one LUT of the multi-input LUT can only display 1 bit in the addition.

[0064] A single-bit full adder consists of 3 inputs (A, B, CIN) and 2 outputs (SUM, COUT), where:

[0065] SUM=A⊕B⊕CIN (1)

[0066]

[0067] According to formula (1) and formula (2), realizing a full adder requires two LUTs to realize SUM and COUT respectively. This has two disadvantages: one is the waste of resources; the other is the large carry delay (LUT connection is long).

[0068] To overcome the above shortcomings, the COUT expression can be transformed as follows:

[0069]

[0070] According to formula (1) and formula (3), both SUM and COUT contain A⊕B, so LUT can be used to implement A⊕B. SUM corresponds to the XOR operation of A⊕B and carry CIN. COUT can use A⊕B as the selection signal. CIN and A are used as the input of the 2-to-1 MUX. As long as C0&1 and ORX0&1 are added in CLB, SUM and COUT of single-bit full addition can be implemented simultaneously using 1 LUT. Table 2 shows the LUT configuration values ​​in CLB when eFPGA implements the 2-bit adder function.

[0071] Table 2

[0072] A[0] B[0] A⊕B Lut 0 0 0 0 0 1 1 4 1 0 1 8 1 1 0 12

[0073] Figure 5 is a schematic diagram of a simplified CLB cascade for implementing a multi-bit adder function according to an embodiment of the present invention, such as Figure 5 As shown, when implementing the multi-bit adder function, multiple Figure 3 The CLB shown, specifically, Figure 5 The left and right parts can be regarded as the implementation process of the adder of independent 6-bit data A and B. The implementation principle of the adder has been theoretically analyzed in the previous article. When more bit data needs to be added, other CLBs can be cascaded through the router part in the PLC, such as Figure 5 As shown, the count carry output of CLB3 is routed to the i_data_in input of CLB4, thereby realizing the addition function of higher bits (greater than 6 bits).

[0074] Embodiment 3

[0075] eFPGA implements counter function:

[0076] An N-bit counter requires N flip-flops, which corresponds to at least N LUTs.

[0077] The 1-bit counter is relatively simple: when the current output is 0, the next output is 1; when the current output is 1, the next output is 0.

[0078] Therefore, starting from the second bit of the counter, the rule is as shown in formula (4):

[0079]

[0080] In formula (4), Qn is the abbreviation of Qnext, which means the next output result, and Qc is the abbreviation of Qcurrent, which means the current output result. When implementing a counter, Qn[n] is the output of the D flip-flop, which is connected to the input of the corresponding LUT, and Qc[n] is the output of the LUT.

[0081] Each bit of the counter requires 1 LUT, but in fact only 1 bit of the LUT is used for input and output. The other bits of the LUT are not used and can be used to implement the fixed 0 input of the carry chain MUX. For the lowest bit (1 bit) of the counter, this structure can still be used, but the two inputs of the MUX in the carry chain are fixed to 0 and 1 respectively. Table 3 shows the LUT configuration values ​​in the CLB when the eFPGA implements the lowest bit adder function.

[0082] Table 3

[0083] A[0] cnt Lut 0 0 0 1 1 8

[0084] Figure 6 is a schematic diagram of a simplified CLB cascade for implementing a multi-bit counter function according to an embodiment of the present invention. Figure 6 As shown, when implementing the multi-bit counter function, multiple counters are required in the PLC. Figure 3 As shown in the CLB, specifically, each CLB in the PLC structure can realize 1-bit counting, and 4 CLBs can realize 4-bit counting at most. The implementation principle of the entire counter is as described above. The input i_data_in of CLB0 is 0. In addition, the corresponding OR gate i_cpu_lut0_bypass on LUT0 inside each CLB is configured to 1 to ensure that the carry can be directly output and is not affected by the configuration of LUT0. Similarly, when a higher bit counting function is to be realized, the output value of the left CLB can be connected to the right CLB through the router structure of the PLC, and a higher bit counting function can be realized by configuring the LUT. In addition, it can also be used in other logical calculations.

[0085] Embodiment 4

[0086] eFPGA implements comparator function:

[0087] The comparator is mainly used to compare the size of two signals. The comparison functions that can be realized include: <, ≤, >, ≥, =, ≠. A LUT4 can realize a maximum of 4-bit logic processing, and can complete the comparison of the size of each signal with a maximum of 2 bits. The comparison result can be transmitted to the next CLB through the carry chain to complete the comparison of higher bits. N-bit signals require N / 4 CLBs to complete, and the CLBs are connected through COUT carry. Table 4 shows the LUT configuration values ​​in the CLB when the eFPGA implements the comparator function determined by various comparison relationships.

[0088] Table 4

[0089]

[0090] Figure 7 is a schematic diagram of a simplified CLB cascade for implementing a comparator function according to an embodiment of the present invention. When implementing the comparator function, multiple CLBs are required in the PLC. Figure 3 The CLB shown, Figure 7 Each CLB in the figure is an electronic device actually involved in realizing the comparison function. Other electronic devices are not shown. In this embodiment, each LUT in a single CLB can realize the output of a comparison result, such as Figure 7 There are two CLB structures on the left side of the figure, with a total of four comparison result outputs. When more comparison result outputs are required, more CLBs need to be cascaded, such as Figure 7Through the router structure inside the PLC, the judgment result of the previous part can be used for the subsequent CLB structure to make further judgments, expanding the comparison capability of the CLB structure. The output result of the CLB comparator inside the PLC can also be passed to the subsequent CLB through the router for other logic implementations. The specific roadbed function depends on the needs.

[0091] In the implementation of the present invention, in addition to the configuration methods of the four common functions listed above, the CLB structure can also implement basic logic functions including shift registers, multipliers, etc.

[0092] As mentioned above, multiple CLBs in the PLC are connected through a signal routing structure. Specifically, the interface between the CLBs is selected by a MUX and then output to the next-level CLB. Figure 8 is a schematic diagram of the interface connection between CLBs according to an embodiment of the present invention, Figure 8 is Figure 3 In addition to showing the CLB structure, the signal routing structure involved in connecting with other CLBs is also shown (the signal routing structure is as shown in FIG. Fig. 9 ), which shows the cascade interface signal relationship between a single CLB and an adjacent CLB. The programmable flexibility of the PLC can be improved through the above-mentioned routing cascade method.

[0093] exist Figure 1 As can be seen from the figure, the connection between the single-column CLBs follows the signal propagation direction from bottom to top, and the signal connection MUX between adjacent CLBs is selected as follows: Fig. 9 and Fig.10 shown.

[0094] Fig. 9 is a schematic diagram of a horizontal signal routing structure and a vertical signal routing structure according to an embodiment of the present invention, Fig. 9 The left side of the figure is a schematic diagram of a horizontal signal routing structure, which includes multiple levels of multiplexer units, each level of multiplexer units includes a different number of multiplexers, specifically, the number of multiplexers in the first level is twice that of the second level, the second level is twice that of the third level, and so on, until the last level includes only one multiplexer. The number of levels of multiplexer units included in the horizontal signal routing structure is related to the scale of CLBs included in the PLC.

[0095] For example: Fig. 9A 4X4 structure PLC is taken as an example, which includes four levels of multiplexer units, wherein the first level multiplexer unit includes eight multiplexers, each two adjacent multiplexers correspond to a CLB, and the four input ends of the two adjacent multiplexers are respectively connected to the four output ends of a CLB; the second level multiplexer unit includes four multiplexers; the third level multiplexer unit includes two multiplexers; and the fourth level multiplexer unit includes one multiplexer.

[0096] The horizontal signal routing structure is used to connect CLBs between different columns. The horizontal signal routing structure makes the signal selection between two adjacent columns more flexible. Here, the output signal between multiple adjacent CLBs can be transmitted to any CLB in the next level, which improves the signal interconnection flexibility between CLBs. In this way, a single PLC can realize some more complex logic functions and improve iteration efficiency.

[0097] Fig. 9 On the right is a schematic diagram of the vertical signal routing structure, such as Fig. 9 As shown, the vertical signal routing structure includes three levels of multiplexer units, wherein the first level multiplexer unit includes four multiplexers, and the input ends of the four multiplexers are respectively connected to five output ends of a CLB and an additional input signal; the second level multiplexer unit includes two multiplexers, and the third level multiplexer unit includes one multiplexer.

[0098] The vertical signal routing structure is used to connect multiple CLBs in the same column. Compared with the horizontal MUX routing structure, the vertical signal selection is simpler. It can route all the outputs of the lower CLB to the upper CLB while simplifying the configuration.

[0099] Fig.10 Schematic diagram of a signal routing mode between horizontal CLBs within a PLC according to an embodiment of the present invention. Fig.10 As shown, a block diagram of the output signal routing structure of the horizontal CLBs in the PLC of the embodiment of the present invention is given, and the outputs of multiple CLBs in the vertical direction all output a signal through a MUX routing structure. Fig. 9 It can be seen that the result of the horizontal CLB routing output is connected to LUT0 of the CLB, and forms a 2-to-1 MUX input signal with the input signals IN_A0~3. Fig.10 Each MUX corresponds to Fig. 9 The signal selection diagram on the left shows that the selection signal configuration inside each MUX is independent of each other, and the o_data_router signals outputted from it are also independent of each other. The advantage of this design is that it greatly increases the configuration flexibility of the PLC, and a single PLC can implement some more complex functions.

[0100] Through the above embodiments of the present invention, the entire eFPGA structure is composed of interconnected PLCs, SRAM, I / O interface and other functional IP modules. By configuring the most basic CLB selection signals and LUT truth tables, different functional requirements can be met, thereby realizing the programmability of the eFPGA structure. At the same time, according to the characteristics of the PLC structure, Figure 2 The single PLC structure in the system is first configured into some small functional modules, and then these functional modules are connected to realize some system-level functions.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A programmable logic cluster PLC, characterized in that: include: A plurality of programmable logic units (CLBs) are arranged in an array form, and a signal routing structure; wherein the signal routing structure comprises a horizontal signal routing structure and a vertical signal routing structure, the horizontal signal routing structure is used for cascading between the CLBs in the same column, or for cascading between the PLC and other PLCs in the horizontal direction; the vertical signal routing structure is used for cascading between the CLBs in different columns, or for cascading between the PLC and other PLCs in the vertical direction.

2. The PLC according to claim 1, characterized in that: The signal routing structure includes a plurality of multiplexers.

3. The PLC according to claim 1, characterized in that: Each of the CLBs includes: a first lookup table, a second lookup table, a first XOR gate, a second XOR gate, a first OR gate, a second OR gate, a multiplexer, a first trigger, and a second trigger; Among them, the output end of the first lookup table is connected to the first input end of the first XOR gate, and the output end of the first XOR gate is connected to the first trigger through the multiplexer; the output end of the second lookup table is connected to the first input end of the second XOR gate, and the output end of the second XOR gate is connected to the second trigger through the multiplexer; the first input end of the first OR gate is connected to the output end of the first lookup table, and the first input end of the second OR gate is connected to the output end of the second lookup table.

4. The PLC according to claim 3, characterized in that: For any of the CLBs in the PLC, when the CLB is used to implement a five-input selector function, the multiplexer includes a first multiplexer; The first input terminal of the first multiplexer is connected to the output terminal of the first lookup table, and the second input terminal of the first multiplexer is connected to the output terminal of the second lookup table.

5. The PLC according to claim 3, characterized in that: In the case where the PLC is used to implement a six-input selector function, the plurality of CLBs include a first CLB and a second CLB, the first CLB and the second CLB are connected via the horizontal signal routing structure, wherein the first CLB and the second CLB are located in different columns; In the first CLB or the second CLB, the multiplexer includes a first multiplexer and a second multiplexer; the first input end of the first multiplexer is connected to the output end of the first lookup table, and the second input end of the first multiplexer is connected to the output end of the second lookup table; the second input end of the second multiplexer is connected to the output end of the first multiplexer; the horizontal signal routing structure is connected between the output end of the first multiplexer of the first CLB and the first input end of the second multiplexer of the second CLB.

6. The PLC according to claim 5, characterized in that: in, The multiplexer in the first CLB or the second CLB further includes a third multiplexer, and a first input terminal of the third multiplexer is connected to a configurable input signal.

7. The PLC according to claim 3, characterized in that: In the case where the PLC is used to implement an N-bit full adder function, for any CLB in the PLC, the multiplexer in the CLB includes: a fourth multiplexer, a fifth multiplexer, a sixth multiplexer and a seventh multiplexer, where N is an integer greater than or equal to 2; Among them, the first input end of the fourth multiplexer is connected to the output end of the first XOR gate, and the second input end of the fourth multiplexer is connected to the output end of the first lookup table; the first input end of the fifth multiplexer is connected to the output end of the second XOR gate, and the second input end of the fifth multiplexer is connected to the output end of the second lookup table; the first input end of the sixth multiplexer is connected to the first input end of the second lookup table, the second input end of the sixth multiplexer is connected to the output end of the seventh multiplexer, and the output end of the sixth multiplexer is connected to the second input end of the seventh multiplexer of the adjacent CLB; the first input end of the seventh multiplexer is connected to the first input end of the first lookup table.

8. The PLC according to claim 3, characterized in that: In the case where the PLC is used to implement a counter function, for any CLB in the PLC, the multiplexer in the CLB includes: a fourth multiplexer, a fifth multiplexer, a sixth multiplexer and a seventh multiplexer, Among them, the first input end of the fourth multiplexer is connected to the output end of the first XOR gate, the second input end of the fourth multiplexer is connected to the output end of the first lookup table, and the output end of the fourth multiplexer is connected to the first trigger; the first input end of the fifth multiplexer is connected to the output end of the second XOR gate, the second input end of the fifth multiplexer is connected to the output end of the second lookup table, and the output end of the fifth multiplexer is connected to the second trigger; the first input end of the sixth multiplexer is connected to the first input end of the second lookup table, the second input end of the sixth multiplexer is connected to the output end of the seventh multiplexer, and the output end of the sixth multiplexer is connected to the second input end of the seventh multiplexer of the adjacent CLB; the first input end of the seventh multiplexer is connected to the first input end of the first lookup table.

9. The PLC according to claim 3, characterized in that: In the case where the PLC is used to implement a comparator function, for any of the CLBs in the PLC, the multiplexer in the CLB includes: a fourth multiplexer, a fifth multiplexer; Among them, the first input end of the fourth multiplexer is connected to the output end of the first XOR gate, and the second input end of the fourth multiplexer is connected to the output end of the first lookup table; the first input end of the fifth multiplexer is connected to the output end of the second XOR gate, and the second input end of the fifth multiplexer is connected to the output end of the second lookup table.

10. A programmable logic device, characterized in that: include: The programmable logic cluster described in any one of claims 1 to 9, an I / O interface part for connecting to an external IC chip, and a random access memory for storing lookup table configuration values ​​in the programmable logic cluster.

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