Multi-core particle layout optimization method and device based on multi-objective optimization algorithm

Abstract

The invention discloses a multi-core-particle layout optimization method and device based on a multi-objective optimization algorithm. The method comprises the following steps: respectively constructing objective optimization functions and constraint conditions of core particle temperature, inter-core-particle transmission delay, total area and inter-core-particle communication power consumption; based on the constraint conditions, performing iterative solution on the target optimization functions by using an NSWOA algorithm to respectively obtain Pareto leading edge surfaces of the target optimization functions; determining a compromise solution by using an MHA algorithm based on the Pareto leading edge surface; and determining the placement positions of the core particles according to the compromise solution, adjusting the directions according to the pin functions and the connection requirements between the functional modules, and obtaining the result of the minimum total wiring length according to the shortest total interconnection line length, thereby obtaining the optimal layout of the multiple core particles. According to the method, the performance and the integration degree of a multi-core system in 2.5 D packaging can be effectively improved by optimizing the multi-core layout.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a multi-chip layout optimization method and device based on a multi-objective optimization algorithm. Background Art

[0002] Traditional single-chip design has problems such as high design complexity and cost, poor process flexibility, low manufacturing yield, and high production cost, and is gradually being replaced by multi-chip systems. Based on 2.5D packaging, multiple chips (CPU, GPU, NPU, etc.) are placed on the silicon interposer. These chips can use a variety of different manufacturing technologies and processes to form a heterogeneous system, achieving higher performance and lower energy consumption, while ensuring the communication performance between chiplets.

[0003] However, the advancement of packaging technology also brings many challenges, such as the layout problem of high-integration chiplet systems. Existing layout optimization techniques mainly optimize a single goal, only considering the minimization of system area or only considering the minimization of transmission delay, which may lead to some adverse effects. This single layout optimization technology is no longer applicable to high-integration chiplet systems, and it is necessary to consider the physical parameters between multiple chiplets (such as temperature, transmission delay, total area, and communication power consumption, etc.). Therefore, it is urgent to propose a multi-chiplet layout optimization method to optimize the multi-chiplet layout to effectively improve the performance and integration of the multi-chiplet system. Summary of the invention

[0004] In order to solve the above-mentioned deficiencies of the prior art, the embodiments of the present application provide a multi-chip layout optimization method and device based on a multi-objective optimization algorithm to improve the performance and integration of the multi-chip system in 2.5D packaging.

[0005] According to a first aspect of an embodiment of the present application, a multi-chip layout optimization method based on a multi-objective optimization algorithm is provided, comprising: Construct the target optimization functions and constraints of chiplet temperature, inter-chiplet transmission delay, total area and inter-chiplet communication power consumption respectively; Based on the constraint conditions, the objective optimization function is iteratively solved using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function; Based on the Pareto front, a compromise solution is determined using the MHA algorithm; The placement of the core particles is determined according to the compromise solution, and the orientation is adjusted according to the pin function and the connection requirements between functional modules. The total wiring length is minimized according to the shortest total interconnection length, thereby obtaining the optimal layout of multiple core particles.

[0006] According to a second aspect of an embodiment of the present application, a multi-chip layout optimization device based on a multi-objective optimization algorithm is provided, comprising: A construction module is used to construct the target optimization functions and constraints of the core particle temperature, the transmission delay between core particles, the total area and the power consumption of the communication between core particles respectively; A solution module, used for iteratively solving the objective optimization function based on the constraint conditions by using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function; A determination module, used for determining a compromise solution based on the Pareto front surface using an MHA algorithm; The optimization module is used to determine the placement position of the core particles according to the compromise solution, adjust the position according to the pin function and the connection requirements between the functional modules, and obtain the result of minimizing the total wiring length according to the shortest total interconnection line length, so as to obtain the optimal layout of multiple core particles.

[0007] According to a third aspect of an embodiment of the present application, there is provided an electronic device, including: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in the first aspect.

[0008] The technical solution provided by the embodiments of the present application may have the following beneficial effects: The present invention optimizes the chip layout through a multi-objective optimization algorithm, effectively solving key problems in the layout such as local high temperature, uneven transmission delay, large overall area and high communication power consumption, and achieving a compromise optimal solution for temperature, transmission delay, total area and communication power consumption, making the chip layout more efficient and reliable.

[0009] The present invention first constructs a multi-objective optimization function and constraints; uses the NSWOA algorithm to iteratively solve the objective optimization function, and obtains the Pareto frontier of each objective optimization function; then uses the MHA algorithm to determine the compromise solution; thereby determining the placement of the core particles; and finally determines the optimal layout of multiple core particles based on the shortest total length of the connection between the core particles; effectively solves the key problems of local high temperature, uneven transmission delay, large overall area, and high communication power consumption in the single-objective optimization of the layout of multiple core particles in the existing solution, making the layout of multiple core particles more efficient and reliable. Compared with the single-objective layout optimization, the present invention has stronger adaptability and can be flexibly adjusted for 2.5D packages of different types and sizes.

[0010] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0012] Figure 1 The present invention is a flowchart of a multi-chip layout optimization method based on a multi-objective optimization algorithm according to an exemplary embodiment.

[0013] Figure 2 The invention is a block diagram of a multi-chip layout optimization device based on a multi-objective optimization algorithm according to an exemplary embodiment. DETAILED DESCRIPTION

[0014] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0015] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0016] Figure 1 is a flowchart of a multi-chip layout optimization method based on a multi-objective optimization algorithm according to an exemplary embodiment. Figure 1 As shown, the method may include the following steps: S1: construct the target optimization functions and constraints for core particle temperature, inter-core particle transmission delay, total area, and inter-core particle communication power consumption respectively; Specifically, 1) the core temperature f T : Indicates the temperature of the chip in working state. Too high temperature will affect the performance and reliability of the chip, and may even cause permanent damage to the chip.

[0017] The objective function of the core particle temperature is expressed as: ; in, is the core particle temperature; } represents the lower left corner coordinate and upper right corner coordinate of core particle n; is the ambient temperature; is the power consumption of the ith chip; is the thermal resistance; is the effective area of ​​the ith core particle; is the heat transfer coefficient between the ith and jth core particles; is the temperature of the jth core particle; is the distance between the ith and jth core particles, expressed as ; Core temperature constraint: The core temperature cannot exceed a certain threshold to prevent overheating. The constraint is expressed as:

[0018] ; Where T max is the maximum threshold of temperature.

[0019] 2) Inter-chip transmission delay f D : Indicates the time required for data transmission between different core particles. The lower the transmission delay, the faster the system responds.

[0020] The objective function of the inter-chip transmission delay is expressed as: ; Among them, f D Inter-chip transmission delay; is the transmission rate between the ith and jth core particles; Transmission delay constraint between core particles: In order to ensure the performance of the overall system, the transmission delay between core particles needs to be less than a certain threshold. The constraint condition is expressed as:

[0021] ; Where D max is the maximum threshold for transmission delay.

[0022] 3) Total area f A : Indicates the area occupied by the entire 2.5D package. The smaller the area, the higher the integration.

[0023] The objective function of the total area is expressed as: ; In the formula, f A is the total area; Total area constraint: The total area of ​​the core cannot exceed the maximum threshold of the total area of ​​the chip. The constraint is expressed as:

[0024] ; in is the total area of ​​the chip.

[0025] 4) Power consumption of chiplet-to-chip communication f P : Represents the power consumed by communication between different cores. The lower the power consumption, the higher the energy efficiency of the system.

[0026] The objective function of the power consumption of inter-chiplet communication is expressed as: ; Among them, f P is the power consumption of inter-chiplet communication; is the communication frequency between the ith and jth coreparticles.

[0027] Constraints on inter-chiplet communication power consumption: In order to achieve better system performance, the inter-chiplet communication power consumption needs to be less than a certain threshold. The constraints are expressed as:

[0028] ; Where P max is the maximum threshold of communication power consumption.

[0029] Compared with the traditional optimization that only considers a single goal, this embodiment significantly improves the overall optimization effect of the core particle layout by synergistically optimizing the above four goals, thereby more effectively achieving the optimal layout.

[0030] S2: Based on the constraint conditions, the objective optimization function is iteratively solved using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function. This step includes the following sub-steps: S21: Read the parameters of the core particles: the position of the core particles, the ambient temperature, the power consumption of the core particles, the thermal resistance; the effective area of ​​the core particles, the thermal conductivity coefficient between the core particles, the temperature of the core particles, the distance between the core particles, the transmission rate between the core particles, and the communication frequency between the core particles; Specifically, read the parameters of the core particle: The location of the core X t =[ { x 1 , y 1 , x 1 ' , y 1 ' }.....{ x n , y n , x n ' , y n ' } ] ; Ambient temperature ; Power consumption of the ith chip Thermal resistance ; The effective area of ​​the ith core particle ; The thermal conductivity between the i-th and j-th core particles ; The temperature of the jth core particle ; The distance between the i-th and j-th core particles ; Transmission rate between the i-th and j-th core particles ; Communication frequency between the i-th and j-th core particles ; S22: Initialize the NSWOA algorithm parameters, select the initial population, and initialize according to the constraints; Specifically, the NSWOA algorithm parameters are initialized, the initial population is selected, and the initialization is performed according to the constraints; wherein the NSWOA algorithm parameters are initialized and the initial population is selected, specifically: the population size N, the maximum number of iterations T and the whale position information X(t) of the NSWOA algorithm are initialized, the corresponding fitness value of each whale is calculated, the whales are sorted according to the size of the fitness value, and a population size of N whales is selected as the initial population.

[0031] S23: Update the current optimal solution through the shrinking and encircling mechanism, spiral mechanism and search and foraging mechanism of the NSWOA algorithm. In each iteration, it is necessary to calculate each objective optimization function for fitness evaluation and identify the current optimal solution; 3) Specifically, the current optimal solution is updated through the shrinking and encircling mechanism, spiral mechanism and search and foraging mechanism of the NSWOA algorithm. In each iteration, the objective optimization function f needs to be calculated. T 、f D 、f A 、f P Perform fitness evaluation and identify the current optimal solution.

[0032] Shrinking and surrounding mechanism: When humpback whales hunt, they need to surround their prey and first determine the location of the prey. The following mathematical model is proposed: in: Where: represents the best whale position vector so far; represents the current whale position vector; t is the current iteration number; A and C are the coefficients; and is a random number between [0,1]; a is a control parameter, which decreases linearly from 2 to 0 as the number of iterations increases; T is the maximum number of iterations.

[0033] Screw mechanism: According to the hunting behavior of humpback whales, they swim towards their prey in a spiral motion, and the mathematical model is: Where: l is a random number between [-1,1], b is a parameter representing the degree of spiral, Indicates the distance between the whale and its prey.

[0034] In addition to swimming in a spiral shape towards the prey, the whale will also shrink the encirclement. Therefore, in this model, it is assumed that P i The probability of choosing the shrinking and encircling mechanism and 1-P i The probability of choosing the spiral model to update the position of the whale is as follows: When attacking prey, the mathematical model sets a decreasing value of a as it approaches the prey, so that the fluctuation range of A also decreases with a. During the iteration process, when the value of a decreases from 2 to 0, A is a random value in [-a, a]. When the value of A is in [−1, 1], the next position of the whale can be any position between its current position and the position of the prey. The algorithm sets that when A<1, the whale attacks the prey.

[0035] Search foraging mechanism: In order to ensure that all whales can fully search in the solution space, the positions of whales are updated according to the distance between them to achieve the purpose of global random search. The established mathematical model is as follows: in, is the randomly selected whale position vector. The algorithm sets that when A ≥ 1, a search agent is randomly selected to update the positions of other whales according to the randomly selected whale position, forcing the whale to deviate from the prey, thereby finding a more suitable prey and realizing global search.

[0036] S24: Repeat the above S21-S23 until the maximum number of iterations T is reached, and the Pareto frontiers of the four objectives are obtained.

[0037] The NSWOA algorithm used in this embodiment has a strong global search capability and does not need to rely on gradient information. It performs well in processing the above-mentioned nonlinear, multi-objective, and high-dimensional optimization problems.

[0038] S3: Based on the Pareto front, a compromise solution is determined using the MHA algorithm; S31: For the objective function, each Pareto optimal solution has a set of corresponding values. Assuming there are n sets of solutions on the Pareto frontier, we get a matrix M, where each row corresponds to a solution. Specifically, preprocessing: For the above four objective functions, each Pareto optimal solution has a set of corresponding values. Assume that there are n solutions on the Pareto frontier, and get an n×4 matrix M, where each row corresponds to a solution.

[0039] S32: By combining the matrix M with three different weight matrices W Q , W K and W V Multiply to calculate the Query, Key, and Value of each solution; Specifically, Query: Each input element (such as a word, character, etc.) has a Query vector. The Query vector represents the information or features we are looking for. When calculating the attention weight, the Query is used to match the Key to determine which elements to focus on and how important they are. Key: Each input element also has a Key vector. The Key vector represents the characteristics or content of the element. The Key is used to match the Query and calculate the similarity or correlation between the two to determine which elements are important to the current Query. Value: Each input element also has a Value vector. The Value vector represents the actual information or feature value. After the attention weights are calculated, these weights are used to weight the Value to generate the final output.

[0040] Calculate Query, Key, and Value by combining M with three different weight matrices W Q , W K and W V Multiply to calculate the query, key and value of each solution. The above three weight matrices are learned during the model training process. The mathematical model is as follows:

[0041] Among them, Q, K and V are the Query, Key and Value of all solutions respectively.

[0042] Calculate the attention weight: Calculate the dot product of each solution's query and all solution's keys, and then normalize it through the softmax function to get the attention weight of each solution to other solutions. The mathematical model is as follows:

[0043] Among them, d k It is the dimension of Key, which is used to scale the size of the dot product to prevent the gradient disappearance problem caused by the dot product being too large.

[0044] The detailed process of mathematical model training is as follows: a) Read a large amount of historical data of the above core particles.

[0045] b) Initialize the weight matrix W Q , W K and W V , these weight matrices are randomly initialized.

[0046] c) Use the above steps 2) and 3) for forward propagation to calculate Q, K, V and attention weights.

[0047] d) Define a loss function to measure the gap between the model's prediction and the true compromise solution. Use the Euclidean distance between the model's predicted compromise solution and the true compromise solution as the loss. The mathematical model is as follows:

[0048] in, and are the values ​​of the compromise solution predicted by the model and the true compromise solution on the i-th objective.

[0049] e) Back propagation and weight update: Calculate the loss function with respect to W Q , W K and W V The gradient of Q , ∇W K and ∇W V , and then use these gradients to update the weight matrix. The update formula is as follows:

[0050] in, is the learning rate, which determines the step size of each update.

[0051] f) Repeat the above steps (forward propagation, loss calculation, back propagation, and weight update), and each iteration needs to traverse all the training data until the performance of the model meets the requirements or the maximum number of iterations.

[0052] S33: The attention weight of each solution to other solutions is obtained by calculating the dot product of the query of each solution and the key of all solutions, and then normalizing it through the softmax function; Specifically, Query and Key are vectors generated by the input data of the model or the output of the previous layer. The dot product of Query and Key is calculated by measuring the correlation or similarity between each solution and other solutions. The larger the dot product value, the stronger the relationship between the solutions. Then, all dot products are normalized by the softmax function so that the sum of the attention weights between all solutions is 1. The role of Softmax is to convert these dot products into probability distributions, which facilitates the subsequent weighted summation of different solutions. By calculating dot products and softmax operations, the model can dynamically assign different attention weights based on the similarity or importance between solutions. This mechanism enables the model to flexibly focus on different solutions according to task requirements. This method can effectively capture the dependencies between different solutions and improve the performance of the model in complex tasks.

[0053] S34: Select the solution with the highest attention weight as the compromise solution; Specifically, from the attention weights of all solutions, the solution with the highest score (weight) is selected as the final compromise result. By selecting the compromise solution, attention can be focused on the solution that contributes most to the final decision, helping the model make more accurate choices.

[0054] S35: Based on the predicted compromise solution and the actual compromise solution, calculate the loss function, back propagate, and update the Query, Key, and Value.

[0055] Specifically, the loss function (such as mean square error, cross entropy, etc.) is used to measure the gap between the predicted compromise solution and the actual true compromise solution. By calculating this loss value, the model can know the deviation between the predicted result and the target value. Then, using the back propagation algorithm, the loss value is passed back from the output layer, and the parameters of the model, including Query, Key, and Value, are adjusted through optimization methods such as gradient descent. The update of these parameters helps the model learn better and improve the prediction performance.

[0056] Through back propagation and parameter update, the model can gradually adjust the query, key and value, optimize the final compromise solution selection, and make the model better approximate the real solution. This design can adaptively adjust the solution selection method according to the input data and target task, thereby improving the generalization ability and accuracy of the model.

[0057] The MHA algorithm is trained in a data-driven way to obtain the corresponding weight matrix. Compared with calculating the optimal compromise solution of the four objectives according to fixed weights, MHA enhances the information capture capability, can update the objective weights in real time, and has stronger adaptability. This makes the compromise solution of multi-objective optimization more accurate and efficient, and can handle the complex relationship between different objectives, significantly improving the overall performance of the optimization process.

[0058] S4: Determine the placement position of the core particles according to the compromise solution, adjust the orientation according to the pin function and the connection requirements between functional modules, and obtain the minimum total wiring length based on the shortest total interconnection length, thereby obtaining the optimal layout of multiple core particles.

[0059] Specifically, according to the compromise solution, the level of the core particles is determined according to the number of interconnection lines of the core particles to be arranged. As shown in Table 1, the more interconnection lines a core particle has, the higher the level of the core particle is. The placement position of the core particle is determined according to the priority arrangement standard, and then the orientation is adjusted according to the pin function and the connection requirements between functional modules. The result of minimizing the total wiring length is obtained based on the shortest total interconnection line length, thereby obtaining the optimal layout of multiple core particles.

[0060] Table 1 is the core particle classification table: S41: The connection length is calculated by summing the distances of all pin locations between each pair of die: Where N is the number of core particles, Pi and Pj are the pin positions of core particles i and j respectively, and ‖p1-p2‖ is the Euclidean distance between two pins; Specifically, by calculating the connection length between each pair of core particles, it is possible to ensure that the distance between the pins of the core particles is minimized during the layout optimization process, thereby reducing the total length of the interconnection line. This can effectively reduce the wiring complexity and reduce signal delay. By calculating the distance between two pins, the length of the interconnection line of different core particle layouts can be comprehensively evaluated, rather than just considering the distance of a single pin, so that the layout is more reasonable.

[0061] S42: Initialization: randomly selecting the placement orientation of each core particle, the placement orientation of the core particles: 0°, 90°, 180°, 270°; Specifically, random initialization can break the local optimal solution in the optimization process, provide multiple possible layout starting points, and provide more options for subsequent optimization. By initializing multiple different layout solutions and increasing the search space, it is helpful to find a better layout solution.

[0062] S43: Iterative optimization: In each iteration, a core particle is randomly selected and its placement is changed, the pin position of the core particle is updated, and the new connection length is calculated; The conditions for accepting a new solution are: if the new connection length is less than the current length, the new solution is accepted, otherwise it remains unchanged; the solution after the maximum number of iterations is taken as the final solution, thereby obtaining the best orientation of each core particle and the final optimal layout.

[0063] Specifically, in each iteration, a core particle is randomly selected and its placement orientation is changed (for example, from 0° to 90°, or from 180° to 270°). According to the new placement orientation, the pin position set of the core particle is updated. The new total connection length L' is calculated. If the new connection length L' is less than the current connection length L, the new solution is accepted, that is, the new placement orientation of the core particle is used as the current solution; otherwise, the original solution is retained. The above process is repeated until the maximum number of iterations is reached. Finally, the placement solution at the end of the iteration is taken as the optimal layout.

[0064] Through these designs, the computational complexity and solution accuracy can be effectively balanced during the optimization process, thereby improving the efficiency and quality of integrated circuit layout and ultimately obtaining a more optimized core layout.

[0065] It can be seen from the above embodiments that the present application may cause some adverse effects, thereby greatly reducing the performance of the multi-core system, because the current multi-core layout optimization mainly optimizes a single goal and only considers the minimization of the system area or the minimization of the transmission delay. Therefore, the present application proposes a multi-core layout optimization method based on a multi-objective optimization algorithm. The Pareto frontier of each objective optimization function is first obtained by the NSWOA algorithm, and then the MHA algorithm is used to determine the compromise solution to determine the position of the core, and finally the placement orientation is adjusted to obtain the optimal multi-core layout solution. Compared with the single-objective layout optimization, the present invention simultaneously considers the four most critical goals in the multi-core system, thereby significantly improving the performance and integration of the multi-core system in the 2.5D package; the method of the present invention has strong adaptability and can be flexibly adjusted for 2.5D packages of different types and sizes.

[0066] Corresponding to the aforementioned embodiment of the multi-chip layout optimization method based on the multi-objective optimization algorithm, the present application also provides an embodiment of the multi-chip layout optimization device based on the multi-objective optimization algorithm.

[0067] Figure 2 is a block diagram of a multi-chip layout optimization device based on a multi-objective optimization algorithm according to an exemplary embodiment. Figure 2 , the device comprises:

[0068] Construction module 1 is used to construct the target optimization functions and constraints of chip temperature, inter-chip transmission delay, total area and inter-chip communication power consumption respectively; Solving module 2, used for iteratively solving the objective optimization function based on the constraint conditions by using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function; A determination module 3 is used to determine a compromise solution based on the Pareto front surface using an MHA algorithm; The optimization module 4 is used to determine the placement position of the core particles according to the compromise solution, adjust the position according to the pin function and the connection requirements between the functional modules, and obtain the result of minimizing the total wiring length according to the shortest total interconnection line length, so as to obtain the optimal layout of multiple core particles.

[0069] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0070] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application scheme. A person of ordinary skill in the art can understand and implement it without paying any creative work.

[0071] Correspondingly, the present application also provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the multi-core layout optimization method based on the multi-objective optimization algorithm as described above.

[0072] Accordingly, the present application also provides a computer-readable storage medium on which computer instructions are stored. When the instructions are executed by a processor, the multi-chip layout optimization method based on the multi-objective optimization algorithm as described above is implemented.

[0073] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0074] It should be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A multi-chip layout optimization method based on a multi-objective optimization algorithm, characterized in that: include: Construct the target optimization functions and constraints of chiplet temperature, inter-chiplet transmission delay, total area and inter-chiplet communication power consumption respectively; Based on the constraint conditions, the objective optimization function is iteratively solved using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function; Based on the Pareto front, a compromise solution is determined using the MHA algorithm; The placement of the core particles is determined according to the compromise solution, and the orientation is adjusted according to the pin function and the connection requirements between functional modules. The total wiring length is minimized according to the shortest total interconnection length, thereby obtaining the optimal layout of multiple core particles.

2. The method according to claim 1, characterized in that The objective function of the core particle temperature is expressed as: ； in, is the core particle temperature; } represents the lower left corner coordinate and upper right corner coordinate of core particle n; is the ambient temperature; is the power consumption of the ith chip; is the thermal resistance; is the effective area of ​​the ith core particle; is the heat transfer coefficient between the ith and jth core particles; is the temperature of the jth core particle; is the distance between the ith and jth core particles, expressed as ; The constraints are expressed as: ； Where T max is the maximum threshold of temperature.

3. The method according to claim 1, characterized in that The objective function of the inter-chip transmission delay is expressed as: ； Among them, f D Inter-chip transmission delay; is the transmission rate between the ith and jth core particles; The constraints are expressed as: ； Where D max is the maximum threshold for transmission delay.

4. The method according to claim 1, characterized in that The objective function of the total area is expressed as: ； In the formula, f A is the total area; The constraints are expressed as: ； in is the maximum threshold of the total chip area.

5. The method according to claim 1, characterized in that The objective function of the power consumption of inter-chiplet communication is expressed as: ； Among them, f P is the power consumption of inter-chiplet communication; is the communication frequency between the ith and jth core particles, The constraints are expressed as: ； Where P max is the maximum threshold of communication power consumption.

6. The method according to claim 1, characterized in that Based on the constraints, the objective optimization function is iteratively solved using the NSWOA algorithm to obtain the Pareto frontier of the multi-objective optimization function, including: S21: Read the parameters of the core particles: the position of the core particles, the ambient temperature, the power consumption of the core particles, the thermal resistance; the effective area of ​​the core particles, the thermal conductivity coefficient between the core particles, the temperature of the core particles, the distance between the core particles, the transmission rate between the core particles, and the communication frequency between the core particles; S22: Initialize the NSWOA algorithm parameters, select the initial population, and initialize according to the constraints; S23: Update the current optimal solution through the shrinking and encircling mechanism, spiral mechanism and search and foraging mechanism of the NSWOA algorithm. In each iteration, it is necessary to calculate each objective optimization function for fitness evaluation and identify the current optimal solution; S24: Repeat the above S21-S23 until the maximum number of iterations is reached, and the Pareto frontiers of the four objectives are obtained.

7. The method according to claim 1, characterized in that Based on the Pareto front, the MHA algorithm is used to determine a compromise solution, including: For the objective function, each Pareto optimal solution has a set of corresponding values. Assuming there are n sets of solutions on the Pareto frontier, we get a matrix M, where each row corresponds to a solution. By combining the matrix M with three different weight matrices W Q , W K and W V Multiply to calculate the Query, Key, and Value of each solution; The attention weight of each solution to other solutions is obtained by calculating the dot product of the query of each solution and the key of all solutions, and then normalizing it through the softmax function; Select the solution with the highest attention weight as the compromise solution; According to the predicted compromise solution and the actual compromise solution, the loss function is calculated, back-propagated, and the Query, Key, and Value are updated.

8. The method according to claim 1, characterized in that The placement of the core particles is determined according to the compromise solution, and the orientation is adjusted according to the pin function and the connection requirements between the functional modules. The total wiring length is minimized according to the shortest total interconnection length, thereby obtaining the optimal layout of the multi-core particles, including: The connection length is calculated by summing the distances of all pin locations between each pair of die: ， Where N is the number of core particles, Pi and Pj are the pin positions of core particles i and j respectively, and ‖p1-p2‖ is the Euclidean distance between two pins; Initialization: randomly selecting the placement orientation of each core particle, the placement orientation of the core particles: 0°, 90°, 180°, 270°; Iterative optimization: In each iteration, a core particle is randomly selected and its placement is changed, the pin position of the core particle is updated, and the new connection length is calculated. The condition for accepting a new solution is: if the new connection length is less than the current length, the new solution is accepted, otherwise it remains unchanged. The solution after the maximum number of iterations is taken as the final solution, thereby obtaining the optimal position of each core particle and the final optimal layout.

9. A multi-chip layout optimization device based on a multi-objective optimization algorithm, characterized in that: include: A construction module is used to construct the target optimization functions and constraints of the core particle temperature, the transmission delay between core particles, the total area and the power consumption of the communication between core particles respectively; A solution module, used for iteratively solving the objective optimization function based on the constraint conditions by using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function; A determination module, used for determining a compromise solution based on the Pareto front surface using an MHA algorithm; The optimization module is used to determine the placement position of the core particles according to the compromise solution, adjust the position according to the pin function and the connection requirements between the functional modules, and obtain the result of minimizing the total wiring length according to the shortest total interconnection line length, so as to obtain the optimal layout of multiple core particles.

10. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 8.

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